Re: [Qemu-devel] [PATCH 2/2] m48t59: add mem_base value to m48t59_init_isa() - Mark Cave-Ayland

From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
To: Peter Maydell <peter.maydell@linaro.org>,
	Artyom Tarasenko <atar4qemu@gmail.com>
Cc: "Paolo Bonzini" <pbonzini@redhat.com>,
	"qemu-ppc@nongnu.org" <qemu-ppc@nongnu.org>,
	qemu-devel <qemu-devel@nongnu.org>,
	"Andreas Färber" <afaerber@suse.de>,
	"Alexander Graf" <agraf@suse.de>
Subject: Re: [Qemu-devel] [PATCH 2/2] m48t59: add mem_base value to m48t59_init_isa()
Date: Mon, 19 Jan 2015 16:48:23 +0000	[thread overview]
Message-ID: <54BD3557.9040706@ilande.co.uk> (raw)
In-Reply-To: <CAFEAcA9X_vTX0YV8iAgLz8pnsVjAtpgVym47T0Vvkhw6kDBcPg@mail.gmail.com>

On 19/01/15 15:04, Peter Maydell wrote:

> On 19 January 2015 at 12:57, Artyom Tarasenko <atar4qemu@gmail.com> wrote:
>> But out of curiosity, would it be possible to have a sysbus device
>> somewhere in a middle of PCI space? Do sysbus devices have higher
>> priority if the address spaces overlap? Or do you mean that the PCI
>> controller needs to be modified to have a hole for a sysbus device?
> 
> You can specify the priority when you map devices into a MemoryRegion,
> so you can handle this by either making the sysbus device a positive
> priority or by making the PCI window have a negative priority.
> 
> (We don't actually get this right on x86 currently,
> which has resulted in some awkwardness for the PPC desire to
> make PCI address 0 valid.)

I'm not sure this would work for SPARC64 since potentially OpenBIOS can
program the I/O BAR for the ebus anywhere (and the NVRAM is located on
the ebus). At the moment we cheat by creating an alias to I/O space at
the top of memory so that OpenBIOS can always access it at a fixed address.

ATB,

Mark.