Re: [Qemu-devel] [PATCH 2/2] m48t59: add mem_base value to m48t59_init_isa()

From: Artyom Tarasenko <atar4qemu@gmail.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: qemu-ppc@nongnu.org,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
	qemu-devel <qemu-devel@nongnu.org>,
	"Andreas Färber" <afaerber@suse.de>,
	"Alexander Graf" <agraf@suse.de>
Subject: Re: [Qemu-devel] [PATCH 2/2] m48t59: add mem_base value to m48t59_init_isa()
Date: Mon, 19 Jan 2015 13:57:00 +0100	[thread overview]
Message-ID: <CACXAS8Di2q=YMU+1MviCxM9SPYr=Fii=20LCqJUOgD_=p7=Tfw@mail.gmail.com> (raw)
In-Reply-To: <54BCFC57.3010709@redhat.com>

On Mon, Jan 19, 2015 at 1:45 PM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> On 19/01/2015 12:35, Mark Cave-Ayland wrote:
>> Similar to m48t59_init(), add a mem_base value so that NVRAM can be mapped via
>> MMIO rather than ioport if required.
>>
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> ---
>
> Is it really ISA if it's MMIO?  In other words, why can't this be a
> sysbus device?

On physical machines it's EBus, which is pretty much like 8-bit ISA.
So, I think modelling it as ISA is closer to to the reality.
But out of curiosity, would it be possible to have a sysbus device
somewhere in a middle of PCI space? Do sysbus devices have higher
priority if the address spaces overlap? Or do you mean that the PCI
controller needs to be modified to have a hole for a sysbus device?

Artyom

-- 
Regards,
Artyom Tarasenko

SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu