[U-Boot] sunxi: Initial A80 support

[U-Boot] sunxi: Initial A80 support

[Hans de Goede]

Hi Ian, ChenYu,

I'm very happy to present this patch series which adds initial A80 support,
with this series a u-boot.bin can be build which can then be fel booted
using Allwinners boot0 fel binary, and then can load linux from a sdcard
using a standard extlinux.conf setup.

Next step getting RSB going and finding out how the 2 pmics are hooked up,
and then slowly work towards getting SPL going.

Ian, as always, can you please review these patches ?

ChenYu, if you want to play with this, it is probably easiest to use my
sunxi-wip branch.

Regards,

Hans

[U-Boot] [PATCH 01/12] sunxi: Drop pll6 setting from clock_init_uart

[Hans de Goede]

As the comment says now that we have SPL support this is no longer necessary,
as PLL6 is already setup with the exact same parameters by the SPL.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/cpu/armv7/sunxi/clock_sun6i.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
index d7a7040..e2a7867 100644
--- a/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun6i.c
@@ -45,10 +45,10 @@ void clock_init_safe(void)
 
 void clock_init_uart(void)
 {
+#if CONFIG_CONS_INDEX < 5
 	struct sunxi_ccm_reg *const ccm =
 		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 
-#if CONFIG_CONS_INDEX < 5
 	/* uart clock source is apb2 */
 	writel(APB2_CLK_SRC_OSC24M|
 	       APB2_CLK_RATE_N_1|
@@ -68,9 +68,6 @@ void clock_init_uart(void)
 	/* enable R_PIO and R_UART clocks, and de-assert resets */
 	prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
 #endif
-
-	/* Dup with clock_init_safe(), drop once sun6i SPL support lands */
-	writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
 }
 
 int clock_twi_onoff(int port, int state)
-- 
2.1.0

[U-Boot] [PATCH 02/12] sunxi: Rename cpu.h to cpu_sun4i.h

[Hans de Goede]

sun4i - sun8i have (aprox.) the same iomem layout, but sun9i is quite
different, so add a wrapper cpu.h which includes the right mach specific
cpu_sun#i.h based on mach, like we already do with clock.h and dram.h .

Note for reviewers, cpu.h is effectively renamed tp cpu_sun4i.h by this
commit, the only change is the #ifndef ... #endif guard around the file.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/include/asm/arch-sunxi/cpu.h       | 148 +-------------------------
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 154 ++++++++++++++++++++++++++++
 2 files changed, 157 insertions(+), 145 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h

diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index 82b3d46..abf11fa 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -1,7 +1,5 @@
 /*
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -9,146 +7,6 @@
 #ifndef _SUNXI_CPU_H
 #define _SUNXI_CPU_H
 
-#define SUNXI_SRAM_A1_BASE		0x00000000
-#define SUNXI_SRAM_A1_SIZE		(16 * 1024)	/* 16 kiB */
+#include <asm/arch/cpu_sun4i.h>
 
-#define SUNXI_SRAM_A2_BASE		0x00004000	/* 16 kiB */
-#define SUNXI_SRAM_A3_BASE		0x00008000	/* 13 kiB */
-#define SUNXI_SRAM_A4_BASE		0x0000b400	/* 3 kiB */
-#define SUNXI_SRAM_D_BASE		0x00010000	/* 4 kiB */
-#define SUNXI_SRAM_B_BASE		0x00020000	/* 64 kiB (secure) */
-
-#define SUNXI_SRAMC_BASE		0x01c00000
-#define SUNXI_DRAMC_BASE		0x01c01000
-#define SUNXI_DMA_BASE			0x01c02000
-#define SUNXI_NFC_BASE			0x01c03000
-#define SUNXI_TS_BASE			0x01c04000
-#define SUNXI_SPI0_BASE			0x01c05000
-#define SUNXI_SPI1_BASE			0x01c06000
-#define SUNXI_MS_BASE			0x01c07000
-#define SUNXI_TVD_BASE			0x01c08000
-#define SUNXI_CSI0_BASE			0x01c09000
-#define SUNXI_TVE0_BASE			0x01c0a000
-#define SUNXI_EMAC_BASE			0x01c0b000
-#define SUNXI_LCD0_BASE			0x01c0C000
-#define SUNXI_LCD1_BASE			0x01c0d000
-#define SUNXI_VE_BASE			0x01c0e000
-#define SUNXI_MMC0_BASE			0x01c0f000
-#define SUNXI_MMC1_BASE			0x01c10000
-#define SUNXI_MMC2_BASE			0x01c11000
-#define SUNXI_MMC3_BASE			0x01c12000
-#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
-#define SUNXI_USB0_BASE			0x01c13000
-#define SUNXI_USB1_BASE			0x01c14000
-#endif
-#define SUNXI_SS_BASE			0x01c15000
-#define SUNXI_HDMI_BASE			0x01c16000
-#define SUNXI_SPI2_BASE			0x01c17000
-#define SUNXI_SATA_BASE			0x01c18000
-#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
-#define SUNXI_PATA_BASE			0x01c19000
-#define SUNXI_ACE_BASE			0x01c1a000
-#define SUNXI_TVE1_BASE			0x01c1b000
-#define SUNXI_USB2_BASE			0x01c1c000
-#else
-#define SUNXI_USB0_BASE			0x01c19000
-#define SUNXI_USB1_BASE			0x01c1a000
-#define SUNXI_USB2_BASE			0x01c1b000
-#endif
-#define SUNXI_CSI1_BASE			0x01c1d000
-#define SUNXI_TZASC_BASE		0x01c1e000
-#define SUNXI_SPI3_BASE			0x01c1f000
-
-#define SUNXI_CCM_BASE			0x01c20000
-#define SUNXI_INTC_BASE			0x01c20400
-#define SUNXI_PIO_BASE			0x01c20800
-#define SUNXI_TIMER_BASE		0x01c20c00
-#define SUNXI_SPDIF_BASE		0x01c21000
-#define SUNXI_AC97_BASE			0x01c21400
-#define SUNXI_IR0_BASE			0x01c21800
-#define SUNXI_IR1_BASE			0x01c21c00
-
-#define SUNXI_IIS_BASE			0x01c22400
-#define SUNXI_LRADC_BASE		0x01c22800
-#define SUNXI_AD_DA_BASE		0x01c22c00
-#define SUNXI_KEYPAD_BASE		0x01c23000
-#define SUNXI_TZPC_BASE			0x01c23400
-#define SUNXI_SID_BASE			0x01c23800
-#define SUNXI_SJTAG_BASE		0x01c23c00
-
-#define SUNXI_TP_BASE			0x01c25000
-#define SUNXI_PMU_BASE			0x01c25400
-#define SUN7I_CPUCFG_BASE              0x01c25c00
-
-#define SUNXI_UART0_BASE		0x01c28000
-#define SUNXI_UART1_BASE		0x01c28400
-#define SUNXI_UART2_BASE		0x01c28800
-#define SUNXI_UART3_BASE		0x01c28c00
-#define SUNXI_UART4_BASE		0x01c29000
-#define SUNXI_UART5_BASE		0x01c29400
-#define SUNXI_UART6_BASE		0x01c29800
-#define SUNXI_UART7_BASE		0x01c29c00
-#define SUNXI_PS2_0_BASE		0x01c2a000
-#define SUNXI_PS2_1_BASE		0x01c2a400
-
-#define SUNXI_TWI0_BASE			0x01c2ac00
-#define SUNXI_TWI1_BASE			0x01c2b000
-#define SUNXI_TWI2_BASE			0x01c2b400
-
-#define SUNXI_CAN_BASE			0x01c2bc00
-
-#define SUNXI_SCR_BASE			0x01c2c400
-
-#ifndef CONFIG_MACH_SUN6I
-#define SUNXI_GPS_BASE			0x01c30000
-#define SUNXI_MALI400_BASE		0x01c40000
-#define SUNXI_GMAC_BASE			0x01c50000
-#else
-#define SUNXI_GMAC_BASE			0x01c30000
-#endif
-
-#define SUNXI_DRAM_COM_BASE		0x01c62000
-#define SUNXI_DRAM_CTL0_BASE		0x01c63000
-#define SUNXI_DRAM_CTL1_BASE		0x01c64000
-#define SUNXI_DRAM_PHY0_BASE		0x01c65000
-#define SUNXI_DRAM_PHY1_BASE		0x01c66000
-
-/* module sram */
-#define SUNXI_SRAM_C_BASE		0x01d00000
-
-#define SUNXI_DE_FE0_BASE		0x01e00000
-#define SUNXI_DE_FE1_BASE		0x01e20000
-#define SUNXI_DE_BE0_BASE		0x01e60000
-#define SUNXI_DE_BE1_BASE		0x01e40000
-#define SUNXI_MP_BASE			0x01e80000
-#define SUNXI_AVG_BASE			0x01ea0000
-
-#define SUNXI_RTC_BASE			0x01f00000
-#define SUNXI_PRCM_BASE			0x01f01400
-#define SUN6I_CPUCFG_BASE		0x01f01c00
-#define SUNXI_R_UART_BASE		0x01f02800
-#define SUNXI_R_PIO_BASE		0x01f02c00
-#define SUN6I_P2WI_BASE			0x01f03400
-#define SUNXI_RSB_BASE			0x01f03400
-
-/* CoreSight Debug Module */
-#define SUNXI_CSDM_BASE			0x3f500000
-
-#define SUNXI_DDRII_DDRIII_BASE		0x40000000	/* 2 GiB */
-
-#define SUNXI_BROM_BASE			0xffff0000	/* 32 kiB */
-
-#define SUNXI_CPU_CFG			(SUNXI_TIMER_BASE + 0x13c)
-
-/* SS bonding ids used for cpu identification */
-#define SUNXI_SS_BOND_ID_A31		4
-#define SUNXI_SS_BOND_ID_A31S		5
-
-#ifndef __ASSEMBLY__
-void sunxi_board_init(void);
-void sunxi_reset(void);
-int sunxi_get_ss_bonding_id(void);
-int sunxi_get_sid(unsigned int *sid);
-#endif /* __ASSEMBLY__ */
-
-#endif /* _CPU_H */
+#endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
new file mode 100644
index 0000000..dae6069
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2007-2011
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Tom Cubie <tangliang@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPU_SUN4I_H
+#define _SUNXI_CPU_SUN4I_H
+
+#define SUNXI_SRAM_A1_BASE		0x00000000
+#define SUNXI_SRAM_A1_SIZE		(16 * 1024)	/* 16 kiB */
+
+#define SUNXI_SRAM_A2_BASE		0x00004000	/* 16 kiB */
+#define SUNXI_SRAM_A3_BASE		0x00008000	/* 13 kiB */
+#define SUNXI_SRAM_A4_BASE		0x0000b400	/* 3 kiB */
+#define SUNXI_SRAM_D_BASE		0x00010000	/* 4 kiB */
+#define SUNXI_SRAM_B_BASE		0x00020000	/* 64 kiB (secure) */
+
+#define SUNXI_SRAMC_BASE		0x01c00000
+#define SUNXI_DRAMC_BASE		0x01c01000
+#define SUNXI_DMA_BASE			0x01c02000
+#define SUNXI_NFC_BASE			0x01c03000
+#define SUNXI_TS_BASE			0x01c04000
+#define SUNXI_SPI0_BASE			0x01c05000
+#define SUNXI_SPI1_BASE			0x01c06000
+#define SUNXI_MS_BASE			0x01c07000
+#define SUNXI_TVD_BASE			0x01c08000
+#define SUNXI_CSI0_BASE			0x01c09000
+#define SUNXI_TVE0_BASE			0x01c0a000
+#define SUNXI_EMAC_BASE			0x01c0b000
+#define SUNXI_LCD0_BASE			0x01c0C000
+#define SUNXI_LCD1_BASE			0x01c0d000
+#define SUNXI_VE_BASE			0x01c0e000
+#define SUNXI_MMC0_BASE			0x01c0f000
+#define SUNXI_MMC1_BASE			0x01c10000
+#define SUNXI_MMC2_BASE			0x01c11000
+#define SUNXI_MMC3_BASE			0x01c12000
+#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
+#define SUNXI_USB0_BASE			0x01c13000
+#define SUNXI_USB1_BASE			0x01c14000
+#endif
+#define SUNXI_SS_BASE			0x01c15000
+#define SUNXI_HDMI_BASE			0x01c16000
+#define SUNXI_SPI2_BASE			0x01c17000
+#define SUNXI_SATA_BASE			0x01c18000
+#if !defined CONFIG_MACH_SUN6I && !defined CONFIG_MACH_SUN8I
+#define SUNXI_PATA_BASE			0x01c19000
+#define SUNXI_ACE_BASE			0x01c1a000
+#define SUNXI_TVE1_BASE			0x01c1b000
+#define SUNXI_USB2_BASE			0x01c1c000
+#else
+#define SUNXI_USB0_BASE			0x01c19000
+#define SUNXI_USB1_BASE			0x01c1a000
+#define SUNXI_USB2_BASE			0x01c1b000
+#endif
+#define SUNXI_CSI1_BASE			0x01c1d000
+#define SUNXI_TZASC_BASE		0x01c1e000
+#define SUNXI_SPI3_BASE			0x01c1f000
+
+#define SUNXI_CCM_BASE			0x01c20000
+#define SUNXI_INTC_BASE			0x01c20400
+#define SUNXI_PIO_BASE			0x01c20800
+#define SUNXI_TIMER_BASE		0x01c20c00
+#define SUNXI_SPDIF_BASE		0x01c21000
+#define SUNXI_AC97_BASE			0x01c21400
+#define SUNXI_IR0_BASE			0x01c21800
+#define SUNXI_IR1_BASE			0x01c21c00
+
+#define SUNXI_IIS_BASE			0x01c22400
+#define SUNXI_LRADC_BASE		0x01c22800
+#define SUNXI_AD_DA_BASE		0x01c22c00
+#define SUNXI_KEYPAD_BASE		0x01c23000
+#define SUNXI_TZPC_BASE			0x01c23400
+#define SUNXI_SID_BASE			0x01c23800
+#define SUNXI_SJTAG_BASE		0x01c23c00
+
+#define SUNXI_TP_BASE			0x01c25000
+#define SUNXI_PMU_BASE			0x01c25400
+#define SUN7I_CPUCFG_BASE              0x01c25c00
+
+#define SUNXI_UART0_BASE		0x01c28000
+#define SUNXI_UART1_BASE		0x01c28400
+#define SUNXI_UART2_BASE		0x01c28800
+#define SUNXI_UART3_BASE		0x01c28c00
+#define SUNXI_UART4_BASE		0x01c29000
+#define SUNXI_UART5_BASE		0x01c29400
+#define SUNXI_UART6_BASE		0x01c29800
+#define SUNXI_UART7_BASE		0x01c29c00
+#define SUNXI_PS2_0_BASE		0x01c2a000
+#define SUNXI_PS2_1_BASE		0x01c2a400
+
+#define SUNXI_TWI0_BASE			0x01c2ac00
+#define SUNXI_TWI1_BASE			0x01c2b000
+#define SUNXI_TWI2_BASE			0x01c2b400
+
+#define SUNXI_CAN_BASE			0x01c2bc00
+
+#define SUNXI_SCR_BASE			0x01c2c400
+
+#ifndef CONFIG_MACH_SUN6I
+#define SUNXI_GPS_BASE			0x01c30000
+#define SUNXI_MALI400_BASE		0x01c40000
+#define SUNXI_GMAC_BASE			0x01c50000
+#else
+#define SUNXI_GMAC_BASE			0x01c30000
+#endif
+
+#define SUNXI_DRAM_COM_BASE		0x01c62000
+#define SUNXI_DRAM_CTL0_BASE		0x01c63000
+#define SUNXI_DRAM_CTL1_BASE		0x01c64000
+#define SUNXI_DRAM_PHY0_BASE		0x01c65000
+#define SUNXI_DRAM_PHY1_BASE		0x01c66000
+
+/* module sram */
+#define SUNXI_SRAM_C_BASE		0x01d00000
+
+#define SUNXI_DE_FE0_BASE		0x01e00000
+#define SUNXI_DE_FE1_BASE		0x01e20000
+#define SUNXI_DE_BE0_BASE		0x01e60000
+#define SUNXI_DE_BE1_BASE		0x01e40000
+#define SUNXI_MP_BASE			0x01e80000
+#define SUNXI_AVG_BASE			0x01ea0000
+
+#define SUNXI_RTC_BASE			0x01f00000
+#define SUNXI_PRCM_BASE			0x01f01400
+#define SUN6I_CPUCFG_BASE		0x01f01c00
+#define SUNXI_R_UART_BASE		0x01f02800
+#define SUNXI_R_PIO_BASE		0x01f02c00
+#define SUN6I_P2WI_BASE			0x01f03400
+#define SUNXI_RSB_BASE			0x01f03400
+
+/* CoreSight Debug Module */
+#define SUNXI_CSDM_BASE			0x3f500000
+
+#define SUNXI_DDRII_DDRIII_BASE		0x40000000	/* 2 GiB */
+
+#define SUNXI_BROM_BASE			0xffff0000	/* 32 kiB */
+
+#define SUNXI_CPU_CFG			(SUNXI_TIMER_BASE + 0x13c)
+
+/* SS bonding ids used for cpu identification */
+#define SUNXI_SS_BOND_ID_A31		4
+#define SUNXI_SS_BOND_ID_A31S		5
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+void sunxi_reset(void);
+int sunxi_get_ss_bonding_id(void);
+int sunxi_get_sid(unsigned int *sid);
+#endif /* __ASSEMBLY__ */
+
+#endif /* _SUNXI_CPU_SUN4I_H */
-- 
2.1.0

[U-Boot] [PATCH 03/12] sunxi: Move clock_get_pllX / clock_set_pllX protos to mach specific headers

[Hans de Goede]

Which pll-s are available depends on the machine type, move the
clock_get_pllX / clock_set_pllX prototypes to the clock_sun?i.h header files
so that we only declare what is actually available. e.g. clock_get_pll5p()
is not available on sun6i / sun8i, and with sun9i we get a completely
different set of plls.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/include/asm/arch-sunxi/clock.h       | 4 ----
 arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 7 +++++++
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 5 +++++
 3 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index 505c363..ea268b1 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -24,10 +24,6 @@
 #ifndef __ASSEMBLY__
 int clock_init(void);
 int clock_twi_onoff(int port, int state);
-void clock_set_pll1(unsigned int hz);
-void clock_set_pll3(unsigned int hz);
-unsigned int clock_get_pll5p(void);
-unsigned int clock_get_pll6(void);
 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz);
 void clock_init_safe(void);
 void clock_init_uart(void);
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
index 84a9a2b..5ebf856 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
@@ -320,4 +320,11 @@ struct sunxi_ccm_reg {
 #define CCM_DE_CTRL_RST			(1 << 30)
 #define CCM_DE_CTRL_GATE		(1 << 31)
 
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+void clock_set_pll3(unsigned int hz);
+unsigned int clock_get_pll5p(void);
+unsigned int clock_get_pll6(void);
+#endif
+
 #endif /* _SUNXI_CLOCK_SUN4I_H */
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index 4711260..e101c54 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -320,6 +320,11 @@ struct sunxi_ccm_reg {
 #define CCM_DE_CTRL_PLL10		(5 << 24)
 #define CCM_DE_CTRL_GATE		(1 << 31)
 
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+void clock_set_pll3(unsigned int hz);
 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
+unsigned int clock_get_pll6(void);
+#endif
 
 #endif /* _SUNXI_CLOCK_SUN6I_H */
-- 
2.1.0

[U-Boot] [PATCH 04/12] sunxi: Update sunxi-common.h to deal with different DRAM base addr on sun9i

[Hans de Goede]

The DRAM Base differs between sun9i and the others and we cannot use
math in various places like the environment setting and linker scripts,
so "simply" define everything which contains the SDRAM_BASE twice.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 include/configs/sunxi-common.h | 88 +++++++++++++++++++++++++++++-------------
 1 file changed, 62 insertions(+), 26 deletions(-)

diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 7a66a4d..59a298d 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -25,7 +25,68 @@
 
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 
+/*
+ * The DRAM Base differs between sun9i and the others and we cannot use
+ * math in various places like the environment setting and linker scripts,
+ * so "simply" define everything which contains the SDRAM_BASE twice.
+ *
+ * Note we want to have everything identical except for the DRAM base address,
+ * when editing this, please keep everything in sync!
+ */
+
+#ifdef CONFIG_MACH_SUN9I
+
+#define CONFIG_SYS_SDRAM_BASE		0x20000000
+#define CONFIG_SYS_LOAD_ADDR		0x22000000
+#define CONFIG_SYS_TEXT_BASE		0x2a000000
+#define CONFIG_SYS_SPL_MALLOC_START	0x2ff00000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000	/* 512 KiB */
+#define CONFIG_SPL_BSS_START_ADDR	0x2ff80000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000	/* 512 KiB */
+
+/* Use the room between the end of bootm_size and the framebuffer */
+#define CONFIG_PRE_CON_BUF_ADDR		0x2f000000
+
+/*
+ * 240M RAM (256M minimum minus space for the framebuffer),
+ * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
+ * 1M script, 1M pxe and the ramdisk at the end.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0xf000000\0" \
+	"kernel_addr_r=0x22000000\0" \
+	"fdt_addr_r=0x23000000\0" \
+	"scriptaddr=0x23100000\0" \
+	"pxefile_addr_r=0x23200000\0" \
+	"ramdisk_addr_r=0x23300000\0"
+
+#else /* ifdef CONFIG_MACH_SUN9I */
+
+#define CONFIG_SYS_SDRAM_BASE		0x40000000
+#define CONFIG_SYS_LOAD_ADDR		0x42000000
 #define CONFIG_SYS_TEXT_BASE		0x4a000000
+#define CONFIG_SYS_SPL_MALLOC_START	0x4ff00000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000	/* 512 KiB */
+#define CONFIG_SPL_BSS_START_ADDR	0x4ff80000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000	/* 512 KiB */
+
+/* Use the room between the end of bootm_size and the framebuffer */
+#define CONFIG_PRE_CON_BUF_ADDR		0x4f000000
+
+/*
+ * 240M RAM (256M minimum minus space for the framebuffer),
+ * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
+ * 1M script, 1M pxe and the ramdisk at the end.
+ */
+#define MEM_LAYOUT_ENV_SETTINGS \
+	"bootm_size=0xf000000\0" \
+	"kernel_addr_r=0x42000000\0" \
+	"fdt_addr_r=0x43000000\0" \
+	"scriptaddr=0x43100000\0" \
+	"pxefile_addr_r=0x43200000\0" \
+	"ramdisk_addr_r=0x43300000\0"
+
+#endif
 
 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM)
 # define CONFIG_CMD_DM
@@ -54,8 +115,6 @@
 # define CONFIG_SYS_NS16550_COM5		SUNXI_R_UART_BASE
 #endif
 
-/* DRAM Base */
-#define CONFIG_SYS_SDRAM_BASE		0x40000000
 #define CONFIG_SYS_INIT_RAM_ADDR	0x0
 #define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* 32 KiB */
 
@@ -113,10 +172,8 @@
 /* Boot Argument Buffer Size */
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
-#define CONFIG_SYS_LOAD_ADDR		0x42000000 /* default load address */
-
 /* standalone support */
-#define CONFIG_STANDALONE_LOAD_ADDR	0x42000000
+#define CONFIG_STANDALONE_LOAD_ADDR	CONFIG_SYS_LOAD_ADDR
 
 /* baudrate */
 #define CONFIG_BAUDRATE			115200
@@ -153,9 +210,6 @@
 
 #else /* CONFIG_SPL */
 
-#define CONFIG_SPL_BSS_START_ADDR	0x4ff80000
-#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KiB */
-
 #define CONFIG_SPL_TEXT_BASE		0x20		/* sram start+header */
 #define CONFIG_SPL_MAX_SIZE		0x5fe0		/* 24KB on sun4i/sun7i */
 
@@ -175,8 +229,6 @@
 /* end of 32 KiB in sram */
 #define LOW_LEVEL_SRAM_STACK		0x00008000 /* End of sram */
 #define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
-#define CONFIG_SYS_SPL_MALLOC_START	0x4ff00000
-#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000	/* 512 KiB */
 
 /* I2C */
 #define CONFIG_SPL_I2C_SUPPORT
@@ -283,22 +335,6 @@
 /* Enable pre-console buffer to get complete log on the VGA console */
 #define CONFIG_PRE_CONSOLE_BUFFER
 #define CONFIG_PRE_CON_BUF_SZ		(1024 * 1024)
-/* Use the room between the end of bootm_size and the framebuffer */
-#define CONFIG_PRE_CON_BUF_ADDR		0x4f000000
-
-/*
- * 240M RAM (256M minimum minus space for the framebuffer),
- * 32M uncompressed kernel, 16M compressed kernel, 1M fdt,
- * 1M script, 1M pxe and the ramdisk at the end.
- */
-#define MEM_LAYOUT_ENV_SETTINGS \
-	"bootm_size=0xf000000\0" \
-	"kernel_addr_r=0x42000000\0" \
-	"fdt_addr_r=0x43000000\0" \
-	"scriptaddr=0x43100000\0" \
-	"pxefile_addr_r=0x43200000\0" \
-	"ramdisk_addr_r=0x43300000\0"
-
 #ifdef CONFIG_MMC
 #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
 #else
-- 
2.1.0

[U-Boot] [PATCH 05/12] sunxi: Move setting of CPU system control register SMP bit to save_boot_params

[Hans de Goede]

According to the "Cortex-A7 MPCore Technical Reference Manual":

"You must ensure this bit is set to 1 before the caches and MMU are enabled,
or any cache and TLB maintenance operations are performed."

Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations,
we should thus enable the SMP bit earlier, and the only chance to do that is
to do it at save_boot_params time.

This does not seem to make any noticable difference, but:
1) According to the manual it is the right thing to do
2) We need to do other magic really early on for sun9i (A80) support, so we
   need to introduce a lowlevel_init.S / save_boot_params function anyways

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/cpu/armv7/sunxi/Makefile        |  1 +
 arch/arm/cpu/armv7/sunxi/board.c         |  8 --------
 arch/arm/cpu/armv7/sunxi/lowlevel_init.S | 23 +++++++++++++++++++++++
 3 files changed, 24 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/cpu/armv7/sunxi/lowlevel_init.S

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 1720f7d..3a6aa6d 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -7,6 +7,7 @@
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
+obj-y	+= lowlevel_init.o
 obj-y	+= timer.o
 obj-y	+= board.o
 obj-y	+= clock.o
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index bc98c56..4449942 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -120,14 +120,6 @@ void s_init(void)
 	 * access gets messed up (seems cache related) */
 	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
 #endif
-#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
-		defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
-	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
-	asm volatile(
-		"mrc p15, 0, r0, c1, c0, 1\n"
-		"orr r0, r0, #1 << 6\n"
-		"mcr p15, 0, r0, c1, c0, 1\n");
-#endif
 
 	clock_init();
 	timer_init();
diff --git a/arch/arm/cpu/armv7/sunxi/lowlevel_init.S b/arch/arm/cpu/armv7/sunxi/lowlevel_init.S
new file mode 100644
index 0000000..b80b3eb
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/lowlevel_init.S
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+#include <version.h>
+#include <linux/linkage.h>
+
+/*
+ * On sunxi we need to do some setup *before* cpu_init_cp15 from start.S
+ * runs, we (ab)use save_boot_params for this.
+ */
+ENTRY(save_boot_params)
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN7I || \
+    defined CONFIG_MACH_SUN8I
+	mrc	p15, 0, r0, c1, c0, 1
+	orr	r0, r0, #(1<<6)
+	mcr	p15, 0, r0, c1, c0, 1
+#endif
+	bx	lr
+ENDPROC(save_boot_params)
-- 
2.1.0

[U-Boot] [PATCH 06/12] sun9i: Add cpu_sun9i.h with iomem defines

[Hans de Goede]

Add a headerfile with all the base addresses from the sun9i blocks.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/include/asm/arch-sunxi/cpu.h       |   4 ++
 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 108 ++++++++++++++++++++++++++++
 2 files changed, 112 insertions(+)
 create mode 100755 arch/arm/include/asm/arch-sunxi/cpu_sun9i.h

diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h
index abf11fa..73583ed 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -7,6 +7,10 @@
 #ifndef _SUNXI_CPU_H
 #define _SUNXI_CPU_H
 
+#if defined(CONFIG_MACH_SUN9I)
+#include <asm/arch/cpu_sun9i.h>
+#else
 #include <asm/arch/cpu_sun4i.h>
+#endif
 
 #endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
new file mode 100755
index 0000000..a2a7839
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ * (C) Copyright 2007-2013
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Jerry Wang <wangflord@allwinnertech.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPU_SUN9I_H
+#define _SUNXI_CPU_SUN9I_H
+
+#define REGS_AHB0_BASE			0x01C00000
+#define REGS_AHB1_BASE			0x00800000
+#define REGS_AHB2_BASE			0x03000000
+#define REGS_APB0_BASE			0x06000000
+#define REGS_APB1_BASE			0x07000000
+#define REGS_RCPUS_BASE			0x08000000
+
+#define SUNXI_SRAM_D_BASE		0x08100000
+
+/* AHB0 Module */
+#define SUNXI_NFC_BASE			(REGS_AHB0_BASE + 0x3000)
+#define SUNXI_TSC_BASE			(REGS_AHB0_BASE + 0x4000)
+
+#define SUNXI_MMC0_BASE			(REGS_AHB0_BASE + 0x0f000)
+#define SUNXI_MMC1_BASE			(REGS_AHB0_BASE + 0x10000)
+#define SUNXI_MMC2_BASE			(REGS_AHB0_BASE + 0x11000)
+#define SUNXI_MMC3_BASE			(REGS_AHB0_BASE + 0x12000)
+#define SUNXI_MMC_COMMON_BASE		(REGS_AHB0_BASE + 0x13000)
+
+#define SUNXI_SPI0_BASE			(REGS_AHB0_BASE + 0x1A000)
+#define SUNXI_SPI1_BASE			(REGS_AHB0_BASE + 0x1B000)
+#define SUNXI_SPI2_BASE			(REGS_AHB0_BASE + 0x1C000)
+#define SUNXI_SPI3_BASE			(REGS_AHB0_BASE + 0x1D000)
+
+#define SUNXI_GIC400_BASE		(REGS_AHB0_BASE + 0x40000)
+#define SUNXI_ARMA9_GIC_BASE		(REGS_AHB0_BASE + 0x41000)
+#define SUNXI_ARMA9_CPUIF_BASE		(REGS_AHB0_BASE + 0x42000)
+
+/* AHB1 Module */
+#define SUNXI_DMA_BASE			(REGS_AHB1_BASE + 0x002000)
+#define SUNXI_USBOTG_BASE		(REGS_AHB1_BASE + 0x100000)
+#define SUNXI_USBEHCI0_BASE		(REGS_AHB1_BASE + 0x200000)
+#define SUNXI_USBEHCI1_BASE		(REGS_AHB1_BASE + 0x201000)
+#define SUNXI_USBEHCI2_BASE		(REGS_AHB1_BASE + 0x202000)
+
+/* AHB2 Module */
+#define SUNXI_DE_SYS_BASE		(REGS_AHB2_BASE + 0x000000)
+#define SUNXI_DISP_SYS_BASE		(REGS_AHB2_BASE + 0x010000)
+#define SUNXI_DE_FE0_BASE		(REGS_AHB2_BASE + 0x100000)
+#define SUNXI_DE_FE1_BASE		(REGS_AHB2_BASE + 0x140000)
+#define SUNXI_DE_FE2_BASE		(REGS_AHB2_BASE + 0x180000)
+
+#define SUNXI_DE_BE0_BASE		(REGS_AHB2_BASE + 0x200000)
+#define SUNXI_DE_BE1_BASE		(REGS_AHB2_BASE + 0x240000)
+#define SUNXI_DE_BE2_BASE		(REGS_AHB2_BASE + 0x280000)
+
+#define SUNXI_DE_DEU0_BASE		(REGS_AHB2_BASE + 0x300000)
+#define SUNXI_DE_DEU1_BASE		(REGS_AHB2_BASE + 0x340000)
+#define SUNXI_DE_DRC0_BASE		(REGS_AHB2_BASE + 0x400000)
+#define SUNXI_DE_DRC1_BASE		(REGS_AHB2_BASE + 0x440000)
+
+#define SUNXI_LCD0_BASE			(REGS_AHB2_BASE + 0xC00000)
+#define SUNXI_LCD1_BASE			(REGS_AHB2_BASE + 0xC10000)
+#define SUNXI_LCD2_BASE			(REGS_AHB2_BASE + 0xC20000)
+#define SUNXI_MIPI_DSI0_BASE		(REGS_AHB2_BASE + 0xC40000)
+/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */
+#define SUNXI_MIPI_DSI0_DPHY_BASE	(REGS_AHB2_BASE + 0xC40100)
+#define SUNXI_HDMI_BASE			(REGS_AHB2_BASE + 0xD00000)
+
+/* APB0 Module */
+#define SUNXI_CCM_BASE			(REGS_APB0_BASE + 0x0000)
+#define SUNXI_CCMMODULE_BASE		(REGS_APB0_BASE + 0x0400)
+#define SUNXI_PIO_BASE			(REGS_APB0_BASE + 0x0800)
+#define SUNXI_R_PIO_BASE		(0x08002C00)
+#define SUNXI_TIMER_BASE		(REGS_APB0_BASE + 0x0C00)
+#define SUNXI_PWM_BASE			(REGS_APB0_BASE + 0x1400)
+#define SUNXI_LRADC_BASE		(REGS_APB0_BASE + 0x1800)
+
+/* APB1 Module */
+#define SUNXI_UART0_BASE		(REGS_APB1_BASE + 0x0000)
+#define SUNXI_UART1_BASE		(REGS_APB1_BASE + 0x0400)
+#define SUNXI_UART2_BASE		(REGS_APB1_BASE + 0x0800)
+#define SUNXI_UART3_BASE		(REGS_APB1_BASE + 0x0C00)
+#define SUNXI_UART4_BASE		(REGS_APB1_BASE + 0x1000)
+#define SUNXI_UART5_BASE		(REGS_APB1_BASE + 0x1400)
+#define SUNXI_TWI0_BASE			(REGS_APB1_BASE + 0x2800)
+#define SUNXI_TWI1_BASE			(REGS_APB1_BASE + 0x2C00)
+#define SUNXI_TWI2_BASE			(REGS_APB1_BASE + 0x3000)
+#define SUNXI_TWI3_BASE			(REGS_APB1_BASE + 0x3400)
+#define SUNXI_TWI4_BASE			(REGS_APB1_BASE + 0x3800)
+
+/* RCPUS Module */
+#define SUNXI_RPRCM_BASE		(REGS_RCPUS_BASE + 0x1400)
+#define SUNXI_R_UART_BASE		(REGS_RCPUS_BASE + 0x2800)
+
+/* Misc. */
+#define SUNXI_BROM_BASE			0xFFFF0000 /* 32K */
+#define SUNXI_CPU_CFG			(SUNXI_TIMER_BASE + 0x13c)
+
+#ifndef __ASSEMBLY__
+void sunxi_board_init(void);
+void sunxi_reset(void);
+int sunxi_get_sid(unsigned int *sid);
+#endif
+
+#endif /* _SUNXI_CPU_SUN9I_H */
-- 
2.1.0

[U-Boot] [PATCH 07/12] sun9i: Add clock_sun9i.h with ccu register layout for sun9i

[Hans de Goede]

Add a headerfile with the sun9i ccu register layout.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/include/asm/arch-sunxi/clock.h       |   2 +
 arch/arm/include/asm/arch-sunxi/clock_sun9i.h | 139 ++++++++++++++++++++++++++
 2 files changed, 141 insertions(+)
 create mode 100644 arch/arm/include/asm/arch-sunxi/clock_sun9i.h

diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h
index ea268b1..3e5d999 100644
--- a/arch/arm/include/asm/arch-sunxi/clock.h
+++ b/arch/arm/include/asm/arch-sunxi/clock.h
@@ -17,6 +17,8 @@
 /* clock control module regs definition */
 #if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
 #include <asm/arch/clock_sun6i.h>
+#elif defined(CONFIG_MACH_SUN9I)
+#include <asm/arch/clock_sun9i.h>
 #else
 #include <asm/arch/clock_sun4i.h>
 #endif
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
new file mode 100644
index 0000000..c506b0a
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h
@@ -0,0 +1,139 @@
+/*
+ * sun9i clock register definitions
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _SUNXI_CLOCK_SUN9I_H
+#define _SUNXI_CLOCK_SUN9I_H
+
+struct sunxi_ccm_reg {
+	u32 pll1_c0_cfg;	/* 0x00 c0cpu# pll configuration */
+	u32 pll2_c1_cfg;	/* 0x04 c1cpu# pll configuration */
+	u32 pll3_audio_cfg;	/* 0x08 audio pll configuration */
+	u32 pll4_periph0_cfg;	/* 0x0c peripheral0 pll configuration */
+	u32 pll5_ve_cfg;	/* 0x10 videoengine pll configuration */
+	u32 pll6_ddr_cfg;	/* 0x14 ddr pll configuration */
+	u32 pll7_video0_cfg;	/* 0x18 video0 pll configuration */
+	u32 pll8_video1_cfg;	/* 0x1c video1 pll configuration */
+	u32 pll9_gpu_cfg;	/* 0x20 gpu pll configuration */
+	u32 pll10_de_cfg;	/* 0x24 displayengine pll configuration */
+	u32 pll11_isp_cfg;	/* 0x28 isp pll6 ontrol */
+	u32 pll12_periph1_cfg;	/* 0x2c peripheral1 pll configuration */
+	u8 reserved1[0x20];	/* 0x30 */
+	u32 cpu_clk_source;	/* 0x50 cpu clk source configuration */
+	u32 c0_cfg;		/* 0x54 cpu cluster 0 clock configuration */
+	u32 c1_cfg;		/* 0x58 cpu cluster 1 clock configuration */
+	u32 gtbus_cfg;		/* 0x5c gtbus clock configuration */
+	u32 ahb0_cfg;		/* 0x60 ahb0 clock configuration */
+	u32 ahb1_cfg;		/* 0x64 ahb1 clock configuration */
+	u32 ahb2_cfg;		/* 0x68 ahb2 clock configuration */
+	u8 reserved2[0x04];	/* 0x6c */
+	u32 apb0_cfg;		/* 0x70 apb0 clock configuration */
+	u32 apb1_cfg;		/* 0x74 apb1 clock configuration */
+	u32 cci400_cfg;		/* 0x78 cci400 clock configuration */
+	u8 reserved3[0x04];	/* 0x7c */
+	u32 ats_cfg;		/* 0x80 ats clock configuration */
+	u32 trace_cfg;		/* 0x84 trace clock configuration */
+	u8 reserved4[0xf8];	/* 0x88 */
+	u32 clk_output_a;	/* 0x180 clk_output_a */
+	u32 clk_output_b;	/* 0x184 clk_output_a */
+	u8 reserved5[0x278];	/* 0x188 */
+
+	u32 nand0_clk_cfg0;	/* 0x400 nand0 clock configuration0 */
+	u32 nand0_clk_cfg1;	/* 0x404 nand1 clock configuration */
+	u8 reserved6[0x08];	/* 0x408 */
+	u32 sd0_clk_cfg;	/* 0x410 sd0 clock configuration */
+	u32 sd1_clk_cfg;	/* 0x414 sd1 clock configuration */
+	u32 sd2_clk_cfg;	/* 0x418 sd2 clock configuration */
+	u32 sd3_clk_cfg;	/* 0x41c sd3 clock configuration */
+	u8 reserved7[0x08];	/* 0x420 */
+	u32 ts_clk_cfg;		/* 0x428 transport stream clock cfg */
+	u32 ss_clk_cfg;		/* 0x42c security system clock cfg */
+	u32 spi0_clk_cfg;	/* 0x430 spi0 clock configuration */
+	u32 spi1_clk_cfg;	/* 0x434 spi1 clock configuration */
+	u32 spi2_clk_cfg;	/* 0x438 spi2 clock configuration */
+	u32 spi3_clk_cfg;	/* 0x43c spi3 clock configuration */
+	u8 reserved8[0x50];	/* 0x440 */
+	u32 de_clk_cfg;		/* 0x490 display engine clock configuration */
+	u8 reserved9[0x04];	/* 0x494 */
+	u32 mp_clk_cfg;		/* 0x498 mp clock configuration */
+	u32 lcd0_clk_cfg;	/* 0x49c LCD0 module clock */
+	u32 lcd1_clk_cfg;	/* 0x4a0 LCD1 module clock */
+	u8 reserved10[0x1c];	/* 0x4a4 */
+	u32 csi_isp_clk_cfg;	/* 0x4c0 CSI ISP module clock */
+	u32 csi0_clk_cfg;	/* 0x4c4 CSI0 module clock */
+	u32 csi1_clk_cfg;	/* 0x4c8 CSI1 module clock */
+	u32 fd_clk_cfg;		/* 0x4cc FD module clock */
+	u32 ve_clk_cfg;		/* 0x4d0 VE module clock */
+	u32 avs_clk_cfg;	/* 0x4d4 AVS module clock */
+	u8 reserved11[0x18];	/* 0x4d8 */
+	u32 gpu_core_clk_cfg;	/* 0x4f0 GPU core clock config */
+	u32 gpu_mem_clk_cfg;	/* 0x4f4 GPU memory clock config */
+	u32 gpu_axi_clk_cfg;	/* 0x4f8 GPU AXI clock config */
+	u8 reserved12[0x10];	/* 0x4fc */
+	u32 gp_adc_clk_cfg;	/* 0x50c General Purpose ADC clk config */
+	u8 reserved13[0x70];	/* 0x510 */
+
+	u32 ahb_gate0;		/* 0x580 AHB0 Gating Register */
+	u32 ahb_gate1;		/* 0x584 AHB1 Gating Register */
+	u32 ahb_gate2;		/* 0x588 AHB2 Gating Register */
+	u8 reserved14[0x04];	/* 0x58c */
+	u32 apb0_gate;		/* 0x590 APB0 Clock Gating Register */
+	u32 apb1_gate;		/* 0x594 APB1 Clock Gating Register */
+	u8 reserved15[0x08];	/* 0x598 */
+	u32 ahb_reset0_cfg;	/* 0x5a0 AHB0 Software Reset Register */
+	u32 ahb_reset1_cfg;	/* 0x5a4 AHB1 Software Reset Register */
+	u32 ahb_reset2_cfg;	/* 0x5a8 AHB2 Software Reset Register */
+	u8 reserved16[0x04];	/* 0x5ac */
+	u32 apb0_reset_cfg;	/* 0x5b0 Bus Software Reset Register 3 */
+	u32 apb1_reset_cfg;	/* 0x5b4 Bus Software Reset Register 4 */
+};
+
+/* pll4_periph0_cfg */
+#define PLL4_CFG_DEFAULT		0x90002800 /* 960 MHz */
+
+#define CCM_PLL4_CTRL_N_SHIFT		8
+#define CCM_PLL4_CTRL_N_MASK		(0xff << CCM_PLL4_CTRL_N_SHIFT)
+#define CCM_PLL4_CTRL_P_SHIFT		16
+#define CCM_PLL4_CTRL_P_MASK		(0x1 << CCM_PLL4_CTRL_P_SHIFT)
+#define CCM_PLL4_CTRL_M_SHIFT		18
+#define CCM_PLL4_CTRL_M_MASK		(0x1 << CCM_PLL4_CTRL_M_SHIFT)
+
+/* sd#_clk_cfg fields */
+#define CCM_MMC_CTRL_M(x)		((x) - 1)
+#define CCM_MMC_CTRL_OCLK_DLY(x)	((x) << 8)
+#define CCM_MMC_CTRL_N(x)		((x) << 16)
+#define CCM_MMC_CTRL_SCLK_DLY(x)	((x) << 20)
+#define CCM_MMC_CTRL_OSCM24		(0 << 24)
+#define CCM_MMC_CTRL_PLL_PERIPH0	(1 << 24)
+#define CCM_MMC_CTRL_ENABLE		(1 << 31)
+
+/* ahb_gate0 fields */
+/* On sun9i all sdc-s share their ahb gate, so ignore (x) */
+#define AHB_GATE_OFFSET_MMC(x)		8
+
+/* apb1_gate fields */
+#define APB1_GATE_UART_SHIFT		16
+#define APB1_GATE_UART_MASK		(0xff << APB1_GATE_UART_SHIFT)
+#define APB1_GATE_TWI_SHIFT		0
+#define APB1_GATE_TWI_MASK		(0xf << APB1_GATE_TWI_SHIFT)
+
+/* ahb_reset0_cfg fields */
+/* On sun9i all sdc-s share their ahb reset, so ignore (x) */
+#define AHB_RESET_OFFSET_MMC(x)		8
+
+/* apb1_reset_cfg fields */
+#define APB1_RESET_UART_SHIFT		16
+#define APB1_RESET_UART_MASK		(0xff << APB1_RESET_UART_SHIFT)
+#define APB1_RESET_TWI_SHIFT		0
+#define APB1_RESET_TWI_MASK		(0xf << APB1_RESET_TWI_SHIFT)
+
+
+#ifndef __ASSEMBLY__
+unsigned int clock_get_pll4_periph0(void);
+#endif
+
+#endif /* _SUNXI_CLOCK_SUN9I_H */
-- 
2.1.0

[U-Boot] [PATCH 08/12] sun9i: Add sun9i (A80) clock setup support

[Hans de Goede]

Add initial sun9i (A80) clock setup support, enough to get the uart + mmc
going.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/cpu/armv7/sunxi/Makefile      |  1 +
 arch/arm/cpu/armv7/sunxi/clock_sun9i.c | 68 ++++++++++++++++++++++++++++++++++
 2 files changed, 69 insertions(+)
 create mode 100644 arch/arm/cpu/armv7/sunxi/clock_sun9i.c

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 3a6aa6d..27264f5 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_MACH_SUN5I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)	+= clock_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)	+= clock_sun4i.o
 obj-$(CONFIG_MACH_SUN8I)	+= clock_sun6i.o
+obj-$(CONFIG_MACH_SUN9I)	+= clock_sun9i.o
 
 ifndef CONFIG_SPL_BUILD
 ifdef CONFIG_ARMV7_PSCI
diff --git a/arch/arm/cpu/armv7/sunxi/clock_sun9i.c b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
new file mode 100644
index 0000000..27179ba
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/clock_sun9i.c
@@ -0,0 +1,68 @@
+/*
+ * sun9i specific clock code
+ *
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/prcm.h>
+#include <asm/arch/sys_proto.h>
+
+void clock_init_uart(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	/* open the clock for uart */
+	setbits_le32(&ccm->apb1_gate,
+		     CLK_GATE_OPEN << (APB1_GATE_UART_SHIFT +
+				       CONFIG_CONS_INDEX - 1));
+	/* deassert uart reset */
+	setbits_le32(&ccm->apb1_reset_cfg,
+		     1 << (APB1_RESET_UART_SHIFT +
+			   CONFIG_CONS_INDEX - 1));
+
+	/* Dup with clock_init_safe(), drop once sun9i SPL support lands */
+	writel(PLL4_CFG_DEFAULT, &ccm->pll4_periph0_cfg);
+}
+
+int clock_twi_onoff(int port, int state)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+	if (port > 4)
+		return -1;
+
+	/* set the apb reset and clock gate for twi */
+	if (state) {
+		setbits_le32(&ccm->apb1_gate,
+			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
+		setbits_le32(&ccm->apb1_reset_cfg,
+			     1 << (APB1_RESET_UART_SHIFT + port));
+	} else {
+		clrbits_le32(&ccm->apb1_reset_cfg,
+			     1 << (APB1_RESET_UART_SHIFT + port));
+		clrbits_le32(&ccm->apb1_gate,
+			     CLK_GATE_OPEN << (APB1_GATE_TWI_SHIFT + port));
+	}
+
+	return 0;
+}
+
+unsigned int clock_get_pll4_periph0(void)
+{
+	struct sunxi_ccm_reg *const ccm =
+		(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+	uint32_t rval = readl(&ccm->pll4_periph0_cfg);
+	int n = ((rval & CCM_PLL4_CTRL_N_MASK) >> CCM_PLL4_CTRL_N_SHIFT);
+	int p = ((rval & CCM_PLL4_CTRL_P_MASK) >> CCM_PLL4_CTRL_P_SHIFT);
+	int m = ((rval & CCM_PLL4_CTRL_M_MASK) >> CCM_PLL4_CTRL_M_SHIFT) + 1;
+	const int k = 1;
+
+	return ((24000000 * n * k) >> p) / m;
+}
-- 
2.1.0

[U-Boot] [PATCH 09/12] sunxi: mmc: Use a realistic timeout when sending a mmc command

[Hans de Goede]

Wait 1 second for the sdcard to respond, rather then waiting for
0xfffff milliseconds.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 drivers/mmc/sunxi_mmc.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 6234981..ee8ad5c 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -355,7 +355,8 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
 		}
 	}
 
-	error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
+	timeout_msecs = 1000;
+	error = mmc_rint_wait(mmc, timeout_msecs, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
 	if (error)
 		goto out;
 
-- 
2.1.0

[U-Boot] [PATCH 10/12] sunxi: mmc: Add support for sun9i (A80)

[Hans de Goede]

The clocks on the A80 are hooked up slightly different, add support for this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/include/asm/arch-sunxi/mmc.h |  5 ++++-
 drivers/mmc/sunxi_mmc.c               | 14 ++++++++++++--
 2 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
index 537f145..0120045 100644
--- a/arch/arm/include/asm/arch-sunxi/mmc.h
+++ b/arch/arm/include/asm/arch-sunxi/mmc.h
@@ -43,7 +43,7 @@ struct sunxi_mmc {
 	u32 chda;		/* 0x90 */
 	u32 cbda;		/* 0x94 */
 	u32 res1[26];
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN9I)
 	u32 res2[64];
 #endif
 	u32 fifo;		/* 0x100 (0x200 on sun6i) FIFO access address */
@@ -123,5 +123,8 @@ struct sunxi_mmc {
 #define SUNXI_MMC_IDIE_TXIRQ		(0x1 << 0)
 #define SUNXI_MMC_IDIE_RXIRQ		(0x1 << 1)
 
+#define SUNXI_MMC_COMMON_CLK_GATE		(1 << 16)
+#define SUNXI_MMC_COMMON_RESET			(1 << 18)
+
 struct mmc *sunxi_mmc_init(int sdc_no);
 #endif /* _SUNXI_MMC_H */
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index ee8ad5c..d60bec7 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -89,8 +89,13 @@ static int mmc_set_mod_clk(struct sunxi_mmc_host *mmchost, unsigned int hz)
 		pll = CCM_MMC_CTRL_OSCM24;
 		pll_hz = 24000000;
 	} else {
+#ifdef CONFIG_MACH_SUN9I
+		pll = CCM_MMC_CTRL_PLL_PERIPH0;
+		pll_hz = clock_get_pll4_periph0();
+#else
 		pll = CCM_MMC_CTRL_PLL6;
 		pll_hz = clock_get_pll6();
+#endif
 	}
 
 	div = pll_hz / hz;
@@ -146,10 +151,15 @@ static int mmc_clk_io_on(int sdc_no)
 	/* config ahb clock */
 	setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no));
 
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN9I)
 	/* unassert reset */
 	setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MMC(sdc_no));
 #endif
+#if defined(CONFIG_MACH_SUN9I)
+	/* sun9i has a mmc-common module, also set the gate and reset there */
+	writel(SUNXI_MMC_COMMON_CLK_GATE | SUNXI_MMC_COMMON_RESET,
+	       SUNXI_MMC_COMMON_BASE + 4 * sdc_no);
+#endif
 
 	return mmc_set_mod_clk(mmchost, 24000000);
 }
@@ -440,7 +450,7 @@ struct mmc *sunxi_mmc_init(int sdc_no)
 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
 	cfg->host_caps = MMC_MODE_4BIT;
 	cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
-#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN9I)
 	cfg->host_caps |= MMC_MODE_HC;
 #endif
 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
-- 
2.1.0

[U-Boot] [PATCH 11/12] sun9i: Basic sun9i (A80) support

[Hans de Goede]

Add initial sun9i (A80) support, only uart + mmc are supported for now.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 arch/arm/cpu/armv7/sunxi/Makefile        |  2 ++
 arch/arm/cpu/armv7/sunxi/board.c         |  4 ++++
 arch/arm/cpu/armv7/sunxi/cpu_info.c      |  5 +++++
 arch/arm/cpu/armv7/sunxi/lowlevel_init.S | 12 +++++++++++-
 arch/arm/include/asm/arch-sunxi/gpio.h   |  3 +++
 board/sunxi/Kconfig                      |  5 +++++
 include/configs/sun9i.h                  | 23 +++++++++++++++++++++++
 7 files changed, 53 insertions(+), 1 deletion(-)
 create mode 100644 include/configs/sun9i.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
index 27264f5..6602cda 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -13,7 +13,9 @@ obj-y	+= board.o
 obj-y	+= clock.o
 obj-y	+= cpu_info.o
 obj-y	+= pinmux.o
+ifndef CONFIG_MACH_SUN9I
 obj-y	+= usbc.o
+endif
 obj-$(CONFIG_MACH_SUN6I)	+= prcm.o
 obj-$(CONFIG_MACH_SUN8I)	+= prcm.o
 obj-$(CONFIG_MACH_SUN6I)	+= p2wi.o
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 4449942..0108a14 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -71,6 +71,10 @@ int gpio_init(void)
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH20_UART0_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH21_UART0_RX);
 	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH12_UART0_TX);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH13_UART0_RX);
+	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
 #elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART1_TX);
 	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART1_RX);
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index b6cb9de..09ea7f2 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -11,6 +11,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/clock.h>
 #include <axp221.h>
+#include <errno.h>
 
 #ifdef CONFIG_MACH_SUN6I
 int sunxi_get_ss_bonding_id(void)
@@ -66,6 +67,8 @@ int print_cpuinfo(void)
 	puts("CPU:   Allwinner A20 (SUN7I)\n");
 #elif defined CONFIG_MACH_SUN8I
 	puts("CPU:   Allwinner A23 (SUN8I)\n");
+#elif defined CONFIG_MACH_SUN9I
+	puts("CPU:   Allwinner A80 (SUN9I)\n");
 #else
 #warning Please update cpu_info.c with correct CPU information
 	puts("CPU:   SUNXI Family\n");
@@ -82,6 +85,8 @@ int sunxi_get_sid(unsigned int *sid)
 #else
 	return -ENODEV;
 #endif
+#elif defined CONFIG_MACH_SUN9I
+	return -ENODEV; /* Not supported yet */
 #else
 	int i;
 
diff --git a/arch/arm/cpu/armv7/sunxi/lowlevel_init.S b/arch/arm/cpu/armv7/sunxi/lowlevel_init.S
index b80b3eb..8a069f7 100644
--- a/arch/arm/cpu/armv7/sunxi/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/sunxi/lowlevel_init.S
@@ -14,10 +14,20 @@
  */
 ENTRY(save_boot_params)
 #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN7I || \
-    defined CONFIG_MACH_SUN8I
+    defined CONFIG_MACH_SUN8I || defined CONFIG_MACH_SUN9I
 	mrc	p15, 0, r0, c1, c0, 1
 	orr	r0, r0, #(1<<6)
 	mcr	p15, 0, r0, c1, c0, 1
 #endif
+#if defined CONFIG_MACH_SUN9I
+	/*
+	 * Dark magic poke of some register in the SYS_CTRL region.
+	 * Allwinners own u-boot does this and without this u-boot causes a
+	 * CPU / system reset as soon as it loads.
+	 */
+	ldr	r0, =0x008000e0
+	ldr	r1, =0x16aa0001
+	str	r1, [r0]
+#endif
 	bx	lr
 ENDPROC(save_boot_params)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 71cc879..3db7fd3 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -174,6 +174,9 @@ enum sunxi_gpio_number {
 
 #define SUN4I_GPH22_SDC1	5
 
+#define SUN9I_GPH12_UART0_TX	2
+#define SUN9I_GPH13_UART0_RX	2
+
 #define SUN6I_GPH20_UART0_TX	2
 #define SUN6I_GPH21_UART0_RX	2
 
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index 847a86f..e65b8af 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -31,6 +31,10 @@ config MACH_SUN8I
 	select CPU_V7
 	select SUPPORT_SPL
 
+config MACH_SUN9I
+	bool "sun9i (Allwinner A80)"
+	select CPU_V7
+
 endchoice
 
 if MACH_SUN6I || MACH_SUN8I
@@ -56,6 +60,7 @@ config SYS_CONFIG_NAME
 	default "sun6i" if MACH_SUN6I
 	default "sun7i" if MACH_SUN7I
 	default "sun8i" if MACH_SUN8I
+	default "sun9i" if MACH_SUN9I
 
 choice
 	prompt "Board"
diff --git a/include/configs/sun9i.h b/include/configs/sun9i.h
new file mode 100644
index 0000000..3fcf477
--- /dev/null
+++ b/include/configs/sun9i.h
@@ -0,0 +1,23 @@
+/*
+ * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * Configuration settings for the Allwinner A80 (sun9i) CPU
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * A80 specific configuration
+ */
+
+#define CONFIG_SYS_PROMPT	"sun9i# "
+
+/*
+ * Include common sunxi configuration where most the settings are
+ */
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
-- 
2.1.0

[U-Boot] [PATCH 12/12] sun9i: Add Merrii_A80_Optimus board / defconfig file

[Hans de Goede]

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
---
 configs/Merrii_A80_Optimus_defconfig | 6 ++++++
 1 file changed, 6 insertions(+)
 create mode 100644 configs/Merrii_A80_Optimus_defconfig

diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
new file mode 100644
index 0000000..5329f8a
--- /dev/null
+++ b/configs/Merrii_A80_Optimus_defconfig
@@ -0,0 +1,6 @@
+CONFIG_FDTFILE="sun9i-a80-optimus.dtb"
+CONFIG_VIDEO=n
+CONFIG_USB_KEYBOARD=n
++S:CONFIG_ARM=y
++S:CONFIG_ARCH_SUNXI=y
++S:CONFIG_MACH_SUN9I=y
-- 
2.1.0

[U-Boot] [PATCH 01/12] sunxi: Drop pll6 setting from clock_init_uart

[Ian Campbell]

On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> As the comment says now that we have SPL support this is no longer necessary,
> as PLL6 is already setup with the exact same parameters by the SPL.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH 02/12] sunxi: Rename cpu.h to cpu_sun4i.h

[Ian Campbell]

On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> sun4i - sun8i have (aprox.) the same iomem layout, but sun9i is quite
> different, so add a wrapper cpu.h which includes the right mach specific
> cpu_sun#i.h based on mach, like we already do with clock.h and dram.h .
> 
> Note for reviewers, cpu.h is effectively renamed tp cpu_sun4i.h by this
> commit, the only change is the #ifndef ... #endif guard around the file.

Using -M with git formate-patch/send-email really helps with this sort
of thing (I've no idea why it's not the default...)

> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH 03/12] sunxi: Move clock_get_pllX / clock_set_pllX protos to mach specific headers

[Ian Campbell]

On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> Which pll-s are available depends on the machine type, move the
> clock_get_pllX / clock_set_pllX prototypes to the clock_sun?i.h header files
> so that we only declare what is actually available. e.g. clock_get_pll5p()
> is not available on sun6i / sun8i, and with sun9i we get a completely
> different set of plls.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH 04/12] sunxi: Update sunxi-common.h to deal with different DRAM base addr on sun9i

[Ian Campbell]

On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> The DRAM Base differs between sun9i and the others and we cannot use
> math in various places like the environment setting and linker scripts,
> so "simply" define everything which contains the SDRAM_BASE twice.

Is it really not possible to use maths in linker scripts? How have I
never noticed that...

Anyway, given that things only differ in the most significant nibble of
the RAM base address I think something like this might work:

/* NB: find out if one of these is already available somewhere */
#define __stringify(x) #x 
#define stringify(x) __stringify(x)

#define SDRAM_OFFSET(x) 0x2##x /* or 0x4 */
#define CONFIG_SYS_SDRAM_BASE SDRAM_OFFSET(0000000)

#define MEM_LAYOUT_ENV_SETTINGS \
	"kernel_addr_r=" stringify(SDRAM_OFFSET(200000)) "\0"
        ...

Ian.

[U-Boot] [PATCH 05/12] sunxi: Move setting of CPU system control register SMP bit to save_boot_params

[Ian Campbell]

On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> According to the "Cortex-A7 MPCore Technical Reference Manual":
> 
> "You must ensure this bit is set to 1 before the caches and MMU are enabled,
> or any cache and TLB maintenance operations are performed."

Given that this is a feature of the Cortex-A7 (actually, I believe it
applies to at least Cortex-A15 too) and not really specific to sunxi,
perhaps we can make this more generic?

> Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations,
> we should thus enable the SMP bit earlier, and the only chance to do that is
> to do it at save_boot_params time.

Would it be so terrible to add an ifdef CORTEX_A7 here, or to call out
to (or call as a macro) a soc_init_cp15?

I'm cc-ing Albert for input these questions.

FWIW I notice there is some OMAP specific code right before the "bl
cpu_init_cp15", although that looks like an even more special case, so
perhaps not really precedent.

> This does not seem to make any noticable difference, but:

"noticeable"

> 1) According to the manual it is the right thing to do
> 2) We need to do other magic really early on for sun9i (A80) support, so we
>    need to introduce a lowlevel_init.S / save_boot_params function anyways
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
>  arch/arm/cpu/armv7/sunxi/Makefile        |  1 +
>  arch/arm/cpu/armv7/sunxi/board.c         |  8 --------
>  arch/arm/cpu/armv7/sunxi/lowlevel_init.S | 23 +++++++++++++++++++++++
>  3 files changed, 24 insertions(+), 8 deletions(-)
>  create mode 100644 arch/arm/cpu/armv7/sunxi/lowlevel_init.S
> 
> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
> index 1720f7d..3a6aa6d 100644
> --- a/arch/arm/cpu/armv7/sunxi/Makefile
> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
> @@ -7,6 +7,7 @@
>  #
>  # SPDX-License-Identifier:	GPL-2.0+
>  #
> +obj-y	+= lowlevel_init.o
>  obj-y	+= timer.o
>  obj-y	+= board.o
>  obj-y	+= clock.o
> diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
> index bc98c56..4449942 100644
> --- a/arch/arm/cpu/armv7/sunxi/board.c
> +++ b/arch/arm/cpu/armv7/sunxi/board.c
> @@ -120,14 +120,6 @@ void s_init(void)
>  	 * access gets messed up (seems cache related) */
>  	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
>  #endif
> -#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
> -		defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
> -	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
> -	asm volatile(
> -		"mrc p15, 0, r0, c1, c0, 1\n"
> -		"orr r0, r0, #1 << 6\n"
> -		"mcr p15, 0, r0, c1, c0, 1\n");
> -#endif
>  
>  	clock_init();
>  	timer_init();
> diff --git a/arch/arm/cpu/armv7/sunxi/lowlevel_init.S b/arch/arm/cpu/armv7/sunxi/lowlevel_init.S
> new file mode 100644
> index 0000000..b80b3eb
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/sunxi/lowlevel_init.S
> @@ -0,0 +1,23 @@
> +/*
> + * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0+
> + */
> +
> +#include <config.h>
> +#include <version.h>
> +#include <linux/linkage.h>
> +
> +/*
> + * On sunxi we need to do some setup *before* cpu_init_cp15 from start.S
> + * runs, we (ab)use save_boot_params for this.
> + */
> +ENTRY(save_boot_params)
> +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN7I || \
> +    defined CONFIG_MACH_SUN8I
> +	mrc	p15, 0, r0, c1, c0, 1
> +	orr	r0, r0, #(1<<6)
> +	mcr	p15, 0, r0, c1, c0, 1
> +#endif
> +	bx	lr
> +ENDPROC(save_boot_params)

[U-Boot] [PATCH 06/12] sun9i: Add cpu_sun9i.h with iomem defines

[Ian Campbell]

On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> Add a headerfile with all the base addresses from the sun9i blocks.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH 07/12] sun9i: Add clock_sun9i.h with ccu register layout for sun9i

[Ian Campbell]

On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> Add a headerfile with the sun9i ccu register layout.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH 08/12] sun9i: Add sun9i (A80) clock setup support

[Ian Campbell]

On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> Add initial sun9i (A80) clock setup support, enough to get the uart + mmc
> going.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

[U-Boot] [PATCH 09/12] sunxi: mmc: Use a realistic timeout when sending a mmc command

[Ian Campbell]

On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> Wait 1 second for the sdcard to respond, rather then waiting for
> 0xfffff milliseconds.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

(needn't wait for the rest of the series I think)

> ---
>  drivers/mmc/sunxi_mmc.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index 6234981..ee8ad5c 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -355,7 +355,8 @@ static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
>  		}
>  	}
>  
> -	error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
> +	timeout_msecs = 1000;

Not strictly necessary to go via the variable, but not harmful either.

> +	error = mmc_rint_wait(mmc, timeout_msecs, SUNXI_MMC_RINT_COMMAND_DONE, "cmd");
>  	if (error)
>  		goto out;
>  

[U-Boot] [PATCH 10/12] sunxi: mmc: Add support for sun9i (A80)

[Ian Campbell]

On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> The clocks on the A80 are hooked up slightly different, add support for this.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

Couple of minor comments:

> ---
>  arch/arm/include/asm/arch-sunxi/mmc.h |  5 ++++-
>  drivers/mmc/sunxi_mmc.c               | 14 ++++++++++++--
>  2 files changed, 16 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
> index 537f145..0120045 100644
> --- a/arch/arm/include/asm/arch-sunxi/mmc.h
> +++ b/arch/arm/include/asm/arch-sunxi/mmc.h
> @@ -43,7 +43,7 @@ struct sunxi_mmc {
>  	u32 chda;		/* 0x90 */
>  	u32 cbda;		/* 0x94 */
>  	u32 res1[26];
> -#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
> +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN9I)
>  	u32 res2[64];
>  #endif
>  	u32 fifo;		/* 0x100 (0x200 on sun6i) FIFO access address */

This comment is now two generations behind.

[...]

> -#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I)
> +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN9I)

Can you wrap this a bit please (and perhaps run checkpatch.pl in case
there are more which my eye wasn't drawn too).

Ian.

[U-Boot] [PATCH 11/12] sun9i: Basic sun9i (A80) support

[Ian Campbell]

On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> Add initial sun9i (A80) support, only uart + mmc are supported for now.
> 
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

Acked-by: Ian Campbell <ijc@hellion.org.uk>

> +#define CONFIG_SYS_PROMPT	"sun9i# "

Should we make all these say "sunxi# " in the common header instead (the
precise SoC is printed in the banner anyhow), or derive from
CONFIG_SYS_CONFIG_NAME?

Ian.

[U-Boot] [PATCH 12/12] sun9i: Add Merrii_A80_Optimus board / defconfig file

[Ian Campbell]

On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> ---
>  configs/Merrii_A80_Optimus_defconfig | 6 ++++++

Needs a MAINTAINERS update, otherwise:
        Acked-by: Ian Campbell <ijc@hellion.org.uk>
        
>  1 file changed, 6 insertions(+)
>  create mode 100644 configs/Merrii_A80_Optimus_defconfig
> 
> diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig
> new file mode 100644
> index 0000000..5329f8a
> --- /dev/null
> +++ b/configs/Merrii_A80_Optimus_defconfig
> @@ -0,0 +1,6 @@
> +CONFIG_FDTFILE="sun9i-a80-optimus.dtb"
> +CONFIG_VIDEO=n
> +CONFIG_USB_KEYBOARD=n
> ++S:CONFIG_ARM=y
> ++S:CONFIG_ARCH_SUNXI=y
> ++S:CONFIG_MACH_SUN9I=y

[U-Boot] [PATCH 04/12] sunxi: Update sunxi-common.h to deal with different DRAM base addr on sun9i

[Hans de Goede]

Hi,

On 17-01-15 23:44, Ian Campbell wrote:
> On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
>> The DRAM Base differs between sun9i and the others and we cannot use
>> math in various places like the environment setting and linker scripts,
>> so "simply" define everything which contains the SDRAM_BASE twice.
>
> Is it really not possible to use maths in linker scripts? How have I
> never noticed that...

I'm not 100% sure on that, I'm sure that it is not possible in the
environment stuff, so I thought lets play it safe and just write it
out fully for everything. I will drop the unconfirmed linker script
reference from the commit message for v2

>
> Anyway, given that things only differ in the most significant nibble of
> the RAM base address I think something like this might work:
>
> /* NB: find out if one of these is already available somewhere */
> #define __stringify(x) #x
> #define stringify(x) __stringify(x)
>
> #define SDRAM_OFFSET(x) 0x2##x /* or 0x4 */
> #define CONFIG_SYS_SDRAM_BASE SDRAM_OFFSET(0000000)
>
> #define MEM_LAYOUT_ENV_SETTINGS \
> 	"kernel_addr_r=" stringify(SDRAM_OFFSET(200000)) "\0"
>          ...

Yeah I think that will work. I'll do that for v2 (it may take a few
days before I get around to doing / posting a v2).

Regards,

Hans

[U-Boot] [PATCH 05/12] sunxi: Move setting of CPU system control register SMP bit to save_boot_params

[Hans de Goede]

Hi,

On 17-01-15 23:51, Ian Campbell wrote:
> On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
>> According to the "Cortex-A7 MPCore Technical Reference Manual":
>>
>> "You must ensure this bit is set to 1 before the caches and MMU are enabled,
>> or any cache and TLB maintenance operations are performed."
>
> Given that this is a feature of the Cortex-A7 (actually, I believe it
> applies to at least Cortex-A15 too) and not really specific to sunxi,
> perhaps we can make this more generic?

Strange enough the bit is different between the A7 and A15, for the A7 the docs
say it must be set before doing anything with caches, on the A15 it only needs
to be set for the core to accept cache management operations from other cpu
cores (or so the docs say), which is likely why it is not in the standard
init sequence yet, as for u-boot it seems to only be necessary to do this on
a Cortex A7. I agree that it would be good to move this to the generic start.S
though, Albert ?


>
>> Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations,
>> we should thus enable the SMP bit earlier, and the only chance to do that is
>> to do it at save_boot_params time.
>
> Would it be so terrible to add an ifdef CORTEX_A7 here, or to call out
> to (or call as a macro) a soc_init_cp15?

 From my pov no that would not be too terrible, but ...
>
> I'm cc-ing Albert for input these questions.

That indeed is Albert's call.

Note that solving this still leaves the A80 magic sram controller poke which
also needs to happen really really early or otherwise the entire SoC just
resets as if the watchdog has triggered, I'm fine with using save_boot_params
for that, it is not its intended purpose, but it works fine for it, so
I see no reason to complicate things with yet another callback.


> FWIW I notice there is some OMAP specific code right before the "bl
> cpu_init_cp15", although that looks like an even more special case, so
> perhaps not really precedent.
>
>> This does not seem to make any noticable difference, but:
>
> "noticeable"
>
>> 1) According to the manual it is the right thing to do
>> 2) We need to do other magic really early on for sun9i (A80) support, so we
>>     need to introduce a lowlevel_init.S / save_boot_params function anyways
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>>   arch/arm/cpu/armv7/sunxi/Makefile        |  1 +
>>   arch/arm/cpu/armv7/sunxi/board.c         |  8 --------
>>   arch/arm/cpu/armv7/sunxi/lowlevel_init.S | 23 +++++++++++++++++++++++
>>   3 files changed, 24 insertions(+), 8 deletions(-)
>>   create mode 100644 arch/arm/cpu/armv7/sunxi/lowlevel_init.S
>>
>> diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile
>> index 1720f7d..3a6aa6d 100644
>> --- a/arch/arm/cpu/armv7/sunxi/Makefile
>> +++ b/arch/arm/cpu/armv7/sunxi/Makefile
>> @@ -7,6 +7,7 @@
>>   #
>>   # SPDX-License-Identifier:	GPL-2.0+
>>   #
>> +obj-y	+= lowlevel_init.o
>>   obj-y	+= timer.o
>>   obj-y	+= board.o
>>   obj-y	+= clock.o
>> diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
>> index bc98c56..4449942 100644
>> --- a/arch/arm/cpu/armv7/sunxi/board.c
>> +++ b/arch/arm/cpu/armv7/sunxi/board.c
>> @@ -120,14 +120,6 @@ void s_init(void)
>>   	 * access gets messed up (seems cache related) */
>>   	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
>>   #endif
>> -#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
>> -		defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
>> -	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
>> -	asm volatile(
>> -		"mrc p15, 0, r0, c1, c0, 1\n"
>> -		"orr r0, r0, #1 << 6\n"
>> -		"mcr p15, 0, r0, c1, c0, 1\n");
>> -#endif
>>
>>   	clock_init();
>>   	timer_init();
>> diff --git a/arch/arm/cpu/armv7/sunxi/lowlevel_init.S b/arch/arm/cpu/armv7/sunxi/lowlevel_init.S
>> new file mode 100644
>> index 0000000..b80b3eb
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv7/sunxi/lowlevel_init.S
>> @@ -0,0 +1,23 @@
>> +/*
>> + * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
>> + *
>> + * SPDX-License-Identifier:	GPL-2.0+
>> + */
>> +
>> +#include <config.h>
>> +#include <version.h>
>> +#include <linux/linkage.h>
>> +
>> +/*
>> + * On sunxi we need to do some setup *before* cpu_init_cp15 from start.S
>> + * runs, we (ab)use save_boot_params for this.
>> + */
>> +ENTRY(save_boot_params)
>> +#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN7I || \
>> +    defined CONFIG_MACH_SUN8I
>> +	mrc	p15, 0, r0, c1, c0, 1
>> +	orr	r0, r0, #(1<<6)
>> +	mcr	p15, 0, r0, c1, c0, 1
>> +#endif
>> +	bx	lr
>> +ENDPROC(save_boot_params)
>
>

Regards,

Hans

[U-Boot] [PATCH 10/12] sunxi: mmc: Add support for sun9i (A80)

[Hans de Goede]

Hi,

On 17-01-15 23:56, Ian Campbell wrote:
> On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
>> The clocks on the A80 are hooked up slightly different, add support for this.
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>
> Acked-by: Ian Campbell <ijc@hellion.org.uk>
>
> Couple of minor comments:
>
>> ---
>>   arch/arm/include/asm/arch-sunxi/mmc.h |  5 ++++-
>>   drivers/mmc/sunxi_mmc.c               | 14 ++++++++++++--
>>   2 files changed, 16 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h
>> index 537f145..0120045 100644
>> --- a/arch/arm/include/asm/arch-sunxi/mmc.h
>> +++ b/arch/arm/include/asm/arch-sunxi/mmc.h
>> @@ -43,7 +43,7 @@ struct sunxi_mmc {
>>   	u32 chda;		/* 0x90 */
>>   	u32 cbda;		/* 0x94 */
>>   	u32 res1[26];
>> -#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
>> +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN9I)
>>   	u32 res2[64];
>>   #endif
>>   	u32 fifo;		/* 0x100 (0x200 on sun6i) FIFO access address */
>
> This comment is now two generations behind.

Fixed.

>
> [...]
>
>> -#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I)
>> +#if defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN7I) || defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN9I)
>
> Can you wrap this a bit please (and perhaps run checkpatch.pl in case
> there are more which my eye wasn't drawn too).

I'm about to push a whole bunch of patches to u-boot-sunxi/next, and I've run all of them
through checkpatch, and fixed all errors and the warnings where relevant.

Regards,

Hans

[U-Boot] [PATCH 11/12] sun9i: Basic sun9i (A80) support

[Hans de Goede]

Hi,

On 17-01-15 23:59, Ian Campbell wrote:
> On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
>> Add initial sun9i (A80) support, only uart + mmc are supported for now.
>>
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>
> Acked-by: Ian Campbell <ijc@hellion.org.uk>
>
>> +#define CONFIG_SYS_PROMPT	"sun9i# "
>
> Should we make all these say "sunxi# " in the common header instead (the
> precise SoC is printed in the banner anyhow),

Yeah that sounds like a good idea, care to submit a patch for that ?

Regards,

Hans

[U-Boot] [PATCH 05/12] sunxi: Move setting of CPU system control register SMP bit to save_boot_params

[Albert ARIBAUD]

Hello Hans,

On Mon, 19 Jan 2015 20:04:58 +0100, Hans de Goede <hdegoede@redhat.com>
wrote:
> Hi,
> 
> On 17-01-15 23:51, Ian Campbell wrote:
> > On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> >> According to the "Cortex-A7 MPCore Technical Reference Manual":
> >>
> >> "You must ensure this bit is set to 1 before the caches and MMU are enabled,
> >> or any cache and TLB maintenance operations are performed."
> >
> > Given that this is a feature of the Cortex-A7 (actually, I believe it
> > applies to at least Cortex-A15 too) and not really specific to sunxi,
> > perhaps we can make this more generic?
> 
> Strange enough the bit is different between the A7 and A15, for the A7 the docs
> say it must be set before doing anything with caches, on the A15 it only needs
> to be set for the core to accept cache management operations from other cpu
> cores (or so the docs say), which is likely why it is not in the standard
> init sequence yet, as for u-boot it seems to only be necessary to do this on
> a Cortex A7. I agree that it would be good to move this to the generic start.S
> though, Albert ?

[...]

> >> Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations,
> >> we should thus enable the SMP bit earlier, and the only chance to do that is
> >> to do it at save_boot_params time.
> >
> > Would it be so terrible to add an ifdef CORTEX_A7 here, or to call out
> > to (or call as a macro) a soc_init_cp15?
> 
>  From my pov no that would not be too terrible, but ...
> >
> > I'm cc-ing Albert for input these questions.
> 
> That indeed is Albert's call.

Will look into this today.

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 11/12] sun9i: Basic sun9i (A80) support

[Ian Campbell]

On Mon, 2015-01-19 at 20:44 +0100, Hans de Goede wrote:
> Hi,
> 
> On 17-01-15 23:59, Ian Campbell wrote:
> > On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> >> Add initial sun9i (A80) support, only uart + mmc are supported for now.
> >>
> >> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
> >
> > Acked-by: Ian Campbell <ijc@hellion.org.uk>
> >
> >> +#define CONFIG_SYS_PROMPT	"sun9i# "
> >
> > Should we make all these say "sunxi# " in the common header instead (the
> > precise SoC is printed in the banner anyhow),
> 
> Yeah that sounds like a good idea, care to submit a patch for that ?

Yep, will do once this one hits #next so I don't need to rebase etc.

> 
> Regards,
> 
> Hans
> 

[U-Boot] [PATCH 05/12] sunxi: Move setting of CPU system control register SMP bit to save_boot_params

[Ian Campbell]

On Mon, 2015-01-19 at 20:04 +0100, Hans de Goede wrote:
> Hi,
> 
> On 17-01-15 23:51, Ian Campbell wrote:
> > On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> >> According to the "Cortex-A7 MPCore Technical Reference Manual":
> >>
> >> "You must ensure this bit is set to 1 before the caches and MMU are enabled,
> >> or any cache and TLB maintenance operations are performed."
> >
> > Given that this is a feature of the Cortex-A7 (actually, I believe it
> > applies to at least Cortex-A15 too) and not really specific to sunxi,
> > perhaps we can make this more generic?
> 
> Strange enough the bit is different between the A7 and A15, for the A7 the docs
> say it must be set before doing anything with caches, on the A15 it only needs
> to be set for the core to accept cache management operations from other cpu
> cores (or so the docs say), which is likely why it is not in the standard
> init sequence yet, as for u-boot it seems to only be necessary to do this on
> a Cortex A7. I agree that it would be good to move this to the generic start.S
> though, Albert ?
> 
> 
> >
> >> Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations,
> >> we should thus enable the SMP bit earlier, and the only chance to do that is
> >> to do it at save_boot_params time.
> >
> > Would it be so terrible to add an ifdef CORTEX_A7 here, or to call out
> > to (or call as a macro) a soc_init_cp15?
> 
>  From my pov no that would not be too terrible, but ...
> >
> > I'm cc-ing Albert for input these questions.
> 
> That indeed is Albert's call.
> 
> Note that solving this still leaves the A80 magic sram controller poke which
> also needs to happen really really early or otherwise the entire SoC just
> resets as if the watchdog has triggered, I'm fine with using save_boot_params
> for that, it is not its intended purpose, but it works fine for it, so
> I see no reason to complicate things with yet another callback.

Ideally it would be possible to do it in the same hook as sets up the
ACTLR.SMP bit.

In general I'm not a big fan of reusing unrelated hooks just because
they happen to be in a convenient location -- it leads to surprises when
you are reading through/modifying the calling code.

Ian.

[U-Boot] [PATCH 05/12] sunxi: Move setting of CPU system control register SMP bit to save_boot_params

[Albert ARIBAUD]

Hello Hans,

On Mon, 19 Jan 2015 20:04:58 +0100, Hans de Goede <hdegoede@redhat.com>
wrote:
> Hi,
> 
> On 17-01-15 23:51, Ian Campbell wrote:
> > On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
> >> According to the "Cortex-A7 MPCore Technical Reference Manual":
> >>
> >> "You must ensure this bit is set to 1 before the caches and MMU are enabled,
> >> or any cache and TLB maintenance operations are performed."
> >
> > Given that this is a feature of the Cortex-A7 (actually, I believe it
> > applies to at least Cortex-A15 too) and not really specific to sunxi,
> > perhaps we can make this more generic?
> 
> Strange enough the bit is different between the A7 and A15, for the A7 the docs
> say it must be set before doing anything with caches, on the A15 it only needs
> to be set for the core to accept cache management operations from other cpu
> cores (or so the docs say), which is likely why it is not in the standard
> init sequence yet, as for u-boot it seems to only be necessary to do this on
> a Cortex A7. I agree that it would be good to move this to the generic start.S
> though, Albert ?

[...]

> >> Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations,
> >> we should thus enable the SMP bit earlier, and the only chance to do that is
> >> to do it at save_boot_params time.
> >
> > Would it be so terrible to add an ifdef CORTEX_A7 here, or to call out
> > to (or call as a macro) a soc_init_cp15?
> 
>  From my pov no that would not be too terrible, but ...
> >
> > I'm cc-ing Albert for input these questions.
> 
> That indeed is Albert's call.

I don't like the idea of #ifdef'ing that much.

OTOH, if we do introduce soc_init_cp15, then we end up with two CP15
init functions, soc_init_cp15 and cpu_init_cp15, with all sorts of
questions on which should be called first and whether one could break
the other's work, and what happens in-between, etc.

Either way, setting CP15 registers is something that all ARM CPUs, and
SoCs require, not just armv7. It's just that other start.S files touch
cp15 directly.

I'm leaning toward grouping all CP15 inits (including cache(s)
and TLB disabling and maybe VBAR setting) in a single CP15 call to
a single soc_init_cp15 function.

Now, SoCs with the same CPU will have a common CP15 init part, and
that part could go into a <cpu>_init_cp15 function which soc_init_cp15
would call. Of course, since we're doing this way before we have any
stack, we will have to handle nested calls by saving and restoring LR
in intermediate function contexts.

> Note that solving this still leaves the A80 magic sram controller poke which
> also needs to happen really really early or otherwise the entire SoC just
> resets as if the watchdog has triggered, I'm fine with using save_boot_params
> for that, it is not its intended purpose, but it works fine for it, so
> I see no reason to complicate things with yet another callback.

Maybe we could turn soc_init_cp15 into a more general soc_init function
which would do whatever is needed, on cp15 or otherwise.

(I see there is one soc_init defined, for spear600, but it is actually
empty and could/should be removed. Patch anyone?)

> Regards,
> 
> Hans

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 05/12] sunxi: Move setting of CPU system control register SMP bit to save_boot_params

[Hans de Goede]

Hi,

On 20-01-15 11:22, Albert ARIBAUD wrote:
> Hello Hans,
>
> On Mon, 19 Jan 2015 20:04:58 +0100, Hans de Goede <hdegoede@redhat.com>
> wrote:
>> Hi,
>>
>> On 17-01-15 23:51, Ian Campbell wrote:
>>> On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
>>>> According to the "Cortex-A7 MPCore Technical Reference Manual":
>>>>
>>>> "You must ensure this bit is set to 1 before the caches and MMU are enabled,
>>>> or any cache and TLB maintenance operations are performed."
>>>
>>> Given that this is a feature of the Cortex-A7 (actually, I believe it
>>> applies to at least Cortex-A15 too) and not really specific to sunxi,
>>> perhaps we can make this more generic?
>>
>> Strange enough the bit is different between the A7 and A15, for the A7 the docs
>> say it must be set before doing anything with caches, on the A15 it only needs
>> to be set for the core to accept cache management operations from other cpu
>> cores (or so the docs say), which is likely why it is not in the standard
>> init sequence yet, as for u-boot it seems to only be necessary to do this on
>> a Cortex A7. I agree that it would be good to move this to the generic start.S
>> though, Albert ?
>
> [...]
>
>>>> Since arch/arm/cpu/armv7/start.S: cpu_init_cp15 does several cache operations,
>>>> we should thus enable the SMP bit earlier, and the only chance to do that is
>>>> to do it at save_boot_params time.
>>>
>>> Would it be so terrible to add an ifdef CORTEX_A7 here, or to call out
>>> to (or call as a macro) a soc_init_cp15?
>>
>>   From my pov no that would not be too terrible, but ...
>>>
>>> I'm cc-ing Albert for input these questions.
>>
>> That indeed is Albert's call.
>
> I don't like the idea of #ifdef'ing that much.
>
> OTOH, if we do introduce soc_init_cp15, then we end up with two CP15
> init functions, soc_init_cp15 and cpu_init_cp15, with all sorts of
> questions on which should be called first and whether one could break
> the other's work, and what happens in-between, etc.
>
> Either way, setting CP15 registers is something that all ARM CPUs, and
> SoCs require, not just armv7. It's just that other start.S files touch
> cp15 directly.
>
> I'm leaning toward grouping all CP15 inits (including cache(s)
> and TLB disabling and maybe VBAR setting) in a single CP15 call to
> a single soc_init_cp15 function.
>
> Now, SoCs with the same CPU will have a common CP15 init part, and
> that part could go into a <cpu>_init_cp15 function which soc_init_cp15
> would call. Of course, since we're doing this way before we have any
> stack, we will have to handle nested calls by saving and restoring LR
> in intermediate function contexts.
>
>> Note that solving this still leaves the A80 magic sram controller poke which
>> also needs to happen really really early or otherwise the entire SoC just
>> resets as if the watchdog has triggered, I'm fine with using save_boot_params
>> for that, it is not its intended purpose, but it works fine for it, so
>> I see no reason to complicate things with yet another callback.
>
> Maybe we could turn soc_init_cp15 into a more general soc_init function
> which would do whatever is needed, on cp15 or otherwise.
>
> (I see there is one soc_init defined, for spear600, but it is actually
> empty and could/should be removed. Patch anyone?)

Hmm, so if I'm reading the above correctly, then I think you want to do
the following:

1) Rename cpu_init_cp15 to cpu_init_cp15_common
2) Add a new soc_init function, with a weak default which just calls
    cpu_init_cp15_common
3) Add a a7_init_cp15 which sets the smp bit
4) Have Cortex A7 SoCs override soc_init with one which first calls
    a7_init_cp15 and then calls cpu_init_cp15_common
5) And on SoC's which need to do something special before or after
    cp15 init, they can do so by overriding soc_init and do what
    ever they need to do there before *or* after calling
    cpu_init_cp15_common

Have I got that right ?

If so I can try to write a patch-set for this, my arm asm is a bit
weak, but I should be able to cobble this together using existing code
as an example.

Regards,

Hans

[U-Boot] [PATCH 05/12] sunxi: Move setting of CPU system control register SMP bit to save_boot_params

[Albert ARIBAUD]

Hello Hans,

On Tue, 20 Jan 2015 15:32:34 +0100, Hans de Goede <hdegoede@redhat.com>
wrote:
> Hi,
> 
> On 20-01-15 11:22, Albert ARIBAUD wrote:
> > Hello Hans,
> >
> > I'm leaning toward grouping all CP15 inits (including cache(s)
> > and TLB disabling and maybe VBAR setting) in a single CP15 call to
> > a single soc_init_cp15 function.
> >
> > Now, SoCs with the same CPU will have a common CP15 init part, and
> > that part could go into a <cpu>_init_cp15 function which soc_init_cp15
> > would call. Of course, since we're doing this way before we have any
> > stack, we will have to handle nested calls by saving and restoring LR
> > in intermediate function contexts.
> >
> >> Note that solving this still leaves the A80 magic sram controller poke which
> >> also needs to happen really really early or otherwise the entire SoC just
> >> resets as if the watchdog has triggered, I'm fine with using save_boot_params
> >> for that, it is not its intended purpose, but it works fine for it, so
> >> I see no reason to complicate things with yet another callback.
> >
> > Maybe we could turn soc_init_cp15 into a more general soc_init function
> > which would do whatever is needed, on cp15 or otherwise.
> >
> > (I see there is one soc_init defined, for spear600, but it is actually
> > empty and could/should be removed. Patch anyone?)
> 
> Hmm, so if I'm reading the above correctly, then I think you want to do
> the following:
> 
> 1) Rename cpu_init_cp15 to cpu_init_cp15_common
> 2) Add a new soc_init function, with a weak default which just calls
>     cpu_init_cp15_common
> 3) Add a a7_init_cp15 which sets the smp bit
> 4) Have Cortex A7 SoCs override soc_init with one which first calls
>     a7_init_cp15 and then calls cpu_init_cp15_common
> 5) And on SoC's which need to do something special before or after
>     cp15 init, they can do so by overriding soc_init and do what
>     ever they need to do there before *or* after calling
>     cpu_init_cp15_common
> 
> Have I got that right ?

Almost entirely. My only comments are on 1) :

- cpu_init_cp15_common does not need the "common" suffix IMO; actually,
  it might be more general than just touching cp15, so we could just
  call it "cpu_init" (1).

- if two CPUs need different versions, then we will want to make
  cpu_init a weak function, with a default based on the 'common
  denominator'.

(1) Note that there is already a cpu_init() function in U-Boot, used by
SH and AVR32; if we want 'cpu_init' to be consistent across architectures,
we might have to change "{soc,cpu}_init" to somehting else (for instance
"{soc,cpu}_setup" or "{soc,cpu}_boot_init") but I don't like that much, or
investigate what the existing cpu_init() does and see if /that/ could be
renamed or merged into a common mechanism (I doubt that the second is
practically feasible).

> If so I can try to write a patch-set for this, my arm asm is a bit
> weak, but I should be able to cobble this together using existing code
> as an example.

Thanks!

> Regards,
> 
> Hans

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 04/12] sunxi: Update sunxi-common.h to deal with different DRAM base addr on sun9i

[Hans de Goede]

Hi Ian,

On 01/17/2015 11:44 PM, Ian Campbell wrote:
> On Thu, 2015-01-15 at 15:52 +0100, Hans de Goede wrote:
>> The DRAM Base differs between sun9i and the others and we cannot use
>> math in various places like the environment setting and linker scripts,
>> so "simply" define everything which contains the SDRAM_BASE twice.
>
> Is it really not possible to use maths in linker scripts? How have I
> never noticed that...
>
> Anyway, given that things only differ in the most significant nibble of
> the RAM base address I think something like this might work:
>
> /* NB: find out if one of these is already available somewhere */
> #define __stringify(x) #x
> #define stringify(x) __stringify(x)
>
> #define SDRAM_OFFSET(x) 0x2##x /* or 0x4 */
> #define CONFIG_SYS_SDRAM_BASE SDRAM_OFFSET(0000000)
>
> #define MEM_LAYOUT_ENV_SETTINGS \
> 	"kernel_addr_r=" stringify(SDRAM_OFFSET(200000)) "\0"
>          ...

I've finally brushed of these patches and I'm working on cleaning them
up now.

Unfortunately a lot of the CONFIG_xxx variables with dram base
address derived values get exported through cpp -E -dM which does
not do macro expansion, and then used in Makefiles to pass to the
linker and such. So I've been unable to get big of the
#ifdef ... #else ... #endif block setting various defines for this.

I've been able to make the environment block use the trick you
suggested, so this does give a nice cleanup.

Regards,

Hans