[PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[Peter Griffin]

Hi folks,

A V2 of this old series incorporating Arnd and Lees Feedback form v1.

Following on from Arnds comments about the picophy driver here
https://lkml.org/lkml/2014/11/13/161, this series fixes the
remaining upstreamed drivers for STI, which are mixing address spaces
in the reg property. We do this in a way similar to the keystone
and bcm7445 platforms, by having sysconfig phandle/ offset pair 
(where only one register is required). Or phandle / integer array
where multiple offsets in the same bank are needed).

This series breaks DT compatability! But the platform support
is WIP and only being used by the few developers who are upstreaming
support for it. I've made each change to the driver / dt doc / dt
file as a single atomic commit so the kernel will remain bisectable. 

This series then also enables the picophy driver, and adds back in
the ehci/ohci dt nodes for stih410 which make use of the picophy.

regards,

Peter.

Changes since v1:
- Add missing space after */ (Lee)
- Change comment to "indexed from" rather than "not indexed from" (Lee)
- Change naming to phy1, phy2 rather than phy@1 phy@2 if there is no reg property (Arnd / Grant)
- Rebased on v3.19-rc3 (me)
- Checkpatch "no space before tabs" warning in stih41*.dtsi (me)

Peter Griffin (7):
  phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg
    property.
  phy: miphy365x: Pass sysconfig register offsets via syscfg dt
    property.
  ARM: STi: DT: STiH407: Add usb2 picophy dt nodes
  ARM: STi: DT: STiH410: Add usb2 picophy dt nodes
  ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb
    controllers.
  ARM: multi_v7_defconfig: Enable stih407 usb picophy
  stmmac: dwmac-sti: Pass sysconfig register offset via syscon dt
    property.

 .../devicetree/bindings/net/sti-dwmac.txt          | 14 ++---
 .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 ++---
 .../devicetree/bindings/phy/phy-stih407-usb.txt    | 10 +---
 arch/arm/boot/dts/stih407-family.dtsi              |  9 +++
 arch/arm/boot/dts/stih410.dtsi                     | 70 ++++++++++++++++++++++
 arch/arm/boot/dts/stih415.dtsi                     | 12 ++--
 arch/arm/boot/dts/stih416.dtsi                     | 22 +++----
 arch/arm/configs/multi_v7_defconfig                |  1 +
 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c    | 13 ++--
 drivers/phy/phy-miphy365x.c                        | 29 ++++-----
 drivers/phy/phy-stih407-usb.c                      | 25 ++++----
 11 files changed, 143 insertions(+), 77 deletions(-)

-- 
1.9.1

[PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[Peter Griffin]

Hi folks,

A V2 of this old series incorporating Arnd and Lees Feedback form v1.

Following on from Arnds comments about the picophy driver here
https://lkml.org/lkml/2014/11/13/161, this series fixes the
remaining upstreamed drivers for STI, which are mixing address spaces
in the reg property. We do this in a way similar to the keystone
and bcm7445 platforms, by having sysconfig phandle/ offset pair 
(where only one register is required). Or phandle / integer array
where multiple offsets in the same bank are needed).

This series breaks DT compatability! But the platform support
is WIP and only being used by the few developers who are upstreaming
support for it. I've made each change to the driver / dt doc / dt
file as a single atomic commit so the kernel will remain bisectable. 

This series then also enables the picophy driver, and adds back in
the ehci/ohci dt nodes for stih410 which make use of the picophy.

regards,

Peter.

Changes since v1:
- Add missing space after */ (Lee)
- Change comment to "indexed from" rather than "not indexed from" (Lee)
- Change naming to phy1, phy2 rather than phy@1 phy@2 if there is no reg property (Arnd / Grant)
- Rebased on v3.19-rc3 (me)
- Checkpatch "no space before tabs" warning in stih41*.dtsi (me)

Peter Griffin (7):
  phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg
    property.
  phy: miphy365x: Pass sysconfig register offsets via syscfg dt
    property.
  ARM: STi: DT: STiH407: Add usb2 picophy dt nodes
  ARM: STi: DT: STiH410: Add usb2 picophy dt nodes
  ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb
    controllers.
  ARM: multi_v7_defconfig: Enable stih407 usb picophy
  stmmac: dwmac-sti: Pass sysconfig register offset via syscon dt
    property.

 .../devicetree/bindings/net/sti-dwmac.txt          | 14 ++---
 .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 ++---
 .../devicetree/bindings/phy/phy-stih407-usb.txt    | 10 +---
 arch/arm/boot/dts/stih407-family.dtsi              |  9 +++
 arch/arm/boot/dts/stih410.dtsi                     | 70 ++++++++++++++++++++++
 arch/arm/boot/dts/stih415.dtsi                     | 12 ++--
 arch/arm/boot/dts/stih416.dtsi                     | 22 +++----
 arch/arm/configs/multi_v7_defconfig                |  1 +
 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c    | 13 ++--
 drivers/phy/phy-miphy365x.c                        | 29 ++++-----
 drivers/phy/phy-stih407-usb.c                      | 25 ++++----
 11 files changed, 143 insertions(+), 77 deletions(-)

-- 
1.9.1

--
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[PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[Peter Griffin]

Hi folks,

A V2 of this old series incorporating Arnd and Lees Feedback form v1.

Following on from Arnds comments about the picophy driver here
https://lkml.org/lkml/2014/11/13/161, this series fixes the
remaining upstreamed drivers for STI, which are mixing address spaces
in the reg property. We do this in a way similar to the keystone
and bcm7445 platforms, by having sysconfig phandle/ offset pair 
(where only one register is required). Or phandle / integer array
where multiple offsets in the same bank are needed).

This series breaks DT compatability! But the platform support
is WIP and only being used by the few developers who are upstreaming
support for it. I've made each change to the driver / dt doc / dt
file as a single atomic commit so the kernel will remain bisectable. 

This series then also enables the picophy driver, and adds back in
the ehci/ohci dt nodes for stih410 which make use of the picophy.

regards,

Peter.

Changes since v1:
- Add missing space after */ (Lee)
- Change comment to "indexed from" rather than "not indexed from" (Lee)
- Change naming to phy1, phy2 rather than phy at 1 phy at 2 if there is no reg property (Arnd / Grant)
- Rebased on v3.19-rc3 (me)
- Checkpatch "no space before tabs" warning in stih41*.dtsi (me)

Peter Griffin (7):
  phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg
    property.
  phy: miphy365x: Pass sysconfig register offsets via syscfg dt
    property.
  ARM: STi: DT: STiH407: Add usb2 picophy dt nodes
  ARM: STi: DT: STiH410: Add usb2 picophy dt nodes
  ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb
    controllers.
  ARM: multi_v7_defconfig: Enable stih407 usb picophy
  stmmac: dwmac-sti: Pass sysconfig register offset via syscon dt
    property.

 .../devicetree/bindings/net/sti-dwmac.txt          | 14 ++---
 .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 ++---
 .../devicetree/bindings/phy/phy-stih407-usb.txt    | 10 +---
 arch/arm/boot/dts/stih407-family.dtsi              |  9 +++
 arch/arm/boot/dts/stih410.dtsi                     | 70 ++++++++++++++++++++++
 arch/arm/boot/dts/stih415.dtsi                     | 12 ++--
 arch/arm/boot/dts/stih416.dtsi                     | 22 +++----
 arch/arm/configs/multi_v7_defconfig                |  1 +
 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c    | 13 ++--
 drivers/phy/phy-miphy365x.c                        | 29 ++++-----
 drivers/phy/phy-stih407-usb.c                      | 25 ++++----
 11 files changed, 143 insertions(+), 77 deletions(-)

-- 
1.9.1

[PATCH v2 1/7] phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg property.

[Peter Griffin]

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the phy driver to not use the reg property to access the sysconfig
register offsets.

This is because other phy's (miphy28, miphy365) have a combination of
memory mapped registers and sysconfig control regs, and we shouldn't
be mixing address spaces in the reg property. In addition we would
ideally like the sysconfig offsets to be passed via DT in a uniform way.

This new method will also allow us to support devices which have sysconfig
registers in different banks more easily and it is also analagous to how
keystone and bcm7745 platforms pass there syscon offsets in DT.

This breaks DT compatibility, but this platform is considered WIP, and
is only used by a few developers who are upstreaming support for it.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 .../devicetree/bindings/phy/phy-stih407-usb.txt    | 10 ++-------
 drivers/phy/phy-stih407-usb.c                      | 25 ++++++++++++----------
 2 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
index 1ef8228..de6a706 100644
--- a/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
+++ b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
@@ -5,10 +5,7 @@ host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC fa
 
 Required properties:
 - compatible		: should be "st,stih407-usb2-phy"
-- reg			: contain the offset and length of the system configuration registers
-			  used as glue logic to control & parameter phy
-- reg-names		: the names of the system configuration registers in "reg", should be "param" and "reg"
-- st,syscfg		: sysconfig register to manage phy parameter at driver level
+- st,syscfg		: phandle of sysconfig bank plus integer array containing phyparam and phyctrl register offsets
 - resets		: list of phandle and reset specifier pairs. There should be two entries, one
 			  for the whole phy and one for the port
 - reset-names		: list of reset signal names. Should be "global" and "port"
@@ -19,11 +16,8 @@ Example:
 
 usb2_picophy0: usbpicophy@f8 {
 	compatible	= "st,stih407-usb2-phy";
-	reg		= <0xf8 0x04>,	/* syscfg 5062 */
-			  <0xf4 0x04>;	/* syscfg 5061 */
-	reg-names	= "param", "ctrl";
 	#phy-cells	= <0>;
-	st,syscfg	= <&syscfg_core>;
+	st,syscfg	= <&syscfg_core 0x100 0xf4>;
 	resets		= <&softreset STIH407_PICOPHY_SOFTRESET>,
 			  <&picophyreset STIH407_PICOPHY0_RESET>;
 	reset-names	= "global", "port";
diff --git a/drivers/phy/phy-stih407-usb.c b/drivers/phy/phy-stih407-usb.c
index 74f0fab..1d5ae5f 100644
--- a/drivers/phy/phy-stih407-usb.c
+++ b/drivers/phy/phy-stih407-usb.c
@@ -22,6 +22,9 @@
 #include <linux/mfd/syscon.h>
 #include <linux/phy/phy.h>
 
+#define PHYPARAM_REG	1
+#define PHYCTRL_REG	2
+
 /* Default PHY_SEL and REFCLKSEL configuration */
 #define STIH407_USB_PICOPHY_CTRL_PORT_CONF	0x6
 #define STIH407_USB_PICOPHY_CTRL_PORT_MASK	0x1f
@@ -93,7 +96,7 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev)
 	struct device_node *np = dev->of_node;
 	struct phy_provider *phy_provider;
 	struct phy *phy;
-	struct resource *res;
+	int ret;
 
 	phy_dev = devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL);
 	if (!phy_dev)
@@ -123,19 +126,19 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev)
 		return PTR_ERR(phy_dev->regmap);
 	}
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
-	if (!res) {
-		dev_err(dev, "No ctrl reg found\n");
-		return -ENXIO;
+	ret = of_property_read_u32_index(np, "st,syscfg", PHYPARAM_REG,
+					&phy_dev->param);
+	if (ret) {
+		dev_err(dev, "can't get phyparam offset (%d)\n", ret);
+		return ret;
 	}
-	phy_dev->ctrl = res->start;
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "param");
-	if (!res) {
-		dev_err(dev, "No param reg found\n");
-		return -ENXIO;
+	ret = of_property_read_u32_index(np, "st,syscfg", PHYCTRL_REG,
+					&phy_dev->ctrl);
+	if (ret) {
+		dev_err(dev, "can't get phyctrl offset (%d)\n", ret);
+		return ret;
 	}
-	phy_dev->param = res->start;
 
 	phy = devm_phy_create(dev, NULL, &stih407_usb2_picophy_data);
 	if (IS_ERR(phy)) {
-- 
1.9.1

[PATCH v2 1/7] phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg property.

[Peter Griffin]

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the phy driver to not use the reg property to access the sysconfig
register offsets.

This is because other phy's (miphy28, miphy365) have a combination of
memory mapped registers and sysconfig control regs, and we shouldn't
be mixing address spaces in the reg property. In addition we would
ideally like the sysconfig offsets to be passed via DT in a uniform way.

This new method will also allow us to support devices which have sysconfig
registers in different banks more easily and it is also analagous to how
keystone and bcm7745 platforms pass there syscon offsets in DT.

This breaks DT compatibility, but this platform is considered WIP, and
is only used by a few developers who are upstreaming support for it.

Signed-off-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Reviewed-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
---
 .../devicetree/bindings/phy/phy-stih407-usb.txt    | 10 ++-------
 drivers/phy/phy-stih407-usb.c                      | 25 ++++++++++++----------
 2 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
index 1ef8228..de6a706 100644
--- a/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
+++ b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
@@ -5,10 +5,7 @@ host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC fa
 
 Required properties:
 - compatible		: should be "st,stih407-usb2-phy"
-- reg			: contain the offset and length of the system configuration registers
-			  used as glue logic to control & parameter phy
-- reg-names		: the names of the system configuration registers in "reg", should be "param" and "reg"
-- st,syscfg		: sysconfig register to manage phy parameter at driver level
+- st,syscfg		: phandle of sysconfig bank plus integer array containing phyparam and phyctrl register offsets
 - resets		: list of phandle and reset specifier pairs. There should be two entries, one
 			  for the whole phy and one for the port
 - reset-names		: list of reset signal names. Should be "global" and "port"
@@ -19,11 +16,8 @@ Example:
 
 usb2_picophy0: usbpicophy@f8 {
 	compatible	= "st,stih407-usb2-phy";
-	reg		= <0xf8 0x04>,	/* syscfg 5062 */
-			  <0xf4 0x04>;	/* syscfg 5061 */
-	reg-names	= "param", "ctrl";
 	#phy-cells	= <0>;
-	st,syscfg	= <&syscfg_core>;
+	st,syscfg	= <&syscfg_core 0x100 0xf4>;
 	resets		= <&softreset STIH407_PICOPHY_SOFTRESET>,
 			  <&picophyreset STIH407_PICOPHY0_RESET>;
 	reset-names	= "global", "port";
diff --git a/drivers/phy/phy-stih407-usb.c b/drivers/phy/phy-stih407-usb.c
index 74f0fab..1d5ae5f 100644
--- a/drivers/phy/phy-stih407-usb.c
+++ b/drivers/phy/phy-stih407-usb.c
@@ -22,6 +22,9 @@
 #include <linux/mfd/syscon.h>
 #include <linux/phy/phy.h>
 
+#define PHYPARAM_REG	1
+#define PHYCTRL_REG	2
+
 /* Default PHY_SEL and REFCLKSEL configuration */
 #define STIH407_USB_PICOPHY_CTRL_PORT_CONF	0x6
 #define STIH407_USB_PICOPHY_CTRL_PORT_MASK	0x1f
@@ -93,7 +96,7 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev)
 	struct device_node *np = dev->of_node;
 	struct phy_provider *phy_provider;
 	struct phy *phy;
-	struct resource *res;
+	int ret;
 
 	phy_dev = devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL);
 	if (!phy_dev)
@@ -123,19 +126,19 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev)
 		return PTR_ERR(phy_dev->regmap);
 	}
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
-	if (!res) {
-		dev_err(dev, "No ctrl reg found\n");
-		return -ENXIO;
+	ret = of_property_read_u32_index(np, "st,syscfg", PHYPARAM_REG,
+					&phy_dev->param);
+	if (ret) {
+		dev_err(dev, "can't get phyparam offset (%d)\n", ret);
+		return ret;
 	}
-	phy_dev->ctrl = res->start;
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "param");
-	if (!res) {
-		dev_err(dev, "No param reg found\n");
-		return -ENXIO;
+	ret = of_property_read_u32_index(np, "st,syscfg", PHYCTRL_REG,
+					&phy_dev->ctrl);
+	if (ret) {
+		dev_err(dev, "can't get phyctrl offset (%d)\n", ret);
+		return ret;
 	}
-	phy_dev->param = res->start;
 
 	phy = devm_phy_create(dev, NULL, &stih407_usb2_picophy_data);
 	if (IS_ERR(phy)) {
-- 
1.9.1

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[PATCH v2 1/7] phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg property.

[Peter Griffin]

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the phy driver to not use the reg property to access the sysconfig
register offsets.

This is because other phy's (miphy28, miphy365) have a combination of
memory mapped registers and sysconfig control regs, and we shouldn't
be mixing address spaces in the reg property. In addition we would
ideally like the sysconfig offsets to be passed via DT in a uniform way.

This new method will also allow us to support devices which have sysconfig
registers in different banks more easily and it is also analagous to how
keystone and bcm7745 platforms pass there syscon offsets in DT.

This breaks DT compatibility, but this platform is considered WIP, and
is only used by a few developers who are upstreaming support for it.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 .../devicetree/bindings/phy/phy-stih407-usb.txt    | 10 ++-------
 drivers/phy/phy-stih407-usb.c                      | 25 ++++++++++++----------
 2 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
index 1ef8228..de6a706 100644
--- a/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
+++ b/Documentation/devicetree/bindings/phy/phy-stih407-usb.txt
@@ -5,10 +5,7 @@ host controllers (when controlling usb2/1.1 devices) available on STiH407 SoC fa
 
 Required properties:
 - compatible		: should be "st,stih407-usb2-phy"
-- reg			: contain the offset and length of the system configuration registers
-			  used as glue logic to control & parameter phy
-- reg-names		: the names of the system configuration registers in "reg", should be "param" and "reg"
-- st,syscfg		: sysconfig register to manage phy parameter at driver level
+- st,syscfg		: phandle of sysconfig bank plus integer array containing phyparam and phyctrl register offsets
 - resets		: list of phandle and reset specifier pairs. There should be two entries, one
 			  for the whole phy and one for the port
 - reset-names		: list of reset signal names. Should be "global" and "port"
@@ -19,11 +16,8 @@ Example:
 
 usb2_picophy0: usbpicophy at f8 {
 	compatible	= "st,stih407-usb2-phy";
-	reg		= <0xf8 0x04>,	/* syscfg 5062 */
-			  <0xf4 0x04>;	/* syscfg 5061 */
-	reg-names	= "param", "ctrl";
 	#phy-cells	= <0>;
-	st,syscfg	= <&syscfg_core>;
+	st,syscfg	= <&syscfg_core 0x100 0xf4>;
 	resets		= <&softreset STIH407_PICOPHY_SOFTRESET>,
 			  <&picophyreset STIH407_PICOPHY0_RESET>;
 	reset-names	= "global", "port";
diff --git a/drivers/phy/phy-stih407-usb.c b/drivers/phy/phy-stih407-usb.c
index 74f0fab..1d5ae5f 100644
--- a/drivers/phy/phy-stih407-usb.c
+++ b/drivers/phy/phy-stih407-usb.c
@@ -22,6 +22,9 @@
 #include <linux/mfd/syscon.h>
 #include <linux/phy/phy.h>
 
+#define PHYPARAM_REG	1
+#define PHYCTRL_REG	2
+
 /* Default PHY_SEL and REFCLKSEL configuration */
 #define STIH407_USB_PICOPHY_CTRL_PORT_CONF	0x6
 #define STIH407_USB_PICOPHY_CTRL_PORT_MASK	0x1f
@@ -93,7 +96,7 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev)
 	struct device_node *np = dev->of_node;
 	struct phy_provider *phy_provider;
 	struct phy *phy;
-	struct resource *res;
+	int ret;
 
 	phy_dev = devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL);
 	if (!phy_dev)
@@ -123,19 +126,19 @@ static int stih407_usb2_picophy_probe(struct platform_device *pdev)
 		return PTR_ERR(phy_dev->regmap);
 	}
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
-	if (!res) {
-		dev_err(dev, "No ctrl reg found\n");
-		return -ENXIO;
+	ret = of_property_read_u32_index(np, "st,syscfg", PHYPARAM_REG,
+					&phy_dev->param);
+	if (ret) {
+		dev_err(dev, "can't get phyparam offset (%d)\n", ret);
+		return ret;
 	}
-	phy_dev->ctrl = res->start;
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "param");
-	if (!res) {
-		dev_err(dev, "No param reg found\n");
-		return -ENXIO;
+	ret = of_property_read_u32_index(np, "st,syscfg", PHYCTRL_REG,
+					&phy_dev->ctrl);
+	if (ret) {
+		dev_err(dev, "can't get phyctrl offset (%d)\n", ret);
+		return ret;
 	}
-	phy_dev->param = res->start;
 
 	phy = devm_phy_create(dev, NULL, &stih407_usb2_picophy_data);
 	if (IS_ERR(phy)) {
-- 
1.9.1

[PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Peter Griffin]

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the miphy365 phy driver to access sysconfig register offsets via
syscfg dt property.

This is because the reg property should not be mixing address spaces
like it does currently for miphy365. This change then also aligns us
to how other platforms such as keystone and bcm7445 pass there syscon
offsets via DT.

This patch breaks DT compatibility, but this platform is considered WIP,
and is only used by a few developers who are upstreaming support for it.
This change has been done as a single atomic commit to ensure it is
bisectable.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
 arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
 drivers/phy/phy-miphy365x.c                        | 29 ++++++++--------------
 3 files changed, 23 insertions(+), 31 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
index 42c8808..9802d5d 100644
--- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
+++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
@@ -6,8 +6,10 @@ for SATA and PCIe.
 
 Required properties (controller (parent) node):
 - compatible    : Should be "st,miphy365x-phy"
-- st,syscfg     : Should be a phandle of the system configuration register group
-		  which contain the SATA, PCIe mode setting bits
+- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
+		  containing the miphy registers and integer array should contain
+		  an entry for each port sub-node, specifying the control
+		  register offset inside the sysconfig group.
 
 Required nodes	:  A sub-node is required for each channel the controller
 		   provides. Address range information including the usual
@@ -26,7 +28,6 @@ Required properties (port (child) node):
 		  registers filled in "reg":
 			- sata:   For SATA devices
 			- pcie:   For PCIe devices
-			- syscfg: To specify the syscfg based config register
 
 Optional properties (port (child) node):
 - st,sata-gen	     :	Generation of locally attached SATA IP. Expected values
@@ -39,20 +40,20 @@ Example:
 
 	miphy365x_phy: miphy365x@fe382000 {
 		compatible      = "st,miphy365x-phy";
-		st,syscfg  	= <&syscfg_rear>;
+		st,syscfg  	= <&syscfg_rear 0x824 0x828>;
 		#address-cells	= <1>;
 		#size-cells	= <1>;
 		ranges;
 
 		phy_port0: port@fe382000 {
-			reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
-			reg-names = "sata", "pcie", "syscfg";
+			reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
+			reg-names = "sata", "pcie";
 			#phy-cells = <1>;
 			st,sata-gen = <3>;
 		};
 
 		phy_port1: port@fe38a000 {
-			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
+			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
 			reg-names = "sata", "pcie", "syscfg";
 			#phy-cells = <1>;
 			st,pcie-tx-pol-inv;
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index fad9073..85afe01 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -283,21 +283,21 @@
 
 		miphy365x_phy: phy@fe382000 {
 			compatible      = "st,miphy365x-phy";
-			st,syscfg  	= <&syscfg_rear>;
+			st,syscfg	= <&syscfg_rear 0x824 0x828>;
 			#address-cells	= <1>;
 			#size-cells	= <1>;
 			ranges;
 
 			phy_port0: port@fe382000 {
 				#phy-cells = <1>;
-				reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
-				reg-names = "sata", "pcie", "syscfg";
+				reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
+				reg-names = "sata", "pcie";
 			};
 
 			phy_port1: port@fe38a000 {
 				#phy-cells = <1>;
-				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
-				reg-names = "sata", "pcie", "syscfg";
+				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
+				reg-names = "sata", "pcie";
 			};
 		};
 
diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
index 6ab43a8..6c80154 100644
--- a/drivers/phy/phy-miphy365x.c
+++ b/drivers/phy/phy-miphy365x.c
@@ -141,7 +141,7 @@ struct miphy365x_phy {
 	bool pcie_tx_pol_inv;
 	bool sata_tx_pol_inv;
 	u32 sata_gen;
-	u64 ctrlreg;
+	u32 ctrlreg;
 	u8 type;
 };
 
@@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
 	bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
 
 	return regmap_update_bits(miphy_dev->regmap,
-				  (unsigned int)miphy_phy->ctrlreg,
+				  miphy_phy->ctrlreg,
 				  SYSCFG_SELECT_SATA_MASK,
 				  sata << SYSCFG_SELECT_SATA_POS);
 }
@@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
 {
 	struct device_node *phynode = miphy_phy->phy->dev.of_node;
 	const char *name;
-	const __be32 *taddr;
 	int type = miphy_phy->type;
 	int ret;
 
@@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
 		return ret;
 	}
 
-	if (!strncmp(name, "syscfg", 6)) {
-		taddr = of_get_address(phynode, index, NULL, NULL);
-		if (!taddr) {
-			dev_err(dev, "failed to fetch syscfg address\n");
-			return -EINVAL;
-		}
-
-		miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
-		if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
-			dev_err(dev, "failed to translate syscfg address\n");
-			return -EINVAL;
-		}
-
-		return 0;
-	}
-
 	if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
 	      (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
 		return 0;
@@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
 			return ret;
 
 		phy_set_drvdata(phy, miphy_dev->phys[port]);
+
 		port++;
+		/* sysconfig offsets are indexed from 1 */
+		ret = of_property_read_u32_index(np, "st,syscfg", port,
+					&miphy_phy->ctrlreg);
+		if (ret) {
+			dev_err(&pdev->dev, "No sysconfig offset found\n");
+			return ret;
+		}
 	}
 
 	provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
-- 
1.9.1

[PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Peter Griffin]

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the miphy365 phy driver to access sysconfig register offsets via
syscfg dt property.

This is because the reg property should not be mixing address spaces
like it does currently for miphy365. This change then also aligns us
to how other platforms such as keystone and bcm7445 pass there syscon
offsets via DT.

This patch breaks DT compatibility, but this platform is considered WIP,
and is only used by a few developers who are upstreaming support for it.
This change has been done as a single atomic commit to ensure it is
bisectable.

Signed-off-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Reviewed-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
---
 .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
 arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
 drivers/phy/phy-miphy365x.c                        | 29 ++++++++--------------
 3 files changed, 23 insertions(+), 31 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
index 42c8808..9802d5d 100644
--- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
+++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
@@ -6,8 +6,10 @@ for SATA and PCIe.
 
 Required properties (controller (parent) node):
 - compatible    : Should be "st,miphy365x-phy"
-- st,syscfg     : Should be a phandle of the system configuration register group
-		  which contain the SATA, PCIe mode setting bits
+- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
+		  containing the miphy registers and integer array should contain
+		  an entry for each port sub-node, specifying the control
+		  register offset inside the sysconfig group.
 
 Required nodes	:  A sub-node is required for each channel the controller
 		   provides. Address range information including the usual
@@ -26,7 +28,6 @@ Required properties (port (child) node):
 		  registers filled in "reg":
 			- sata:   For SATA devices
 			- pcie:   For PCIe devices
-			- syscfg: To specify the syscfg based config register
 
 Optional properties (port (child) node):
 - st,sata-gen	     :	Generation of locally attached SATA IP. Expected values
@@ -39,20 +40,20 @@ Example:
 
 	miphy365x_phy: miphy365x@fe382000 {
 		compatible      = "st,miphy365x-phy";
-		st,syscfg  	= <&syscfg_rear>;
+		st,syscfg  	= <&syscfg_rear 0x824 0x828>;
 		#address-cells	= <1>;
 		#size-cells	= <1>;
 		ranges;
 
 		phy_port0: port@fe382000 {
-			reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
-			reg-names = "sata", "pcie", "syscfg";
+			reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
+			reg-names = "sata", "pcie";
 			#phy-cells = <1>;
 			st,sata-gen = <3>;
 		};
 
 		phy_port1: port@fe38a000 {
-			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
+			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
 			reg-names = "sata", "pcie", "syscfg";
 			#phy-cells = <1>;
 			st,pcie-tx-pol-inv;
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index fad9073..85afe01 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -283,21 +283,21 @@
 
 		miphy365x_phy: phy@fe382000 {
 			compatible      = "st,miphy365x-phy";
-			st,syscfg  	= <&syscfg_rear>;
+			st,syscfg	= <&syscfg_rear 0x824 0x828>;
 			#address-cells	= <1>;
 			#size-cells	= <1>;
 			ranges;
 
 			phy_port0: port@fe382000 {
 				#phy-cells = <1>;
-				reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
-				reg-names = "sata", "pcie", "syscfg";
+				reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
+				reg-names = "sata", "pcie";
 			};
 
 			phy_port1: port@fe38a000 {
 				#phy-cells = <1>;
-				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
-				reg-names = "sata", "pcie", "syscfg";
+				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
+				reg-names = "sata", "pcie";
 			};
 		};
 
diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
index 6ab43a8..6c80154 100644
--- a/drivers/phy/phy-miphy365x.c
+++ b/drivers/phy/phy-miphy365x.c
@@ -141,7 +141,7 @@ struct miphy365x_phy {
 	bool pcie_tx_pol_inv;
 	bool sata_tx_pol_inv;
 	u32 sata_gen;
-	u64 ctrlreg;
+	u32 ctrlreg;
 	u8 type;
 };
 
@@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
 	bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
 
 	return regmap_update_bits(miphy_dev->regmap,
-				  (unsigned int)miphy_phy->ctrlreg,
+				  miphy_phy->ctrlreg,
 				  SYSCFG_SELECT_SATA_MASK,
 				  sata << SYSCFG_SELECT_SATA_POS);
 }
@@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
 {
 	struct device_node *phynode = miphy_phy->phy->dev.of_node;
 	const char *name;
-	const __be32 *taddr;
 	int type = miphy_phy->type;
 	int ret;
 
@@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
 		return ret;
 	}
 
-	if (!strncmp(name, "syscfg", 6)) {
-		taddr = of_get_address(phynode, index, NULL, NULL);
-		if (!taddr) {
-			dev_err(dev, "failed to fetch syscfg address\n");
-			return -EINVAL;
-		}
-
-		miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
-		if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
-			dev_err(dev, "failed to translate syscfg address\n");
-			return -EINVAL;
-		}
-
-		return 0;
-	}
-
 	if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
 	      (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
 		return 0;
@@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
 			return ret;
 
 		phy_set_drvdata(phy, miphy_dev->phys[port]);
+
 		port++;
+		/* sysconfig offsets are indexed from 1 */
+		ret = of_property_read_u32_index(np, "st,syscfg", port,
+					&miphy_phy->ctrlreg);
+		if (ret) {
+			dev_err(&pdev->dev, "No sysconfig offset found\n");
+			return ret;
+		}
 	}
 
 	provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
-- 
1.9.1

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[PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Peter Griffin]

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
update the miphy365 phy driver to access sysconfig register offsets via
syscfg dt property.

This is because the reg property should not be mixing address spaces
like it does currently for miphy365. This change then also aligns us
to how other platforms such as keystone and bcm7445 pass there syscon
offsets via DT.

This patch breaks DT compatibility, but this platform is considered WIP,
and is only used by a few developers who are upstreaming support for it.
This change has been done as a single atomic commit to ensure it is
bisectable.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
 arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
 drivers/phy/phy-miphy365x.c                        | 29 ++++++++--------------
 3 files changed, 23 insertions(+), 31 deletions(-)

diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
index 42c8808..9802d5d 100644
--- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
+++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
@@ -6,8 +6,10 @@ for SATA and PCIe.
 
 Required properties (controller (parent) node):
 - compatible    : Should be "st,miphy365x-phy"
-- st,syscfg     : Should be a phandle of the system configuration register group
-		  which contain the SATA, PCIe mode setting bits
+- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
+		  containing the miphy registers and integer array should contain
+		  an entry for each port sub-node, specifying the control
+		  register offset inside the sysconfig group.
 
 Required nodes	:  A sub-node is required for each channel the controller
 		   provides. Address range information including the usual
@@ -26,7 +28,6 @@ Required properties (port (child) node):
 		  registers filled in "reg":
 			- sata:   For SATA devices
 			- pcie:   For PCIe devices
-			- syscfg: To specify the syscfg based config register
 
 Optional properties (port (child) node):
 - st,sata-gen	     :	Generation of locally attached SATA IP. Expected values
@@ -39,20 +40,20 @@ Example:
 
 	miphy365x_phy: miphy365x at fe382000 {
 		compatible      = "st,miphy365x-phy";
-		st,syscfg  	= <&syscfg_rear>;
+		st,syscfg  	= <&syscfg_rear 0x824 0x828>;
 		#address-cells	= <1>;
 		#size-cells	= <1>;
 		ranges;
 
 		phy_port0: port at fe382000 {
-			reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
-			reg-names = "sata", "pcie", "syscfg";
+			reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
+			reg-names = "sata", "pcie";
 			#phy-cells = <1>;
 			st,sata-gen = <3>;
 		};
 
 		phy_port1: port at fe38a000 {
-			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
+			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
 			reg-names = "sata", "pcie", "syscfg";
 			#phy-cells = <1>;
 			st,pcie-tx-pol-inv;
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index fad9073..85afe01 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -283,21 +283,21 @@
 
 		miphy365x_phy: phy at fe382000 {
 			compatible      = "st,miphy365x-phy";
-			st,syscfg  	= <&syscfg_rear>;
+			st,syscfg	= <&syscfg_rear 0x824 0x828>;
 			#address-cells	= <1>;
 			#size-cells	= <1>;
 			ranges;
 
 			phy_port0: port at fe382000 {
 				#phy-cells = <1>;
-				reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
-				reg-names = "sata", "pcie", "syscfg";
+				reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
+				reg-names = "sata", "pcie";
 			};
 
 			phy_port1: port at fe38a000 {
 				#phy-cells = <1>;
-				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
-				reg-names = "sata", "pcie", "syscfg";
+				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
+				reg-names = "sata", "pcie";
 			};
 		};
 
diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
index 6ab43a8..6c80154 100644
--- a/drivers/phy/phy-miphy365x.c
+++ b/drivers/phy/phy-miphy365x.c
@@ -141,7 +141,7 @@ struct miphy365x_phy {
 	bool pcie_tx_pol_inv;
 	bool sata_tx_pol_inv;
 	u32 sata_gen;
-	u64 ctrlreg;
+	u32 ctrlreg;
 	u8 type;
 };
 
@@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
 	bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
 
 	return regmap_update_bits(miphy_dev->regmap,
-				  (unsigned int)miphy_phy->ctrlreg,
+				  miphy_phy->ctrlreg,
 				  SYSCFG_SELECT_SATA_MASK,
 				  sata << SYSCFG_SELECT_SATA_POS);
 }
@@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
 {
 	struct device_node *phynode = miphy_phy->phy->dev.of_node;
 	const char *name;
-	const __be32 *taddr;
 	int type = miphy_phy->type;
 	int ret;
 
@@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
 		return ret;
 	}
 
-	if (!strncmp(name, "syscfg", 6)) {
-		taddr = of_get_address(phynode, index, NULL, NULL);
-		if (!taddr) {
-			dev_err(dev, "failed to fetch syscfg address\n");
-			return -EINVAL;
-		}
-
-		miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
-		if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
-			dev_err(dev, "failed to translate syscfg address\n");
-			return -EINVAL;
-		}
-
-		return 0;
-	}
-
 	if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
 	      (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
 		return 0;
@@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
 			return ret;
 
 		phy_set_drvdata(phy, miphy_dev->phys[port]);
+
 		port++;
+		/* sysconfig offsets are indexed from 1 */
+		ret = of_property_read_u32_index(np, "st,syscfg", port,
+					&miphy_phy->ctrlreg);
+		if (ret) {
+			dev_err(&pdev->dev, "No sysconfig offset found\n");
+			return ret;
+		}
 	}
 
 	provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
-- 
1.9.1

[PATCH v2 3/7] ARM: STi: DT: STiH407: Add usb2 picophy dt nodes

[Peter Griffin]

This patch adds the dt nodes for the usb2 picophy found on the stih407
device family. It is used on stih407 by the dwc3 usb3 controller when
controlling usb2/1.1 devices.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/boot/dts/stih407-family.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 3e31d32..d4a8f84 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -274,5 +274,14 @@
 
 			status = "disabled";
 		};
+
+		usb2_picophy0: phy1 {
+			compatible = "st,stih407-usb2-phy";
+			#phy-cells = <0>;
+			st,syscfg = <&syscfg_core 0x100 0xf4>;
+			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+				 <&picophyreset STIH407_PICOPHY0_RESET>;
+			reset-names = "global", "port";
+		};
 	};
 };
-- 
1.9.1

[PATCH v2 3/7] ARM: STi: DT: STiH407: Add usb2 picophy dt nodes

[Peter Griffin]

This patch adds the dt nodes for the usb2 picophy found on the stih407
device family. It is used on stih407 by the dwc3 usb3 controller when
controlling usb2/1.1 devices.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/boot/dts/stih407-family.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index 3e31d32..d4a8f84 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -274,5 +274,14 @@
 
 			status = "disabled";
 		};
+
+		usb2_picophy0: phy1 {
+			compatible = "st,stih407-usb2-phy";
+			#phy-cells = <0>;
+			st,syscfg = <&syscfg_core 0x100 0xf4>;
+			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+				 <&picophyreset STIH407_PICOPHY0_RESET>;
+			reset-names = "global", "port";
+		};
 	};
 };
-- 
1.9.1

[PATCH v2 4/7] ARM: STi: DT: STiH410: Add usb2 picophy dt nodes

[Peter Griffin]

This patch adds the dt nodes for the extra usb2 picophys found on
the stih410.

These two picophys are used in conjunction with the extra ehci/ohci usb
controllers also found on the stih410 SoC.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/boot/dts/stih410.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index c05627e..2e5e9ed 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -10,5 +10,23 @@
 #include "stih407-family.dtsi"
 #include "stih410-pinctrl.dtsi"
 / {
+	soc {
+		usb2_picophy1: phy2 {
+			compatible = "st,stih407-usb2-phy";
+			#phy-cells = <0>;
+			st,syscfg = <&syscfg_core 0xf8 0xf4>;
+			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+				 <&picophyreset STIH407_PICOPHY0_RESET>;
+			reset-names = "global", "port";
+		};
 
+		usb2_picophy2: phy3 {
+			compatible = "st,stih407-usb2-phy";
+			#phy-cells = <0>;
+			st,syscfg = <&syscfg_core 0xfc 0xf4>;
+			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+				 <&picophyreset STIH407_PICOPHY1_RESET>;
+			reset-names = "global", "port";
+		};
+	};
 };
-- 
1.9.1

[PATCH v2 4/7] ARM: STi: DT: STiH410: Add usb2 picophy dt nodes

[Peter Griffin]

This patch adds the dt nodes for the extra usb2 picophys found on
the stih410.

These two picophys are used in conjunction with the extra ehci/ohci usb
controllers also found on the stih410 SoC.

Signed-off-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Reviewed-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
---
 arch/arm/boot/dts/stih410.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index c05627e..2e5e9ed 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -10,5 +10,23 @@
 #include "stih407-family.dtsi"
 #include "stih410-pinctrl.dtsi"
 / {
+	soc {
+		usb2_picophy1: phy2 {
+			compatible = "st,stih407-usb2-phy";
+			#phy-cells = <0>;
+			st,syscfg = <&syscfg_core 0xf8 0xf4>;
+			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+				 <&picophyreset STIH407_PICOPHY0_RESET>;
+			reset-names = "global", "port";
+		};
 
+		usb2_picophy2: phy3 {
+			compatible = "st,stih407-usb2-phy";
+			#phy-cells = <0>;
+			st,syscfg = <&syscfg_core 0xfc 0xf4>;
+			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+				 <&picophyreset STIH407_PICOPHY1_RESET>;
+			reset-names = "global", "port";
+		};
+	};
 };
-- 
1.9.1

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[PATCH v2 4/7] ARM: STi: DT: STiH410: Add usb2 picophy dt nodes

[Peter Griffin]

This patch adds the dt nodes for the extra usb2 picophys found on
the stih410.

These two picophys are used in conjunction with the extra ehci/ohci usb
controllers also found on the stih410 SoC.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/boot/dts/stih410.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index c05627e..2e5e9ed 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -10,5 +10,23 @@
 #include "stih407-family.dtsi"
 #include "stih410-pinctrl.dtsi"
 / {
+	soc {
+		usb2_picophy1: phy2 {
+			compatible = "st,stih407-usb2-phy";
+			#phy-cells = <0>;
+			st,syscfg = <&syscfg_core 0xf8 0xf4>;
+			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+				 <&picophyreset STIH407_PICOPHY0_RESET>;
+			reset-names = "global", "port";
+		};
 
+		usb2_picophy2: phy3 {
+			compatible = "st,stih407-usb2-phy";
+			#phy-cells = <0>;
+			st,syscfg = <&syscfg_core 0xfc 0xf4>;
+			resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+				 <&picophyreset STIH407_PICOPHY1_RESET>;
+			reset-names = "global", "port";
+		};
+	};
 };
-- 
1.9.1

[PATCH v2 5/7] ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb controllers.

[Peter Griffin]

This patch adds the DT nodes for the extra ehci and ohci usb controllers
on the stih410 SoC.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/boot/dts/stih410.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 2e5e9ed..37995f4 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -28,5 +28,57 @@
 				 <&picophyreset STIH407_PICOPHY1_RESET>;
 			reset-names = "global", "port";
 		};
+
+		ohci0: usb@9a03c00 {
+			compatible = "st,st-ohci-300x";
+			reg = <0x9a03c00 0x100>;
+			interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
+			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
+				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
+			reset-names = "power", "softreset";
+			phys = <&usb2_picophy1>;
+			phy-names = "usb";
+		};
+
+		ehci0: usb@9a03e00 {
+			compatible = "st,st-ehci-300x";
+			reg = <0x9a03e00 0x100>;
+			interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
+				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
+			reset-names = "power", "softreset";
+			phys = <&usb2_picophy1>;
+			phy-names = "usb";
+		};
+
+		ohci1: usb@9a83c00 {
+			compatible = "st,st-ohci-300x";
+			reg = <0x9a83c00 0x100>;
+			interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
+			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
+				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
+			reset-names = "power", "softreset";
+			phys = <&usb2_picophy2>;
+			phy-names = "usb";
+		};
+
+		ehci1: usb@9a83e00 {
+			compatible = "st,st-ehci-300x";
+			reg = <0x9a83e00 0x100>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>;
+			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
+				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
+			reset-names = "power", "softreset";
+			phys = <&usb2_picophy2>;
+			phy-names = "usb";
+		};
 	};
 };
-- 
1.9.1

[PATCH v2 5/7] ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb controllers.

[Peter Griffin]

This patch adds the DT nodes for the extra ehci and ohci usb controllers
on the stih410 SoC.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/boot/dts/stih410.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 2e5e9ed..37995f4 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -28,5 +28,57 @@
 				 <&picophyreset STIH407_PICOPHY1_RESET>;
 			reset-names = "global", "port";
 		};
+
+		ohci0: usb@9a03c00 {
+			compatible = "st,st-ohci-300x";
+			reg = <0x9a03c00 0x100>;
+			interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
+			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
+				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
+			reset-names = "power", "softreset";
+			phys = <&usb2_picophy1>;
+			phy-names = "usb";
+		};
+
+		ehci0: usb@9a03e00 {
+			compatible = "st,st-ehci-300x";
+			reg = <0x9a03e00 0x100>;
+			interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
+				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
+			reset-names = "power", "softreset";
+			phys = <&usb2_picophy1>;
+			phy-names = "usb";
+		};
+
+		ohci1: usb@9a83c00 {
+			compatible = "st,st-ohci-300x";
+			reg = <0x9a83c00 0x100>;
+			interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
+			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
+				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
+			reset-names = "power", "softreset";
+			phys = <&usb2_picophy2>;
+			phy-names = "usb";
+		};
+
+		ehci1: usb@9a83e00 {
+			compatible = "st,st-ehci-300x";
+			reg = <0x9a83e00 0x100>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>;
+			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
+				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
+			reset-names = "power", "softreset";
+			phys = <&usb2_picophy2>;
+			phy-names = "usb";
+		};
 	};
 };
-- 
1.9.1

[PATCH v2 5/7] ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb controllers.

[Peter Griffin]

This patch adds the DT nodes for the extra ehci and ohci usb controllers
on the stih410 SoC.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/boot/dts/stih410.dtsi | 52 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi
index 2e5e9ed..37995f4 100644
--- a/arch/arm/boot/dts/stih410.dtsi
+++ b/arch/arm/boot/dts/stih410.dtsi
@@ -28,5 +28,57 @@
 				 <&picophyreset STIH407_PICOPHY1_RESET>;
 			reset-names = "global", "port";
 		};
+
+		ohci0: usb at 9a03c00 {
+			compatible = "st,st-ohci-300x";
+			reg = <0x9a03c00 0x100>;
+			interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
+			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
+				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
+			reset-names = "power", "softreset";
+			phys = <&usb2_picophy1>;
+			phy-names = "usb";
+		};
+
+		ehci0: usb at 9a03e00 {
+			compatible = "st,st-ehci-300x";
+			reg = <0x9a03e00 0x100>;
+			interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb0>;
+			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+			resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
+				 <&softreset STIH407_USB2_PORT0_SOFTRESET>;
+			reset-names = "power", "softreset";
+			phys = <&usb2_picophy1>;
+			phy-names = "usb";
+		};
+
+		ohci1: usb at 9a83c00 {
+			compatible = "st,st-ohci-300x";
+			reg = <0x9a83c00 0x100>;
+			interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
+			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
+				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
+			reset-names = "power", "softreset";
+			phys = <&usb2_picophy2>;
+			phy-names = "usb";
+		};
+
+		ehci1: usb at 9a83e00 {
+			compatible = "st,st-ehci-300x";
+			reg = <0x9a83e00 0x100>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_usb1>;
+			clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+			resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
+				 <&softreset STIH407_USB2_PORT1_SOFTRESET>;
+			reset-names = "power", "softreset";
+			phys = <&usb2_picophy2>;
+			phy-names = "usb";
+		};
 	};
 };
-- 
1.9.1

[PATCH v2 6/7] ARM: multi_v7_defconfig: Enable stih407 usb picophy

[Peter Griffin]

This patch enables the picoPHY usb phy which is used by
the usb2 and usb3 host controllers when controlling usb2/1.1
devices. It is found in stih407 family SoC's from STMicroelectronics.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index bc393b7..444685c 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -456,6 +456,7 @@ CONFIG_OMAP_USB2=y
 CONFIG_TI_PIPE3=y
 CONFIG_PHY_MIPHY365X=y
 CONFIG_PHY_STIH41X_USB=y
+CONFIG_PHY_STIH407_USB=y
 CONFIG_PHY_SUN4I_USB=y
 CONFIG_EXT4_FS=y
 CONFIG_AUTOFS4_FS=y
-- 
1.9.1

[PATCH v2 6/7] ARM: multi_v7_defconfig: Enable stih407 usb picophy

[Peter Griffin]

This patch enables the picoPHY usb phy which is used by
the usb2 and usb3 host controllers when controlling usb2/1.1
devices. It is found in stih407 family SoC's from STMicroelectronics.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index bc393b7..444685c 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -456,6 +456,7 @@ CONFIG_OMAP_USB2=y
 CONFIG_TI_PIPE3=y
 CONFIG_PHY_MIPHY365X=y
 CONFIG_PHY_STIH41X_USB=y
+CONFIG_PHY_STIH407_USB=y
 CONFIG_PHY_SUN4I_USB=y
 CONFIG_EXT4_FS=y
 CONFIG_AUTOFS4_FS=y
-- 
1.9.1

[PATCH v2 7/7] stmmac: dwmac-sti: Pass sysconfig register offset via syscon dt property.

[Peter Griffin]

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
we should not be mixing address spaces in the reg property like this driver
currently does. This patch updates the driver, dt docs and also the existing
dt nodes to pass the sysconfig offset in the syscon dt property.

This patch breaks DT compatibility! But this platform is considered WIP,
and is only used by a few developers who are upstreaming support for it.
This change has been done as a single atomic commit to ensure it is
bisectable.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 Documentation/devicetree/bindings/net/sti-dwmac.txt | 14 +++++---------
 arch/arm/boot/dts/stih415.dtsi                      | 12 ++++++------
 arch/arm/boot/dts/stih416.dtsi                      | 12 ++++++------
 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c     | 13 +++++++------
 4 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/sti-dwmac.txt b/Documentation/devicetree/bindings/net/sti-dwmac.txt
index 6762a6b..d05c1e1 100644
--- a/Documentation/devicetree/bindings/net/sti-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/sti-dwmac.txt
@@ -9,14 +9,10 @@ The device node has following properties.
 Required properties:
  - compatible	: Can be "st,stih415-dwmac", "st,stih416-dwmac",
    "st,stih407-dwmac", "st,stid127-dwmac".
- - reg : Offset of the glue configuration register map in system
-   configuration regmap pointed by st,syscon property and size.
- - st,syscon : Should be phandle to system configuration node which
-   encompases this glue registers.
+ - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
+   encompases the glue register, and the offset of the control register.
  - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
    register available on STiH407 SoC.
- - sti-ethconf: this is the gmac glue logic register to enable the GMAC,
-   select among the different modes and program the clk retiming.
  - pinctrl-0: pin-control for all the MII mode supported.
 
 Optional properties:
@@ -40,10 +36,10 @@ ethernet0: dwmac@9630000 {
 	device_type = "network";
 	status = "disabled";
 	compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
-	reg = <0x9630000 0x8000>, <0x80 0x4>;
-	reg-names = "stmmaceth", "sti-ethconf";
+	reg = <0x9630000 0x8000>;
+	reg-names = "stmmaceth";
 
-	st,syscon = <&syscfg_sbc_reg>;
+	st,syscon = <&syscfg_sbc_reg 0x80>;
 	st,gmac_en;
 	resets = <&softreset STIH407_ETH1_SOFTRESET>;
 	reset-names = "stmmaceth";
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 9198c12..19b019b 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -153,8 +153,8 @@
 			compatible	= "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
 			status 		= "disabled";
 
-			reg 		= <0xfe810000 0x8000>, <0x148 0x4>;
-			reg-names	= "stmmaceth", "sti-ethconf";
+			reg		= <0xfe810000 0x8000>;
+			reg-names	= "stmmaceth";
 
 			interrupts 	= <0 147 0>, <0 148 0>, <0 149 0>;
 			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
@@ -165,7 +165,7 @@
 			snps,mixed-burst;
 			snps,force_sf_dma_mode;
 
-			st,syscon	= <&syscfg_rear>;
+			st,syscon	= <&syscfg_rear 0x148>;
 
 			pinctrl-names 	= "default";
 			pinctrl-0	= <&pinctrl_mii0>;
@@ -177,8 +177,8 @@
 			device_type = "network";
 			compatible	= "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
 			status 		= "disabled";
-			reg		= <0xfef08000 0x8000>, <0x74 0x4>;
-			reg-names	= "stmmaceth", "sti-ethconf";
+			reg		= <0xfef08000 0x8000>;
+			reg-names	= "stmmaceth";
 			interrupts 	= <0 150 0>, <0 151 0>, <0 152 0>;
 			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 
@@ -186,7 +186,7 @@
 			snps,mixed-burst;
 			snps,force_sf_dma_mode;
 
-			st,syscon		= <&syscfg_sbc>;
+			st,syscon		= <&syscfg_sbc 0x74>;
 
 			resets			= <&softreset STIH415_ETH1_SOFTRESET>;
 			reset-names		= "stmmaceth";
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 85afe01..ea28eba 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -163,8 +163,8 @@
 			device_type 	= "network";
 			compatible	= "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
 			status 		= "disabled";
-			reg 		= <0xfe810000 0x8000>, <0x8bc 0x4>;
-			reg-names	= "stmmaceth", "sti-ethconf";
+			reg		= <0xfe810000 0x8000>;
+			reg-names	= "stmmaceth";
 
 			interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
 			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
@@ -172,7 +172,7 @@
 			snps,pbl 	= <32>;
 			snps,mixed-burst;
 
-			st,syscon		= <&syscfg_rear>;
+			st,syscon		= <&syscfg_rear 0x8bc>;
 			resets			= <&softreset STIH416_ETH0_SOFTRESET>;
 			reset-names		= "stmmaceth";
 			pinctrl-names 	= "default";
@@ -185,15 +185,15 @@
 			device_type = "network";
 			compatible		= "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
 			status 		= "disabled";
-			reg		= <0xfef08000 0x8000>, <0x7f0 0x4>;
-			reg-names	= "stmmaceth", "sti-ethconf";
+			reg		= <0xfef08000 0x8000>;
+			reg-names	= "stmmaceth";
 			interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
 			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 
 			snps,pbl	= <32>;
 			snps,mixed-burst;
 
-			st,syscon	= <&syscfg_sbc>;
+			st,syscon	= <&syscfg_sbc 0x7f0>;
 
 			resets		= <&softreset STIH416_ETH1_SOFTRESET>;
 			reset-names	= "stmmaceth";
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
index 056b358..bb6e2dc 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
@@ -122,7 +122,7 @@ struct sti_dwmac {
 	bool ext_phyclk;	/* Clock from external PHY */
 	u32 tx_retime_src;	/* TXCLK Retiming*/
 	struct clk *clk;	/* PHY clock */
-	int ctrl_reg;		/* GMAC glue-logic control register */
+	u32 ctrl_reg;		/* GMAC glue-logic control register */
 	int clk_sel_reg;	/* GMAC ext clk selection register */
 	struct device *dev;
 	struct regmap *regmap;
@@ -285,11 +285,6 @@ static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
 	if (!np)
 		return -EINVAL;
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-ethconf");
-	if (!res)
-		return -ENODATA;
-	dwmac->ctrl_reg = res->start;
-
 	/* clk selection from extra syscfg register */
 	dwmac->clk_sel_reg = -ENXIO;
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf");
@@ -300,6 +295,12 @@ static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
+	err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->ctrl_reg);
+	if (err) {
+		dev_err(dev, "Can't get sysconfig ctrl offset (%d)\n", err);
+		return err;
+	}
+
 	dwmac->dev = dev;
 	dwmac->interface = of_get_phy_mode(np);
 	dwmac->regmap = regmap;
-- 
1.9.1

[PATCH v2 7/7] stmmac: dwmac-sti: Pass sysconfig register offset via syscon dt property.

[Peter Griffin]

Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
we should not be mixing address spaces in the reg property like this driver
currently does. This patch updates the driver, dt docs and also the existing
dt nodes to pass the sysconfig offset in the syscon dt property.

This patch breaks DT compatibility! But this platform is considered WIP,
and is only used by a few developers who are upstreaming support for it.
This change has been done as a single atomic commit to ensure it is
bisectable.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
---
 Documentation/devicetree/bindings/net/sti-dwmac.txt | 14 +++++---------
 arch/arm/boot/dts/stih415.dtsi                      | 12 ++++++------
 arch/arm/boot/dts/stih416.dtsi                      | 12 ++++++------
 drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c     | 13 +++++++------
 4 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/sti-dwmac.txt b/Documentation/devicetree/bindings/net/sti-dwmac.txt
index 6762a6b..d05c1e1 100644
--- a/Documentation/devicetree/bindings/net/sti-dwmac.txt
+++ b/Documentation/devicetree/bindings/net/sti-dwmac.txt
@@ -9,14 +9,10 @@ The device node has following properties.
 Required properties:
  - compatible	: Can be "st,stih415-dwmac", "st,stih416-dwmac",
    "st,stih407-dwmac", "st,stid127-dwmac".
- - reg : Offset of the glue configuration register map in system
-   configuration regmap pointed by st,syscon property and size.
- - st,syscon : Should be phandle to system configuration node which
-   encompases this glue registers.
+ - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
+   encompases the glue register, and the offset of the control register.
  - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
    register available on STiH407 SoC.
- - sti-ethconf: this is the gmac glue logic register to enable the GMAC,
-   select among the different modes and program the clk retiming.
  - pinctrl-0: pin-control for all the MII mode supported.
 
 Optional properties:
@@ -40,10 +36,10 @@ ethernet0: dwmac at 9630000 {
 	device_type = "network";
 	status = "disabled";
 	compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
-	reg = <0x9630000 0x8000>, <0x80 0x4>;
-	reg-names = "stmmaceth", "sti-ethconf";
+	reg = <0x9630000 0x8000>;
+	reg-names = "stmmaceth";
 
-	st,syscon = <&syscfg_sbc_reg>;
+	st,syscon = <&syscfg_sbc_reg 0x80>;
 	st,gmac_en;
 	resets = <&softreset STIH407_ETH1_SOFTRESET>;
 	reset-names = "stmmaceth";
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index 9198c12..19b019b 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -153,8 +153,8 @@
 			compatible	= "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
 			status 		= "disabled";
 
-			reg 		= <0xfe810000 0x8000>, <0x148 0x4>;
-			reg-names	= "stmmaceth", "sti-ethconf";
+			reg		= <0xfe810000 0x8000>;
+			reg-names	= "stmmaceth";
 
 			interrupts 	= <0 147 0>, <0 148 0>, <0 149 0>;
 			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
@@ -165,7 +165,7 @@
 			snps,mixed-burst;
 			snps,force_sf_dma_mode;
 
-			st,syscon	= <&syscfg_rear>;
+			st,syscon	= <&syscfg_rear 0x148>;
 
 			pinctrl-names 	= "default";
 			pinctrl-0	= <&pinctrl_mii0>;
@@ -177,8 +177,8 @@
 			device_type = "network";
 			compatible	= "st,stih415-dwmac", "snps,dwmac", "snps,dwmac-3.610";
 			status 		= "disabled";
-			reg		= <0xfef08000 0x8000>, <0x74 0x4>;
-			reg-names	= "stmmaceth", "sti-ethconf";
+			reg		= <0xfef08000 0x8000>;
+			reg-names	= "stmmaceth";
 			interrupts 	= <0 150 0>, <0 151 0>, <0 152 0>;
 			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 
@@ -186,7 +186,7 @@
 			snps,mixed-burst;
 			snps,force_sf_dma_mode;
 
-			st,syscon		= <&syscfg_sbc>;
+			st,syscon		= <&syscfg_sbc 0x74>;
 
 			resets			= <&softreset STIH415_ETH1_SOFTRESET>;
 			reset-names		= "stmmaceth";
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 85afe01..ea28eba 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -163,8 +163,8 @@
 			device_type 	= "network";
 			compatible	= "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
 			status 		= "disabled";
-			reg 		= <0xfe810000 0x8000>, <0x8bc 0x4>;
-			reg-names	= "stmmaceth", "sti-ethconf";
+			reg		= <0xfe810000 0x8000>;
+			reg-names	= "stmmaceth";
 
 			interrupts = <0 133 0>, <0 134 0>, <0 135 0>;
 			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
@@ -172,7 +172,7 @@
 			snps,pbl 	= <32>;
 			snps,mixed-burst;
 
-			st,syscon		= <&syscfg_rear>;
+			st,syscon		= <&syscfg_rear 0x8bc>;
 			resets			= <&softreset STIH416_ETH0_SOFTRESET>;
 			reset-names		= "stmmaceth";
 			pinctrl-names 	= "default";
@@ -185,15 +185,15 @@
 			device_type = "network";
 			compatible		= "st,stih416-dwmac", "snps,dwmac", "snps,dwmac-3.710";
 			status 		= "disabled";
-			reg		= <0xfef08000 0x8000>, <0x7f0 0x4>;
-			reg-names	= "stmmaceth", "sti-ethconf";
+			reg		= <0xfef08000 0x8000>;
+			reg-names	= "stmmaceth";
 			interrupts = <0 136 0>, <0 137 0>, <0 138 0>;
 			interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 
 			snps,pbl	= <32>;
 			snps,mixed-burst;
 
-			st,syscon	= <&syscfg_sbc>;
+			st,syscon	= <&syscfg_sbc 0x7f0>;
 
 			resets		= <&softreset STIH416_ETH1_SOFTRESET>;
 			reset-names	= "stmmaceth";
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
index 056b358..bb6e2dc 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c
@@ -122,7 +122,7 @@ struct sti_dwmac {
 	bool ext_phyclk;	/* Clock from external PHY */
 	u32 tx_retime_src;	/* TXCLK Retiming*/
 	struct clk *clk;	/* PHY clock */
-	int ctrl_reg;		/* GMAC glue-logic control register */
+	u32 ctrl_reg;		/* GMAC glue-logic control register */
 	int clk_sel_reg;	/* GMAC ext clk selection register */
 	struct device *dev;
 	struct regmap *regmap;
@@ -285,11 +285,6 @@ static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
 	if (!np)
 		return -EINVAL;
 
-	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-ethconf");
-	if (!res)
-		return -ENODATA;
-	dwmac->ctrl_reg = res->start;
-
 	/* clk selection from extra syscfg register */
 	dwmac->clk_sel_reg = -ENXIO;
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sti-clkconf");
@@ -300,6 +295,12 @@ static int sti_dwmac_parse_data(struct sti_dwmac *dwmac,
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
+	err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->ctrl_reg);
+	if (err) {
+		dev_err(dev, "Can't get sysconfig ctrl offset (%d)\n", err);
+		return err;
+	}
+
 	dwmac->dev = dev;
 	dwmac->interface = of_get_phy_mode(np);
 	dwmac->regmap = regmap;
-- 
1.9.1

Re: [PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[Maxime Coquelin]

Hi Peter,

On 01/07/2015 04:04 PM, Peter Griffin wrote:
> Hi folks,
>
> A V2 of this old series incorporating Arnd and Lees Feedback form v1.
>
> Following on from Arnds comments about the picophy driver here
> https://lkml.org/lkml/2014/11/13/161, this series fixes the
> remaining upstreamed drivers for STI, which are mixing address spaces
> in the reg property. We do this in a way similar to the keystone
> and bcm7445 platforms, by having sysconfig phandle/ offset pair
> (where only one register is required). Or phandle / integer array
> where multiple offsets in the same bank are needed).
>
> This series breaks DT compatability! But the platform support
> is WIP and only being used by the few developers who are upstreaming
> support for it. I've made each change to the driver / dt doc / dt
> file as a single atomic commit so the kernel will remain bisectable.
>
> This series then also enables the picophy driver, and adds back in
> the ehci/ohci dt nodes for stih410 which make use of the picophy.
>
> regards,
>
> Peter.
>
> Changes since v1:
> - Add missing space after */ (Lee)
> - Change comment to "indexed from" rather than "not indexed from" (Lee)
> - Change naming to phy1, phy2 rather than phy@1 phy@2 if there is no reg property (Arnd / Grant)
> - Rebased on v3.19-rc3 (me)
> - Checkpatch "no space before tabs" warning in stih41*.dtsi (me)
>
> Peter Griffin (7):
>    phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg
>      property.
>    phy: miphy365x: Pass sysconfig register offsets via syscfg dt
>      property.
>    ARM: STi: DT: STiH407: Add usb2 picophy dt nodes
>    ARM: STi: DT: STiH410: Add usb2 picophy dt nodes
>    ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb
>      controllers.
>    ARM: multi_v7_defconfig: Enable stih407 usb picophy
>    stmmac: dwmac-sti: Pass sysconfig register offset via syscon dt
>      property.
>
>   .../devicetree/bindings/net/sti-dwmac.txt          | 14 ++---
>   .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 ++---
>   .../devicetree/bindings/phy/phy-stih407-usb.txt    | 10 +---
>   arch/arm/boot/dts/stih407-family.dtsi              |  9 +++
>   arch/arm/boot/dts/stih410.dtsi                     | 70 ++++++++++++++++++++++
>   arch/arm/boot/dts/stih415.dtsi                     | 12 ++--
>   arch/arm/boot/dts/stih416.dtsi                     | 22 +++----
>   arch/arm/configs/multi_v7_defconfig                |  1 +
>   drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c    | 13 ++--
>   drivers/phy/phy-miphy365x.c                        | 29 ++++-----
>   drivers/phy/phy-stih407-usb.c                      | 25 ++++----
>   11 files changed, 143 insertions(+), 77 deletions(-)
>

Thanks! The series looks good to me.

DT patches applied to sti-dt-for-v3.20 branch,
and defconfig patch applied to sti-defconfig-for-v3.20.


Regards,
Maxime

Re: [PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[Maxime Coquelin]

Hi Peter,

On 01/07/2015 04:04 PM, Peter Griffin wrote:
> Hi folks,
>
> A V2 of this old series incorporating Arnd and Lees Feedback form v1.
>
> Following on from Arnds comments about the picophy driver here
> https://lkml.org/lkml/2014/11/13/161, this series fixes the
> remaining upstreamed drivers for STI, which are mixing address spaces
> in the reg property. We do this in a way similar to the keystone
> and bcm7445 platforms, by having sysconfig phandle/ offset pair
> (where only one register is required). Or phandle / integer array
> where multiple offsets in the same bank are needed).
>
> This series breaks DT compatability! But the platform support
> is WIP and only being used by the few developers who are upstreaming
> support for it. I've made each change to the driver / dt doc / dt
> file as a single atomic commit so the kernel will remain bisectable.
>
> This series then also enables the picophy driver, and adds back in
> the ehci/ohci dt nodes for stih410 which make use of the picophy.
>
> regards,
>
> Peter.
>
> Changes since v1:
> - Add missing space after */ (Lee)
> - Change comment to "indexed from" rather than "not indexed from" (Lee)
> - Change naming to phy1, phy2 rather than phy@1 phy@2 if there is no reg property (Arnd / Grant)
> - Rebased on v3.19-rc3 (me)
> - Checkpatch "no space before tabs" warning in stih41*.dtsi (me)
>
> Peter Griffin (7):
>    phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg
>      property.
>    phy: miphy365x: Pass sysconfig register offsets via syscfg dt
>      property.
>    ARM: STi: DT: STiH407: Add usb2 picophy dt nodes
>    ARM: STi: DT: STiH410: Add usb2 picophy dt nodes
>    ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb
>      controllers.
>    ARM: multi_v7_defconfig: Enable stih407 usb picophy
>    stmmac: dwmac-sti: Pass sysconfig register offset via syscon dt
>      property.
>
>   .../devicetree/bindings/net/sti-dwmac.txt          | 14 ++---
>   .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 ++---
>   .../devicetree/bindings/phy/phy-stih407-usb.txt    | 10 +---
>   arch/arm/boot/dts/stih407-family.dtsi              |  9 +++
>   arch/arm/boot/dts/stih410.dtsi                     | 70 ++++++++++++++++++++++
>   arch/arm/boot/dts/stih415.dtsi                     | 12 ++--
>   arch/arm/boot/dts/stih416.dtsi                     | 22 +++----
>   arch/arm/configs/multi_v7_defconfig                |  1 +
>   drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c    | 13 ++--
>   drivers/phy/phy-miphy365x.c                        | 29 ++++-----
>   drivers/phy/phy-stih407-usb.c                      | 25 ++++----
>   11 files changed, 143 insertions(+), 77 deletions(-)
>

Thanks! The series looks good to me.

DT patches applied to sti-dt-for-v3.20 branch,
and defconfig patch applied to sti-defconfig-for-v3.20.


Regards,
Maxime

[PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[Maxime Coquelin]

Hi Peter,

On 01/07/2015 04:04 PM, Peter Griffin wrote:
> Hi folks,
>
> A V2 of this old series incorporating Arnd and Lees Feedback form v1.
>
> Following on from Arnds comments about the picophy driver here
> https://lkml.org/lkml/2014/11/13/161, this series fixes the
> remaining upstreamed drivers for STI, which are mixing address spaces
> in the reg property. We do this in a way similar to the keystone
> and bcm7445 platforms, by having sysconfig phandle/ offset pair
> (where only one register is required). Or phandle / integer array
> where multiple offsets in the same bank are needed).
>
> This series breaks DT compatability! But the platform support
> is WIP and only being used by the few developers who are upstreaming
> support for it. I've made each change to the driver / dt doc / dt
> file as a single atomic commit so the kernel will remain bisectable.
>
> This series then also enables the picophy driver, and adds back in
> the ehci/ohci dt nodes for stih410 which make use of the picophy.
>
> regards,
>
> Peter.
>
> Changes since v1:
> - Add missing space after */ (Lee)
> - Change comment to "indexed from" rather than "not indexed from" (Lee)
> - Change naming to phy1, phy2 rather than phy at 1 phy at 2 if there is no reg property (Arnd / Grant)
> - Rebased on v3.19-rc3 (me)
> - Checkpatch "no space before tabs" warning in stih41*.dtsi (me)
>
> Peter Griffin (7):
>    phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg
>      property.
>    phy: miphy365x: Pass sysconfig register offsets via syscfg dt
>      property.
>    ARM: STi: DT: STiH407: Add usb2 picophy dt nodes
>    ARM: STi: DT: STiH410: Add usb2 picophy dt nodes
>    ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb
>      controllers.
>    ARM: multi_v7_defconfig: Enable stih407 usb picophy
>    stmmac: dwmac-sti: Pass sysconfig register offset via syscon dt
>      property.
>
>   .../devicetree/bindings/net/sti-dwmac.txt          | 14 ++---
>   .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 ++---
>   .../devicetree/bindings/phy/phy-stih407-usb.txt    | 10 +---
>   arch/arm/boot/dts/stih407-family.dtsi              |  9 +++
>   arch/arm/boot/dts/stih410.dtsi                     | 70 ++++++++++++++++++++++
>   arch/arm/boot/dts/stih415.dtsi                     | 12 ++--
>   arch/arm/boot/dts/stih416.dtsi                     | 22 +++----
>   arch/arm/configs/multi_v7_defconfig                |  1 +
>   drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c    | 13 ++--
>   drivers/phy/phy-miphy365x.c                        | 29 ++++-----
>   drivers/phy/phy-stih407-usb.c                      | 25 ++++----
>   11 files changed, 143 insertions(+), 77 deletions(-)
>

Thanks! The series looks good to me.

DT patches applied to sti-dt-for-v3.20 branch,
and defconfig patch applied to sti-defconfig-for-v3.20.


Regards,
Maxime

Re: [PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[David Miller]

From: Peter Griffin <peter.griffin@linaro.org>
Date: Wed,  7 Jan 2015 15:04:05 +0000

> A V2 of this old series incorporating Arnd and Lees Feedback form v1.
> 
> Following on from Arnds comments about the picophy driver here
> https://lkml.org/lkml/2014/11/13/161, this series fixes the
> remaining upstreamed drivers for STI, which are mixing address spaces
> in the reg property. We do this in a way similar to the keystone
> and bcm7445 platforms, by having sysconfig phandle/ offset pair 
> (where only one register is required). Or phandle / integer array
> where multiple offsets in the same bank are needed).
> 
> This series breaks DT compatability! But the platform support
> is WIP and only being used by the few developers who are upstreaming
> support for it. I've made each change to the driver / dt doc / dt
> file as a single atomic commit so the kernel will remain bisectable. 
> 
> This series then also enables the picophy driver, and adds back in
> the ehci/ohci dt nodes for stih410 which make use of the picophy.

Series applied to net-next, thanks.

Re: [PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[David Miller]

From: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Date: Wed,  7 Jan 2015 15:04:05 +0000

> A V2 of this old series incorporating Arnd and Lees Feedback form v1.
> 
> Following on from Arnds comments about the picophy driver here
> https://lkml.org/lkml/2014/11/13/161, this series fixes the
> remaining upstreamed drivers for STI, which are mixing address spaces
> in the reg property. We do this in a way similar to the keystone
> and bcm7445 platforms, by having sysconfig phandle/ offset pair 
> (where only one register is required). Or phandle / integer array
> where multiple offsets in the same bank are needed).
> 
> This series breaks DT compatability! But the platform support
> is WIP and only being used by the few developers who are upstreaming
> support for it. I've made each change to the driver / dt doc / dt
> file as a single atomic commit so the kernel will remain bisectable. 
> 
> This series then also enables the picophy driver, and adds back in
> the ehci/ohci dt nodes for stih410 which make use of the picophy.

Series applied to net-next, thanks.
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[PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[David Miller]

From: Peter Griffin <peter.griffin@linaro.org>
Date: Wed,  7 Jan 2015 15:04:05 +0000

> A V2 of this old series incorporating Arnd and Lees Feedback form v1.
> 
> Following on from Arnds comments about the picophy driver here
> https://lkml.org/lkml/2014/11/13/161, this series fixes the
> remaining upstreamed drivers for STI, which are mixing address spaces
> in the reg property. We do this in a way similar to the keystone
> and bcm7445 platforms, by having sysconfig phandle/ offset pair 
> (where only one register is required). Or phandle / integer array
> where multiple offsets in the same bank are needed).
> 
> This series breaks DT compatability! But the platform support
> is WIP and only being used by the few developers who are upstreaming
> support for it. I've made each change to the driver / dt doc / dt
> file as a single atomic commit so the kernel will remain bisectable. 
> 
> This series then also enables the picophy driver, and adds back in
> the ehci/ohci dt nodes for stih410 which make use of the picophy.

Series applied to net-next, thanks.

Re: [PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[Maxime Coquelin]

Hi David,
On 01/12/2015 12:54 AM, David Miller wrote:
> From: Peter Griffin <peter.griffin@linaro.org>
> Date: Wed,  7 Jan 2015 15:04:05 +0000
>
>> A V2 of this old series incorporating Arnd and Lees Feedback form v1.
>>
>> Following on from Arnds comments about the picophy driver here
>> https://lkml.org/lkml/2014/11/13/161, this series fixes the
>> remaining upstreamed drivers for STI, which are mixing address spaces
>> in the reg property. We do this in a way similar to the keystone
>> and bcm7445 platforms, by having sysconfig phandle/ offset pair
>> (where only one register is required). Or phandle / integer array
>> where multiple offsets in the same bank are needed).
>>
>> This series breaks DT compatability! But the platform support
>> is WIP and only being used by the few developers who are upstreaming
>> support for it. I've made each change to the driver / dt doc / dt
>> file as a single atomic commit so the kernel will remain bisectable.
>>
>> This series then also enables the picophy driver, and adds back in
>> the ehci/ohci dt nodes for stih410 which make use of the picophy.
> Series applied to net-next, thanks.
Did you apply all the series to net-next?

I need the DT patches in STi SoC tree, that will go to Linus tree via 
arm-soc, hopefully for v3.20.

How could we synchronize?
Maybe I could create an immutable tag on top of STi DT branch, which is 
based on top of v3.19-rc1,
that you would merge in your tree?

Please let me know your preferred way.

Thanks,
Maxime

Re: [PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[Maxime Coquelin]

Hi David,
On 01/12/2015 12:54 AM, David Miller wrote:
> From: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Date: Wed,  7 Jan 2015 15:04:05 +0000
>
>> A V2 of this old series incorporating Arnd and Lees Feedback form v1.
>>
>> Following on from Arnds comments about the picophy driver here
>> https://lkml.org/lkml/2014/11/13/161, this series fixes the
>> remaining upstreamed drivers for STI, which are mixing address spaces
>> in the reg property. We do this in a way similar to the keystone
>> and bcm7445 platforms, by having sysconfig phandle/ offset pair
>> (where only one register is required). Or phandle / integer array
>> where multiple offsets in the same bank are needed).
>>
>> This series breaks DT compatability! But the platform support
>> is WIP and only being used by the few developers who are upstreaming
>> support for it. I've made each change to the driver / dt doc / dt
>> file as a single atomic commit so the kernel will remain bisectable.
>>
>> This series then also enables the picophy driver, and adds back in
>> the ehci/ohci dt nodes for stih410 which make use of the picophy.
> Series applied to net-next, thanks.
Did you apply all the series to net-next?

I need the DT patches in STi SoC tree, that will go to Linus tree via 
arm-soc, hopefully for v3.20.

How could we synchronize?
Maybe I could create an immutable tag on top of STi DT branch, which is 
based on top of v3.19-rc1,
that you would merge in your tree?

Please let me know your preferred way.

Thanks,
Maxime

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Re: [PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[Maxime Coquelin]

Hi David,
On 01/12/2015 12:54 AM, David Miller wrote:
> From: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Date: Wed,  7 Jan 2015 15:04:05 +0000
>
>> A V2 of this old series incorporating Arnd and Lees Feedback form v1.
>>
>> Following on from Arnds comments about the picophy driver here
>> https://lkml.org/lkml/2014/11/13/161, this series fixes the
>> remaining upstreamed drivers for STI, which are mixing address spaces
>> in the reg property. We do this in a way similar to the keystone
>> and bcm7445 platforms, by having sysconfig phandle/ offset pair
>> (where only one register is required). Or phandle / integer array
>> where multiple offsets in the same bank are needed).
>>
>> This series breaks DT compatability! But the platform support
>> is WIP and only being used by the few developers who are upstreaming
>> support for it. I've made each change to the driver / dt doc / dt
>> file as a single atomic commit so the kernel will remain bisectable.
>>
>> This series then also enables the picophy driver, and adds back in
>> the ehci/ohci dt nodes for stih410 which make use of the picophy.
> Series applied to net-next, thanks.
Did you apply all the series to net-next?

I need the DT patches in STi SoC tree, that will go to Linus tree via 
arm-soc, hopefully for v3.20.

How could we synchronize?
Maybe I could create an immutable tag on top of STi DT branch, which is 
based on top of v3.19-rc1,
that you would merge in your tree?

Please let me know your preferred way.

Thanks,
Maxime

--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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[PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[Maxime Coquelin]

Hi David,
On 01/12/2015 12:54 AM, David Miller wrote:
> From: Peter Griffin <peter.griffin@linaro.org>
> Date: Wed,  7 Jan 2015 15:04:05 +0000
>
>> A V2 of this old series incorporating Arnd and Lees Feedback form v1.
>>
>> Following on from Arnds comments about the picophy driver here
>> https://lkml.org/lkml/2014/11/13/161, this series fixes the
>> remaining upstreamed drivers for STI, which are mixing address spaces
>> in the reg property. We do this in a way similar to the keystone
>> and bcm7445 platforms, by having sysconfig phandle/ offset pair
>> (where only one register is required). Or phandle / integer array
>> where multiple offsets in the same bank are needed).
>>
>> This series breaks DT compatability! But the platform support
>> is WIP and only being used by the few developers who are upstreaming
>> support for it. I've made each change to the driver / dt doc / dt
>> file as a single atomic commit so the kernel will remain bisectable.
>>
>> This series then also enables the picophy driver, and adds back in
>> the ehci/ohci dt nodes for stih410 which make use of the picophy.
> Series applied to net-next, thanks.
Did you apply all the series to net-next?

I need the DT patches in STi SoC tree, that will go to Linus tree via 
arm-soc, hopefully for v3.20.

How could we synchronize?
Maybe I could create an immutable tag on top of STi DT branch, which is 
based on top of v3.19-rc1,
that you would merge in your tree?

Please let me know your preferred way.

Thanks,
Maxime

Re: [PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[Kishon Vijay Abraham I]

Hi,

On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
> Hi folks,
> 
> A V2 of this old series incorporating Arnd and Lees Feedback form v1.
> 
> Following on from Arnds comments about the picophy driver here
> https://lkml.org/lkml/2014/11/13/161, this series fixes the
> remaining upstreamed drivers for STI, which are mixing address spaces
> in the reg property. We do this in a way similar to the keystone
> and bcm7445 platforms, by having sysconfig phandle/ offset pair 
> (where only one register is required). Or phandle / integer array
> where multiple offsets in the same bank are needed).
> 
> This series breaks DT compatability! But the platform support
> is WIP and only being used by the few developers who are upstreaming
> support for it. I've made each change to the driver / dt doc / dt
> file as a single atomic commit so the kernel will remain bisectable. 
> 
> This series then also enables the picophy driver, and adds back in
> the ehci/ohci dt nodes for stih410 which make use of the picophy.
> 
> regards,
> 
> Peter.
> 
> Changes since v1:
> - Add missing space after */ (Lee)
> - Change comment to "indexed from" rather than "not indexed from" (Lee)
> - Change naming to phy1, phy2 rather than phy@1 phy@2 if there is no reg property (Arnd / Grant)
> - Rebased on v3.19-rc3 (me)
> - Checkpatch "no space before tabs" warning in stih41*.dtsi (me)
> 
> Peter Griffin (7):
>   phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg
>     property.
>   phy: miphy365x: Pass sysconfig register offsets via syscfg dt
>     property.
>   ARM: STi: DT: STiH407: Add usb2 picophy dt nodes
>   ARM: STi: DT: STiH410: Add usb2 picophy dt nodes
>   ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb
>     controllers.
>   ARM: multi_v7_defconfig: Enable stih407 usb picophy
>   stmmac: dwmac-sti: Pass sysconfig register offset via syscon dt
>     property.
> 
>  .../devicetree/bindings/net/sti-dwmac.txt          | 14 ++---
>  .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 ++---
>  .../devicetree/bindings/phy/phy-stih407-usb.txt    | 10 +---
>  arch/arm/boot/dts/stih407-family.dtsi              |  9 +++
>  arch/arm/boot/dts/stih410.dtsi                     | 70 ++++++++++++++++++++++
>  arch/arm/boot/dts/stih415.dtsi                     | 12 ++--
>  arch/arm/boot/dts/stih416.dtsi                     | 22 +++----
>  arch/arm/configs/multi_v7_defconfig                |  1 +
>  drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c    | 13 ++--
>  drivers/phy/phy-miphy365x.c                        | 29 ++++-----
>  drivers/phy/phy-stih407-usb.c                      | 25 ++++----
>  11 files changed, 143 insertions(+), 77 deletions(-)
> 

Queued the first two patches of this series in linux-phy.

Thanks
Kishon

Re: [PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[Kishon Vijay Abraham I]

Hi,

On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
> Hi folks,
> 
> A V2 of this old series incorporating Arnd and Lees Feedback form v1.
> 
> Following on from Arnds comments about the picophy driver here
> https://lkml.org/lkml/2014/11/13/161, this series fixes the
> remaining upstreamed drivers for STI, which are mixing address spaces
> in the reg property. We do this in a way similar to the keystone
> and bcm7445 platforms, by having sysconfig phandle/ offset pair 
> (where only one register is required). Or phandle / integer array
> where multiple offsets in the same bank are needed).
> 
> This series breaks DT compatability! But the platform support
> is WIP and only being used by the few developers who are upstreaming
> support for it. I've made each change to the driver / dt doc / dt
> file as a single atomic commit so the kernel will remain bisectable. 
> 
> This series then also enables the picophy driver, and adds back in
> the ehci/ohci dt nodes for stih410 which make use of the picophy.
> 
> regards,
> 
> Peter.
> 
> Changes since v1:
> - Add missing space after */ (Lee)
> - Change comment to "indexed from" rather than "not indexed from" (Lee)
> - Change naming to phy1, phy2 rather than phy@1 phy@2 if there is no reg property (Arnd / Grant)
> - Rebased on v3.19-rc3 (me)
> - Checkpatch "no space before tabs" warning in stih41*.dtsi (me)
> 
> Peter Griffin (7):
>   phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg
>     property.
>   phy: miphy365x: Pass sysconfig register offsets via syscfg dt
>     property.
>   ARM: STi: DT: STiH407: Add usb2 picophy dt nodes
>   ARM: STi: DT: STiH410: Add usb2 picophy dt nodes
>   ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb
>     controllers.
>   ARM: multi_v7_defconfig: Enable stih407 usb picophy
>   stmmac: dwmac-sti: Pass sysconfig register offset via syscon dt
>     property.
> 
>  .../devicetree/bindings/net/sti-dwmac.txt          | 14 ++---
>  .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 ++---
>  .../devicetree/bindings/phy/phy-stih407-usb.txt    | 10 +---
>  arch/arm/boot/dts/stih407-family.dtsi              |  9 +++
>  arch/arm/boot/dts/stih410.dtsi                     | 70 ++++++++++++++++++++++
>  arch/arm/boot/dts/stih415.dtsi                     | 12 ++--
>  arch/arm/boot/dts/stih416.dtsi                     | 22 +++----
>  arch/arm/configs/multi_v7_defconfig                |  1 +
>  drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c    | 13 ++--
>  drivers/phy/phy-miphy365x.c                        | 29 ++++-----
>  drivers/phy/phy-stih407-usb.c                      | 25 ++++----
>  11 files changed, 143 insertions(+), 77 deletions(-)
> 

Queued the first two patches of this series in linux-phy.

Thanks
Kishon

[PATCH v2 0/7] Fix sti drivers whcih mix reg address spaces

[Kishon Vijay Abraham I]

Hi,

On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
> Hi folks,
> 
> A V2 of this old series incorporating Arnd and Lees Feedback form v1.
> 
> Following on from Arnds comments about the picophy driver here
> https://lkml.org/lkml/2014/11/13/161, this series fixes the
> remaining upstreamed drivers for STI, which are mixing address spaces
> in the reg property. We do this in a way similar to the keystone
> and bcm7445 platforms, by having sysconfig phandle/ offset pair 
> (where only one register is required). Or phandle / integer array
> where multiple offsets in the same bank are needed).
> 
> This series breaks DT compatability! But the platform support
> is WIP and only being used by the few developers who are upstreaming
> support for it. I've made each change to the driver / dt doc / dt
> file as a single atomic commit so the kernel will remain bisectable. 
> 
> This series then also enables the picophy driver, and adds back in
> the ehci/ohci dt nodes for stih410 which make use of the picophy.
> 
> regards,
> 
> Peter.
> 
> Changes since v1:
> - Add missing space after */ (Lee)
> - Change comment to "indexed from" rather than "not indexed from" (Lee)
> - Change naming to phy1, phy2 rather than phy at 1 phy at 2 if there is no reg property (Arnd / Grant)
> - Rebased on v3.19-rc3 (me)
> - Checkpatch "no space before tabs" warning in stih41*.dtsi (me)
> 
> Peter Griffin (7):
>   phy: phy-stih407-usb: Pass sysconfig register offsets via syscfg
>     property.
>   phy: miphy365x: Pass sysconfig register offsets via syscfg dt
>     property.
>   ARM: STi: DT: STiH407: Add usb2 picophy dt nodes
>   ARM: STi: DT: STiH410: Add usb2 picophy dt nodes
>   ARM: STi: DT: STiH410: Add DT nodes for the ehci and ohci usb
>     controllers.
>   ARM: multi_v7_defconfig: Enable stih407 usb picophy
>   stmmac: dwmac-sti: Pass sysconfig register offset via syscon dt
>     property.
> 
>  .../devicetree/bindings/net/sti-dwmac.txt          | 14 ++---
>  .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 ++---
>  .../devicetree/bindings/phy/phy-stih407-usb.txt    | 10 +---
>  arch/arm/boot/dts/stih407-family.dtsi              |  9 +++
>  arch/arm/boot/dts/stih410.dtsi                     | 70 ++++++++++++++++++++++
>  arch/arm/boot/dts/stih415.dtsi                     | 12 ++--
>  arch/arm/boot/dts/stih416.dtsi                     | 22 +++----
>  arch/arm/configs/multi_v7_defconfig                |  1 +
>  drivers/net/ethernet/stmicro/stmmac/dwmac-sti.c    | 13 ++--
>  drivers/phy/phy-miphy365x.c                        | 29 ++++-----
>  drivers/phy/phy-stih407-usb.c                      | 25 ++++----
>  11 files changed, 143 insertions(+), 77 deletions(-)
> 

Queued the first two patches of this series in linux-phy.

Thanks
Kishon

Re: [PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Kishon Vijay Abraham I]

Hi,

On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
> Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
> update the miphy365 phy driver to access sysconfig register offsets via
> syscfg dt property.
> 
> This is because the reg property should not be mixing address spaces
> like it does currently for miphy365. This change then also aligns us
> to how other platforms such as keystone and bcm7445 pass there syscon
> offsets via DT.
> 
> This patch breaks DT compatibility, but this platform is considered WIP,
> and is only used by a few developers who are upstreaming support for it.
> This change has been done as a single atomic commit to ensure it is
> bisectable.

I'm dropping this from my tree since I didn't get Ack from
"arch/arm/boot/dts/stih416.dtsi" Maintainer.

Thanks
Kishon
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
> ---
>  .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
>  arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
>  drivers/phy/phy-miphy365x.c                        | 29 ++++++++--------------
>  3 files changed, 23 insertions(+), 31 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> index 42c8808..9802d5d 100644
> --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> @@ -6,8 +6,10 @@ for SATA and PCIe.
>  
>  Required properties (controller (parent) node):
>  - compatible    : Should be "st,miphy365x-phy"
> -- st,syscfg     : Should be a phandle of the system configuration register group
> -		  which contain the SATA, PCIe mode setting bits
> +- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
> +		  containing the miphy registers and integer array should contain
> +		  an entry for each port sub-node, specifying the control
> +		  register offset inside the sysconfig group.
>  
>  Required nodes	:  A sub-node is required for each channel the controller
>  		   provides. Address range information including the usual
> @@ -26,7 +28,6 @@ Required properties (port (child) node):
>  		  registers filled in "reg":
>  			- sata:   For SATA devices
>  			- pcie:   For PCIe devices
> -			- syscfg: To specify the syscfg based config register
>  
>  Optional properties (port (child) node):
>  - st,sata-gen	     :	Generation of locally attached SATA IP. Expected values
> @@ -39,20 +40,20 @@ Example:
>  
>  	miphy365x_phy: miphy365x@fe382000 {
>  		compatible      = "st,miphy365x-phy";
> -		st,syscfg  	= <&syscfg_rear>;
> +		st,syscfg  	= <&syscfg_rear 0x824 0x828>;
>  		#address-cells	= <1>;
>  		#size-cells	= <1>;
>  		ranges;
>  
>  		phy_port0: port@fe382000 {
> -			reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
> -			reg-names = "sata", "pcie", "syscfg";
> +			reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
> +			reg-names = "sata", "pcie";
>  			#phy-cells = <1>;
>  			st,sata-gen = <3>;
>  		};
>  
>  		phy_port1: port@fe38a000 {
> -			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
> +			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
>  			reg-names = "sata", "pcie", "syscfg";
>  			#phy-cells = <1>;
>  			st,pcie-tx-pol-inv;
> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
> index fad9073..85afe01 100644
> --- a/arch/arm/boot/dts/stih416.dtsi
> +++ b/arch/arm/boot/dts/stih416.dtsi
> @@ -283,21 +283,21 @@
>  
>  		miphy365x_phy: phy@fe382000 {
>  			compatible      = "st,miphy365x-phy";
> -			st,syscfg  	= <&syscfg_rear>;
> +			st,syscfg	= <&syscfg_rear 0x824 0x828>;
>  			#address-cells	= <1>;
>  			#size-cells	= <1>;
>  			ranges;
>  
>  			phy_port0: port@fe382000 {
>  				#phy-cells = <1>;
> -				reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
> -				reg-names = "sata", "pcie", "syscfg";
> +				reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
> +				reg-names = "sata", "pcie";
>  			};
>  
>  			phy_port1: port@fe38a000 {
>  				#phy-cells = <1>;
> -				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
> -				reg-names = "sata", "pcie", "syscfg";
> +				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
> +				reg-names = "sata", "pcie";
>  			};
>  		};
>  
> diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
> index 6ab43a8..6c80154 100644
> --- a/drivers/phy/phy-miphy365x.c
> +++ b/drivers/phy/phy-miphy365x.c
> @@ -141,7 +141,7 @@ struct miphy365x_phy {
>  	bool pcie_tx_pol_inv;
>  	bool sata_tx_pol_inv;
>  	u32 sata_gen;
> -	u64 ctrlreg;
> +	u32 ctrlreg;
>  	u8 type;
>  };
>  
> @@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
>  	bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
>  
>  	return regmap_update_bits(miphy_dev->regmap,
> -				  (unsigned int)miphy_phy->ctrlreg,
> +				  miphy_phy->ctrlreg,
>  				  SYSCFG_SELECT_SATA_MASK,
>  				  sata << SYSCFG_SELECT_SATA_POS);
>  }
> @@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
>  {
>  	struct device_node *phynode = miphy_phy->phy->dev.of_node;
>  	const char *name;
> -	const __be32 *taddr;
>  	int type = miphy_phy->type;
>  	int ret;
>  
> @@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
>  		return ret;
>  	}
>  
> -	if (!strncmp(name, "syscfg", 6)) {
> -		taddr = of_get_address(phynode, index, NULL, NULL);
> -		if (!taddr) {
> -			dev_err(dev, "failed to fetch syscfg address\n");
> -			return -EINVAL;
> -		}
> -
> -		miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
> -		if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
> -			dev_err(dev, "failed to translate syscfg address\n");
> -			return -EINVAL;
> -		}
> -
> -		return 0;
> -	}
> -
>  	if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
>  	      (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
>  		return 0;
> @@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
>  			return ret;
>  
>  		phy_set_drvdata(phy, miphy_dev->phys[port]);
> +
>  		port++;
> +		/* sysconfig offsets are indexed from 1 */
> +		ret = of_property_read_u32_index(np, "st,syscfg", port,
> +					&miphy_phy->ctrlreg);
> +		if (ret) {
> +			dev_err(&pdev->dev, "No sysconfig offset found\n");
> +			return ret;
> +		}
>  	}
>  
>  	provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
> 

Re: [PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Kishon Vijay Abraham I]

Hi,

On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
> Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
> update the miphy365 phy driver to access sysconfig register offsets via
> syscfg dt property.
> 
> This is because the reg property should not be mixing address spaces
> like it does currently for miphy365. This change then also aligns us
> to how other platforms such as keystone and bcm7445 pass there syscon
> offsets via DT.
> 
> This patch breaks DT compatibility, but this platform is considered WIP,
> and is only used by a few developers who are upstreaming support for it.
> This change has been done as a single atomic commit to ensure it is
> bisectable.

I'm dropping this from my tree since I didn't get Ack from
"arch/arm/boot/dts/stih416.dtsi" Maintainer.

Thanks
Kishon
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
> ---
>  .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
>  arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
>  drivers/phy/phy-miphy365x.c                        | 29 ++++++++--------------
>  3 files changed, 23 insertions(+), 31 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> index 42c8808..9802d5d 100644
> --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> @@ -6,8 +6,10 @@ for SATA and PCIe.
>  
>  Required properties (controller (parent) node):
>  - compatible    : Should be "st,miphy365x-phy"
> -- st,syscfg     : Should be a phandle of the system configuration register group
> -		  which contain the SATA, PCIe mode setting bits
> +- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
> +		  containing the miphy registers and integer array should contain
> +		  an entry for each port sub-node, specifying the control
> +		  register offset inside the sysconfig group.
>  
>  Required nodes	:  A sub-node is required for each channel the controller
>  		   provides. Address range information including the usual
> @@ -26,7 +28,6 @@ Required properties (port (child) node):
>  		  registers filled in "reg":
>  			- sata:   For SATA devices
>  			- pcie:   For PCIe devices
> -			- syscfg: To specify the syscfg based config register
>  
>  Optional properties (port (child) node):
>  - st,sata-gen	     :	Generation of locally attached SATA IP. Expected values
> @@ -39,20 +40,20 @@ Example:
>  
>  	miphy365x_phy: miphy365x@fe382000 {
>  		compatible      = "st,miphy365x-phy";
> -		st,syscfg  	= <&syscfg_rear>;
> +		st,syscfg  	= <&syscfg_rear 0x824 0x828>;
>  		#address-cells	= <1>;
>  		#size-cells	= <1>;
>  		ranges;
>  
>  		phy_port0: port@fe382000 {
> -			reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
> -			reg-names = "sata", "pcie", "syscfg";
> +			reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
> +			reg-names = "sata", "pcie";
>  			#phy-cells = <1>;
>  			st,sata-gen = <3>;
>  		};
>  
>  		phy_port1: port@fe38a000 {
> -			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
> +			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
>  			reg-names = "sata", "pcie", "syscfg";
>  			#phy-cells = <1>;
>  			st,pcie-tx-pol-inv;
> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
> index fad9073..85afe01 100644
> --- a/arch/arm/boot/dts/stih416.dtsi
> +++ b/arch/arm/boot/dts/stih416.dtsi
> @@ -283,21 +283,21 @@
>  
>  		miphy365x_phy: phy@fe382000 {
>  			compatible      = "st,miphy365x-phy";
> -			st,syscfg  	= <&syscfg_rear>;
> +			st,syscfg	= <&syscfg_rear 0x824 0x828>;
>  			#address-cells	= <1>;
>  			#size-cells	= <1>;
>  			ranges;
>  
>  			phy_port0: port@fe382000 {
>  				#phy-cells = <1>;
> -				reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
> -				reg-names = "sata", "pcie", "syscfg";
> +				reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
> +				reg-names = "sata", "pcie";
>  			};
>  
>  			phy_port1: port@fe38a000 {
>  				#phy-cells = <1>;
> -				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
> -				reg-names = "sata", "pcie", "syscfg";
> +				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
> +				reg-names = "sata", "pcie";
>  			};
>  		};
>  
> diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
> index 6ab43a8..6c80154 100644
> --- a/drivers/phy/phy-miphy365x.c
> +++ b/drivers/phy/phy-miphy365x.c
> @@ -141,7 +141,7 @@ struct miphy365x_phy {
>  	bool pcie_tx_pol_inv;
>  	bool sata_tx_pol_inv;
>  	u32 sata_gen;
> -	u64 ctrlreg;
> +	u32 ctrlreg;
>  	u8 type;
>  };
>  
> @@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
>  	bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
>  
>  	return regmap_update_bits(miphy_dev->regmap,
> -				  (unsigned int)miphy_phy->ctrlreg,
> +				  miphy_phy->ctrlreg,
>  				  SYSCFG_SELECT_SATA_MASK,
>  				  sata << SYSCFG_SELECT_SATA_POS);
>  }
> @@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
>  {
>  	struct device_node *phynode = miphy_phy->phy->dev.of_node;
>  	const char *name;
> -	const __be32 *taddr;
>  	int type = miphy_phy->type;
>  	int ret;
>  
> @@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
>  		return ret;
>  	}
>  
> -	if (!strncmp(name, "syscfg", 6)) {
> -		taddr = of_get_address(phynode, index, NULL, NULL);
> -		if (!taddr) {
> -			dev_err(dev, "failed to fetch syscfg address\n");
> -			return -EINVAL;
> -		}
> -
> -		miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
> -		if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
> -			dev_err(dev, "failed to translate syscfg address\n");
> -			return -EINVAL;
> -		}
> -
> -		return 0;
> -	}
> -
>  	if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
>  	      (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
>  		return 0;
> @@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
>  			return ret;
>  
>  		phy_set_drvdata(phy, miphy_dev->phys[port]);
> +
>  		port++;
> +		/* sysconfig offsets are indexed from 1 */
> +		ret = of_property_read_u32_index(np, "st,syscfg", port,
> +					&miphy_phy->ctrlreg);
> +		if (ret) {
> +			dev_err(&pdev->dev, "No sysconfig offset found\n");
> +			return ret;
> +		}
>  	}
>  
>  	provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
> 

[PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Kishon Vijay Abraham I]

Hi,

On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
> Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
> update the miphy365 phy driver to access sysconfig register offsets via
> syscfg dt property.
> 
> This is because the reg property should not be mixing address spaces
> like it does currently for miphy365. This change then also aligns us
> to how other platforms such as keystone and bcm7445 pass there syscon
> offsets via DT.
> 
> This patch breaks DT compatibility, but this platform is considered WIP,
> and is only used by a few developers who are upstreaming support for it.
> This change has been done as a single atomic commit to ensure it is
> bisectable.

I'm dropping this from my tree since I didn't get Ack from
"arch/arm/boot/dts/stih416.dtsi" Maintainer.

Thanks
Kishon
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
> ---
>  .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
>  arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
>  drivers/phy/phy-miphy365x.c                        | 29 ++++++++--------------
>  3 files changed, 23 insertions(+), 31 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> index 42c8808..9802d5d 100644
> --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
> @@ -6,8 +6,10 @@ for SATA and PCIe.
>  
>  Required properties (controller (parent) node):
>  - compatible    : Should be "st,miphy365x-phy"
> -- st,syscfg     : Should be a phandle of the system configuration register group
> -		  which contain the SATA, PCIe mode setting bits
> +- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
> +		  containing the miphy registers and integer array should contain
> +		  an entry for each port sub-node, specifying the control
> +		  register offset inside the sysconfig group.
>  
>  Required nodes	:  A sub-node is required for each channel the controller
>  		   provides. Address range information including the usual
> @@ -26,7 +28,6 @@ Required properties (port (child) node):
>  		  registers filled in "reg":
>  			- sata:   For SATA devices
>  			- pcie:   For PCIe devices
> -			- syscfg: To specify the syscfg based config register
>  
>  Optional properties (port (child) node):
>  - st,sata-gen	     :	Generation of locally attached SATA IP. Expected values
> @@ -39,20 +40,20 @@ Example:
>  
>  	miphy365x_phy: miphy365x at fe382000 {
>  		compatible      = "st,miphy365x-phy";
> -		st,syscfg  	= <&syscfg_rear>;
> +		st,syscfg  	= <&syscfg_rear 0x824 0x828>;
>  		#address-cells	= <1>;
>  		#size-cells	= <1>;
>  		ranges;
>  
>  		phy_port0: port at fe382000 {
> -			reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
> -			reg-names = "sata", "pcie", "syscfg";
> +			reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
> +			reg-names = "sata", "pcie";
>  			#phy-cells = <1>;
>  			st,sata-gen = <3>;
>  		};
>  
>  		phy_port1: port at fe38a000 {
> -			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
> +			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
>  			reg-names = "sata", "pcie", "syscfg";
>  			#phy-cells = <1>;
>  			st,pcie-tx-pol-inv;
> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
> index fad9073..85afe01 100644
> --- a/arch/arm/boot/dts/stih416.dtsi
> +++ b/arch/arm/boot/dts/stih416.dtsi
> @@ -283,21 +283,21 @@
>  
>  		miphy365x_phy: phy at fe382000 {
>  			compatible      = "st,miphy365x-phy";
> -			st,syscfg  	= <&syscfg_rear>;
> +			st,syscfg	= <&syscfg_rear 0x824 0x828>;
>  			#address-cells	= <1>;
>  			#size-cells	= <1>;
>  			ranges;
>  
>  			phy_port0: port at fe382000 {
>  				#phy-cells = <1>;
> -				reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
> -				reg-names = "sata", "pcie", "syscfg";
> +				reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
> +				reg-names = "sata", "pcie";
>  			};
>  
>  			phy_port1: port at fe38a000 {
>  				#phy-cells = <1>;
> -				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
> -				reg-names = "sata", "pcie", "syscfg";
> +				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
> +				reg-names = "sata", "pcie";
>  			};
>  		};
>  
> diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
> index 6ab43a8..6c80154 100644
> --- a/drivers/phy/phy-miphy365x.c
> +++ b/drivers/phy/phy-miphy365x.c
> @@ -141,7 +141,7 @@ struct miphy365x_phy {
>  	bool pcie_tx_pol_inv;
>  	bool sata_tx_pol_inv;
>  	u32 sata_gen;
> -	u64 ctrlreg;
> +	u32 ctrlreg;
>  	u8 type;
>  };
>  
> @@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
>  	bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
>  
>  	return regmap_update_bits(miphy_dev->regmap,
> -				  (unsigned int)miphy_phy->ctrlreg,
> +				  miphy_phy->ctrlreg,
>  				  SYSCFG_SELECT_SATA_MASK,
>  				  sata << SYSCFG_SELECT_SATA_POS);
>  }
> @@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
>  {
>  	struct device_node *phynode = miphy_phy->phy->dev.of_node;
>  	const char *name;
> -	const __be32 *taddr;
>  	int type = miphy_phy->type;
>  	int ret;
>  
> @@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
>  		return ret;
>  	}
>  
> -	if (!strncmp(name, "syscfg", 6)) {
> -		taddr = of_get_address(phynode, index, NULL, NULL);
> -		if (!taddr) {
> -			dev_err(dev, "failed to fetch syscfg address\n");
> -			return -EINVAL;
> -		}
> -
> -		miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
> -		if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
> -			dev_err(dev, "failed to translate syscfg address\n");
> -			return -EINVAL;
> -		}
> -
> -		return 0;
> -	}
> -
>  	if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
>  	      (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
>  		return 0;
> @@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
>  			return ret;
>  
>  		phy_set_drvdata(phy, miphy_dev->phys[port]);
> +
>  		port++;
> +		/* sysconfig offsets are indexed from 1 */
> +		ret = of_property_read_u32_index(np, "st,syscfg", port,
> +					&miphy_phy->ctrlreg);
> +		if (ret) {
> +			dev_err(&pdev->dev, "No sysconfig offset found\n");
> +			return ret;
> +		}
>  	}
>  
>  	provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
> 

Re: [PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Maxime Coquelin]

Hi Kishon,

On 01/30/2015 11:35 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
>> Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
>> update the miphy365 phy driver to access sysconfig register offsets via
>> syscfg dt property.
>>
>> This is because the reg property should not be mixing address spaces
>> like it does currently for miphy365. This change then also aligns us
>> to how other platforms such as keystone and bcm7445 pass there syscon
>> offsets via DT.
>>
>> This patch breaks DT compatibility, but this platform is considered WIP,
>> and is only used by a few developers who are upstreaming support for it.
>> This change has been done as a single atomic commit to ensure it is
>> bisectable.
> I'm dropping this from my tree since I didn't get Ack from
> "arch/arm/boot/dts/stih416.dtsi" Maintainer.
Sorry, on cover letter, I replied the series looked good to me.
So you can add:

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

And even:

Tested-by: Maxime Coquelin <maxime.coquelin@st.com>

Kind regards,
Maxime

>
> Thanks
> Kishon
>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>> ---
>>   .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
>>   arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
>>   drivers/phy/phy-miphy365x.c                        | 29 ++++++++--------------
>>   3 files changed, 23 insertions(+), 31 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>> index 42c8808..9802d5d 100644
>> --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>> @@ -6,8 +6,10 @@ for SATA and PCIe.
>>   
>>   Required properties (controller (parent) node):
>>   - compatible    : Should be "st,miphy365x-phy"
>> -- st,syscfg     : Should be a phandle of the system configuration register group
>> -		  which contain the SATA, PCIe mode setting bits
>> +- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
>> +		  containing the miphy registers and integer array should contain
>> +		  an entry for each port sub-node, specifying the control
>> +		  register offset inside the sysconfig group.
>>   
>>   Required nodes	:  A sub-node is required for each channel the controller
>>   		   provides. Address range information including the usual
>> @@ -26,7 +28,6 @@ Required properties (port (child) node):
>>   		  registers filled in "reg":
>>   			- sata:   For SATA devices
>>   			- pcie:   For PCIe devices
>> -			- syscfg: To specify the syscfg based config register
>>   
>>   Optional properties (port (child) node):
>>   - st,sata-gen	     :	Generation of locally attached SATA IP. Expected values
>> @@ -39,20 +40,20 @@ Example:
>>   
>>   	miphy365x_phy: miphy365x@fe382000 {
>>   		compatible      = "st,miphy365x-phy";
>> -		st,syscfg  	= <&syscfg_rear>;
>> +		st,syscfg  	= <&syscfg_rear 0x824 0x828>;
>>   		#address-cells	= <1>;
>>   		#size-cells	= <1>;
>>   		ranges;
>>   
>>   		phy_port0: port@fe382000 {
>> -			reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>> -			reg-names = "sata", "pcie", "syscfg";
>> +			reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>> +			reg-names = "sata", "pcie";
>>   			#phy-cells = <1>;
>>   			st,sata-gen = <3>;
>>   		};
>>   
>>   		phy_port1: port@fe38a000 {
>> -			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
>> +			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
>>   			reg-names = "sata", "pcie", "syscfg";
>>   			#phy-cells = <1>;
>>   			st,pcie-tx-pol-inv;
>> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
>> index fad9073..85afe01 100644
>> --- a/arch/arm/boot/dts/stih416.dtsi
>> +++ b/arch/arm/boot/dts/stih416.dtsi
>> @@ -283,21 +283,21 @@
>>   
>>   		miphy365x_phy: phy@fe382000 {
>>   			compatible      = "st,miphy365x-phy";
>> -			st,syscfg  	= <&syscfg_rear>;
>> +			st,syscfg	= <&syscfg_rear 0x824 0x828>;
>>   			#address-cells	= <1>;
>>   			#size-cells	= <1>;
>>   			ranges;
>>   
>>   			phy_port0: port@fe382000 {
>>   				#phy-cells = <1>;
>> -				reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>> -				reg-names = "sata", "pcie", "syscfg";
>> +				reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>> +				reg-names = "sata", "pcie";
>>   			};
>>   
>>   			phy_port1: port@fe38a000 {
>>   				#phy-cells = <1>;
>> -				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
>> -				reg-names = "sata", "pcie", "syscfg";
>> +				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
>> +				reg-names = "sata", "pcie";
>>   			};
>>   		};
>>   
>> diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
>> index 6ab43a8..6c80154 100644
>> --- a/drivers/phy/phy-miphy365x.c
>> +++ b/drivers/phy/phy-miphy365x.c
>> @@ -141,7 +141,7 @@ struct miphy365x_phy {
>>   	bool pcie_tx_pol_inv;
>>   	bool sata_tx_pol_inv;
>>   	u32 sata_gen;
>> -	u64 ctrlreg;
>> +	u32 ctrlreg;
>>   	u8 type;
>>   };
>>   
>> @@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
>>   	bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
>>   
>>   	return regmap_update_bits(miphy_dev->regmap,
>> -				  (unsigned int)miphy_phy->ctrlreg,
>> +				  miphy_phy->ctrlreg,
>>   				  SYSCFG_SELECT_SATA_MASK,
>>   				  sata << SYSCFG_SELECT_SATA_POS);
>>   }
>> @@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
>>   {
>>   	struct device_node *phynode = miphy_phy->phy->dev.of_node;
>>   	const char *name;
>> -	const __be32 *taddr;
>>   	int type = miphy_phy->type;
>>   	int ret;
>>   
>> @@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
>>   		return ret;
>>   	}
>>   
>> -	if (!strncmp(name, "syscfg", 6)) {
>> -		taddr = of_get_address(phynode, index, NULL, NULL);
>> -		if (!taddr) {
>> -			dev_err(dev, "failed to fetch syscfg address\n");
>> -			return -EINVAL;
>> -		}
>> -
>> -		miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
>> -		if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
>> -			dev_err(dev, "failed to translate syscfg address\n");
>> -			return -EINVAL;
>> -		}
>> -
>> -		return 0;
>> -	}
>> -
>>   	if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
>>   	      (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
>>   		return 0;
>> @@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
>>   			return ret;
>>   
>>   		phy_set_drvdata(phy, miphy_dev->phys[port]);
>> +
>>   		port++;
>> +		/* sysconfig offsets are indexed from 1 */
>> +		ret = of_property_read_u32_index(np, "st,syscfg", port,
>> +					&miphy_phy->ctrlreg);
>> +		if (ret) {
>> +			dev_err(&pdev->dev, "No sysconfig offset found\n");
>> +			return ret;
>> +		}
>>   	}
>>   
>>   	provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
>>

Re: [PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Maxime Coquelin]

Hi Kishon,

On 01/30/2015 11:35 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
>> Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
>> update the miphy365 phy driver to access sysconfig register offsets via
>> syscfg dt property.
>>
>> This is because the reg property should not be mixing address spaces
>> like it does currently for miphy365. This change then also aligns us
>> to how other platforms such as keystone and bcm7445 pass there syscon
>> offsets via DT.
>>
>> This patch breaks DT compatibility, but this platform is considered WIP,
>> and is only used by a few developers who are upstreaming support for it.
>> This change has been done as a single atomic commit to ensure it is
>> bisectable.
> I'm dropping this from my tree since I didn't get Ack from
> "arch/arm/boot/dts/stih416.dtsi" Maintainer.
Sorry, on cover letter, I replied the series looked good to me.
So you can add:

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

And even:

Tested-by: Maxime Coquelin <maxime.coquelin@st.com>

Kind regards,
Maxime

>
> Thanks
> Kishon
>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>> ---
>>   .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
>>   arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
>>   drivers/phy/phy-miphy365x.c                        | 29 ++++++++--------------
>>   3 files changed, 23 insertions(+), 31 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>> index 42c8808..9802d5d 100644
>> --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>> @@ -6,8 +6,10 @@ for SATA and PCIe.
>>   
>>   Required properties (controller (parent) node):
>>   - compatible    : Should be "st,miphy365x-phy"
>> -- st,syscfg     : Should be a phandle of the system configuration register group
>> -		  which contain the SATA, PCIe mode setting bits
>> +- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
>> +		  containing the miphy registers and integer array should contain
>> +		  an entry for each port sub-node, specifying the control
>> +		  register offset inside the sysconfig group.
>>   
>>   Required nodes	:  A sub-node is required for each channel the controller
>>   		   provides. Address range information including the usual
>> @@ -26,7 +28,6 @@ Required properties (port (child) node):
>>   		  registers filled in "reg":
>>   			- sata:   For SATA devices
>>   			- pcie:   For PCIe devices
>> -			- syscfg: To specify the syscfg based config register
>>   
>>   Optional properties (port (child) node):
>>   - st,sata-gen	     :	Generation of locally attached SATA IP. Expected values
>> @@ -39,20 +40,20 @@ Example:
>>   
>>   	miphy365x_phy: miphy365x@fe382000 {
>>   		compatible      = "st,miphy365x-phy";
>> -		st,syscfg  	= <&syscfg_rear>;
>> +		st,syscfg  	= <&syscfg_rear 0x824 0x828>;
>>   		#address-cells	= <1>;
>>   		#size-cells	= <1>;
>>   		ranges;
>>   
>>   		phy_port0: port@fe382000 {
>> -			reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>> -			reg-names = "sata", "pcie", "syscfg";
>> +			reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>> +			reg-names = "sata", "pcie";
>>   			#phy-cells = <1>;
>>   			st,sata-gen = <3>;
>>   		};
>>   
>>   		phy_port1: port@fe38a000 {
>> -			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
>> +			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
>>   			reg-names = "sata", "pcie", "syscfg";
>>   			#phy-cells = <1>;
>>   			st,pcie-tx-pol-inv;
>> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
>> index fad9073..85afe01 100644
>> --- a/arch/arm/boot/dts/stih416.dtsi
>> +++ b/arch/arm/boot/dts/stih416.dtsi
>> @@ -283,21 +283,21 @@
>>   
>>   		miphy365x_phy: phy@fe382000 {
>>   			compatible      = "st,miphy365x-phy";
>> -			st,syscfg  	= <&syscfg_rear>;
>> +			st,syscfg	= <&syscfg_rear 0x824 0x828>;
>>   			#address-cells	= <1>;
>>   			#size-cells	= <1>;
>>   			ranges;
>>   
>>   			phy_port0: port@fe382000 {
>>   				#phy-cells = <1>;
>> -				reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>> -				reg-names = "sata", "pcie", "syscfg";
>> +				reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>> +				reg-names = "sata", "pcie";
>>   			};
>>   
>>   			phy_port1: port@fe38a000 {
>>   				#phy-cells = <1>;
>> -				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
>> -				reg-names = "sata", "pcie", "syscfg";
>> +				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
>> +				reg-names = "sata", "pcie";
>>   			};
>>   		};
>>   
>> diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
>> index 6ab43a8..6c80154 100644
>> --- a/drivers/phy/phy-miphy365x.c
>> +++ b/drivers/phy/phy-miphy365x.c
>> @@ -141,7 +141,7 @@ struct miphy365x_phy {
>>   	bool pcie_tx_pol_inv;
>>   	bool sata_tx_pol_inv;
>>   	u32 sata_gen;
>> -	u64 ctrlreg;
>> +	u32 ctrlreg;
>>   	u8 type;
>>   };
>>   
>> @@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
>>   	bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
>>   
>>   	return regmap_update_bits(miphy_dev->regmap,
>> -				  (unsigned int)miphy_phy->ctrlreg,
>> +				  miphy_phy->ctrlreg,
>>   				  SYSCFG_SELECT_SATA_MASK,
>>   				  sata << SYSCFG_SELECT_SATA_POS);
>>   }
>> @@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
>>   {
>>   	struct device_node *phynode = miphy_phy->phy->dev.of_node;
>>   	const char *name;
>> -	const __be32 *taddr;
>>   	int type = miphy_phy->type;
>>   	int ret;
>>   
>> @@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
>>   		return ret;
>>   	}
>>   
>> -	if (!strncmp(name, "syscfg", 6)) {
>> -		taddr = of_get_address(phynode, index, NULL, NULL);
>> -		if (!taddr) {
>> -			dev_err(dev, "failed to fetch syscfg address\n");
>> -			return -EINVAL;
>> -		}
>> -
>> -		miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
>> -		if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
>> -			dev_err(dev, "failed to translate syscfg address\n");
>> -			return -EINVAL;
>> -		}
>> -
>> -		return 0;
>> -	}
>> -
>>   	if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
>>   	      (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
>>   		return 0;
>> @@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
>>   			return ret;
>>   
>>   		phy_set_drvdata(phy, miphy_dev->phys[port]);
>> +
>>   		port++;
>> +		/* sysconfig offsets are indexed from 1 */
>> +		ret = of_property_read_u32_index(np, "st,syscfg", port,
>> +					&miphy_phy->ctrlreg);
>> +		if (ret) {
>> +			dev_err(&pdev->dev, "No sysconfig offset found\n");
>> +			return ret;
>> +		}
>>   	}
>>   
>>   	provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
>>

[PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Maxime Coquelin]

Hi Kishon,

On 01/30/2015 11:35 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
>> Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
>> update the miphy365 phy driver to access sysconfig register offsets via
>> syscfg dt property.
>>
>> This is because the reg property should not be mixing address spaces
>> like it does currently for miphy365. This change then also aligns us
>> to how other platforms such as keystone and bcm7445 pass there syscon
>> offsets via DT.
>>
>> This patch breaks DT compatibility, but this platform is considered WIP,
>> and is only used by a few developers who are upstreaming support for it.
>> This change has been done as a single atomic commit to ensure it is
>> bisectable.
> I'm dropping this from my tree since I didn't get Ack from
> "arch/arm/boot/dts/stih416.dtsi" Maintainer.
Sorry, on cover letter, I replied the series looked good to me.
So you can add:

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

And even:

Tested-by: Maxime Coquelin <maxime.coquelin@st.com>

Kind regards,
Maxime

>
> Thanks
> Kishon
>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>> ---
>>   .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
>>   arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
>>   drivers/phy/phy-miphy365x.c                        | 29 ++++++++--------------
>>   3 files changed, 23 insertions(+), 31 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>> index 42c8808..9802d5d 100644
>> --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>> @@ -6,8 +6,10 @@ for SATA and PCIe.
>>   
>>   Required properties (controller (parent) node):
>>   - compatible    : Should be "st,miphy365x-phy"
>> -- st,syscfg     : Should be a phandle of the system configuration register group
>> -		  which contain the SATA, PCIe mode setting bits
>> +- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
>> +		  containing the miphy registers and integer array should contain
>> +		  an entry for each port sub-node, specifying the control
>> +		  register offset inside the sysconfig group.
>>   
>>   Required nodes	:  A sub-node is required for each channel the controller
>>   		   provides. Address range information including the usual
>> @@ -26,7 +28,6 @@ Required properties (port (child) node):
>>   		  registers filled in "reg":
>>   			- sata:   For SATA devices
>>   			- pcie:   For PCIe devices
>> -			- syscfg: To specify the syscfg based config register
>>   
>>   Optional properties (port (child) node):
>>   - st,sata-gen	     :	Generation of locally attached SATA IP. Expected values
>> @@ -39,20 +40,20 @@ Example:
>>   
>>   	miphy365x_phy: miphy365x at fe382000 {
>>   		compatible      = "st,miphy365x-phy";
>> -		st,syscfg  	= <&syscfg_rear>;
>> +		st,syscfg  	= <&syscfg_rear 0x824 0x828>;
>>   		#address-cells	= <1>;
>>   		#size-cells	= <1>;
>>   		ranges;
>>   
>>   		phy_port0: port at fe382000 {
>> -			reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>> -			reg-names = "sata", "pcie", "syscfg";
>> +			reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>> +			reg-names = "sata", "pcie";
>>   			#phy-cells = <1>;
>>   			st,sata-gen = <3>;
>>   		};
>>   
>>   		phy_port1: port at fe38a000 {
>> -			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
>> +			reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
>>   			reg-names = "sata", "pcie", "syscfg";
>>   			#phy-cells = <1>;
>>   			st,pcie-tx-pol-inv;
>> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
>> index fad9073..85afe01 100644
>> --- a/arch/arm/boot/dts/stih416.dtsi
>> +++ b/arch/arm/boot/dts/stih416.dtsi
>> @@ -283,21 +283,21 @@
>>   
>>   		miphy365x_phy: phy at fe382000 {
>>   			compatible      = "st,miphy365x-phy";
>> -			st,syscfg  	= <&syscfg_rear>;
>> +			st,syscfg	= <&syscfg_rear 0x824 0x828>;
>>   			#address-cells	= <1>;
>>   			#size-cells	= <1>;
>>   			ranges;
>>   
>>   			phy_port0: port at fe382000 {
>>   				#phy-cells = <1>;
>> -				reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>> -				reg-names = "sata", "pcie", "syscfg";
>> +				reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>> +				reg-names = "sata", "pcie";
>>   			};
>>   
>>   			phy_port1: port at fe38a000 {
>>   				#phy-cells = <1>;
>> -				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
>> -				reg-names = "sata", "pcie", "syscfg";
>> +				reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
>> +				reg-names = "sata", "pcie";
>>   			};
>>   		};
>>   
>> diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
>> index 6ab43a8..6c80154 100644
>> --- a/drivers/phy/phy-miphy365x.c
>> +++ b/drivers/phy/phy-miphy365x.c
>> @@ -141,7 +141,7 @@ struct miphy365x_phy {
>>   	bool pcie_tx_pol_inv;
>>   	bool sata_tx_pol_inv;
>>   	u32 sata_gen;
>> -	u64 ctrlreg;
>> +	u32 ctrlreg;
>>   	u8 type;
>>   };
>>   
>> @@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
>>   	bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
>>   
>>   	return regmap_update_bits(miphy_dev->regmap,
>> -				  (unsigned int)miphy_phy->ctrlreg,
>> +				  miphy_phy->ctrlreg,
>>   				  SYSCFG_SELECT_SATA_MASK,
>>   				  sata << SYSCFG_SELECT_SATA_POS);
>>   }
>> @@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
>>   {
>>   	struct device_node *phynode = miphy_phy->phy->dev.of_node;
>>   	const char *name;
>> -	const __be32 *taddr;
>>   	int type = miphy_phy->type;
>>   	int ret;
>>   
>> @@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
>>   		return ret;
>>   	}
>>   
>> -	if (!strncmp(name, "syscfg", 6)) {
>> -		taddr = of_get_address(phynode, index, NULL, NULL);
>> -		if (!taddr) {
>> -			dev_err(dev, "failed to fetch syscfg address\n");
>> -			return -EINVAL;
>> -		}
>> -
>> -		miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
>> -		if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
>> -			dev_err(dev, "failed to translate syscfg address\n");
>> -			return -EINVAL;
>> -		}
>> -
>> -		return 0;
>> -	}
>> -
>>   	if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
>>   	      (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
>>   		return 0;
>> @@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
>>   			return ret;
>>   
>>   		phy_set_drvdata(phy, miphy_dev->phys[port]);
>> +
>>   		port++;
>> +		/* sysconfig offsets are indexed from 1 */
>> +		ret = of_property_read_u32_index(np, "st,syscfg", port,
>> +					&miphy_phy->ctrlreg);
>> +		if (ret) {
>> +			dev_err(&pdev->dev, "No sysconfig offset found\n");
>> +			return ret;
>> +		}
>>   	}
>>   
>>   	provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
>>

Re: [PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Kishon Vijay Abraham I]

Hi,

On Friday 30 January 2015 04:18 PM, Maxime Coquelin wrote:
> Hi Kishon,
> 
> On 01/30/2015 11:35 AM, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
>>> Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
>>> update the miphy365 phy driver to access sysconfig register offsets via
>>> syscfg dt property.
>>>
>>> This is because the reg property should not be mixing address spaces
>>> like it does currently for miphy365. This change then also aligns us
>>> to how other platforms such as keystone and bcm7445 pass there syscon
>>> offsets via DT.
>>>
>>> This patch breaks DT compatibility, but this platform is considered WIP,
>>> and is only used by a few developers who are upstreaming support for it.
>>> This change has been done as a single atomic commit to ensure it is
>>> bisectable.
>> I'm dropping this from my tree since I didn't get Ack from
>> "arch/arm/boot/dts/stih416.dtsi" Maintainer.
> Sorry, on cover letter, I replied the series looked good to me.
> So you can add:
> 
> Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
> 
> And even:
> 
> Tested-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks. I'll merge them now.
I'd assume there won't be any conflicts when it gets merged to linus tree.

Cheers
Kishon

> 
> Kind regards,
> Maxime
> 
>>
>> Thanks
>> Kishon
>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>>> ---
>>>   .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
>>>   arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
>>>   drivers/phy/phy-miphy365x.c                        | 29
>>> ++++++++--------------
>>>   3 files changed, 23 insertions(+), 31 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>> b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>> index 42c8808..9802d5d 100644
>>> --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>> @@ -6,8 +6,10 @@ for SATA and PCIe.
>>>     Required properties (controller (parent) node):
>>>   - compatible    : Should be "st,miphy365x-phy"
>>> -- st,syscfg     : Should be a phandle of the system configuration register
>>> group
>>> -          which contain the SATA, PCIe mode setting bits
>>> +- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
>>> +          containing the miphy registers and integer array should contain
>>> +          an entry for each port sub-node, specifying the control
>>> +          register offset inside the sysconfig group.
>>>     Required nodes    :  A sub-node is required for each channel the controller
>>>              provides. Address range information including the usual
>>> @@ -26,7 +28,6 @@ Required properties (port (child) node):
>>>             registers filled in "reg":
>>>               - sata:   For SATA devices
>>>               - pcie:   For PCIe devices
>>> -            - syscfg: To specify the syscfg based config register
>>>     Optional properties (port (child) node):
>>>   - st,sata-gen         :    Generation of locally attached SATA IP.
>>> Expected values
>>> @@ -39,20 +40,20 @@ Example:
>>>         miphy365x_phy: miphy365x@fe382000 {
>>>           compatible      = "st,miphy365x-phy";
>>> -        st,syscfg      = <&syscfg_rear>;
>>> +        st,syscfg      = <&syscfg_rear 0x824 0x828>;
>>>           #address-cells    = <1>;
>>>           #size-cells    = <1>;
>>>           ranges;
>>>             phy_port0: port@fe382000 {
>>> -            reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>> -            reg-names = "sata", "pcie", "syscfg";
>>> +            reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>> +            reg-names = "sata", "pcie";
>>>               #phy-cells = <1>;
>>>               st,sata-gen = <3>;
>>>           };
>>>             phy_port1: port@fe38a000 {
>>> -            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
>>> +            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
>>>               reg-names = "sata", "pcie", "syscfg";
>>>               #phy-cells = <1>;
>>>               st,pcie-tx-pol-inv;
>>> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
>>> index fad9073..85afe01 100644
>>> --- a/arch/arm/boot/dts/stih416.dtsi
>>> +++ b/arch/arm/boot/dts/stih416.dtsi
>>> @@ -283,21 +283,21 @@
>>>             miphy365x_phy: phy@fe382000 {
>>>               compatible      = "st,miphy365x-phy";
>>> -            st,syscfg      = <&syscfg_rear>;
>>> +            st,syscfg    = <&syscfg_rear 0x824 0x828>;
>>>               #address-cells    = <1>;
>>>               #size-cells    = <1>;
>>>               ranges;
>>>                 phy_port0: port@fe382000 {
>>>                   #phy-cells = <1>;
>>> -                reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>> -                reg-names = "sata", "pcie", "syscfg";
>>> +                reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>> +                reg-names = "sata", "pcie";
>>>               };
>>>                 phy_port1: port@fe38a000 {
>>>                   #phy-cells = <1>;
>>> -                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
>>> -                reg-names = "sata", "pcie", "syscfg";
>>> +                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
>>> +                reg-names = "sata", "pcie";
>>>               };
>>>           };
>>>   diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
>>> index 6ab43a8..6c80154 100644
>>> --- a/drivers/phy/phy-miphy365x.c
>>> +++ b/drivers/phy/phy-miphy365x.c
>>> @@ -141,7 +141,7 @@ struct miphy365x_phy {
>>>       bool pcie_tx_pol_inv;
>>>       bool sata_tx_pol_inv;
>>>       u32 sata_gen;
>>> -    u64 ctrlreg;
>>> +    u32 ctrlreg;
>>>       u8 type;
>>>   };
>>>   @@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy
>>> *miphy_phy,
>>>       bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
>>>         return regmap_update_bits(miphy_dev->regmap,
>>> -                  (unsigned int)miphy_phy->ctrlreg,
>>> +                  miphy_phy->ctrlreg,
>>>                     SYSCFG_SELECT_SATA_MASK,
>>>                     sata << SYSCFG_SELECT_SATA_POS);
>>>   }
>>> @@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>> miphy365x_phy *miphy_phy,
>>>   {
>>>       struct device_node *phynode = miphy_phy->phy->dev.of_node;
>>>       const char *name;
>>> -    const __be32 *taddr;
>>>       int type = miphy_phy->type;
>>>       int ret;
>>>   @@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>> miphy365x_phy *miphy_phy,
>>>           return ret;
>>>       }
>>>   -    if (!strncmp(name, "syscfg", 6)) {
>>> -        taddr = of_get_address(phynode, index, NULL, NULL);
>>> -        if (!taddr) {
>>> -            dev_err(dev, "failed to fetch syscfg address\n");
>>> -            return -EINVAL;
>>> -        }
>>> -
>>> -        miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
>>> -        if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
>>> -            dev_err(dev, "failed to translate syscfg address\n");
>>> -            return -EINVAL;
>>> -        }
>>> -
>>> -        return 0;
>>> -    }
>>> -
>>>       if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
>>>             (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
>>>           return 0;
>>> @@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
>>>               return ret;
>>>             phy_set_drvdata(phy, miphy_dev->phys[port]);
>>> +
>>>           port++;
>>> +        /* sysconfig offsets are indexed from 1 */
>>> +        ret = of_property_read_u32_index(np, "st,syscfg", port,
>>> +                    &miphy_phy->ctrlreg);
>>> +        if (ret) {
>>> +            dev_err(&pdev->dev, "No sysconfig offset found\n");
>>> +            return ret;
>>> +        }
>>>       }
>>>         provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
>>>
> 

Re: [PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Kishon Vijay Abraham I]

Hi,

On Friday 30 January 2015 04:18 PM, Maxime Coquelin wrote:
> Hi Kishon,
> 
> On 01/30/2015 11:35 AM, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
>>> Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
>>> update the miphy365 phy driver to access sysconfig register offsets via
>>> syscfg dt property.
>>>
>>> This is because the reg property should not be mixing address spaces
>>> like it does currently for miphy365. This change then also aligns us
>>> to how other platforms such as keystone and bcm7445 pass there syscon
>>> offsets via DT.
>>>
>>> This patch breaks DT compatibility, but this platform is considered WIP,
>>> and is only used by a few developers who are upstreaming support for it.
>>> This change has been done as a single atomic commit to ensure it is
>>> bisectable.
>> I'm dropping this from my tree since I didn't get Ack from
>> "arch/arm/boot/dts/stih416.dtsi" Maintainer.
> Sorry, on cover letter, I replied the series looked good to me.
> So you can add:
> 
> Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
> 
> And even:
> 
> Tested-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks. I'll merge them now.
I'd assume there won't be any conflicts when it gets merged to linus tree.

Cheers
Kishon

> 
> Kind regards,
> Maxime
> 
>>
>> Thanks
>> Kishon
>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>>> ---
>>>   .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
>>>   arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
>>>   drivers/phy/phy-miphy365x.c                        | 29
>>> ++++++++--------------
>>>   3 files changed, 23 insertions(+), 31 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>> b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>> index 42c8808..9802d5d 100644
>>> --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>> @@ -6,8 +6,10 @@ for SATA and PCIe.
>>>     Required properties (controller (parent) node):
>>>   - compatible    : Should be "st,miphy365x-phy"
>>> -- st,syscfg     : Should be a phandle of the system configuration register
>>> group
>>> -          which contain the SATA, PCIe mode setting bits
>>> +- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
>>> +          containing the miphy registers and integer array should contain
>>> +          an entry for each port sub-node, specifying the control
>>> +          register offset inside the sysconfig group.
>>>     Required nodes    :  A sub-node is required for each channel the controller
>>>              provides. Address range information including the usual
>>> @@ -26,7 +28,6 @@ Required properties (port (child) node):
>>>             registers filled in "reg":
>>>               - sata:   For SATA devices
>>>               - pcie:   For PCIe devices
>>> -            - syscfg: To specify the syscfg based config register
>>>     Optional properties (port (child) node):
>>>   - st,sata-gen         :    Generation of locally attached SATA IP.
>>> Expected values
>>> @@ -39,20 +40,20 @@ Example:
>>>         miphy365x_phy: miphy365x@fe382000 {
>>>           compatible      = "st,miphy365x-phy";
>>> -        st,syscfg      = <&syscfg_rear>;
>>> +        st,syscfg      = <&syscfg_rear 0x824 0x828>;
>>>           #address-cells    = <1>;
>>>           #size-cells    = <1>;
>>>           ranges;
>>>             phy_port0: port@fe382000 {
>>> -            reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>> -            reg-names = "sata", "pcie", "syscfg";
>>> +            reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>> +            reg-names = "sata", "pcie";
>>>               #phy-cells = <1>;
>>>               st,sata-gen = <3>;
>>>           };
>>>             phy_port1: port@fe38a000 {
>>> -            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
>>> +            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
>>>               reg-names = "sata", "pcie", "syscfg";
>>>               #phy-cells = <1>;
>>>               st,pcie-tx-pol-inv;
>>> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
>>> index fad9073..85afe01 100644
>>> --- a/arch/arm/boot/dts/stih416.dtsi
>>> +++ b/arch/arm/boot/dts/stih416.dtsi
>>> @@ -283,21 +283,21 @@
>>>             miphy365x_phy: phy@fe382000 {
>>>               compatible      = "st,miphy365x-phy";
>>> -            st,syscfg      = <&syscfg_rear>;
>>> +            st,syscfg    = <&syscfg_rear 0x824 0x828>;
>>>               #address-cells    = <1>;
>>>               #size-cells    = <1>;
>>>               ranges;
>>>                 phy_port0: port@fe382000 {
>>>                   #phy-cells = <1>;
>>> -                reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>> -                reg-names = "sata", "pcie", "syscfg";
>>> +                reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>> +                reg-names = "sata", "pcie";
>>>               };
>>>                 phy_port1: port@fe38a000 {
>>>                   #phy-cells = <1>;
>>> -                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
>>> -                reg-names = "sata", "pcie", "syscfg";
>>> +                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
>>> +                reg-names = "sata", "pcie";
>>>               };
>>>           };
>>>   diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
>>> index 6ab43a8..6c80154 100644
>>> --- a/drivers/phy/phy-miphy365x.c
>>> +++ b/drivers/phy/phy-miphy365x.c
>>> @@ -141,7 +141,7 @@ struct miphy365x_phy {
>>>       bool pcie_tx_pol_inv;
>>>       bool sata_tx_pol_inv;
>>>       u32 sata_gen;
>>> -    u64 ctrlreg;
>>> +    u32 ctrlreg;
>>>       u8 type;
>>>   };
>>>   @@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy
>>> *miphy_phy,
>>>       bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
>>>         return regmap_update_bits(miphy_dev->regmap,
>>> -                  (unsigned int)miphy_phy->ctrlreg,
>>> +                  miphy_phy->ctrlreg,
>>>                     SYSCFG_SELECT_SATA_MASK,
>>>                     sata << SYSCFG_SELECT_SATA_POS);
>>>   }
>>> @@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>> miphy365x_phy *miphy_phy,
>>>   {
>>>       struct device_node *phynode = miphy_phy->phy->dev.of_node;
>>>       const char *name;
>>> -    const __be32 *taddr;
>>>       int type = miphy_phy->type;
>>>       int ret;
>>>   @@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>> miphy365x_phy *miphy_phy,
>>>           return ret;
>>>       }
>>>   -    if (!strncmp(name, "syscfg", 6)) {
>>> -        taddr = of_get_address(phynode, index, NULL, NULL);
>>> -        if (!taddr) {
>>> -            dev_err(dev, "failed to fetch syscfg address\n");
>>> -            return -EINVAL;
>>> -        }
>>> -
>>> -        miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
>>> -        if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
>>> -            dev_err(dev, "failed to translate syscfg address\n");
>>> -            return -EINVAL;
>>> -        }
>>> -
>>> -        return 0;
>>> -    }
>>> -
>>>       if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
>>>             (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
>>>           return 0;
>>> @@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
>>>               return ret;
>>>             phy_set_drvdata(phy, miphy_dev->phys[port]);
>>> +
>>>           port++;
>>> +        /* sysconfig offsets are indexed from 1 */
>>> +        ret = of_property_read_u32_index(np, "st,syscfg", port,
>>> +                    &miphy_phy->ctrlreg);
>>> +        if (ret) {
>>> +            dev_err(&pdev->dev, "No sysconfig offset found\n");
>>> +            return ret;
>>> +        }
>>>       }
>>>         provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
>>>
> 

[PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Kishon Vijay Abraham I]

Hi,

On Friday 30 January 2015 04:18 PM, Maxime Coquelin wrote:
> Hi Kishon,
> 
> On 01/30/2015 11:35 AM, Kishon Vijay Abraham I wrote:
>> Hi,
>>
>> On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
>>> Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
>>> update the miphy365 phy driver to access sysconfig register offsets via
>>> syscfg dt property.
>>>
>>> This is because the reg property should not be mixing address spaces
>>> like it does currently for miphy365. This change then also aligns us
>>> to how other platforms such as keystone and bcm7445 pass there syscon
>>> offsets via DT.
>>>
>>> This patch breaks DT compatibility, but this platform is considered WIP,
>>> and is only used by a few developers who are upstreaming support for it.
>>> This change has been done as a single atomic commit to ensure it is
>>> bisectable.
>> I'm dropping this from my tree since I didn't get Ack from
>> "arch/arm/boot/dts/stih416.dtsi" Maintainer.
> Sorry, on cover letter, I replied the series looked good to me.
> So you can add:
> 
> Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
> 
> And even:
> 
> Tested-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks. I'll merge them now.
I'd assume there won't be any conflicts when it gets merged to linus tree.

Cheers
Kishon

> 
> Kind regards,
> Maxime
> 
>>
>> Thanks
>> Kishon
>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>>> ---
>>>   .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
>>>   arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
>>>   drivers/phy/phy-miphy365x.c                        | 29
>>> ++++++++--------------
>>>   3 files changed, 23 insertions(+), 31 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>> b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>> index 42c8808..9802d5d 100644
>>> --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>> @@ -6,8 +6,10 @@ for SATA and PCIe.
>>>     Required properties (controller (parent) node):
>>>   - compatible    : Should be "st,miphy365x-phy"
>>> -- st,syscfg     : Should be a phandle of the system configuration register
>>> group
>>> -          which contain the SATA, PCIe mode setting bits
>>> +- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
>>> +          containing the miphy registers and integer array should contain
>>> +          an entry for each port sub-node, specifying the control
>>> +          register offset inside the sysconfig group.
>>>     Required nodes    :  A sub-node is required for each channel the controller
>>>              provides. Address range information including the usual
>>> @@ -26,7 +28,6 @@ Required properties (port (child) node):
>>>             registers filled in "reg":
>>>               - sata:   For SATA devices
>>>               - pcie:   For PCIe devices
>>> -            - syscfg: To specify the syscfg based config register
>>>     Optional properties (port (child) node):
>>>   - st,sata-gen         :    Generation of locally attached SATA IP.
>>> Expected values
>>> @@ -39,20 +40,20 @@ Example:
>>>         miphy365x_phy: miphy365x at fe382000 {
>>>           compatible      = "st,miphy365x-phy";
>>> -        st,syscfg      = <&syscfg_rear>;
>>> +        st,syscfg      = <&syscfg_rear 0x824 0x828>;
>>>           #address-cells    = <1>;
>>>           #size-cells    = <1>;
>>>           ranges;
>>>             phy_port0: port at fe382000 {
>>> -            reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>> -            reg-names = "sata", "pcie", "syscfg";
>>> +            reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>> +            reg-names = "sata", "pcie";
>>>               #phy-cells = <1>;
>>>               st,sata-gen = <3>;
>>>           };
>>>             phy_port1: port at fe38a000 {
>>> -            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
>>> +            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
>>>               reg-names = "sata", "pcie", "syscfg";
>>>               #phy-cells = <1>;
>>>               st,pcie-tx-pol-inv;
>>> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
>>> index fad9073..85afe01 100644
>>> --- a/arch/arm/boot/dts/stih416.dtsi
>>> +++ b/arch/arm/boot/dts/stih416.dtsi
>>> @@ -283,21 +283,21 @@
>>>             miphy365x_phy: phy at fe382000 {
>>>               compatible      = "st,miphy365x-phy";
>>> -            st,syscfg      = <&syscfg_rear>;
>>> +            st,syscfg    = <&syscfg_rear 0x824 0x828>;
>>>               #address-cells    = <1>;
>>>               #size-cells    = <1>;
>>>               ranges;
>>>                 phy_port0: port at fe382000 {
>>>                   #phy-cells = <1>;
>>> -                reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>> -                reg-names = "sata", "pcie", "syscfg";
>>> +                reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>> +                reg-names = "sata", "pcie";
>>>               };
>>>                 phy_port1: port at fe38a000 {
>>>                   #phy-cells = <1>;
>>> -                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
>>> -                reg-names = "sata", "pcie", "syscfg";
>>> +                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
>>> +                reg-names = "sata", "pcie";
>>>               };
>>>           };
>>>   diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
>>> index 6ab43a8..6c80154 100644
>>> --- a/drivers/phy/phy-miphy365x.c
>>> +++ b/drivers/phy/phy-miphy365x.c
>>> @@ -141,7 +141,7 @@ struct miphy365x_phy {
>>>       bool pcie_tx_pol_inv;
>>>       bool sata_tx_pol_inv;
>>>       u32 sata_gen;
>>> -    u64 ctrlreg;
>>> +    u32 ctrlreg;
>>>       u8 type;
>>>   };
>>>   @@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy
>>> *miphy_phy,
>>>       bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
>>>         return regmap_update_bits(miphy_dev->regmap,
>>> -                  (unsigned int)miphy_phy->ctrlreg,
>>> +                  miphy_phy->ctrlreg,
>>>                     SYSCFG_SELECT_SATA_MASK,
>>>                     sata << SYSCFG_SELECT_SATA_POS);
>>>   }
>>> @@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>> miphy365x_phy *miphy_phy,
>>>   {
>>>       struct device_node *phynode = miphy_phy->phy->dev.of_node;
>>>       const char *name;
>>> -    const __be32 *taddr;
>>>       int type = miphy_phy->type;
>>>       int ret;
>>>   @@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>> miphy365x_phy *miphy_phy,
>>>           return ret;
>>>       }
>>>   -    if (!strncmp(name, "syscfg", 6)) {
>>> -        taddr = of_get_address(phynode, index, NULL, NULL);
>>> -        if (!taddr) {
>>> -            dev_err(dev, "failed to fetch syscfg address\n");
>>> -            return -EINVAL;
>>> -        }
>>> -
>>> -        miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
>>> -        if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
>>> -            dev_err(dev, "failed to translate syscfg address\n");
>>> -            return -EINVAL;
>>> -        }
>>> -
>>> -        return 0;
>>> -    }
>>> -
>>>       if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
>>>             (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
>>>           return 0;
>>> @@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
>>>               return ret;
>>>             phy_set_drvdata(phy, miphy_dev->phys[port]);
>>> +
>>>           port++;
>>> +        /* sysconfig offsets are indexed from 1 */
>>> +        ret = of_property_read_u32_index(np, "st,syscfg", port,
>>> +                    &miphy_phy->ctrlreg);
>>> +        if (ret) {
>>> +            dev_err(&pdev->dev, "No sysconfig offset found\n");
>>> +            return ret;
>>> +        }
>>>       }
>>>         provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
>>>
> 

Re: [PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Maxime Coquelin]

On 01/30/2015 12:08 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Friday 30 January 2015 04:18 PM, Maxime Coquelin wrote:
>> Hi Kishon,
>>
>> On 01/30/2015 11:35 AM, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
>>>> Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
>>>> update the miphy365 phy driver to access sysconfig register offsets via
>>>> syscfg dt property.
>>>>
>>>> This is because the reg property should not be mixing address spaces
>>>> like it does currently for miphy365. This change then also aligns us
>>>> to how other platforms such as keystone and bcm7445 pass there syscon
>>>> offsets via DT.
>>>>
>>>> This patch breaks DT compatibility, but this platform is considered WIP,
>>>> and is only used by a few developers who are upstreaming support for it.
>>>> This change has been done as a single atomic commit to ensure it is
>>>> bisectable.
>>> I'm dropping this from my tree since I didn't get Ack from
>>> "arch/arm/boot/dts/stih416.dtsi" Maintainer.
>> Sorry, on cover letter, I replied the series looked good to me.
>> So you can add:
>>
>> Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
>>
>> And even:
>>
>> Tested-by: Maxime Coquelin <maxime.coquelin@st.com>
> Thanks. I'll merge them now.
> I'd assume there won't be any conflicts when it gets merged to linus tree.
Thanks Kishon,

I have merged this patch with the last DT pull-request I sent for v3.20, 
and didn't had any conflicts.
So I'm confident there won't be any issue.

Br,
Maxime
>
> Cheers
> Kishon
>
>> Kind regards,
>> Maxime
>>
>>> Thanks
>>> Kishon
>>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>>> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>>>> ---
>>>>    .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
>>>>    arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
>>>>    drivers/phy/phy-miphy365x.c                        | 29
>>>> ++++++++--------------
>>>>    3 files changed, 23 insertions(+), 31 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> index 42c8808..9802d5d 100644
>>>> --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> @@ -6,8 +6,10 @@ for SATA and PCIe.
>>>>      Required properties (controller (parent) node):
>>>>    - compatible    : Should be "st,miphy365x-phy"
>>>> -- st,syscfg     : Should be a phandle of the system configuration register
>>>> group
>>>> -          which contain the SATA, PCIe mode setting bits
>>>> +- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
>>>> +          containing the miphy registers and integer array should contain
>>>> +          an entry for each port sub-node, specifying the control
>>>> +          register offset inside the sysconfig group.
>>>>      Required nodes    :  A sub-node is required for each channel the controller
>>>>               provides. Address range information including the usual
>>>> @@ -26,7 +28,6 @@ Required properties (port (child) node):
>>>>              registers filled in "reg":
>>>>                - sata:   For SATA devices
>>>>                - pcie:   For PCIe devices
>>>> -            - syscfg: To specify the syscfg based config register
>>>>      Optional properties (port (child) node):
>>>>    - st,sata-gen         :    Generation of locally attached SATA IP.
>>>> Expected values
>>>> @@ -39,20 +40,20 @@ Example:
>>>>          miphy365x_phy: miphy365x@fe382000 {
>>>>            compatible      = "st,miphy365x-phy";
>>>> -        st,syscfg      = <&syscfg_rear>;
>>>> +        st,syscfg      = <&syscfg_rear 0x824 0x828>;
>>>>            #address-cells    = <1>;
>>>>            #size-cells    = <1>;
>>>>            ranges;
>>>>              phy_port0: port@fe382000 {
>>>> -            reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>>> -            reg-names = "sata", "pcie", "syscfg";
>>>> +            reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>>> +            reg-names = "sata", "pcie";
>>>>                #phy-cells = <1>;
>>>>                st,sata-gen = <3>;
>>>>            };
>>>>              phy_port1: port@fe38a000 {
>>>> -            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
>>>> +            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
>>>>                reg-names = "sata", "pcie", "syscfg";
>>>>                #phy-cells = <1>;
>>>>                st,pcie-tx-pol-inv;
>>>> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
>>>> index fad9073..85afe01 100644
>>>> --- a/arch/arm/boot/dts/stih416.dtsi
>>>> +++ b/arch/arm/boot/dts/stih416.dtsi
>>>> @@ -283,21 +283,21 @@
>>>>              miphy365x_phy: phy@fe382000 {
>>>>                compatible      = "st,miphy365x-phy";
>>>> -            st,syscfg      = <&syscfg_rear>;
>>>> +            st,syscfg    = <&syscfg_rear 0x824 0x828>;
>>>>                #address-cells    = <1>;
>>>>                #size-cells    = <1>;
>>>>                ranges;
>>>>                  phy_port0: port@fe382000 {
>>>>                    #phy-cells = <1>;
>>>> -                reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>>> -                reg-names = "sata", "pcie", "syscfg";
>>>> +                reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>>> +                reg-names = "sata", "pcie";
>>>>                };
>>>>                  phy_port1: port@fe38a000 {
>>>>                    #phy-cells = <1>;
>>>> -                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
>>>> -                reg-names = "sata", "pcie", "syscfg";
>>>> +                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
>>>> +                reg-names = "sata", "pcie";
>>>>                };
>>>>            };
>>>>    diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
>>>> index 6ab43a8..6c80154 100644
>>>> --- a/drivers/phy/phy-miphy365x.c
>>>> +++ b/drivers/phy/phy-miphy365x.c
>>>> @@ -141,7 +141,7 @@ struct miphy365x_phy {
>>>>        bool pcie_tx_pol_inv;
>>>>        bool sata_tx_pol_inv;
>>>>        u32 sata_gen;
>>>> -    u64 ctrlreg;
>>>> +    u32 ctrlreg;
>>>>        u8 type;
>>>>    };
>>>>    @@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy
>>>> *miphy_phy,
>>>>        bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
>>>>          return regmap_update_bits(miphy_dev->regmap,
>>>> -                  (unsigned int)miphy_phy->ctrlreg,
>>>> +                  miphy_phy->ctrlreg,
>>>>                      SYSCFG_SELECT_SATA_MASK,
>>>>                      sata << SYSCFG_SELECT_SATA_POS);
>>>>    }
>>>> @@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>>> miphy365x_phy *miphy_phy,
>>>>    {
>>>>        struct device_node *phynode = miphy_phy->phy->dev.of_node;
>>>>        const char *name;
>>>> -    const __be32 *taddr;
>>>>        int type = miphy_phy->type;
>>>>        int ret;
>>>>    @@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>>> miphy365x_phy *miphy_phy,
>>>>            return ret;
>>>>        }
>>>>    -    if (!strncmp(name, "syscfg", 6)) {
>>>> -        taddr = of_get_address(phynode, index, NULL, NULL);
>>>> -        if (!taddr) {
>>>> -            dev_err(dev, "failed to fetch syscfg address\n");
>>>> -            return -EINVAL;
>>>> -        }
>>>> -
>>>> -        miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
>>>> -        if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
>>>> -            dev_err(dev, "failed to translate syscfg address\n");
>>>> -            return -EINVAL;
>>>> -        }
>>>> -
>>>> -        return 0;
>>>> -    }
>>>> -
>>>>        if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
>>>>              (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
>>>>            return 0;
>>>> @@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
>>>>                return ret;
>>>>              phy_set_drvdata(phy, miphy_dev->phys[port]);
>>>> +
>>>>            port++;
>>>> +        /* sysconfig offsets are indexed from 1 */
>>>> +        ret = of_property_read_u32_index(np, "st,syscfg", port,
>>>> +                    &miphy_phy->ctrlreg);
>>>> +        if (ret) {
>>>> +            dev_err(&pdev->dev, "No sysconfig offset found\n");
>>>> +            return ret;
>>>> +        }
>>>>        }
>>>>          provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
>>>>

Re: [PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Maxime Coquelin]

On 01/30/2015 12:08 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Friday 30 January 2015 04:18 PM, Maxime Coquelin wrote:
>> Hi Kishon,
>>
>> On 01/30/2015 11:35 AM, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
>>>> Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
>>>> update the miphy365 phy driver to access sysconfig register offsets via
>>>> syscfg dt property.
>>>>
>>>> This is because the reg property should not be mixing address spaces
>>>> like it does currently for miphy365. This change then also aligns us
>>>> to how other platforms such as keystone and bcm7445 pass there syscon
>>>> offsets via DT.
>>>>
>>>> This patch breaks DT compatibility, but this platform is considered WIP,
>>>> and is only used by a few developers who are upstreaming support for it.
>>>> This change has been done as a single atomic commit to ensure it is
>>>> bisectable.
>>> I'm dropping this from my tree since I didn't get Ack from
>>> "arch/arm/boot/dts/stih416.dtsi" Maintainer.
>> Sorry, on cover letter, I replied the series looked good to me.
>> So you can add:
>>
>> Acked-by: Maxime Coquelin <maxime.coquelin-qxv4g6HH51o@public.gmane.org>
>>
>> And even:
>>
>> Tested-by: Maxime Coquelin <maxime.coquelin-qxv4g6HH51o@public.gmane.org>
> Thanks. I'll merge them now.
> I'd assume there won't be any conflicts when it gets merged to linus tree.
Thanks Kishon,

I have merged this patch with the last DT pull-request I sent for v3.20, 
and didn't had any conflicts.
So I'm confident there won't be any issue.

Br,
Maxime
>
> Cheers
> Kishon
>
>> Kind regards,
>> Maxime
>>
>>> Thanks
>>> Kishon
>>>> Signed-off-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>>> Reviewed-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
>>>> ---
>>>>    .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
>>>>    arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
>>>>    drivers/phy/phy-miphy365x.c                        | 29
>>>> ++++++++--------------
>>>>    3 files changed, 23 insertions(+), 31 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> index 42c8808..9802d5d 100644
>>>> --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> @@ -6,8 +6,10 @@ for SATA and PCIe.
>>>>      Required properties (controller (parent) node):
>>>>    - compatible    : Should be "st,miphy365x-phy"
>>>> -- st,syscfg     : Should be a phandle of the system configuration register
>>>> group
>>>> -          which contain the SATA, PCIe mode setting bits
>>>> +- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
>>>> +          containing the miphy registers and integer array should contain
>>>> +          an entry for each port sub-node, specifying the control
>>>> +          register offset inside the sysconfig group.
>>>>      Required nodes    :  A sub-node is required for each channel the controller
>>>>               provides. Address range information including the usual
>>>> @@ -26,7 +28,6 @@ Required properties (port (child) node):
>>>>              registers filled in "reg":
>>>>                - sata:   For SATA devices
>>>>                - pcie:   For PCIe devices
>>>> -            - syscfg: To specify the syscfg based config register
>>>>      Optional properties (port (child) node):
>>>>    - st,sata-gen         :    Generation of locally attached SATA IP.
>>>> Expected values
>>>> @@ -39,20 +40,20 @@ Example:
>>>>          miphy365x_phy: miphy365x@fe382000 {
>>>>            compatible      = "st,miphy365x-phy";
>>>> -        st,syscfg      = <&syscfg_rear>;
>>>> +        st,syscfg      = <&syscfg_rear 0x824 0x828>;
>>>>            #address-cells    = <1>;
>>>>            #size-cells    = <1>;
>>>>            ranges;
>>>>              phy_port0: port@fe382000 {
>>>> -            reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>>> -            reg-names = "sata", "pcie", "syscfg";
>>>> +            reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>>> +            reg-names = "sata", "pcie";
>>>>                #phy-cells = <1>;
>>>>                st,sata-gen = <3>;
>>>>            };
>>>>              phy_port1: port@fe38a000 {
>>>> -            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
>>>> +            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
>>>>                reg-names = "sata", "pcie", "syscfg";
>>>>                #phy-cells = <1>;
>>>>                st,pcie-tx-pol-inv;
>>>> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
>>>> index fad9073..85afe01 100644
>>>> --- a/arch/arm/boot/dts/stih416.dtsi
>>>> +++ b/arch/arm/boot/dts/stih416.dtsi
>>>> @@ -283,21 +283,21 @@
>>>>              miphy365x_phy: phy@fe382000 {
>>>>                compatible      = "st,miphy365x-phy";
>>>> -            st,syscfg      = <&syscfg_rear>;
>>>> +            st,syscfg    = <&syscfg_rear 0x824 0x828>;
>>>>                #address-cells    = <1>;
>>>>                #size-cells    = <1>;
>>>>                ranges;
>>>>                  phy_port0: port@fe382000 {
>>>>                    #phy-cells = <1>;
>>>> -                reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>>> -                reg-names = "sata", "pcie", "syscfg";
>>>> +                reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>>> +                reg-names = "sata", "pcie";
>>>>                };
>>>>                  phy_port1: port@fe38a000 {
>>>>                    #phy-cells = <1>;
>>>> -                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
>>>> -                reg-names = "sata", "pcie", "syscfg";
>>>> +                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
>>>> +                reg-names = "sata", "pcie";
>>>>                };
>>>>            };
>>>>    diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
>>>> index 6ab43a8..6c80154 100644
>>>> --- a/drivers/phy/phy-miphy365x.c
>>>> +++ b/drivers/phy/phy-miphy365x.c
>>>> @@ -141,7 +141,7 @@ struct miphy365x_phy {
>>>>        bool pcie_tx_pol_inv;
>>>>        bool sata_tx_pol_inv;
>>>>        u32 sata_gen;
>>>> -    u64 ctrlreg;
>>>> +    u32 ctrlreg;
>>>>        u8 type;
>>>>    };
>>>>    @@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy
>>>> *miphy_phy,
>>>>        bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
>>>>          return regmap_update_bits(miphy_dev->regmap,
>>>> -                  (unsigned int)miphy_phy->ctrlreg,
>>>> +                  miphy_phy->ctrlreg,
>>>>                      SYSCFG_SELECT_SATA_MASK,
>>>>                      sata << SYSCFG_SELECT_SATA_POS);
>>>>    }
>>>> @@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>>> miphy365x_phy *miphy_phy,
>>>>    {
>>>>        struct device_node *phynode = miphy_phy->phy->dev.of_node;
>>>>        const char *name;
>>>> -    const __be32 *taddr;
>>>>        int type = miphy_phy->type;
>>>>        int ret;
>>>>    @@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>>> miphy365x_phy *miphy_phy,
>>>>            return ret;
>>>>        }
>>>>    -    if (!strncmp(name, "syscfg", 6)) {
>>>> -        taddr = of_get_address(phynode, index, NULL, NULL);
>>>> -        if (!taddr) {
>>>> -            dev_err(dev, "failed to fetch syscfg address\n");
>>>> -            return -EINVAL;
>>>> -        }
>>>> -
>>>> -        miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
>>>> -        if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
>>>> -            dev_err(dev, "failed to translate syscfg address\n");
>>>> -            return -EINVAL;
>>>> -        }
>>>> -
>>>> -        return 0;
>>>> -    }
>>>> -
>>>>        if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
>>>>              (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
>>>>            return 0;
>>>> @@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
>>>>                return ret;
>>>>              phy_set_drvdata(phy, miphy_dev->phys[port]);
>>>> +
>>>>            port++;
>>>> +        /* sysconfig offsets are indexed from 1 */
>>>> +        ret = of_property_read_u32_index(np, "st,syscfg", port,
>>>> +                    &miphy_phy->ctrlreg);
>>>> +        if (ret) {
>>>> +            dev_err(&pdev->dev, "No sysconfig offset found\n");
>>>> +            return ret;
>>>> +        }
>>>>        }
>>>>          provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
>>>>

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Re: [PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Maxime Coquelin]

On 01/30/2015 12:08 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Friday 30 January 2015 04:18 PM, Maxime Coquelin wrote:
>> Hi Kishon,
>>
>> On 01/30/2015 11:35 AM, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
>>>> Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
>>>> update the miphy365 phy driver to access sysconfig register offsets via
>>>> syscfg dt property.
>>>>
>>>> This is because the reg property should not be mixing address spaces
>>>> like it does currently for miphy365. This change then also aligns us
>>>> to how other platforms such as keystone and bcm7445 pass there syscon
>>>> offsets via DT.
>>>>
>>>> This patch breaks DT compatibility, but this platform is considered WIP,
>>>> and is only used by a few developers who are upstreaming support for it.
>>>> This change has been done as a single atomic commit to ensure it is
>>>> bisectable.
>>> I'm dropping this from my tree since I didn't get Ack from
>>> "arch/arm/boot/dts/stih416.dtsi" Maintainer.
>> Sorry, on cover letter, I replied the series looked good to me.
>> So you can add:
>>
>> Acked-by: Maxime Coquelin <maxime.coquelin-qxv4g6HH51o@public.gmane.org>
>>
>> And even:
>>
>> Tested-by: Maxime Coquelin <maxime.coquelin-qxv4g6HH51o@public.gmane.org>
> Thanks. I'll merge them now.
> I'd assume there won't be any conflicts when it gets merged to linus tree.
Thanks Kishon,

I have merged this patch with the last DT pull-request I sent for v3.20, 
and didn't had any conflicts.
So I'm confident there won't be any issue.

Br,
Maxime
>
> Cheers
> Kishon
>
>> Kind regards,
>> Maxime
>>
>>> Thanks
>>> Kishon
>>>> Signed-off-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>>> Reviewed-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
>>>> ---
>>>>    .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
>>>>    arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
>>>>    drivers/phy/phy-miphy365x.c                        | 29
>>>> ++++++++--------------
>>>>    3 files changed, 23 insertions(+), 31 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> index 42c8808..9802d5d 100644
>>>> --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> @@ -6,8 +6,10 @@ for SATA and PCIe.
>>>>      Required properties (controller (parent) node):
>>>>    - compatible    : Should be "st,miphy365x-phy"
>>>> -- st,syscfg     : Should be a phandle of the system configuration register
>>>> group
>>>> -          which contain the SATA, PCIe mode setting bits
>>>> +- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
>>>> +          containing the miphy registers and integer array should contain
>>>> +          an entry for each port sub-node, specifying the control
>>>> +          register offset inside the sysconfig group.
>>>>      Required nodes    :  A sub-node is required for each channel the controller
>>>>               provides. Address range information including the usual
>>>> @@ -26,7 +28,6 @@ Required properties (port (child) node):
>>>>              registers filled in "reg":
>>>>                - sata:   For SATA devices
>>>>                - pcie:   For PCIe devices
>>>> -            - syscfg: To specify the syscfg based config register
>>>>      Optional properties (port (child) node):
>>>>    - st,sata-gen         :    Generation of locally attached SATA IP.
>>>> Expected values
>>>> @@ -39,20 +40,20 @@ Example:
>>>>          miphy365x_phy: miphy365x@fe382000 {
>>>>            compatible      = "st,miphy365x-phy";
>>>> -        st,syscfg      = <&syscfg_rear>;
>>>> +        st,syscfg      = <&syscfg_rear 0x824 0x828>;
>>>>            #address-cells    = <1>;
>>>>            #size-cells    = <1>;
>>>>            ranges;
>>>>              phy_port0: port@fe382000 {
>>>> -            reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>>> -            reg-names = "sata", "pcie", "syscfg";
>>>> +            reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>>> +            reg-names = "sata", "pcie";
>>>>                #phy-cells = <1>;
>>>>                st,sata-gen = <3>;
>>>>            };
>>>>              phy_port1: port@fe38a000 {
>>>> -            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
>>>> +            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
>>>>                reg-names = "sata", "pcie", "syscfg";
>>>>                #phy-cells = <1>;
>>>>                st,pcie-tx-pol-inv;
>>>> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
>>>> index fad9073..85afe01 100644
>>>> --- a/arch/arm/boot/dts/stih416.dtsi
>>>> +++ b/arch/arm/boot/dts/stih416.dtsi
>>>> @@ -283,21 +283,21 @@
>>>>              miphy365x_phy: phy@fe382000 {
>>>>                compatible      = "st,miphy365x-phy";
>>>> -            st,syscfg      = <&syscfg_rear>;
>>>> +            st,syscfg    = <&syscfg_rear 0x824 0x828>;
>>>>                #address-cells    = <1>;
>>>>                #size-cells    = <1>;
>>>>                ranges;
>>>>                  phy_port0: port@fe382000 {
>>>>                    #phy-cells = <1>;
>>>> -                reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>>> -                reg-names = "sata", "pcie", "syscfg";
>>>> +                reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>>> +                reg-names = "sata", "pcie";
>>>>                };
>>>>                  phy_port1: port@fe38a000 {
>>>>                    #phy-cells = <1>;
>>>> -                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
>>>> -                reg-names = "sata", "pcie", "syscfg";
>>>> +                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
>>>> +                reg-names = "sata", "pcie";
>>>>                };
>>>>            };
>>>>    diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
>>>> index 6ab43a8..6c80154 100644
>>>> --- a/drivers/phy/phy-miphy365x.c
>>>> +++ b/drivers/phy/phy-miphy365x.c
>>>> @@ -141,7 +141,7 @@ struct miphy365x_phy {
>>>>        bool pcie_tx_pol_inv;
>>>>        bool sata_tx_pol_inv;
>>>>        u32 sata_gen;
>>>> -    u64 ctrlreg;
>>>> +    u32 ctrlreg;
>>>>        u8 type;
>>>>    };
>>>>    @@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy
>>>> *miphy_phy,
>>>>        bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
>>>>          return regmap_update_bits(miphy_dev->regmap,
>>>> -                  (unsigned int)miphy_phy->ctrlreg,
>>>> +                  miphy_phy->ctrlreg,
>>>>                      SYSCFG_SELECT_SATA_MASK,
>>>>                      sata << SYSCFG_SELECT_SATA_POS);
>>>>    }
>>>> @@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>>> miphy365x_phy *miphy_phy,
>>>>    {
>>>>        struct device_node *phynode = miphy_phy->phy->dev.of_node;
>>>>        const char *name;
>>>> -    const __be32 *taddr;
>>>>        int type = miphy_phy->type;
>>>>        int ret;
>>>>    @@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>>> miphy365x_phy *miphy_phy,
>>>>            return ret;
>>>>        }
>>>>    -    if (!strncmp(name, "syscfg", 6)) {
>>>> -        taddr = of_get_address(phynode, index, NULL, NULL);
>>>> -        if (!taddr) {
>>>> -            dev_err(dev, "failed to fetch syscfg address\n");
>>>> -            return -EINVAL;
>>>> -        }
>>>> -
>>>> -        miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
>>>> -        if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
>>>> -            dev_err(dev, "failed to translate syscfg address\n");
>>>> -            return -EINVAL;
>>>> -        }
>>>> -
>>>> -        return 0;
>>>> -    }
>>>> -
>>>>        if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
>>>>              (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
>>>>            return 0;
>>>> @@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
>>>>                return ret;
>>>>              phy_set_drvdata(phy, miphy_dev->phys[port]);
>>>> +
>>>>            port++;
>>>> +        /* sysconfig offsets are indexed from 1 */
>>>> +        ret = of_property_read_u32_index(np, "st,syscfg", port,
>>>> +                    &miphy_phy->ctrlreg);
>>>> +        if (ret) {
>>>> +            dev_err(&pdev->dev, "No sysconfig offset found\n");
>>>> +            return ret;
>>>> +        }
>>>>        }
>>>>          provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
>>>>

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[PATCH v2 2/7] phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.

[Maxime Coquelin]

On 01/30/2015 12:08 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Friday 30 January 2015 04:18 PM, Maxime Coquelin wrote:
>> Hi Kishon,
>>
>> On 01/30/2015 11:35 AM, Kishon Vijay Abraham I wrote:
>>> Hi,
>>>
>>> On Wednesday 07 January 2015 08:34 PM, Peter Griffin wrote:
>>>> Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161,
>>>> update the miphy365 phy driver to access sysconfig register offsets via
>>>> syscfg dt property.
>>>>
>>>> This is because the reg property should not be mixing address spaces
>>>> like it does currently for miphy365. This change then also aligns us
>>>> to how other platforms such as keystone and bcm7445 pass there syscon
>>>> offsets via DT.
>>>>
>>>> This patch breaks DT compatibility, but this platform is considered WIP,
>>>> and is only used by a few developers who are upstreaming support for it.
>>>> This change has been done as a single atomic commit to ensure it is
>>>> bisectable.
>>> I'm dropping this from my tree since I didn't get Ack from
>>> "arch/arm/boot/dts/stih416.dtsi" Maintainer.
>> Sorry, on cover letter, I replied the series looked good to me.
>> So you can add:
>>
>> Acked-by: Maxime Coquelin <maxime.coquelin@st.com>
>>
>> And even:
>>
>> Tested-by: Maxime Coquelin <maxime.coquelin@st.com>
> Thanks. I'll merge them now.
> I'd assume there won't be any conflicts when it gets merged to linus tree.
Thanks Kishon,

I have merged this patch with the last DT pull-request I sent for v3.20, 
and didn't had any conflicts.
So I'm confident there won't be any issue.

Br,
Maxime
>
> Cheers
> Kishon
>
>> Kind regards,
>> Maxime
>>
>>> Thanks
>>> Kishon
>>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>>> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
>>>> ---
>>>>    .../devicetree/bindings/phy/phy-miphy365x.txt      | 15 +++++------
>>>>    arch/arm/boot/dts/stih416.dtsi                     | 10 ++++----
>>>>    drivers/phy/phy-miphy365x.c                        | 29
>>>> ++++++++--------------
>>>>    3 files changed, 23 insertions(+), 31 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> index 42c8808..9802d5d 100644
>>>> --- a/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> +++ b/Documentation/devicetree/bindings/phy/phy-miphy365x.txt
>>>> @@ -6,8 +6,10 @@ for SATA and PCIe.
>>>>      Required properties (controller (parent) node):
>>>>    - compatible    : Should be "st,miphy365x-phy"
>>>> -- st,syscfg     : Should be a phandle of the system configuration register
>>>> group
>>>> -          which contain the SATA, PCIe mode setting bits
>>>> +- st,syscfg     : Phandle / integer array property. Phandle of sysconfig group
>>>> +          containing the miphy registers and integer array should contain
>>>> +          an entry for each port sub-node, specifying the control
>>>> +          register offset inside the sysconfig group.
>>>>      Required nodes    :  A sub-node is required for each channel the controller
>>>>               provides. Address range information including the usual
>>>> @@ -26,7 +28,6 @@ Required properties (port (child) node):
>>>>              registers filled in "reg":
>>>>                - sata:   For SATA devices
>>>>                - pcie:   For PCIe devices
>>>> -            - syscfg: To specify the syscfg based config register
>>>>      Optional properties (port (child) node):
>>>>    - st,sata-gen         :    Generation of locally attached SATA IP.
>>>> Expected values
>>>> @@ -39,20 +40,20 @@ Example:
>>>>          miphy365x_phy: miphy365x at fe382000 {
>>>>            compatible      = "st,miphy365x-phy";
>>>> -        st,syscfg      = <&syscfg_rear>;
>>>> +        st,syscfg      = <&syscfg_rear 0x824 0x828>;
>>>>            #address-cells    = <1>;
>>>>            #size-cells    = <1>;
>>>>            ranges;
>>>>              phy_port0: port at fe382000 {
>>>> -            reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>>> -            reg-names = "sata", "pcie", "syscfg";
>>>> +            reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>>> +            reg-names = "sata", "pcie";
>>>>                #phy-cells = <1>;
>>>>                st,sata-gen = <3>;
>>>>            };
>>>>              phy_port1: port at fe38a000 {
>>>> -            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;;
>>>> +            reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
>>>>                reg-names = "sata", "pcie", "syscfg";
>>>>                #phy-cells = <1>;
>>>>                st,pcie-tx-pol-inv;
>>>> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
>>>> index fad9073..85afe01 100644
>>>> --- a/arch/arm/boot/dts/stih416.dtsi
>>>> +++ b/arch/arm/boot/dts/stih416.dtsi
>>>> @@ -283,21 +283,21 @@
>>>>              miphy365x_phy: phy at fe382000 {
>>>>                compatible      = "st,miphy365x-phy";
>>>> -            st,syscfg      = <&syscfg_rear>;
>>>> +            st,syscfg    = <&syscfg_rear 0x824 0x828>;
>>>>                #address-cells    = <1>;
>>>>                #size-cells    = <1>;
>>>>                ranges;
>>>>                  phy_port0: port at fe382000 {
>>>>                    #phy-cells = <1>;
>>>> -                reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>;
>>>> -                reg-names = "sata", "pcie", "syscfg";
>>>> +                reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
>>>> +                reg-names = "sata", "pcie";
>>>>                };
>>>>                  phy_port1: port at fe38a000 {
>>>>                    #phy-cells = <1>;
>>>> -                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>;
>>>> -                reg-names = "sata", "pcie", "syscfg";
>>>> +                reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;
>>>> +                reg-names = "sata", "pcie";
>>>>                };
>>>>            };
>>>>    diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
>>>> index 6ab43a8..6c80154 100644
>>>> --- a/drivers/phy/phy-miphy365x.c
>>>> +++ b/drivers/phy/phy-miphy365x.c
>>>> @@ -141,7 +141,7 @@ struct miphy365x_phy {
>>>>        bool pcie_tx_pol_inv;
>>>>        bool sata_tx_pol_inv;
>>>>        u32 sata_gen;
>>>> -    u64 ctrlreg;
>>>> +    u32 ctrlreg;
>>>>        u8 type;
>>>>    };
>>>>    @@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy
>>>> *miphy_phy,
>>>>        bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
>>>>          return regmap_update_bits(miphy_dev->regmap,
>>>> -                  (unsigned int)miphy_phy->ctrlreg,
>>>> +                  miphy_phy->ctrlreg,
>>>>                      SYSCFG_SELECT_SATA_MASK,
>>>>                      sata << SYSCFG_SELECT_SATA_POS);
>>>>    }
>>>> @@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>>> miphy365x_phy *miphy_phy,
>>>>    {
>>>>        struct device_node *phynode = miphy_phy->phy->dev.of_node;
>>>>        const char *name;
>>>> -    const __be32 *taddr;
>>>>        int type = miphy_phy->type;
>>>>        int ret;
>>>>    @@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct
>>>> miphy365x_phy *miphy_phy,
>>>>            return ret;
>>>>        }
>>>>    -    if (!strncmp(name, "syscfg", 6)) {
>>>> -        taddr = of_get_address(phynode, index, NULL, NULL);
>>>> -        if (!taddr) {
>>>> -            dev_err(dev, "failed to fetch syscfg address\n");
>>>> -            return -EINVAL;
>>>> -        }
>>>> -
>>>> -        miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
>>>> -        if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
>>>> -            dev_err(dev, "failed to translate syscfg address\n");
>>>> -            return -EINVAL;
>>>> -        }
>>>> -
>>>> -        return 0;
>>>> -    }
>>>> -
>>>>        if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
>>>>              (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
>>>>            return 0;
>>>> @@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
>>>>                return ret;
>>>>              phy_set_drvdata(phy, miphy_dev->phys[port]);
>>>> +
>>>>            port++;
>>>> +        /* sysconfig offsets are indexed from 1 */
>>>> +        ret = of_property_read_u32_index(np, "st,syscfg", port,
>>>> +                    &miphy_phy->ctrlreg);
>>>> +        if (ret) {
>>>> +            dev_err(&pdev->dev, "No sysconfig offset found\n");
>>>> +            return ret;
>>>> +        }
>>>>        }
>>>>          provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
>>>>