Re: [PATCH 2/2] xen: arm: Warn if timer interrupts are not level triggered

From: Julien Grall <julien.grall@linaro.org>
To: Ian Campbell <ian.campbell@citrix.com>
Cc: stefano.stabellini@eu.citrix.com, tim@xen.org, xen-devel@lists.xen.org
Subject: Re: [PATCH 2/2] xen: arm: Warn if timer interrupts are not level triggered
Date: Thu, 19 Feb 2015 16:20:18 +0000	[thread overview]
Message-ID: <54E60D42.7060405@linaro.org> (raw)
In-Reply-To: <1424362240.30924.110.camel@citrix.com>

On 19/02/15 16:10, Ian Campbell wrote:
> On Thu, 2015-02-19 at 15:41 +0000, Julien Grall wrote:
>>> I did consider overriding the incorrect DT on such systems but since
>>> so far it has only been observed on emulators and we have code in
>>> place to deal with edge triggering here I think warning is sufficient
>>> for now.
> [...]
>>> + *
>>> + * Check each interrupt and warn if we find ourselves in this situation.
>>> + */
>>
>> Based on the comment, would it make sense to override the type of
>> interrupt to level in anycase? Even if the GIC allows us to write on ICFGR.
> 
> See the comment in the commit message (quoted above)

Sorry, I skipped this part of the commit message. I wasn't not sure
there is others issues that we don't have spot because of the edge
interrupt.

Regardless the question,this patch look good to me. With the 2 nits I
spotted on my previous email:

Reviewed-by: Julien Grall <julien.grall@linaro.org>

Regards,

-- 
Julien Grall