* [PATCH 1/5] drm/amd/powerplay: use PP_CAP macro for disable_mclk_switching_for_frame_lock
@ 2018-02-13 19:46 Alex Deucher
[not found] ` <20180213194637.23389-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Alex Deucher @ 2018-02-13 19:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Rather than open coding it.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 03a93b0eff38..6a153ad1b942 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3165,10 +3165,10 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
minimum_clocks.memoryClock = stable_pstate_mclk;
}
- disable_mclk_switching_for_frame_lock = phm_cap_enabled(
- hwmgr->platform_descriptor.platformCaps,
- PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
- disable_mclk_switching_for_vr = PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
+ disable_mclk_switching_for_frame_lock =
+ PP_CAP(PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
+ disable_mclk_switching_for_vr =
+ PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
disable_mclk_switching = (info.display_count > 1) ||
--
2.13.6
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/5] drm/amd/powerplay/vega10: allow mclk switching with no displays
[not found] ` <20180213194637.23389-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
@ 2018-02-13 19:46 ` Alex Deucher
2018-02-13 19:46 ` [PATCH 3/5] drm/amd/powerplay/smu7: " Alex Deucher
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2018-02-13 19:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
If there are no displays attached, there is no reason to disable
mclk switching.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
index 6a153ad1b942..1d442a498bf6 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c
@@ -3171,10 +3171,13 @@ static int vega10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
PP_CAP(PHM_PlatformCaps_DisableMclkSwitchForVR);
force_mclk_high = PP_CAP(PHM_PlatformCaps_ForceMclkHigh);
- disable_mclk_switching = (info.display_count > 1) ||
- disable_mclk_switching_for_frame_lock ||
- disable_mclk_switching_for_vr ||
- force_mclk_high;
+ if (info.display_count == 0)
+ disable_mclk_switching = false;
+ else
+ disable_mclk_switching = (info.display_count > 1) ||
+ disable_mclk_switching_for_frame_lock ||
+ disable_mclk_switching_for_vr ||
+ force_mclk_high;
sclk = vega10_ps->performance_levels[0].gfx_clock;
mclk = vega10_ps->performance_levels[0].mem_clock;
--
2.13.6
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/5] drm/amd/powerplay/smu7: allow mclk switching with no displays
[not found] ` <20180213194637.23389-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-02-13 19:46 ` [PATCH 2/5] drm/amd/powerplay/vega10: allow mclk switching with no displays Alex Deucher
@ 2018-02-13 19:46 ` Alex Deucher
2018-02-13 19:46 ` [PATCH 4/5] drm/amdgpu/cgs: add refresh rate checking to non-DC display code Alex Deucher
2018-02-13 19:46 ` [PATCH 5/5] drm/amdgpu/powerplay/smu7: drop refresh rate checks for mclk switching Alex Deucher
3 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2018-02-13 19:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
If there are no displays attached, there is no reason to disable
mclk switching.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 937971361b65..84600ff6f4de 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2904,10 +2904,13 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
PHM_PlatformCaps_DisableMclkSwitchingForFrameLock);
- disable_mclk_switching = ((1 < info.display_count) ||
- disable_mclk_switching_for_frame_lock ||
- smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
- (mode_info.refresh_rate > 120));
+ if (info.display_count == 0)
+ disable_mclk_switching = false;
+ else
+ disable_mclk_switching = ((1 < info.display_count) ||
+ disable_mclk_switching_for_frame_lock ||
+ smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
+ (mode_info.refresh_rate > 120));
sclk = smu7_ps->performance_levels[0].engine_clock;
mclk = smu7_ps->performance_levels[0].memory_clock;
--
2.13.6
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/5] drm/amdgpu/cgs: add refresh rate checking to non-DC display code
[not found] ` <20180213194637.23389-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-02-13 19:46 ` [PATCH 2/5] drm/amd/powerplay/vega10: allow mclk switching with no displays Alex Deucher
2018-02-13 19:46 ` [PATCH 3/5] drm/amd/powerplay/smu7: " Alex Deucher
@ 2018-02-13 19:46 ` Alex Deucher
2018-02-13 19:46 ` [PATCH 5/5] drm/amdgpu/powerplay/smu7: drop refresh rate checks for mclk switching Alex Deucher
3 siblings, 0 replies; 6+ messages in thread
From: Alex Deucher @ 2018-02-13 19:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher
Clamp the vblank period to 0 if the refresh rate is larger than
120 hz for non-DC. This allows us to remove the refresh rate
checks from powerplay for mclk switching.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 71b4aec7f650..dc3360b16bda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -953,6 +953,11 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
(amdgpu_crtc->v_border * 2);
mode_info->vblank_time_us = vblank_lines * line_time_us;
mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
+ /* we have issues with mclk switching with refresh rates
+ * over 120 hz on the non-DC code.
+ */
+ if (mode_info->refresh_rate > 120)
+ mode_info->vblank_time_us = 0;
mode_info = NULL;
}
}
--
2.13.6
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 5/5] drm/amdgpu/powerplay/smu7: drop refresh rate checks for mclk switching
[not found] ` <20180213194637.23389-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
` (2 preceding siblings ...)
2018-02-13 19:46 ` [PATCH 4/5] drm/amdgpu/cgs: add refresh rate checking to non-DC display code Alex Deucher
@ 2018-02-13 19:46 ` Alex Deucher
[not found] ` <20180213194637.23389-5-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
3 siblings, 1 reply; 6+ messages in thread
From: Alex Deucher @ 2018-02-13 19:46 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Alex Deucher, Harry Wentland
The logic has moved to cgs. mclk switching with DC at higher refresh
rates should work.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Harry Wentland <harry.wentland.@amd.com>
---
drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
index 84600ff6f4de..0202841ae639 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
@@ -2909,8 +2909,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
else
disable_mclk_switching = ((1 < info.display_count) ||
disable_mclk_switching_for_frame_lock ||
- smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
- (mode_info.refresh_rate > 120));
+ smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us));
sclk = smu7_ps->performance_levels[0].engine_clock;
mclk = smu7_ps->performance_levels[0].memory_clock;
--
2.13.6
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 5/5] drm/amdgpu/powerplay/smu7: drop refresh rate checks for mclk switching
[not found] ` <20180213194637.23389-5-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
@ 2018-02-14 16:54 ` Eric Huang
0 siblings, 0 replies; 6+ messages in thread
From: Eric Huang @ 2018-02-14 16:54 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
The series: Reviewed-by: Eric Huang <JinhuiEric.Huang@amd.com>
On 2018-02-13 02:46 PM, Alex Deucher wrote:
> The logic has moved to cgs. mclk switching with DC at higher refresh
> rates should work.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> Cc: Harry Wentland <harry.wentland.@amd.com>
> ---
> drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> index 84600ff6f4de..0202841ae639 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c
> @@ -2909,8 +2909,7 @@ static int smu7_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
> else
> disable_mclk_switching = ((1 < info.display_count) ||
> disable_mclk_switching_for_frame_lock ||
> - smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us) ||
> - (mode_info.refresh_rate > 120));
> + smu7_vblank_too_short(hwmgr, mode_info.vblank_time_us));
>
> sclk = smu7_ps->performance_levels[0].engine_clock;
> mclk = smu7_ps->performance_levels[0].memory_clock;
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-02-14 16:54 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2018-02-13 19:46 [PATCH 1/5] drm/amd/powerplay: use PP_CAP macro for disable_mclk_switching_for_frame_lock Alex Deucher
[not found] ` <20180213194637.23389-1-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-02-13 19:46 ` [PATCH 2/5] drm/amd/powerplay/vega10: allow mclk switching with no displays Alex Deucher
2018-02-13 19:46 ` [PATCH 3/5] drm/amd/powerplay/smu7: " Alex Deucher
2018-02-13 19:46 ` [PATCH 4/5] drm/amdgpu/cgs: add refresh rate checking to non-DC display code Alex Deucher
2018-02-13 19:46 ` [PATCH 5/5] drm/amdgpu/powerplay/smu7: drop refresh rate checks for mclk switching Alex Deucher
[not found] ` <20180213194637.23389-5-alexander.deucher-5C7GfCeVMHo@public.gmane.org>
2018-02-14 16:54 ` Eric Huang
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