at91 clocks

at91 clocks

[Jonas Andersson]

Hi all,

I am working on a system with at91sam9260 soc. Trying to move from 
kernel 3.17.4 to 3.19.2. I have problem with pck1 clock.

In my old code i use clk_get() to get pck1 and pllb, set pllb as parent 
for pck1, set rate for pck1, enable pck1. Extract from 
/sys/kernel/debug/at91_clk:
pllb       users= 1 on   96000000 Hz main
pck1       users= 1 on   12000000 Hz pllb

In my new code i have defined the two clocks in DT:
         clocks = <&prog1>, <&pllb>;
         clock-names = "codec", "parent";
Extract from  /sys/kernel/debug/clk/clk_summary:
        mainck                             2            2 
18432000          0 0
           prog1                           1            1 
9216000          0 0
              pck1                         0            0 
9216000          0 0
           pllbck                          0            0 0          0 0
              usbck                        0            0 0          0 0
                 udpck                     0            0 0          0 0
                 uhpck                     0            0 0          0 0

I know i probably have to enable pck1 also.
But my main problem is that I got the wrong frequency and parent of prog1.
Why?

Thanks
  Jonas

at91 clocks

[Boris Brezillon]

Hi Jonas,

On Tue, 24 Mar 2015 15:32:08 +0100
Jonas Andersson <jonas@microbit.se> wrote:

> Hi all,
> 
> I am working on a system with at91sam9260 soc. Trying to move from 
> kernel 3.17.4 to 3.19.2. I have problem with pck1 clock.
> 
> In my old code i use clk_get() to get pck1 and pllb, set pllb as parent 
> for pck1, set rate for pck1, enable pck1.

How do you do that (clk_set_parent + clk_set_rate) ?
Could you paste your code somewhere ?

> Extract from 
> /sys/kernel/debug/at91_clk:
> pllb       users= 1 on   96000000 Hz main
> pck1       users= 1 on   12000000 Hz pllb
> 
> In my new code i have defined the two clocks in DT:
>          clocks = <&prog1>, <&pllb>;
>          clock-names = "codec", "parent";
> Extract from  /sys/kernel/debug/clk/clk_summary:
>         mainck                             2            2 
> 18432000          0 0
>            prog1                           1            1 
> 9216000          0 0
>               pck1                         0            0 
> 9216000          0 0
>            pllbck                          0            0 0          0 0
>               usbck                        0            0 0          0 0
>                  udpck                     0            0 0          0 0
>                  uhpck                     0            0 0          0 0
> 
> I know i probably have to enable pck1 also.
> But my main problem is that I got the wrong frequency and parent of prog1.
> Why?

With the new implementation calling clk_set_rate(pck1, 120000000)
should do the job: it should choose the best parent clk and divisor.

Best Regards,

Boris


-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

at91 clocks

[Jonas Andersson]

Hi Boris and others,

On 2015-03-25 01:32, Boris Brezillon wrote:
> Hi Jonas,
>
> On Tue, 24 Mar 2015 15:32:08 +0100
> Jonas Andersson <jonas@microbit.se> wrote:
>
>> Hi all,
>>
>> I am working on a system with at91sam9260 soc. Trying to move from
>> kernel 3.17.4 to 3.19.2. I have problem with pck1 clock.
>>
>> In my old code i use clk_get() to get pck1 and pllb, set pllb as parent
>> for pck1, set rate for pck1, enable pck1.
> How do you do that (clk_set_parent + clk_set_rate) ?
> Could you paste your code somewhere ?

Yes, see http://pastie.org/10052161

>
>> Extract from
>> /sys/kernel/debug/at91_clk:
>> pllb       users= 1 on   96000000 Hz main
>> pck1       users= 1 on   12000000 Hz pllb
>>
> With the new implementation calling clk_set_rate(pck1, 120000000)
> should do the job: it should choose the best parent clk and divisor.

Ok thank you for that information. I tried that now (new code in link 
above), and i got a clock output but not exactly my wanted 12MHz. I 
measure 9.216MHz at pck1 output.

        mainck                             2            2 
18432000          0 0
           prog1                           1            1 
9216000          0 0
              pck1                         1            1 
9216000          0 0

pllbck is still unused.

I tried kernel 4.0-rc5 but it hangs in boot after ethernet init.

Best regards
  Jonas

at91 clocks

[Boris Brezillon]

Hi Jonas,

On Wed, 25 Mar 2015 10:06:46 +0100
Jonas Andersson <jonas@microbit.se> wrote:

> Hi Boris and others,
> 
> On 2015-03-25 01:32, Boris Brezillon wrote:
> > Hi Jonas,
> >
> > On Tue, 24 Mar 2015 15:32:08 +0100
> > Jonas Andersson <jonas@microbit.se> wrote:
> >
> >> Hi all,
> >>
> >> I am working on a system with at91sam9260 soc. Trying to move from
> >> kernel 3.17.4 to 3.19.2. I have problem with pck1 clock.
> >>
> >> In my old code i use clk_get() to get pck1 and pllb, set pllb as parent
> >> for pck1, set rate for pck1, enable pck1.
> > How do you do that (clk_set_parent + clk_set_rate) ?
> > Could you paste your code somewhere ?
> 
> Yes, see http://pastie.org/10052161

Your pllb seems to be configured to output a 0Hz rate, and I'm not
forwarding rate change to prog clk parents yet.
That's definitely something I should work on, but in the meantime you
could try to manually set pllb rate.

> 
> >
> >> Extract from
> >> /sys/kernel/debug/at91_clk:
> >> pllb       users= 1 on   96000000 Hz main
> >> pck1       users= 1 on   12000000 Hz pllb
> >>
> > With the new implementation calling clk_set_rate(pck1, 120000000)
> > should do the job: it should choose the best parent clk and divisor.
> 
> Ok thank you for that information. I tried that now (new code in link 
> above), and i got a clock output but not exactly my wanted 12MHz. I 
> measure 9.216MHz at pck1 output.
> 
>         mainck                             2            2 
> 18432000          0 0
>            prog1                           1            1 
> 9216000          0 0
>               pck1                         1            1 
> 9216000          0 0
> 
> pllbck is still unused.
> 
> I tried kernel 4.0-rc5 but it hangs in boot after ethernet init.

Is this related to the changes I suggested ?

Best Regards,

Boris


-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

at91 clocks

[Nicolas Ferre]

Le 25/03/2015 17:37, Boris Brezillon a ?crit :
> Hi Jonas,
> 
> On Wed, 25 Mar 2015 10:06:46 +0100
> Jonas Andersson <jonas@microbit.se> wrote:
> 
>> Hi Boris and others,
>>
>> On 2015-03-25 01:32, Boris Brezillon wrote:
>>> Hi Jonas,
>>>
>>> On Tue, 24 Mar 2015 15:32:08 +0100
>>> Jonas Andersson <jonas@microbit.se> wrote:
>>>
>>>> Hi all,
>>>>
>>>> I am working on a system with at91sam9260 soc. Trying to move from
>>>> kernel 3.17.4 to 3.19.2. I have problem with pck1 clock.
>>>>
>>>> In my old code i use clk_get() to get pck1 and pllb, set pllb as parent
>>>> for pck1, set rate for pck1, enable pck1.
>>> How do you do that (clk_set_parent + clk_set_rate) ?
>>> Could you paste your code somewhere ?
>>
>> Yes, see http://pastie.org/10052161
> 
> Your pllb seems to be configured to output a 0Hz rate, and I'm not
> forwarding rate change to prog clk parents yet.
> That's definitely something I should work on, but in the meantime you
> could try to manually set pllb rate.
> 
>>
>>>
>>>> Extract from
>>>> /sys/kernel/debug/at91_clk:
>>>> pllb       users= 1 on   96000000 Hz main
>>>> pck1       users= 1 on   12000000 Hz pllb
>>>>
>>> With the new implementation calling clk_set_rate(pck1, 120000000)
>>> should do the job: it should choose the best parent clk and divisor.
>>
>> Ok thank you for that information. I tried that now (new code in link 
>> above), and i got a clock output but not exactly my wanted 12MHz. I 
>> measure 9.216MHz at pck1 output.
>>
>>         mainck                             2            2 
>> 18432000          0 0
>>            prog1                           1            1 
>> 9216000          0 0
>>               pck1                         1            1 
>> 9216000          0 0
>>
>> pllbck is still unused.
>>
>> I tried kernel 4.0-rc5 but it hangs in boot after ethernet init.
> 
> Is this related to the changes I suggested ?

It seems to be related as I tried to boot an at91sam9260ek with current
Linus' tree and it doesn't hangs after Ethernet on my side...

Bye,
-- 
Nicolas Ferre

at91 clocks

[Jonas Andersson]

Hi Boris and others,

>>>> Hi all,
>>>>
>>>> I am working on a system with at91sam9260 soc. Trying to move from
>>>> kernel 3.17.4 to 3.19.2. I have problem with pck1 clock.
>>>>
>>>> In my old code i use clk_get() to get pck1 and pllb, set pllb as parent
>>>> for pck1, set rate for pck1, enable pck1.
>>> How do you do that (clk_set_parent + clk_set_rate) ?
>>> Could you paste your code somewhere ?
>> Yes, seehttp://pastie.org/10052161
> Your pllb seems to be configured to output a 0Hz rate, and I'm not
> forwarding rate change to prog clk parents yet.
> That's definitely something I should work on, but in the meantime you
> could try to manually set pllb rate.

I tried to set pllb rate to 96MHz but it still shows 0Hz. |clk_set_rate 
returns 0|.

>
>> I tried kernel 4.0-rc5 but it hangs in boot after ethernet init. 
> Is this related to the changes I suggested ?
>
No, it doesnt work before changes. I will try to get it running later, 
direct from linus tree without modifications..

Thanks for help.
  Jonas

at91 clocks

[Boris Brezillon]

Hi Jonas,

On Thu, 26 Mar 2015 10:53:05 +0100
Jonas Andersson <jonas@microbit.se> wrote:

> Hi Boris and others,
> 
> >>>> Hi all,
> >>>>
> >>>> I am working on a system with at91sam9260 soc. Trying to move from
> >>>> kernel 3.17.4 to 3.19.2. I have problem with pck1 clock.
> >>>>
> >>>> In my old code i use clk_get() to get pck1 and pllb, set pllb as parent
> >>>> for pck1, set rate for pck1, enable pck1.
> >>> How do you do that (clk_set_parent + clk_set_rate) ?
> >>> Could you paste your code somewhere ?
> >> Yes, see http://pastie.org/10052161

Could you paste the new version of your code (the one with clk_set_rate
on pllb) ?

> > Your pllb seems to be configured to output a 0Hz rate, and I'm not
> > forwarding rate change to prog clk parents yet.
> > That's definitely something I should work on, but in the meantime you
> > could try to manually set pllb rate.
> 
> I tried to set pllb rate to 96MHz but it still shows 0Hz. |clk_set_rate 
> returns 0|.

Have you tested pllb pointer value ? As you can see here [1], the CCF
is not complaining when you pass a NULL pointer.

> 
> >
> >> I tried kernel 4.0-rc5 but it hangs in boot after ethernet init. 
> > Is this related to the changes I suggested ?
> >
> No, it doesnt work before changes. I will try to get it running later, 
> direct from linus tree without modifications..

This might not be related to your clock problem then. Have your tried
to boot 4.0-rc4 ?

Best Regards,

Boris

[1]http://lxr.free-electrons.com/source/drivers/clk/clk.c#L1535

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

at91 clocks

[Jonas Andersson]

Hi Nicolas,

On 2015-03-25 19:18, Nicolas Ferre wrote:
> I tried kernel 4.0-rc5 but it hangs in boot after ethernet init.
>> Is this related to the changes I suggested ?
> It seems to be related as I tried to boot an at91sam9260ek with current
> Linus' tree and it doesn't hangs after Ethernet on my side...
>
Could you send me your dts and .config? I can not boot any unmodified 
4.0 rc on my board. Tested rc1, rc4, rc5, HEAD.

Output
...
[    1.730000] macb fffc4000.ethernet eth0: attached PHY driver [Generic 
PHY] (mii_bus:phy_addr=fffc4000.etherne:00, irq=-1)
[   82.570000] random: nonblocking pool is initialized

Best regards
  Jonas

at91 clocks

[Nicolas Ferre]

Le 27/03/2015 10:28, Jonas Andersson a ?crit :
> Hi Nicolas,
> 
> On 2015-03-25 19:18, Nicolas Ferre wrote:
>> I tried kernel 4.0-rc5 but it hangs in boot after ethernet init.
>>> Is this related to the changes I suggested ?
>> It seems to be related as I tried to boot an at91sam9260ek with current
>> Linus' tree and it doesn't hangs after Ethernet on my side...
>>
> Could you send me your dts and .config? I can not boot any unmodified 
> 4.0 rc on my board. Tested rc1, rc4, rc5, HEAD.

Yes: here are they:
at91sam9260ek.dts
http://paste.debian.net/163475/

.config
http://paste.debian.net/163477/

Best regards,

> Output
> ...
> [    1.730000] macb fffc4000.ethernet eth0: attached PHY driver [Generic 
> PHY] (mii_bus:phy_addr=fffc4000.etherne:00, irq=-1)
> [   82.570000] random: nonblocking pool is initialized
> 
> Best regards
>   Jonas
> 
> 
> 


-- 
Nicolas Ferre

at91 clocks

[Jonas Andersson]

Hi Boris,

On 2015-03-26 16:28, Boris Brezillon wrote:
>>>>>> Hi all,
>>>>>>
>>>>>> I am working on a system with at91sam9260 soc. Trying to move from
>>>>>> kernel 3.17.4 to 3.19.2. I have problem with pck1 clock.
>>>>>>
>>>>>> In my old code i use clk_get() to get pck1 and pllb, set pllb as parent
>>>>>> for pck1, set rate for pck1, enable pck1.
>>>>> How do you do that (clk_set_parent + clk_set_rate) ?
>>>>> Could you paste your code somewhere ?
>>>> Yes, see http://pastie.org/10052161
> Could you paste the new version of your code (the one with clk_set_rate
> on pllb) ?
Added this at http://pastie.org/10057041
>>> Your pllb seems to be configured to output a 0Hz rate, and I'm not
>>> forwarding rate change to prog clk parents yet.
>>> That's definitely something I should work on, but in the meantime you
>>> could try to manually set pllb rate.
>> I tried to set pllb rate to 96MHz but it still shows 0Hz. |clk_set_rate
>> returns 0|.
> Have you tested pllb pointer value ? As you can see here [1], the CCF
> is not complaining when you pass a NULL pointer.

I tested with IS_ERR, changed this to IS_ERR_OR_NULL, but the pointer is ok.

Best regards
  Jonas

at91 clocks

[Boris Brezillon]

Hi Jonas,

On Fri, 27 Mar 2015 11:21:50 +0100
Jonas Andersson <jonas@microbit.se> wrote:

> Hi Boris,
> 
> On 2015-03-26 16:28, Boris Brezillon wrote:
> >>>>>> Hi all,
> >>>>>>
> >>>>>> I am working on a system with at91sam9260 soc. Trying to move from
> >>>>>> kernel 3.17.4 to 3.19.2. I have problem with pck1 clock.
> >>>>>>
> >>>>>> In my old code i use clk_get() to get pck1 and pllb, set pllb as parent
> >>>>>> for pck1, set rate for pck1, enable pck1.
> >>>>> How do you do that (clk_set_parent + clk_set_rate) ?
> >>>>> Could you paste your code somewhere ?
> >>>> Yes, see http://pastie.org/10052161
> > Could you paste the new version of your code (the one with clk_set_rate
> > on pllb) ?
> Added this at http://pastie.org/10057041

Seems good.

> >>> Your pllb seems to be configured to output a 0Hz rate, and I'm not
> >>> forwarding rate change to prog clk parents yet.
> >>> That's definitely something I should work on, but in the meantime you
> >>> could try to manually set pllb rate.
> >> I tried to set pllb rate to 96MHz but it still shows 0Hz. |clk_set_rate
> >> returns 0|.
> > Have you tested pllb pointer value ? As you can see here [1], the CCF
> > is not complaining when you pass a NULL pointer.
> 
> I tested with IS_ERR, changed this to IS_ERR_OR_NULL, but the pointer is ok.

Can you print clk_get_rate(parent_clk) result ?

Best Regards,

Boris


-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

at91 clocks

[Boris Brezillon]

On Fri, 27 Mar 2015 13:20:03 +0100
Boris Brezillon <boris.brezillon@free-electrons.com> wrote:


> > 
> > I tested with IS_ERR, changed this to IS_ERR_OR_NULL, but the pointer is ok.
> 
> Can you print clk_get_rate(parent_clk) result ?

Could you also paste me the whole clk_summary content ?


-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

at91 clocks

[Jonas Andersson]

Hi Boris,
On 2015-03-27 13:25, Boris Brezillon wrote:
> On Fri, 27 Mar 2015 13:20:03 +0100
> Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
>
>
>>> I tested with IS_ERR, changed this to IS_ERR_OR_NULL, but the pointer is ok.
>> Can you print clk_get_rate(parent_clk) result ?
> Could you also paste me the whole clk_summary content ?
>
>
http://pastie.org/10057268

Best regards
  Jonas

at91 clocks

[Boris Brezillon]

On Fri, 27 Mar 2015 13:51:46 +0100
Jonas Andersson <jonas@microbit.se> wrote:

> Hi Boris,
> On 2015-03-27 13:25, Boris Brezillon wrote:
> > On Fri, 27 Mar 2015 13:20:03 +0100
> > Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
> >
> >
> >>> I tested with IS_ERR, changed this to IS_ERR_OR_NULL, but the pointer is ok.
> >> Can you print clk_get_rate(parent_clk) result ?
> > Could you also paste me the whole clk_summary content ?
> >
> >
> http://pastie.org/10057268

Could you try with this patch [1] ?
Anyway, I don't understand why clk_set_rate returns 0 even when it
fails to set the appropriate rate.
Could you add some traces in drivers/clk/at91/clk-pll.c
(clk_pll_round_rate, clk_pll_set_rate and clk_pll_get_best_div_mul) ?

Thanks,

Boris

[1]http://code.bulix.org/gxxhc4-88138

-- 
Boris Brezillon, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

at91 clocks

[Jonas Andersson]

Hi Boris,

On 2015-03-27 14:54, Boris Brezillon wrote:
>>>
>>> Could you also paste me the whole clk_summary content ?
>>>
>>>
>> http://pastie.org/10057268
> Could you try with this patch [1] ?

Yes, it works now! Thank you.

> Anyway, I don't understand why clk_set_rate returns 0 even when it
> fails to set the appropriate rate.
> Could you add some traces in drivers/clk/at91/clk-pll.c
> (clk_pll_round_rate, clk_pll_set_rate and clk_pll_get_best_div_mul) ?

Yes I'll try to do it on Monday next week.

> Thanks,
>
> Boris
>
> [1]http://code.bulix.org/gxxhc4-88138
>
Best regards
  Jonas

at91 clocks

[Jonas Andersson]

Hi Boris,

On 2015-03-27 15:42, Jonas Andersson wrote:
>
>> Anyway, I don't understand why clk_set_rate returns 0 even when it
>> fails to set the appropriate rate.
>> Could you add some traces in drivers/clk/at91/clk-pll.c
>> (clk_pll_round_rate, clk_pll_set_rate and clk_pll_get_best_div_mul) ?
>
> Yes I'll try to do it on Monday next week.
>
Result and source at http://pastie.org/10062457

Best regards
  Jonas