[PATCH v2 0/8] Add sd/emmc support for stih407 family silicon

[PATCH v2 0/8] Add sd/emmc support for stih407 family silicon

[Peter Griffin]

Hi,

This series adds sd/emmc support to the sdhci-st.c driver for stih407
family silicon. The changes mainly involve congiguring some extra glue
registers in the flashSS which configure the Arasan controller.

This series also adds support for UHS modes for eMMC. To allow
UHS HS200/SD104 modes to function correctly, due to the
tight timing constriants, support for delay management is also added.
Two types of delay management are supported, static delay management and
dynamic delay management, this delay management is only available
on eMMC pads on stih410 and later silicon.

This series has been tested with stih410-b2120 on eMMC and sd, at various
clock speeds. As part of this testing a bug was also found in the
upstream flexgen clock set_rate implementation (now fixed upstream).

    max-frequency = 200Mhz
    /dev/mmcblk0p1:
     Timing buffered disk reads: 270 MB in  3.02 seconds =  89.54 MB/sec
    
    max-frequency = 100Mhz
    root@debian-armhf:~# hdparm -t /dev/mmcblk0p1
    /dev/mmcblk0p1:
     Timing buffered disk reads: 210 MB in  3.00 seconds =  70.00 MB/sec
    
    max-frequency = 50Mhz
    root@debian-armhf:~# hdparm -t /dev/mmcblk0p1
    /dev/mmcblk0p1:
     Timing buffered disk reads: 118 MB in  3.00 seconds =  39.28 MB/sec

It has also been tested on stih416-b2020 to ensure we have caused no
regressions. Finally the dt documentation has been updated to reflect
the changes in the driver code. Intrestingly it seems we are the first
upstream platform to be using some of the uhs bindings such as
sd-uhs-sdr104.

Changes since v1:
 - Partition the changes into smaller patches to aid review process (Ulf)

regards,

Peter.

Peter Griffin (8):
  mmc: sdhci-st: Add macros for register offsets and bitfields for mmcss
    glue regs
  mmc: sdhci-st: Add support for de-asserting reset signal and top regs
    resource
  mmc: sdhci-st: Add delay management functions for top registers
    (eMMC).
  mmc: sdhci-st: Add st_mmcss_cconfig function to configure mmcss glue
    registers.
  mmc: sdhci-st: Add sdhci_st_set_uhs_signaling function.
  mmc: sdhci-st: Update the quirks for this controller.
  mmc: sdhci-st: Update ST SDHCI binding documentation.
  ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

 Documentation/devicetree/bindings/mmc/sdhci-st.txt | 100 +++++-
 arch/arm/boot/dts/stih407-family.dtsi              |  30 ++
 arch/arm/boot/dts/stih410-b2120.dts                |  10 +
 arch/arm/boot/dts/stihxxx-b2120.dtsi               |   8 +
 drivers/mmc/host/sdhci-st.c                        | 344 ++++++++++++++++++++-
 5 files changed, 478 insertions(+), 14 deletions(-)

-- 
1.9.1

[PATCH v2 0/8] Add sd/emmc support for stih407 family silicon

[Peter Griffin]

Hi,

This series adds sd/emmc support to the sdhci-st.c driver for stih407
family silicon. The changes mainly involve congiguring some extra glue
registers in the flashSS which configure the Arasan controller.

This series also adds support for UHS modes for eMMC. To allow
UHS HS200/SD104 modes to function correctly, due to the
tight timing constriants, support for delay management is also added.
Two types of delay management are supported, static delay management and
dynamic delay management, this delay management is only available
on eMMC pads on stih410 and later silicon.

This series has been tested with stih410-b2120 on eMMC and sd, at various
clock speeds. As part of this testing a bug was also found in the
upstream flexgen clock set_rate implementation (now fixed upstream).

    max-frequency = 200Mhz
    /dev/mmcblk0p1:
     Timing buffered disk reads: 270 MB in  3.02 seconds =  89.54 MB/sec
    
    max-frequency = 100Mhz
    root at debian-armhf:~# hdparm -t /dev/mmcblk0p1
    /dev/mmcblk0p1:
     Timing buffered disk reads: 210 MB in  3.00 seconds =  70.00 MB/sec
    
    max-frequency = 50Mhz
    root at debian-armhf:~# hdparm -t /dev/mmcblk0p1
    /dev/mmcblk0p1:
     Timing buffered disk reads: 118 MB in  3.00 seconds =  39.28 MB/sec

It has also been tested on stih416-b2020 to ensure we have caused no
regressions. Finally the dt documentation has been updated to reflect
the changes in the driver code. Intrestingly it seems we are the first
upstream platform to be using some of the uhs bindings such as
sd-uhs-sdr104.

Changes since v1:
 - Partition the changes into smaller patches to aid review process (Ulf)

regards,

Peter.

Peter Griffin (8):
  mmc: sdhci-st: Add macros for register offsets and bitfields for mmcss
    glue regs
  mmc: sdhci-st: Add support for de-asserting reset signal and top regs
    resource
  mmc: sdhci-st: Add delay management functions for top registers
    (eMMC).
  mmc: sdhci-st: Add st_mmcss_cconfig function to configure mmcss glue
    registers.
  mmc: sdhci-st: Add sdhci_st_set_uhs_signaling function.
  mmc: sdhci-st: Update the quirks for this controller.
  mmc: sdhci-st: Update ST SDHCI binding documentation.
  ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

 Documentation/devicetree/bindings/mmc/sdhci-st.txt | 100 +++++-
 arch/arm/boot/dts/stih407-family.dtsi              |  30 ++
 arch/arm/boot/dts/stih410-b2120.dts                |  10 +
 arch/arm/boot/dts/stihxxx-b2120.dtsi               |   8 +
 drivers/mmc/host/sdhci-st.c                        | 344 ++++++++++++++++++++-
 5 files changed, 478 insertions(+), 14 deletions(-)

-- 
1.9.1

[PATCH v2 1/8] mmc: sdhci-st: Add macros for register offsets and bitfields for mmcss glue regs

[Peter Griffin]

The stih407 family SoC's have additional glue registers in the flashSS which
are used to configure the Arasan controller.

This patch adds macros for the register offsets and bitfields which will be used by
subsequent patches to support stih407 family SoC's.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 91 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index 882b07e..a3bc3c3 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -26,6 +26,97 @@
 
 #include "sdhci-pltfm.h"
 
+/* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */
+
+#define	ST_MMC_CCONFIG_REG_1		0x400
+#define ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT	BIT(24)
+#define ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ	BIT(12)
+#define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT	BIT(8)
+#define ST_MMC_CCONFIG_ASYNC_WAKEUP	BIT(0)
+#define ST_MMC_CCONFIG_1_DEFAULT	\
+				((ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT) | \
+				 (ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ) | \
+				 (ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT))
+
+#define ST_MMC_CCONFIG_REG_2		0x404
+#define ST_MMC_CCONFIG_HIGH_SPEED	BIT(28)
+#define ST_MMC_CCONFIG_ADMA2		BIT(24)
+#define ST_MMC_CCONFIG_8BIT		BIT(20)
+#define ST_MMC_CCONFIG_MAX_BLK_LEN	16
+#define  MAX_BLK_LEN_1024		1
+#define  MAX_BLK_LEN_2048		2
+#define BASE_CLK_FREQ_200		0xc8
+#define BASE_CLK_FREQ_100		0x64
+#define BASE_CLK_FREQ_50		0x32
+#define ST_MMC_CCONFIG_2_DEFAULT \
+	(ST_MMC_CCONFIG_HIGH_SPEED | ST_MMC_CCONFIG_ADMA2 | \
+	 ST_MMC_CCONFIG_8BIT | \
+	 (MAX_BLK_LEN_1024 << ST_MMC_CCONFIG_MAX_BLK_LEN))
+
+#define ST_MMC_CCONFIG_REG_3			0x408
+#define ST_MMC_CCONFIG_EMMC_SLOT_TYPE		BIT(28)
+#define ST_MMC_CCONFIG_64BIT			BIT(24)
+#define ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	BIT(20)
+#define ST_MMC_CCONFIG_1P8_VOLT			BIT(16)
+#define ST_MMC_CCONFIG_3P0_VOLT			BIT(12)
+#define ST_MMC_CCONFIG_3P3_VOLT			BIT(8)
+#define ST_MMC_CCONFIG_SUSP_RES_SUPPORT		BIT(4)
+#define ST_MMC_CCONFIG_SDMA			BIT(0)
+#define ST_MMC_CCONFIG_3_DEFAULT	\
+			 (ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	| \
+			  ST_MMC_CCONFIG_3P3_VOLT		| \
+			  ST_MMC_CCONFIG_SUSP_RES_SUPPORT	| \
+			  ST_MMC_CCONFIG_SDMA)
+
+#define ST_MMC_CCONFIG_REG_4	0x40c
+#define ST_MMC_CCONFIG_D_DRIVER	BIT(20)
+#define ST_MMC_CCONFIG_C_DRIVER	BIT(16)
+#define ST_MMC_CCONFIG_A_DRIVER	BIT(12)
+#define ST_MMC_CCONFIG_DDR50	BIT(8)
+#define ST_MMC_CCONFIG_SDR104	BIT(4)
+#define ST_MMC_CCONFIG_SDR50	BIT(0)
+#define ST_MMC_CCONFIG_4_DEFAULT	0
+
+#define ST_MMC_CCONFIG_REG_5		0x410
+#define ST_MMC_CCONFIG_TUNING_FOR_SDR50	BIT(8)
+#define RETUNING_TIMER_CNT_MAX		0xf
+#define ST_MMC_CCONFIG_5_DEFAULT	0
+
+/* I/O configuration for Arasan IP */
+#define	ST_MMC_GP_OUTPUT	0x450
+#define ST_MMC_GP_OUTPUT_CD	BIT(12)
+
+#define ST_MMC_STATUS_R		0x460
+
+#define ST_TOP_MMC_DLY_FIX_OFF(x)	(x - 0x8)
+
+/* TOP config registers to manage static and dynamic delay */
+#define	ST_TOP_MMC_TX_CLK_DLY			ST_TOP_MMC_DLY_FIX_OFF(0x8)
+#define	ST_TOP_MMC_RX_CLK_DLY			ST_TOP_MMC_DLY_FIX_OFF(0xc)
+/* MMC delay control register */
+#define	ST_TOP_MMC_DLY_CTRL			ST_TOP_MMC_DLY_FIX_OFF(0x18)
+#define	ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_CMD	BIT(0)
+#define	ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_PH_SEL	BIT(1)
+#define	ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE	BIT(8)
+#define	ST_TOP_MMC_DLY_CTRL_RX_DLL_ENABLE	BIT(9)
+#define	ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY	BIT(10)
+#define	ST_TOP_MMC_START_DLL_LOCK		BIT(11)
+
+/* register to provide the phase-shift value for DLL */
+#define	ST_TOP_MMC_TX_DLL_STEP_DLY		ST_TOP_MMC_DLY_FIX_OFF(0x1c)
+#define	ST_TOP_MMC_RX_DLL_STEP_DLY		ST_TOP_MMC_DLY_FIX_OFF(0x20)
+#define	ST_TOP_MMC_RX_CMD_STEP_DLY		ST_TOP_MMC_DLY_FIX_OFF(0x24)
+
+/* phase shift delay on the tx clk 2.188ns */
+#define	ST_TOP_MMC_TX_DLL_STEP_DLY_VALID	0x6
+
+#define	ST_TOP_MMC_DLY_MAX			0xf
+
+#define ST_TOP_MMC_DYN_DLY_CONF	\
+		(ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE | \
+		 ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY | \
+		 ST_TOP_MMC_START_DLL_LOCK)
+
 static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
 {
 	u32 ret;
-- 
1.9.1

[PATCH v2 1/8] mmc: sdhci-st: Add macros for register offsets and bitfields for mmcss glue regs

[Peter Griffin]

The stih407 family SoC's have additional glue registers in the flashSS which
are used to configure the Arasan controller.

This patch adds macros for the register offsets and bitfields which will be used by
subsequent patches to support stih407 family SoC's.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 91 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index 882b07e..a3bc3c3 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -26,6 +26,97 @@
 
 #include "sdhci-pltfm.h"
 
+/* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */
+
+#define	ST_MMC_CCONFIG_REG_1		0x400
+#define ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT	BIT(24)
+#define ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ	BIT(12)
+#define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT	BIT(8)
+#define ST_MMC_CCONFIG_ASYNC_WAKEUP	BIT(0)
+#define ST_MMC_CCONFIG_1_DEFAULT	\
+				((ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT) | \
+				 (ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ) | \
+				 (ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT))
+
+#define ST_MMC_CCONFIG_REG_2		0x404
+#define ST_MMC_CCONFIG_HIGH_SPEED	BIT(28)
+#define ST_MMC_CCONFIG_ADMA2		BIT(24)
+#define ST_MMC_CCONFIG_8BIT		BIT(20)
+#define ST_MMC_CCONFIG_MAX_BLK_LEN	16
+#define  MAX_BLK_LEN_1024		1
+#define  MAX_BLK_LEN_2048		2
+#define BASE_CLK_FREQ_200		0xc8
+#define BASE_CLK_FREQ_100		0x64
+#define BASE_CLK_FREQ_50		0x32
+#define ST_MMC_CCONFIG_2_DEFAULT \
+	(ST_MMC_CCONFIG_HIGH_SPEED | ST_MMC_CCONFIG_ADMA2 | \
+	 ST_MMC_CCONFIG_8BIT | \
+	 (MAX_BLK_LEN_1024 << ST_MMC_CCONFIG_MAX_BLK_LEN))
+
+#define ST_MMC_CCONFIG_REG_3			0x408
+#define ST_MMC_CCONFIG_EMMC_SLOT_TYPE		BIT(28)
+#define ST_MMC_CCONFIG_64BIT			BIT(24)
+#define ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	BIT(20)
+#define ST_MMC_CCONFIG_1P8_VOLT			BIT(16)
+#define ST_MMC_CCONFIG_3P0_VOLT			BIT(12)
+#define ST_MMC_CCONFIG_3P3_VOLT			BIT(8)
+#define ST_MMC_CCONFIG_SUSP_RES_SUPPORT		BIT(4)
+#define ST_MMC_CCONFIG_SDMA			BIT(0)
+#define ST_MMC_CCONFIG_3_DEFAULT	\
+			 (ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	| \
+			  ST_MMC_CCONFIG_3P3_VOLT		| \
+			  ST_MMC_CCONFIG_SUSP_RES_SUPPORT	| \
+			  ST_MMC_CCONFIG_SDMA)
+
+#define ST_MMC_CCONFIG_REG_4	0x40c
+#define ST_MMC_CCONFIG_D_DRIVER	BIT(20)
+#define ST_MMC_CCONFIG_C_DRIVER	BIT(16)
+#define ST_MMC_CCONFIG_A_DRIVER	BIT(12)
+#define ST_MMC_CCONFIG_DDR50	BIT(8)
+#define ST_MMC_CCONFIG_SDR104	BIT(4)
+#define ST_MMC_CCONFIG_SDR50	BIT(0)
+#define ST_MMC_CCONFIG_4_DEFAULT	0
+
+#define ST_MMC_CCONFIG_REG_5		0x410
+#define ST_MMC_CCONFIG_TUNING_FOR_SDR50	BIT(8)
+#define RETUNING_TIMER_CNT_MAX		0xf
+#define ST_MMC_CCONFIG_5_DEFAULT	0
+
+/* I/O configuration for Arasan IP */
+#define	ST_MMC_GP_OUTPUT	0x450
+#define ST_MMC_GP_OUTPUT_CD	BIT(12)
+
+#define ST_MMC_STATUS_R		0x460
+
+#define ST_TOP_MMC_DLY_FIX_OFF(x)	(x - 0x8)
+
+/* TOP config registers to manage static and dynamic delay */
+#define	ST_TOP_MMC_TX_CLK_DLY			ST_TOP_MMC_DLY_FIX_OFF(0x8)
+#define	ST_TOP_MMC_RX_CLK_DLY			ST_TOP_MMC_DLY_FIX_OFF(0xc)
+/* MMC delay control register */
+#define	ST_TOP_MMC_DLY_CTRL			ST_TOP_MMC_DLY_FIX_OFF(0x18)
+#define	ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_CMD	BIT(0)
+#define	ST_TOP_MMC_DLY_CTRL_DLL_BYPASS_PH_SEL	BIT(1)
+#define	ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE	BIT(8)
+#define	ST_TOP_MMC_DLY_CTRL_RX_DLL_ENABLE	BIT(9)
+#define	ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY	BIT(10)
+#define	ST_TOP_MMC_START_DLL_LOCK		BIT(11)
+
+/* register to provide the phase-shift value for DLL */
+#define	ST_TOP_MMC_TX_DLL_STEP_DLY		ST_TOP_MMC_DLY_FIX_OFF(0x1c)
+#define	ST_TOP_MMC_RX_DLL_STEP_DLY		ST_TOP_MMC_DLY_FIX_OFF(0x20)
+#define	ST_TOP_MMC_RX_CMD_STEP_DLY		ST_TOP_MMC_DLY_FIX_OFF(0x24)
+
+/* phase shift delay on the tx clk 2.188ns */
+#define	ST_TOP_MMC_TX_DLL_STEP_DLY_VALID	0x6
+
+#define	ST_TOP_MMC_DLY_MAX			0xf
+
+#define ST_TOP_MMC_DYN_DLY_CONF	\
+		(ST_TOP_MMC_DLY_CTRL_TX_DLL_ENABLE | \
+		 ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY | \
+		 ST_TOP_MMC_START_DLL_LOCK)
+
 static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
 {
 	u32 ret;
-- 
1.9.1

[PATCH v2 2/8] mmc: sdhci-st: Add support for de-asserting reset signal and top regs resource

[Peter Griffin]

STiH407 family SoC's can have a reset signal for the controller which needs to
be managed. Also the eMMC controller has some additional 'top' memory mapped
registers which are used to manage the dynamic and static delay required for
UHS modes. This patch adds support for creating the mapping, which will be used
by subsequent patches.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 52 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 49 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index a3bc3c3..0101ae9 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -23,9 +23,14 @@
 #include <linux/module.h>
 #include <linux/err.h>
 #include <linux/mmc/host.h>
-
+#include <linux/reset.h>
 #include "sdhci-pltfm.h"
 
+struct st_mmc_platform_data {
+	struct  reset_control *rstc;
+	void __iomem *top_ioaddr;
+};
+
 /* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */
 
 #define	ST_MMC_CCONFIG_REG_1		0x400
@@ -151,10 +156,16 @@ static const struct sdhci_pltfm_data sdhci_st_pdata = {
 static int sdhci_st_probe(struct platform_device *pdev)
 {
 	struct sdhci_host *host;
+	struct st_mmc_platform_data *pdata;
 	struct sdhci_pltfm_host *pltfm_host;
 	struct clk *clk;
 	int ret = 0;
 	u16 host_version;
+	struct resource *res;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
 
 	clk =  devm_clk_get(&pdev->dev, "mmc");
 	if (IS_ERR(clk)) {
@@ -162,10 +173,17 @@ static int sdhci_st_probe(struct platform_device *pdev)
 		return PTR_ERR(clk);
 	}
 
+	pdata->rstc = devm_reset_control_get(&pdev->dev, NULL);
+	if (IS_ERR(pdata->rstc))
+		pdata->rstc = NULL;
+	else
+		reset_control_deassert(pdata->rstc);
+
 	host = sdhci_pltfm_init(pdev, &sdhci_st_pdata, 0);
 	if (IS_ERR(host)) {
 		dev_err(&pdev->dev, "Failed sdhci_pltfm_init\n");
-		return PTR_ERR(host);
+		ret = PTR_ERR(host);
+		goto err_pltfm_init;
 	}
 
 	ret = mmc_of_parse(host->mmc);
@@ -176,7 +194,17 @@ static int sdhci_st_probe(struct platform_device *pdev)
 
 	clk_prepare_enable(clk);
 
+	/* Configure the FlashSS Top registers for setting eMMC TX/RX delay */
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+					   "top-mmc-delay");
+	pdata->top_ioaddr = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(pdata->top_ioaddr)) {
+		dev_warn(&pdev->dev, "FlashSS Top Dly registers not available");
+		pdata->top_ioaddr = NULL;
+	}
+
 	pltfm_host = sdhci_priv(host);
+	pltfm_host->priv = pdata;
 	pltfm_host->clk = clk;
 
 	ret = sdhci_add_host(host);
@@ -200,6 +228,9 @@ err_out:
 	clk_disable_unprepare(clk);
 err_of:
 	sdhci_pltfm_free(pdev);
+err_pltfm_init:
+	if (pdata->rstc)
+		reset_control_assert(pdata->rstc);
 
 	return ret;
 }
@@ -208,10 +239,17 @@ static int sdhci_st_remove(struct platform_device *pdev)
 {
 	struct sdhci_host *host = platform_get_drvdata(pdev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+	int ret;
 
 	clk_disable_unprepare(pltfm_host->clk);
 
-	return sdhci_pltfm_unregister(pdev);
+	ret = sdhci_pltfm_unregister(pdev);
+
+	if (pdata->rstc)
+		reset_control_assert(pdata->rstc);
+
+	return ret;
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -219,11 +257,15 @@ static int sdhci_st_suspend(struct device *dev)
 {
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
 	int ret = sdhci_suspend_host(host);
 
 	if (ret)
 		goto out;
 
+	if (pdata->rstc)
+		reset_control_assert(pdata->rstc);
+
 	clk_disable_unprepare(pltfm_host->clk);
 out:
 	return ret;
@@ -233,9 +275,13 @@ static int sdhci_st_resume(struct device *dev)
 {
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
 
 	clk_prepare_enable(pltfm_host->clk);
 
+	if (pdata->rstc)
+		reset_control_deassert(pdata->rstc);
+
 	return sdhci_resume_host(host);
 }
 #endif
-- 
1.9.1

[PATCH v2 2/8] mmc: sdhci-st: Add support for de-asserting reset signal and top regs resource

[Peter Griffin]

STiH407 family SoC's can have a reset signal for the controller which needs to
be managed. Also the eMMC controller has some additional 'top' memory mapped
registers which are used to manage the dynamic and static delay required for
UHS modes. This patch adds support for creating the mapping, which will be used
by subsequent patches.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 52 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 49 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index a3bc3c3..0101ae9 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -23,9 +23,14 @@
 #include <linux/module.h>
 #include <linux/err.h>
 #include <linux/mmc/host.h>
-
+#include <linux/reset.h>
 #include "sdhci-pltfm.h"
 
+struct st_mmc_platform_data {
+	struct  reset_control *rstc;
+	void __iomem *top_ioaddr;
+};
+
 /* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */
 
 #define	ST_MMC_CCONFIG_REG_1		0x400
@@ -151,10 +156,16 @@ static const struct sdhci_pltfm_data sdhci_st_pdata = {
 static int sdhci_st_probe(struct platform_device *pdev)
 {
 	struct sdhci_host *host;
+	struct st_mmc_platform_data *pdata;
 	struct sdhci_pltfm_host *pltfm_host;
 	struct clk *clk;
 	int ret = 0;
 	u16 host_version;
+	struct resource *res;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
 
 	clk =  devm_clk_get(&pdev->dev, "mmc");
 	if (IS_ERR(clk)) {
@@ -162,10 +173,17 @@ static int sdhci_st_probe(struct platform_device *pdev)
 		return PTR_ERR(clk);
 	}
 
+	pdata->rstc = devm_reset_control_get(&pdev->dev, NULL);
+	if (IS_ERR(pdata->rstc))
+		pdata->rstc = NULL;
+	else
+		reset_control_deassert(pdata->rstc);
+
 	host = sdhci_pltfm_init(pdev, &sdhci_st_pdata, 0);
 	if (IS_ERR(host)) {
 		dev_err(&pdev->dev, "Failed sdhci_pltfm_init\n");
-		return PTR_ERR(host);
+		ret = PTR_ERR(host);
+		goto err_pltfm_init;
 	}
 
 	ret = mmc_of_parse(host->mmc);
@@ -176,7 +194,17 @@ static int sdhci_st_probe(struct platform_device *pdev)
 
 	clk_prepare_enable(clk);
 
+	/* Configure the FlashSS Top registers for setting eMMC TX/RX delay */
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+					   "top-mmc-delay");
+	pdata->top_ioaddr = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(pdata->top_ioaddr)) {
+		dev_warn(&pdev->dev, "FlashSS Top Dly registers not available");
+		pdata->top_ioaddr = NULL;
+	}
+
 	pltfm_host = sdhci_priv(host);
+	pltfm_host->priv = pdata;
 	pltfm_host->clk = clk;
 
 	ret = sdhci_add_host(host);
@@ -200,6 +228,9 @@ err_out:
 	clk_disable_unprepare(clk);
 err_of:
 	sdhci_pltfm_free(pdev);
+err_pltfm_init:
+	if (pdata->rstc)
+		reset_control_assert(pdata->rstc);
 
 	return ret;
 }
@@ -208,10 +239,17 @@ static int sdhci_st_remove(struct platform_device *pdev)
 {
 	struct sdhci_host *host = platform_get_drvdata(pdev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+	int ret;
 
 	clk_disable_unprepare(pltfm_host->clk);
 
-	return sdhci_pltfm_unregister(pdev);
+	ret = sdhci_pltfm_unregister(pdev);
+
+	if (pdata->rstc)
+		reset_control_assert(pdata->rstc);
+
+	return ret;
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -219,11 +257,15 @@ static int sdhci_st_suspend(struct device *dev)
 {
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
 	int ret = sdhci_suspend_host(host);
 
 	if (ret)
 		goto out;
 
+	if (pdata->rstc)
+		reset_control_assert(pdata->rstc);
+
 	clk_disable_unprepare(pltfm_host->clk);
 out:
 	return ret;
@@ -233,9 +275,13 @@ static int sdhci_st_resume(struct device *dev)
 {
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
 
 	clk_prepare_enable(pltfm_host->clk);
 
+	if (pdata->rstc)
+		reset_control_deassert(pdata->rstc);
+
 	return sdhci_resume_host(host);
 }
 #endif
-- 
1.9.1

[PATCH v2 2/8] mmc: sdhci-st: Add support for de-asserting reset signal and top regs resource

[Peter Griffin]

STiH407 family SoC's can have a reset signal for the controller which needs to
be managed. Also the eMMC controller has some additional 'top' memory mapped
registers which are used to manage the dynamic and static delay required for
UHS modes. This patch adds support for creating the mapping, which will be used
by subsequent patches.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 52 ++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 49 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index a3bc3c3..0101ae9 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -23,9 +23,14 @@
 #include <linux/module.h>
 #include <linux/err.h>
 #include <linux/mmc/host.h>
-
+#include <linux/reset.h>
 #include "sdhci-pltfm.h"
 
+struct st_mmc_platform_data {
+	struct  reset_control *rstc;
+	void __iomem *top_ioaddr;
+};
+
 /* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */
 
 #define	ST_MMC_CCONFIG_REG_1		0x400
@@ -151,10 +156,16 @@ static const struct sdhci_pltfm_data sdhci_st_pdata = {
 static int sdhci_st_probe(struct platform_device *pdev)
 {
 	struct sdhci_host *host;
+	struct st_mmc_platform_data *pdata;
 	struct sdhci_pltfm_host *pltfm_host;
 	struct clk *clk;
 	int ret = 0;
 	u16 host_version;
+	struct resource *res;
+
+	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+	if (!pdata)
+		return -ENOMEM;
 
 	clk =  devm_clk_get(&pdev->dev, "mmc");
 	if (IS_ERR(clk)) {
@@ -162,10 +173,17 @@ static int sdhci_st_probe(struct platform_device *pdev)
 		return PTR_ERR(clk);
 	}
 
+	pdata->rstc = devm_reset_control_get(&pdev->dev, NULL);
+	if (IS_ERR(pdata->rstc))
+		pdata->rstc = NULL;
+	else
+		reset_control_deassert(pdata->rstc);
+
 	host = sdhci_pltfm_init(pdev, &sdhci_st_pdata, 0);
 	if (IS_ERR(host)) {
 		dev_err(&pdev->dev, "Failed sdhci_pltfm_init\n");
-		return PTR_ERR(host);
+		ret = PTR_ERR(host);
+		goto err_pltfm_init;
 	}
 
 	ret = mmc_of_parse(host->mmc);
@@ -176,7 +194,17 @@ static int sdhci_st_probe(struct platform_device *pdev)
 
 	clk_prepare_enable(clk);
 
+	/* Configure the FlashSS Top registers for setting eMMC TX/RX delay */
+	res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+					   "top-mmc-delay");
+	pdata->top_ioaddr = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(pdata->top_ioaddr)) {
+		dev_warn(&pdev->dev, "FlashSS Top Dly registers not available");
+		pdata->top_ioaddr = NULL;
+	}
+
 	pltfm_host = sdhci_priv(host);
+	pltfm_host->priv = pdata;
 	pltfm_host->clk = clk;
 
 	ret = sdhci_add_host(host);
@@ -200,6 +228,9 @@ err_out:
 	clk_disable_unprepare(clk);
 err_of:
 	sdhci_pltfm_free(pdev);
+err_pltfm_init:
+	if (pdata->rstc)
+		reset_control_assert(pdata->rstc);
 
 	return ret;
 }
@@ -208,10 +239,17 @@ static int sdhci_st_remove(struct platform_device *pdev)
 {
 	struct sdhci_host *host = platform_get_drvdata(pdev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+	int ret;
 
 	clk_disable_unprepare(pltfm_host->clk);
 
-	return sdhci_pltfm_unregister(pdev);
+	ret = sdhci_pltfm_unregister(pdev);
+
+	if (pdata->rstc)
+		reset_control_assert(pdata->rstc);
+
+	return ret;
 }
 
 #ifdef CONFIG_PM_SLEEP
@@ -219,11 +257,15 @@ static int sdhci_st_suspend(struct device *dev)
 {
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
 	int ret = sdhci_suspend_host(host);
 
 	if (ret)
 		goto out;
 
+	if (pdata->rstc)
+		reset_control_assert(pdata->rstc);
+
 	clk_disable_unprepare(pltfm_host->clk);
 out:
 	return ret;
@@ -233,9 +275,13 @@ static int sdhci_st_resume(struct device *dev)
 {
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
 
 	clk_prepare_enable(pltfm_host->clk);
 
+	if (pdata->rstc)
+		reset_control_deassert(pdata->rstc);
+
 	return sdhci_resume_host(host);
 }
 #endif
-- 
1.9.1

[PATCH v2 3/8] mmc: sdhci-st: Add delay management functions for top registers (eMMC).

[Peter Griffin]

Due to the tight timing constriants in some UHS modes, it is required to have
some delay management in the design. Two types of delay management are supported
in the HW: -

1) Static delay management
2) Dynamic delay management

NB: The delay management is only there when eMMC interface is selected.

1: Static delay management: is used to provide PVT dependent static delay on the
clock/data lines to manage setup/hold requirements of the interface. The maximum
delay possible is 3.25ns. These delays are PVT dependent, and thus delay values
applied are not accurate and vary across provcess voltage and temperature range.
Due to this these delays must not be used on the very time critical paths.

2. Dynamic delay locked loop (DLL): is used to provide dynamic delay management.
The advantage of DLL is that it provides accurate & PVT indepedent delay.

The DLL is used to provide delay on the loopback clock on "Read Path" to capture
read data reliably. On TX path the clock on which output data is transmitted is
delayed, resulting in delay of TX data.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 58 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index 0101ae9..3443cc0 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -122,6 +122,64 @@ struct st_mmc_platform_data {
 		 ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY | \
 		 ST_TOP_MMC_START_DLL_LOCK)
 
+/*
+ * For clock speeds greater than 90MHz, we need to check that the
+ * DLL procedure has finished before switching to ultra-speed modes.
+ */
+#define	CLK_TO_CHECK_DLL_LOCK	90000000
+
+static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
+{
+	if (ioaddr) {
+		writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
+		writel_relaxed(ST_TOP_MMC_DLY_MAX,
+				ioaddr + ST_TOP_MMC_TX_CLK_DLY);
+	}
+}
+
+static inline void st_mmcss_set_dll(void __iomem *ioaddr)
+{
+	if (ioaddr) {
+		writel_relaxed(ST_TOP_MMC_DYN_DLY_CONF,
+			ioaddr + ST_TOP_MMC_DLY_CTRL);
+		writel_relaxed(ST_TOP_MMC_TX_DLL_STEP_DLY_VALID,
+			ioaddr + ST_TOP_MMC_TX_DLL_STEP_DLY);
+	}
+}
+
+static int st_mmcss_lock_dll(void __iomem *ioaddr)
+{
+	unsigned long curr, value;
+	unsigned long finish = jiffies + HZ;
+
+	/* Checks if the DLL procedure is finished */
+	do {
+		curr = jiffies;
+		value = readl(ioaddr + ST_MMC_STATUS_R);
+		if (value & 0x1)
+			return 0;
+
+		cpu_relax();
+	} while (!time_after_eq(curr, finish));
+
+	return -EBUSY;
+}
+
+static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
+{
+	int ret = 0;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+
+	if (host->clock > CLK_TO_CHECK_DLL_LOCK) {
+		st_mmcss_set_dll(pdata->top_ioaddr);
+		ret = st_mmcss_lock_dll(host->ioaddr);
+	}
+
+	return ret;
+}
+
+
 static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
 {
 	u32 ret;
-- 
1.9.1

[PATCH v2 3/8] mmc: sdhci-st: Add delay management functions for top registers (eMMC).

[Peter Griffin]

Due to the tight timing constriants in some UHS modes, it is required to have
some delay management in the design. Two types of delay management are supported
in the HW: -

1) Static delay management
2) Dynamic delay management

NB: The delay management is only there when eMMC interface is selected.

1: Static delay management: is used to provide PVT dependent static delay on the
clock/data lines to manage setup/hold requirements of the interface. The maximum
delay possible is 3.25ns. These delays are PVT dependent, and thus delay values
applied are not accurate and vary across provcess voltage and temperature range.
Due to this these delays must not be used on the very time critical paths.

2. Dynamic delay locked loop (DLL): is used to provide dynamic delay management.
The advantage of DLL is that it provides accurate & PVT indepedent delay.

The DLL is used to provide delay on the loopback clock on "Read Path" to capture
read data reliably. On TX path the clock on which output data is transmitted is
delayed, resulting in delay of TX data.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 58 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index 0101ae9..3443cc0 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -122,6 +122,64 @@ struct st_mmc_platform_data {
 		 ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY | \
 		 ST_TOP_MMC_START_DLL_LOCK)
 
+/*
+ * For clock speeds greater than 90MHz, we need to check that the
+ * DLL procedure has finished before switching to ultra-speed modes.
+ */
+#define	CLK_TO_CHECK_DLL_LOCK	90000000
+
+static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
+{
+	if (ioaddr) {
+		writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
+		writel_relaxed(ST_TOP_MMC_DLY_MAX,
+				ioaddr + ST_TOP_MMC_TX_CLK_DLY);
+	}
+}
+
+static inline void st_mmcss_set_dll(void __iomem *ioaddr)
+{
+	if (ioaddr) {
+		writel_relaxed(ST_TOP_MMC_DYN_DLY_CONF,
+			ioaddr + ST_TOP_MMC_DLY_CTRL);
+		writel_relaxed(ST_TOP_MMC_TX_DLL_STEP_DLY_VALID,
+			ioaddr + ST_TOP_MMC_TX_DLL_STEP_DLY);
+	}
+}
+
+static int st_mmcss_lock_dll(void __iomem *ioaddr)
+{
+	unsigned long curr, value;
+	unsigned long finish = jiffies + HZ;
+
+	/* Checks if the DLL procedure is finished */
+	do {
+		curr = jiffies;
+		value = readl(ioaddr + ST_MMC_STATUS_R);
+		if (value & 0x1)
+			return 0;
+
+		cpu_relax();
+	} while (!time_after_eq(curr, finish));
+
+	return -EBUSY;
+}
+
+static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
+{
+	int ret = 0;
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+
+	if (host->clock > CLK_TO_CHECK_DLL_LOCK) {
+		st_mmcss_set_dll(pdata->top_ioaddr);
+		ret = st_mmcss_lock_dll(host->ioaddr);
+	}
+
+	return ret;
+}
+
+
 static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
 {
 	u32 ret;
-- 
1.9.1

[PATCH v2 4/8] mmc: sdhci-st: Add st_mmcss_cconfig function to configure mmcss glue registers.

[Peter Griffin]

STiH407 family SoC's have glue registers in the flashSS subsystem which
are used to configure the Arasan HC. This patch configures these glue
registers according to what has been specified in the DT.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 88 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index 3443cc0..11cf4e2 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -137,6 +137,87 @@ static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
 	}
 }
 
+/**
+ * st_mmcss_cconfig: configure the Arasan HC inside the flashSS.
+ * @np: dt device node.
+ * @host: sdhci host
+ * Description: this function is to configure the Arasan host controller.
+ * On some ST SoCs, i.e. STiH407 family, the MMC devices inside a dedicated
+ * flashSS sub-system which needs to be configured to be compliant to eMMC 4.5
+ * or eMMC4.3.  This has to be done before registering the sdhci host.
+ */
+static void st_mmcss_cconfig(struct device_node *np, struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct mmc_host *mhost = host->mmc;
+	u32 cconf2, cconf3, cconf4, cconf5;
+
+	if (!of_device_is_compatible(np, "st,sdhci-stih407"))
+		return;
+
+	cconf2 = ST_MMC_CCONFIG_2_DEFAULT;
+	cconf3 = ST_MMC_CCONFIG_3_DEFAULT;
+	cconf4 = ST_MMC_CCONFIG_4_DEFAULT;
+	cconf5 = ST_MMC_CCONFIG_5_DEFAULT;
+
+	writel_relaxed(ST_MMC_CCONFIG_1_DEFAULT,
+			host->ioaddr + ST_MMC_CCONFIG_REG_1);
+
+	/* Set clock frequency, default to 50MHz if max-frequency is not
+	 * provided */
+
+	switch (mhost->f_max) {
+	case 200000000:
+		clk_set_rate(pltfm_host->clk, mhost->f_max);
+		cconf2 |= BASE_CLK_FREQ_200;
+		break;
+	case 100000000:
+		clk_set_rate(pltfm_host->clk, mhost->f_max);
+		cconf2 |= BASE_CLK_FREQ_100;
+		break;
+	default:
+		clk_set_rate(pltfm_host->clk, 50000000);
+		cconf2 |= BASE_CLK_FREQ_50;
+	}
+
+	writel_relaxed(cconf2, host->ioaddr + ST_MMC_CCONFIG_REG_2);
+
+	if (mhost->caps & MMC_CAP_NONREMOVABLE)
+		cconf3 |= ST_MMC_CCONFIG_EMMC_SLOT_TYPE;
+	else
+		/* CARD _D ET_CTRL */
+		writel_relaxed(ST_MMC_GP_OUTPUT_CD,
+				host->ioaddr + ST_MMC_GP_OUTPUT);
+
+	if (mhost->caps & MMC_CAP_UHS_SDR50) {
+		/* use 1.8V */
+		cconf3 |= ST_MMC_CCONFIG_1P8_VOLT;
+		cconf4 |= ST_MMC_CCONFIG_SDR50;
+		/* Use tuning */
+		cconf5 |= ST_MMC_CCONFIG_TUNING_FOR_SDR50;
+		/* Max timeout for retuning */
+		cconf5 |= RETUNING_TIMER_CNT_MAX;
+	}
+
+	if (mhost->caps & MMC_CAP_UHS_SDR104) {
+		/*
+		 * SDR104 implies the HC can support HS200 mode, so
+		 * it's mandatory to use 1.8V
+		 */
+		cconf3 |= ST_MMC_CCONFIG_1P8_VOLT;
+		cconf4 |= ST_MMC_CCONFIG_SDR104;
+		/* Max timeout for retuning */
+		cconf5 |= RETUNING_TIMER_CNT_MAX;
+	}
+
+	if (mhost->caps & MMC_CAP_UHS_DDR50)
+		cconf4 |= ST_MMC_CCONFIG_DDR50;
+
+	writel_relaxed(cconf3, host->ioaddr + ST_MMC_CCONFIG_REG_3);
+	writel_relaxed(cconf4, host->ioaddr + ST_MMC_CCONFIG_REG_4);
+	writel_relaxed(cconf5, host->ioaddr + ST_MMC_CCONFIG_REG_5);
+}
+
 static inline void st_mmcss_set_dll(void __iomem *ioaddr)
 {
 	if (ioaddr) {
@@ -213,6 +294,7 @@ static const struct sdhci_pltfm_data sdhci_st_pdata = {
 
 static int sdhci_st_probe(struct platform_device *pdev)
 {
+	struct device_node *np = pdev->dev.of_node;
 	struct sdhci_host *host;
 	struct st_mmc_platform_data *pdata;
 	struct sdhci_pltfm_host *pltfm_host;
@@ -265,6 +347,9 @@ static int sdhci_st_probe(struct platform_device *pdev)
 	pltfm_host->priv = pdata;
 	pltfm_host->clk = clk;
 
+	/* Configure the Arasan HC inside the flashSS */
+	st_mmcss_cconfig(np, host);
+
 	ret = sdhci_add_host(host);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed sdhci_add_host\n");
@@ -334,12 +419,15 @@ static int sdhci_st_resume(struct device *dev)
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+	struct device_node *np = dev->of_node;
 
 	clk_prepare_enable(pltfm_host->clk);
 
 	if (pdata->rstc)
 		reset_control_deassert(pdata->rstc);
 
+	st_mmcss_cconfig(np, host);
+
 	return sdhci_resume_host(host);
 }
 #endif
-- 
1.9.1

[PATCH v2 4/8] mmc: sdhci-st: Add st_mmcss_cconfig function to configure mmcss glue registers.

[Peter Griffin]

STiH407 family SoC's have glue registers in the flashSS subsystem which
are used to configure the Arasan HC. This patch configures these glue
registers according to what has been specified in the DT.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 88 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 88 insertions(+)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index 3443cc0..11cf4e2 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -137,6 +137,87 @@ static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
 	}
 }
 
+/**
+ * st_mmcss_cconfig: configure the Arasan HC inside the flashSS.
+ * @np: dt device node.
+ * @host: sdhci host
+ * Description: this function is to configure the Arasan host controller.
+ * On some ST SoCs, i.e. STiH407 family, the MMC devices inside a dedicated
+ * flashSS sub-system which needs to be configured to be compliant to eMMC 4.5
+ * or eMMC4.3.  This has to be done before registering the sdhci host.
+ */
+static void st_mmcss_cconfig(struct device_node *np, struct sdhci_host *host)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct mmc_host *mhost = host->mmc;
+	u32 cconf2, cconf3, cconf4, cconf5;
+
+	if (!of_device_is_compatible(np, "st,sdhci-stih407"))
+		return;
+
+	cconf2 = ST_MMC_CCONFIG_2_DEFAULT;
+	cconf3 = ST_MMC_CCONFIG_3_DEFAULT;
+	cconf4 = ST_MMC_CCONFIG_4_DEFAULT;
+	cconf5 = ST_MMC_CCONFIG_5_DEFAULT;
+
+	writel_relaxed(ST_MMC_CCONFIG_1_DEFAULT,
+			host->ioaddr + ST_MMC_CCONFIG_REG_1);
+
+	/* Set clock frequency, default to 50MHz if max-frequency is not
+	 * provided */
+
+	switch (mhost->f_max) {
+	case 200000000:
+		clk_set_rate(pltfm_host->clk, mhost->f_max);
+		cconf2 |= BASE_CLK_FREQ_200;
+		break;
+	case 100000000:
+		clk_set_rate(pltfm_host->clk, mhost->f_max);
+		cconf2 |= BASE_CLK_FREQ_100;
+		break;
+	default:
+		clk_set_rate(pltfm_host->clk, 50000000);
+		cconf2 |= BASE_CLK_FREQ_50;
+	}
+
+	writel_relaxed(cconf2, host->ioaddr + ST_MMC_CCONFIG_REG_2);
+
+	if (mhost->caps & MMC_CAP_NONREMOVABLE)
+		cconf3 |= ST_MMC_CCONFIG_EMMC_SLOT_TYPE;
+	else
+		/* CARD _D ET_CTRL */
+		writel_relaxed(ST_MMC_GP_OUTPUT_CD,
+				host->ioaddr + ST_MMC_GP_OUTPUT);
+
+	if (mhost->caps & MMC_CAP_UHS_SDR50) {
+		/* use 1.8V */
+		cconf3 |= ST_MMC_CCONFIG_1P8_VOLT;
+		cconf4 |= ST_MMC_CCONFIG_SDR50;
+		/* Use tuning */
+		cconf5 |= ST_MMC_CCONFIG_TUNING_FOR_SDR50;
+		/* Max timeout for retuning */
+		cconf5 |= RETUNING_TIMER_CNT_MAX;
+	}
+
+	if (mhost->caps & MMC_CAP_UHS_SDR104) {
+		/*
+		 * SDR104 implies the HC can support HS200 mode, so
+		 * it's mandatory to use 1.8V
+		 */
+		cconf3 |= ST_MMC_CCONFIG_1P8_VOLT;
+		cconf4 |= ST_MMC_CCONFIG_SDR104;
+		/* Max timeout for retuning */
+		cconf5 |= RETUNING_TIMER_CNT_MAX;
+	}
+
+	if (mhost->caps & MMC_CAP_UHS_DDR50)
+		cconf4 |= ST_MMC_CCONFIG_DDR50;
+
+	writel_relaxed(cconf3, host->ioaddr + ST_MMC_CCONFIG_REG_3);
+	writel_relaxed(cconf4, host->ioaddr + ST_MMC_CCONFIG_REG_4);
+	writel_relaxed(cconf5, host->ioaddr + ST_MMC_CCONFIG_REG_5);
+}
+
 static inline void st_mmcss_set_dll(void __iomem *ioaddr)
 {
 	if (ioaddr) {
@@ -213,6 +294,7 @@ static const struct sdhci_pltfm_data sdhci_st_pdata = {
 
 static int sdhci_st_probe(struct platform_device *pdev)
 {
+	struct device_node *np = pdev->dev.of_node;
 	struct sdhci_host *host;
 	struct st_mmc_platform_data *pdata;
 	struct sdhci_pltfm_host *pltfm_host;
@@ -265,6 +347,9 @@ static int sdhci_st_probe(struct platform_device *pdev)
 	pltfm_host->priv = pdata;
 	pltfm_host->clk = clk;
 
+	/* Configure the Arasan HC inside the flashSS */
+	st_mmcss_cconfig(np, host);
+
 	ret = sdhci_add_host(host);
 	if (ret) {
 		dev_err(&pdev->dev, "Failed sdhci_add_host\n");
@@ -334,12 +419,15 @@ static int sdhci_st_resume(struct device *dev)
 	struct sdhci_host *host = dev_get_drvdata(dev);
 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+	struct device_node *np = dev->of_node;
 
 	clk_prepare_enable(pltfm_host->clk);
 
 	if (pdata->rstc)
 		reset_control_deassert(pdata->rstc);
 
+	st_mmcss_cconfig(np, host);
+
 	return sdhci_resume_host(host);
 }
 #endif
-- 
1.9.1

[PATCH v2 5/8] mmc: sdhci-st: Add sdhci_st_set_uhs_signaling function.

[Peter Griffin]

To allow UHS modes to work properly we need to provide the st specific
set_uhs_signaling callback function. This function differs from the
generic sdhci_set_uhs_signaling callback in that we need to configure
the correct delay depending on the UHS mode, and also set the V18_EN
bit.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 50 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index 11cf4e2..d53bc82 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -260,6 +260,55 @@ static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
 	return ret;
 }
 
+static void sdhci_st_set_uhs_signaling(struct sdhci_host *host,
+					unsigned int uhs)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+	u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+	int ret = 0;
+
+	/* Select Bus Speed Mode for host */
+	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+	switch (uhs) {
+	/*
+	 * Set V18_EN -- UHS modes do not work without this.
+	 * does not change signaling voltage
+	 */
+
+	case MMC_TIMING_UHS_SDR12:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180;
+		break;
+	case MMC_TIMING_UHS_SDR25:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180;
+		break;
+	case MMC_TIMING_UHS_SDR50:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
+		ret = sdhci_st_set_dll_for_clock(host);
+		break;
+	case MMC_TIMING_UHS_SDR104:
+	case MMC_TIMING_MMC_HS200:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
+		ret =  sdhci_st_set_dll_for_clock(host);
+		break;
+	case MMC_TIMING_UHS_DDR50:
+	case MMC_TIMING_MMC_DDR52:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
+		break;
+	}
+
+	if (ret)
+		dev_warn(mmc_dev(host->mmc), "Error setting dll for clock\n");
+
+	dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2);
+
+	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+}
 
 static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
 {
@@ -283,6 +332,7 @@ static const struct sdhci_ops sdhci_st_ops = {
 	.set_bus_width = sdhci_set_bus_width,
 	.read_l = sdhci_st_readl,
 	.reset = sdhci_reset,
+	.set_uhs_signaling = sdhci_st_set_uhs_signaling,
 };
 
 static const struct sdhci_pltfm_data sdhci_st_pdata = {
-- 
1.9.1

[PATCH v2 5/8] mmc: sdhci-st: Add sdhci_st_set_uhs_signaling function.

[Peter Griffin]

To allow UHS modes to work properly we need to provide the st specific
set_uhs_signaling callback function. This function differs from the
generic sdhci_set_uhs_signaling callback in that we need to configure
the correct delay depending on the UHS mode, and also set the V18_EN
bit.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 50 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index 11cf4e2..d53bc82 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -260,6 +260,55 @@ static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
 	return ret;
 }
 
+static void sdhci_st_set_uhs_signaling(struct sdhci_host *host,
+					unsigned int uhs)
+{
+	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+	struct st_mmc_platform_data *pdata = pltfm_host->priv;
+	u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+	int ret = 0;
+
+	/* Select Bus Speed Mode for host */
+	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+	switch (uhs) {
+	/*
+	 * Set V18_EN -- UHS modes do not work without this.
+	 * does not change signaling voltage
+	 */
+
+	case MMC_TIMING_UHS_SDR12:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180;
+		break;
+	case MMC_TIMING_UHS_SDR25:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180;
+		break;
+	case MMC_TIMING_UHS_SDR50:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
+		ret = sdhci_st_set_dll_for_clock(host);
+		break;
+	case MMC_TIMING_UHS_SDR104:
+	case MMC_TIMING_MMC_HS200:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
+		ret =  sdhci_st_set_dll_for_clock(host);
+		break;
+	case MMC_TIMING_UHS_DDR50:
+	case MMC_TIMING_MMC_DDR52:
+		st_mmcss_set_static_delay(pdata->top_ioaddr);
+		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
+		break;
+	}
+
+	if (ret)
+		dev_warn(mmc_dev(host->mmc), "Error setting dll for clock\n");
+
+	dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2);
+
+	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+}
 
 static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
 {
@@ -283,6 +332,7 @@ static const struct sdhci_ops sdhci_st_ops = {
 	.set_bus_width = sdhci_set_bus_width,
 	.read_l = sdhci_st_readl,
 	.reset = sdhci_reset,
+	.set_uhs_signaling = sdhci_st_set_uhs_signaling,
 };
 
 static const struct sdhci_pltfm_data sdhci_st_pdata = {
-- 
1.9.1

[PATCH v2 6/8] mmc: sdhci-st: Update the quirks for this controller.

[Peter Griffin]

Some additional quirks need to be enabled now we support UHS
modes. This avoids some spurious warnings like

"Got data interrupt 0x00000002 even though no data operation was in progress"

Testing on stih410-b2120 board achieves the following speeds
with HS200 eMMC card.

max-frequency = 200Mhz
/dev/mmcblk0p1:
 Timing buffered disk reads: 270 MB in  3.02 seconds =  89.54 MB/sec

max-frequency = 100Mhz
root@debian-armhf:~# hdparm -t /dev/mmcblk0p1
/dev/mmcblk0p1:
 Timing buffered disk reads: 210 MB in  3.00 seconds =  70.00 MB/sec

max-frequency = 50Mhz
root@debian-armhf:~# hdparm -t /dev/mmcblk0p1
/dev/mmcblk0p1:
 Timing buffered disk reads: 118 MB in  3.00 seconds =  39.28 MB/sec

This is better than the 3.10 kernel which achieves 77.59 MB/sec
at 200Mhz clock (same board/soc/eMMC).

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index d53bc82..c6957b8 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -338,7 +338,10 @@ static const struct sdhci_ops sdhci_st_ops = {
 static const struct sdhci_pltfm_data sdhci_st_pdata = {
 	.ops = &sdhci_st_ops,
 	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
-	    SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+		SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+		SDHCI_QUIRK_NO_HISPD_BIT,
+	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+		SDHCI_QUIRK2_STOP_WITH_TC,
 };
 
 
-- 
1.9.1

[PATCH v2 6/8] mmc: sdhci-st: Update the quirks for this controller.

[Peter Griffin]

Some additional quirks need to be enabled now we support UHS
modes. This avoids some spurious warnings like

"Got data interrupt 0x00000002 even though no data operation was in progress"

Testing on stih410-b2120 board achieves the following speeds
with HS200 eMMC card.

max-frequency = 200Mhz
/dev/mmcblk0p1:
 Timing buffered disk reads: 270 MB in  3.02 seconds =  89.54 MB/sec

max-frequency = 100Mhz
root at debian-armhf:~# hdparm -t /dev/mmcblk0p1
/dev/mmcblk0p1:
 Timing buffered disk reads: 210 MB in  3.00 seconds =  70.00 MB/sec

max-frequency = 50Mhz
root at debian-armhf:~# hdparm -t /dev/mmcblk0p1
/dev/mmcblk0p1:
 Timing buffered disk reads: 118 MB in  3.00 seconds =  39.28 MB/sec

This is better than the 3.10 kernel which achieves 77.59 MB/sec
at 200Mhz clock (same board/soc/eMMC).

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
---
 drivers/mmc/host/sdhci-st.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
index d53bc82..c6957b8 100644
--- a/drivers/mmc/host/sdhci-st.c
+++ b/drivers/mmc/host/sdhci-st.c
@@ -338,7 +338,10 @@ static const struct sdhci_ops sdhci_st_ops = {
 static const struct sdhci_pltfm_data sdhci_st_pdata = {
 	.ops = &sdhci_st_ops,
 	.quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
-	    SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
+		SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+		SDHCI_QUIRK_NO_HISPD_BIT,
+	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
+		SDHCI_QUIRK2_STOP_WITH_TC,
 };
 
 
-- 
1.9.1

[PATCH v2 7/8] mmc: sdhci-st: Update ST SDHCI binding documentation.

[Peter Griffin]

This patch updates the binding information to reflect the
extra dt options which are now supported by the sdhci-st.c
driver which enable support for stih407 family silicon.

Stih410 SoC and later support UHS modes for eMMC, so the
driver now makes use of these common bindings. Examples
are provided for both eMMC (which has additional bindings)
and also sd slot for stih407.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 Documentation/devicetree/bindings/mmc/sdhci-st.txt | 100 ++++++++++++++++++---
 1 file changed, 90 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-st.txt b/Documentation/devicetree/bindings/mmc/sdhci-st.txt
index 7527db4..18d950d 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-st.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-st.txt
@@ -5,20 +5,62 @@ Documentation/devicetree/bindings/mmc/mmc.txt and the properties
 used by the sdhci-st driver.
 
 Required properties:
-- compatible :  Must be "st,sdhci"
-- clock-names : Should be "mmc"
-                See: Documentation/devicetree/bindings/resource-names.txt
-- clocks :      Phandle of the clock used by the sdhci controler
-                See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+- compatible:		Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
+			to set the internal glue logic used for configuring the MMC
+			subsystem (mmcss) inside the FlashSS (available in STiH407 SoC
+			family).
+
+- clock-names:		Should be "mmc".
+			See: Documentation/devicetree/bindings/resource-names.txt
+- clocks:		Phandle to the clock.
+			See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+- interrupts:		One mmc interrupt should be described here.
+- interrupt-names:	Should be "mmcirq".
+
+- pinctrl-names:	A pinctrl state names "default" must be defined.
+- pinctrl-0:		Phandle referencing pin configuration of the sd/emmc controller.
+			See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+
+- reg:			This must provide the host controller base address and it can also
+			contain the FlashSS Top register for TX/RX delay used by the driver
+			to configure DLL inside the flashSS, if so reg-names must also be
+			specified.
 
 Optional properties:
-- non-removable: non-removable slot
-                 See: Documentation/devicetree/bindings/mmc/mmc.txt
-- bus-width: Number of data lines
-                 See: Documentation/devicetree/bindings/mmc/mmc.txt
+- reg-names:		Should be "mmc" and "top-mmc-delay". "top-mmc-delay" is optional
+			for eMMC on stih407 family silicon to configure DLL inside FlashSS.
+
+- non-removable:	Non-removable slot. Also used for configuring mmcss in STiH407 SoC
+			family.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- bus-width:		Number of data lines.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- max-frequency: 	Can be 200MHz, 100Mz or 50MHz (default) and used for
+			configuring the CCONFIG3 in the mmcss.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- resets:		Phandle and reset specifier pair to softreset line of HC IP.
+			See: Documentation/devicetree/bindings/reset/reset.txt
+
+- vqmmc-supply:		Phandle to the regulator dt node, mentioned as the vcc/vdd
+			supply in eMMC/SD specs.
+
+- sd-uhs--sdr50:	To enable the SDR50 in the mmcss.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- sd-uhs-sdr104:	To enable the SDR104 in the mmcss.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- sd-uhs-ddr50:		To enable the DDR50 in the mmcss.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
 
 Example:
 
+/* Example stih416e eMMC configuration */
+
 mmc0: sdhci@fe81e000 {
 	compatible	= "st,sdhci";
 	status		= "disabled";
@@ -29,5 +71,43 @@ mmc0: sdhci@fe81e000 {
 	pinctrl-0	= <&pinctrl_mmc0>;
 	clock-names	= "mmc";
 	clocks		= <&clk_s_a1_ls 1>;
-	bus-width       = <8>
+	bus-width	= <8>
+
+/* Example SD stih407 family configuration */
+
+mmc1: sdhci@09080000 {
+	compatible	= "st,sdhci-stih407", "st,sdhci";
+	status		= "disabled";
+	reg		= <0x09080000 0x7ff>;
+	reg-names	= "mmc";
+	interrupts	= <GIC_SPI 90 IRQ_TYPE_NONE>;
+	interrupt-names	= "mmcirq";
+	pinctrl-names	= "default";
+	pinctrl-0	= <&pinctrl_sd1>;
+	clock-names	= "mmc";
+	clocks		= <&clk_s_c0_flexgen CLK_MMC_1>;
+	resets		= <&softreset STIH407_MMC1_SOFTRESET>;
+	bus-width	= <4>;
+};
+
+/* Example eMMC stih407 family configuration */
+
+mmc0: sdhci@09060000 {
+	compatible	= "st,sdhci-stih407", "st,sdhci";
+	status		= "disabled";
+	reg		= <0x09060000 0x7ff>, <0x9061008 0x20>;
+	reg-names	= "mmc", "top-mmc-delay";
+	interrupts	= <GIC_SPI 92 IRQ_TYPE_NONE>;
+	interrupt-names	= "mmcirq";
+	pinctrl-names	= "default";
+	pinctrl-0	= <&pinctrl_mmc0>;
+	clock-names	= "mmc";
+	clocks		= <&clk_s_c0_flexgen CLK_MMC_0>;
+	vqmmc-supply	= <&vmmc_reg>;
+	max-frequency	= <200000000>;
+	bus-width	= <8>;
+	non-removable;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
 };
-- 
1.9.1

[PATCH v2 7/8] mmc: sdhci-st: Update ST SDHCI binding documentation.

[Peter Griffin]

This patch updates the binding information to reflect the
extra dt options which are now supported by the sdhci-st.c
driver which enable support for stih407 family silicon.

Stih410 SoC and later support UHS modes for eMMC, so the
driver now makes use of these common bindings. Examples
are provided for both eMMC (which has additional bindings)
and also sd slot for stih407.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 Documentation/devicetree/bindings/mmc/sdhci-st.txt | 100 ++++++++++++++++++---
 1 file changed, 90 insertions(+), 10 deletions(-)

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-st.txt b/Documentation/devicetree/bindings/mmc/sdhci-st.txt
index 7527db4..18d950d 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-st.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-st.txt
@@ -5,20 +5,62 @@ Documentation/devicetree/bindings/mmc/mmc.txt and the properties
 used by the sdhci-st driver.
 
 Required properties:
-- compatible :  Must be "st,sdhci"
-- clock-names : Should be "mmc"
-                See: Documentation/devicetree/bindings/resource-names.txt
-- clocks :      Phandle of the clock used by the sdhci controler
-                See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+- compatible:		Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
+			to set the internal glue logic used for configuring the MMC
+			subsystem (mmcss) inside the FlashSS (available in STiH407 SoC
+			family).
+
+- clock-names:		Should be "mmc".
+			See: Documentation/devicetree/bindings/resource-names.txt
+- clocks:		Phandle to the clock.
+			See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+
+- interrupts:		One mmc interrupt should be described here.
+- interrupt-names:	Should be "mmcirq".
+
+- pinctrl-names:	A pinctrl state names "default" must be defined.
+- pinctrl-0:		Phandle referencing pin configuration of the sd/emmc controller.
+			See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+
+- reg:			This must provide the host controller base address and it can also
+			contain the FlashSS Top register for TX/RX delay used by the driver
+			to configure DLL inside the flashSS, if so reg-names must also be
+			specified.
 
 Optional properties:
-- non-removable: non-removable slot
-                 See: Documentation/devicetree/bindings/mmc/mmc.txt
-- bus-width: Number of data lines
-                 See: Documentation/devicetree/bindings/mmc/mmc.txt
+- reg-names:		Should be "mmc" and "top-mmc-delay". "top-mmc-delay" is optional
+			for eMMC on stih407 family silicon to configure DLL inside FlashSS.
+
+- non-removable:	Non-removable slot. Also used for configuring mmcss in STiH407 SoC
+			family.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- bus-width:		Number of data lines.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- max-frequency: 	Can be 200MHz, 100Mz or 50MHz (default) and used for
+			configuring the CCONFIG3 in the mmcss.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- resets:		Phandle and reset specifier pair to softreset line of HC IP.
+			See: Documentation/devicetree/bindings/reset/reset.txt
+
+- vqmmc-supply:		Phandle to the regulator dt node, mentioned as the vcc/vdd
+			supply in eMMC/SD specs.
+
+- sd-uhs--sdr50:	To enable the SDR50 in the mmcss.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- sd-uhs-sdr104:	To enable the SDR104 in the mmcss.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+
+- sd-uhs-ddr50:		To enable the DDR50 in the mmcss.
+			See:  Documentation/devicetree/bindings/mmc/mmc.txt.
 
 Example:
 
+/* Example stih416e eMMC configuration */
+
 mmc0: sdhci at fe81e000 {
 	compatible	= "st,sdhci";
 	status		= "disabled";
@@ -29,5 +71,43 @@ mmc0: sdhci at fe81e000 {
 	pinctrl-0	= <&pinctrl_mmc0>;
 	clock-names	= "mmc";
 	clocks		= <&clk_s_a1_ls 1>;
-	bus-width       = <8>
+	bus-width	= <8>
+
+/* Example SD stih407 family configuration */
+
+mmc1: sdhci at 09080000 {
+	compatible	= "st,sdhci-stih407", "st,sdhci";
+	status		= "disabled";
+	reg		= <0x09080000 0x7ff>;
+	reg-names	= "mmc";
+	interrupts	= <GIC_SPI 90 IRQ_TYPE_NONE>;
+	interrupt-names	= "mmcirq";
+	pinctrl-names	= "default";
+	pinctrl-0	= <&pinctrl_sd1>;
+	clock-names	= "mmc";
+	clocks		= <&clk_s_c0_flexgen CLK_MMC_1>;
+	resets		= <&softreset STIH407_MMC1_SOFTRESET>;
+	bus-width	= <4>;
+};
+
+/* Example eMMC stih407 family configuration */
+
+mmc0: sdhci at 09060000 {
+	compatible	= "st,sdhci-stih407", "st,sdhci";
+	status		= "disabled";
+	reg		= <0x09060000 0x7ff>, <0x9061008 0x20>;
+	reg-names	= "mmc", "top-mmc-delay";
+	interrupts	= <GIC_SPI 92 IRQ_TYPE_NONE>;
+	interrupt-names	= "mmcirq";
+	pinctrl-names	= "default";
+	pinctrl-0	= <&pinctrl_mmc0>;
+	clock-names	= "mmc";
+	clocks		= <&clk_s_c0_flexgen CLK_MMC_0>;
+	vqmmc-supply	= <&vmmc_reg>;
+	max-frequency	= <200000000>;
+	bus-width	= <8>;
+	non-removable;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
 };
-- 
1.9.1

[PATCH v2 8/8] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

[Peter Griffin]

The nodes have been split to allow as much commonality as possible.
The stih407 has a silicon bug with eMMC UHS modes (with top regs)
and as such doesn't have any of the uhs dt properties.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/stih410-b2120.dts   | 10 ++++++++++
 arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 ++++++++
 3 files changed, 48 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index c06a546..77614a5 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -336,5 +336,35 @@
 				resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
 			};
 		};
+
+		mmc0: sdhci@09060000 {
+			compatible = "st,sdhci-stih407", "st,sdhci";
+			status = "disabled";
+			reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
+			reg-names = "mmc", "top-mmc-delay";
+			interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
+			interrupt-names = "mmcirq";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_mmc0>;
+			clock-names = "mmc";
+			clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
+			bus-width = <8>;
+			non-removable;
+		};
+
+		mmc1: sdhci@09080000 {
+			compatible = "st,sdhci-stih407", "st,sdhci";
+			status = "disabled";
+			reg = <0x09080000 0x7ff>;
+			reg-names = "mmc";
+			interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
+			interrupt-names = "mmcirq";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_sd1>;
+			clock-names = "mmc";
+			clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
+			resets = <&softreset STIH407_MMC1_SOFTRESET>;
+			bus-width = <4>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
index 2f61a99..16f02c5 100644
--- a/arch/arm/boot/dts/stih410-b2120.dts
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -26,4 +26,14 @@
 	aliases {
 		ttyAS0 = &sbc_serial0;
 	};
+
+	soc {
+
+		mmc0: sdhci@09060000 {
+			max-frequency = <200000000>;
+			sd-uhs-sdr50;
+			sd-uhs-sdr104;
+			sd-uhs-ddr50;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index c1d8590..64fa0b5 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -47,6 +47,14 @@
 			status = "okay";
 		};
 
+		mmc0: sdhci@09060000 {
+			status = "okay";
+		};
+
+		mmc1: sdhci@09080000 {
+			status = "okay";
+		};
+
 		/* SSC11 to HDMI */
 		hdmiddc: i2c@9541000 {
 			status = "okay";
-- 
1.9.1

[PATCH v2 8/8] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

[Peter Griffin]

The nodes have been split to allow as much commonality as possible.
The stih407 has a silicon bug with eMMC UHS modes (with top regs)
and as such doesn't have any of the uhs dt properties.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/stih410-b2120.dts   | 10 ++++++++++
 arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 ++++++++
 3 files changed, 48 insertions(+)

diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
index c06a546..77614a5 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -336,5 +336,35 @@
 				resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
 			};
 		};
+
+		mmc0: sdhci at 09060000 {
+			compatible = "st,sdhci-stih407", "st,sdhci";
+			status = "disabled";
+			reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
+			reg-names = "mmc", "top-mmc-delay";
+			interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
+			interrupt-names = "mmcirq";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_mmc0>;
+			clock-names = "mmc";
+			clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
+			bus-width = <8>;
+			non-removable;
+		};
+
+		mmc1: sdhci at 09080000 {
+			compatible = "st,sdhci-stih407", "st,sdhci";
+			status = "disabled";
+			reg = <0x09080000 0x7ff>;
+			reg-names = "mmc";
+			interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
+			interrupt-names = "mmcirq";
+			pinctrl-names = "default";
+			pinctrl-0 = <&pinctrl_sd1>;
+			clock-names = "mmc";
+			clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
+			resets = <&softreset STIH407_MMC1_SOFTRESET>;
+			bus-width = <4>;
+		};
 	};
 };
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
index 2f61a99..16f02c5 100644
--- a/arch/arm/boot/dts/stih410-b2120.dts
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -26,4 +26,14 @@
 	aliases {
 		ttyAS0 = &sbc_serial0;
 	};
+
+	soc {
+
+		mmc0: sdhci at 09060000 {
+			max-frequency = <200000000>;
+			sd-uhs-sdr50;
+			sd-uhs-sdr104;
+			sd-uhs-ddr50;
+		};
+	};
 };
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index c1d8590..64fa0b5 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -47,6 +47,14 @@
 			status = "okay";
 		};
 
+		mmc0: sdhci at 09060000 {
+			status = "okay";
+		};
+
+		mmc1: sdhci at 09080000 {
+			status = "okay";
+		};
+
 		/* SSC11 to HDMI */
 		hdmiddc: i2c at 9541000 {
 			status = "okay";
-- 
1.9.1

Re: [PATCH v2 1/8] mmc: sdhci-st: Add macros for register offsets and bitfields for mmcss glue regs

[Maxime Coquelin]

Hi Peter,

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> The stih407 family SoC's have additional glue registers in the flashSS which
> are used to configure the Arasan controller.
>
> This patch adds macros for the register offsets and bitfields which will be used by
> subsequent patches to support stih407 family SoC's.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 91 +++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 91 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
> index 882b07e..a3bc3c3 100644
> --- a/drivers/mmc/host/sdhci-st.c
> +++ b/drivers/mmc/host/sdhci-st.c
> @@ -26,6 +26,97 @@
>   
>   #include "sdhci-pltfm.h"
>   
> +/* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */
> +
> +#define	ST_MMC_CCONFIG_REG_1		0x400
Maybe my mail client, but I see a tab instead of a space after #define.
> +#define ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT	BIT(24)
> +#define ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ	BIT(12)
> +#define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT	BIT(8)
> +#define ST_MMC_CCONFIG_ASYNC_WAKEUP	BIT(0)
> +#define ST_MMC_CCONFIG_1_DEFAULT	\
> +				((ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT) | \
> +				 (ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ) | \
> +				 (ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT))
> +
> +#define ST_MMC_CCONFIG_REG_2		0x404
> +#define ST_MMC_CCONFIG_HIGH_SPEED	BIT(28)
> +#define ST_MMC_CCONFIG_ADMA2		BIT(24)
> +#define ST_MMC_CCONFIG_8BIT		BIT(20)
> +#define ST_MMC_CCONFIG_MAX_BLK_LEN	16
> +#define  MAX_BLK_LEN_1024		1
> +#define  MAX_BLK_LEN_2048		2
> +#define BASE_CLK_FREQ_200		0xc8
> +#define BASE_CLK_FREQ_100		0x64
> +#define BASE_CLK_FREQ_50		0x32
> +#define ST_MMC_CCONFIG_2_DEFAULT \
> +	(ST_MMC_CCONFIG_HIGH_SPEED | ST_MMC_CCONFIG_ADMA2 | \
> +	 ST_MMC_CCONFIG_8BIT | \
> +	 (MAX_BLK_LEN_1024 << ST_MMC_CCONFIG_MAX_BLK_LEN))
> +
> +#define ST_MMC_CCONFIG_REG_3			0x408
> +#define ST_MMC_CCONFIG_EMMC_SLOT_TYPE		BIT(28)
> +#define ST_MMC_CCONFIG_64BIT			BIT(24)
> +#define ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	BIT(20)
> +#define ST_MMC_CCONFIG_1P8_VOLT			BIT(16)
> +#define ST_MMC_CCONFIG_3P0_VOLT			BIT(12)
> +#define ST_MMC_CCONFIG_3P3_VOLT			BIT(8)
> +#define ST_MMC_CCONFIG_SUSP_RES_SUPPORT		BIT(4)
> +#define ST_MMC_CCONFIG_SDMA			BIT(0)
> +#define ST_MMC_CCONFIG_3_DEFAULT	\
> +			 (ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	| \
> +			  ST_MMC_CCONFIG_3P3_VOLT		| \
> +			  ST_MMC_CCONFIG_SUSP_RES_SUPPORT	| \
> +			  ST_MMC_CCONFIG_SDMA)
> +
> +#define ST_MMC_CCONFIG_REG_4	0x40c
> +#define ST_MMC_CCONFIG_D_DRIVER	BIT(20)
> +#define ST_MMC_CCONFIG_C_DRIVER	BIT(16)
> +#define ST_MMC_CCONFIG_A_DRIVER	BIT(12)
> +#define ST_MMC_CCONFIG_DDR50	BIT(8)
> +#define ST_MMC_CCONFIG_SDR104	BIT(4)
> +#define ST_MMC_CCONFIG_SDR50	BIT(0)
> +#define ST_MMC_CCONFIG_4_DEFAULT	0
> +
> +#define ST_MMC_CCONFIG_REG_5		0x410
> +#define ST_MMC_CCONFIG_TUNING_FOR_SDR50	BIT(8)
> +#define RETUNING_TIMER_CNT_MAX		0xf
> +#define ST_MMC_CCONFIG_5_DEFAULT	0
> +
> +/* I/O configuration for Arasan IP */
> +#define	ST_MMC_GP_OUTPUT	0x450
Same Here.

Best regards,
Maxime

Re: [PATCH v2 1/8] mmc: sdhci-st: Add macros for register offsets and bitfields for mmcss glue regs

[Maxime Coquelin]

Hi Peter,

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> The stih407 family SoC's have additional glue registers in the flashSS which
> are used to configure the Arasan controller.
>
> This patch adds macros for the register offsets and bitfields which will be used by
> subsequent patches to support stih407 family SoC's.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 91 +++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 91 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
> index 882b07e..a3bc3c3 100644
> --- a/drivers/mmc/host/sdhci-st.c
> +++ b/drivers/mmc/host/sdhci-st.c
> @@ -26,6 +26,97 @@
>   
>   #include "sdhci-pltfm.h"
>   
> +/* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */
> +
> +#define	ST_MMC_CCONFIG_REG_1		0x400
Maybe my mail client, but I see a tab instead of a space after #define.
> +#define ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT	BIT(24)
> +#define ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ	BIT(12)
> +#define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT	BIT(8)
> +#define ST_MMC_CCONFIG_ASYNC_WAKEUP	BIT(0)
> +#define ST_MMC_CCONFIG_1_DEFAULT	\
> +				((ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT) | \
> +				 (ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ) | \
> +				 (ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT))
> +
> +#define ST_MMC_CCONFIG_REG_2		0x404
> +#define ST_MMC_CCONFIG_HIGH_SPEED	BIT(28)
> +#define ST_MMC_CCONFIG_ADMA2		BIT(24)
> +#define ST_MMC_CCONFIG_8BIT		BIT(20)
> +#define ST_MMC_CCONFIG_MAX_BLK_LEN	16
> +#define  MAX_BLK_LEN_1024		1
> +#define  MAX_BLK_LEN_2048		2
> +#define BASE_CLK_FREQ_200		0xc8
> +#define BASE_CLK_FREQ_100		0x64
> +#define BASE_CLK_FREQ_50		0x32
> +#define ST_MMC_CCONFIG_2_DEFAULT \
> +	(ST_MMC_CCONFIG_HIGH_SPEED | ST_MMC_CCONFIG_ADMA2 | \
> +	 ST_MMC_CCONFIG_8BIT | \
> +	 (MAX_BLK_LEN_1024 << ST_MMC_CCONFIG_MAX_BLK_LEN))
> +
> +#define ST_MMC_CCONFIG_REG_3			0x408
> +#define ST_MMC_CCONFIG_EMMC_SLOT_TYPE		BIT(28)
> +#define ST_MMC_CCONFIG_64BIT			BIT(24)
> +#define ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	BIT(20)
> +#define ST_MMC_CCONFIG_1P8_VOLT			BIT(16)
> +#define ST_MMC_CCONFIG_3P0_VOLT			BIT(12)
> +#define ST_MMC_CCONFIG_3P3_VOLT			BIT(8)
> +#define ST_MMC_CCONFIG_SUSP_RES_SUPPORT		BIT(4)
> +#define ST_MMC_CCONFIG_SDMA			BIT(0)
> +#define ST_MMC_CCONFIG_3_DEFAULT	\
> +			 (ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	| \
> +			  ST_MMC_CCONFIG_3P3_VOLT		| \
> +			  ST_MMC_CCONFIG_SUSP_RES_SUPPORT	| \
> +			  ST_MMC_CCONFIG_SDMA)
> +
> +#define ST_MMC_CCONFIG_REG_4	0x40c
> +#define ST_MMC_CCONFIG_D_DRIVER	BIT(20)
> +#define ST_MMC_CCONFIG_C_DRIVER	BIT(16)
> +#define ST_MMC_CCONFIG_A_DRIVER	BIT(12)
> +#define ST_MMC_CCONFIG_DDR50	BIT(8)
> +#define ST_MMC_CCONFIG_SDR104	BIT(4)
> +#define ST_MMC_CCONFIG_SDR50	BIT(0)
> +#define ST_MMC_CCONFIG_4_DEFAULT	0
> +
> +#define ST_MMC_CCONFIG_REG_5		0x410
> +#define ST_MMC_CCONFIG_TUNING_FOR_SDR50	BIT(8)
> +#define RETUNING_TIMER_CNT_MAX		0xf
> +#define ST_MMC_CCONFIG_5_DEFAULT	0
> +
> +/* I/O configuration for Arasan IP */
> +#define	ST_MMC_GP_OUTPUT	0x450
Same Here.

Best regards,
Maxime

[PATCH v2 1/8] mmc: sdhci-st: Add macros for register offsets and bitfields for mmcss glue regs

[Maxime Coquelin]

Hi Peter,

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> The stih407 family SoC's have additional glue registers in the flashSS which
> are used to configure the Arasan controller.
>
> This patch adds macros for the register offsets and bitfields which will be used by
> subsequent patches to support stih407 family SoC's.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 91 +++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 91 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
> index 882b07e..a3bc3c3 100644
> --- a/drivers/mmc/host/sdhci-st.c
> +++ b/drivers/mmc/host/sdhci-st.c
> @@ -26,6 +26,97 @@
>   
>   #include "sdhci-pltfm.h"
>   
> +/* MMCSS glue logic to setup the HC on some ST SoCs (e.g. STiH407 family) */
> +
> +#define	ST_MMC_CCONFIG_REG_1		0x400
Maybe my mail client, but I see a tab instead of a space after #define.
> +#define ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT	BIT(24)
> +#define ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ	BIT(12)
> +#define ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT	BIT(8)
> +#define ST_MMC_CCONFIG_ASYNC_WAKEUP	BIT(0)
> +#define ST_MMC_CCONFIG_1_DEFAULT	\
> +				((ST_MMC_CCONFIG_TIMEOUT_CLK_UNIT) | \
> +				 (ST_MMC_CCONFIG_TIMEOUT_CLK_FREQ) | \
> +				 (ST_MMC_CCONFIG_TUNING_COUNT_DEFAULT))
> +
> +#define ST_MMC_CCONFIG_REG_2		0x404
> +#define ST_MMC_CCONFIG_HIGH_SPEED	BIT(28)
> +#define ST_MMC_CCONFIG_ADMA2		BIT(24)
> +#define ST_MMC_CCONFIG_8BIT		BIT(20)
> +#define ST_MMC_CCONFIG_MAX_BLK_LEN	16
> +#define  MAX_BLK_LEN_1024		1
> +#define  MAX_BLK_LEN_2048		2
> +#define BASE_CLK_FREQ_200		0xc8
> +#define BASE_CLK_FREQ_100		0x64
> +#define BASE_CLK_FREQ_50		0x32
> +#define ST_MMC_CCONFIG_2_DEFAULT \
> +	(ST_MMC_CCONFIG_HIGH_SPEED | ST_MMC_CCONFIG_ADMA2 | \
> +	 ST_MMC_CCONFIG_8BIT | \
> +	 (MAX_BLK_LEN_1024 << ST_MMC_CCONFIG_MAX_BLK_LEN))
> +
> +#define ST_MMC_CCONFIG_REG_3			0x408
> +#define ST_MMC_CCONFIG_EMMC_SLOT_TYPE		BIT(28)
> +#define ST_MMC_CCONFIG_64BIT			BIT(24)
> +#define ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	BIT(20)
> +#define ST_MMC_CCONFIG_1P8_VOLT			BIT(16)
> +#define ST_MMC_CCONFIG_3P0_VOLT			BIT(12)
> +#define ST_MMC_CCONFIG_3P3_VOLT			BIT(8)
> +#define ST_MMC_CCONFIG_SUSP_RES_SUPPORT		BIT(4)
> +#define ST_MMC_CCONFIG_SDMA			BIT(0)
> +#define ST_MMC_CCONFIG_3_DEFAULT	\
> +			 (ST_MMC_CCONFIG_ASYNCH_INTR_SUPPORT	| \
> +			  ST_MMC_CCONFIG_3P3_VOLT		| \
> +			  ST_MMC_CCONFIG_SUSP_RES_SUPPORT	| \
> +			  ST_MMC_CCONFIG_SDMA)
> +
> +#define ST_MMC_CCONFIG_REG_4	0x40c
> +#define ST_MMC_CCONFIG_D_DRIVER	BIT(20)
> +#define ST_MMC_CCONFIG_C_DRIVER	BIT(16)
> +#define ST_MMC_CCONFIG_A_DRIVER	BIT(12)
> +#define ST_MMC_CCONFIG_DDR50	BIT(8)
> +#define ST_MMC_CCONFIG_SDR104	BIT(4)
> +#define ST_MMC_CCONFIG_SDR50	BIT(0)
> +#define ST_MMC_CCONFIG_4_DEFAULT	0
> +
> +#define ST_MMC_CCONFIG_REG_5		0x410
> +#define ST_MMC_CCONFIG_TUNING_FOR_SDR50	BIT(8)
> +#define RETUNING_TIMER_CNT_MAX		0xf
> +#define ST_MMC_CCONFIG_5_DEFAULT	0
> +
> +/* I/O configuration for Arasan IP */
> +#define	ST_MMC_GP_OUTPUT	0x450
Same Here.

Best regards,
Maxime

Re: [PATCH v2 2/8] mmc: sdhci-st: Add support for de-asserting reset signal and top regs resource

[Maxime Coquelin]

Hi Peter,

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> STiH407 family SoC's can have a reset signal for the controller which needs to
> be managed. Also the eMMC controller has some additional 'top' memory mapped
> registers which are used to manage the dynamic and static delay required for
> UHS modes. This patch adds support for creating the mapping, which will be used
> by subsequent patches.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 52 ++++++++++++++++++++++++++++++++++++++++++---
>   1 file changed, 49 insertions(+), 3 deletions(-)
>

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

Re: [PATCH v2 2/8] mmc: sdhci-st: Add support for de-asserting reset signal and top regs resource

[Maxime Coquelin]

Hi Peter,

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> STiH407 family SoC's can have a reset signal for the controller which needs to
> be managed. Also the eMMC controller has some additional 'top' memory mapped
> registers which are used to manage the dynamic and static delay required for
> UHS modes. This patch adds support for creating the mapping, which will be used
> by subsequent patches.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 52 ++++++++++++++++++++++++++++++++++++++++++---
>   1 file changed, 49 insertions(+), 3 deletions(-)
>

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

[PATCH v2 2/8] mmc: sdhci-st: Add support for de-asserting reset signal and top regs resource

[Maxime Coquelin]

Hi Peter,

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> STiH407 family SoC's can have a reset signal for the controller which needs to
> be managed. Also the eMMC controller has some additional 'top' memory mapped
> registers which are used to manage the dynamic and static delay required for
> UHS modes. This patch adds support for creating the mapping, which will be used
> by subsequent patches.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 52 ++++++++++++++++++++++++++++++++++++++++++---
>   1 file changed, 49 insertions(+), 3 deletions(-)
>

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

Re: [PATCH v2 3/8] mmc: sdhci-st: Add delay management functions for top registers (eMMC).

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> Due to the tight timing constriants in some UHS modes, it is required to have
s/constriant/constraints/
> some delay management in the design. Two types of delay management are supported
> in the HW: -
>
> 1) Static delay management
> 2) Dynamic delay management
>
> NB: The delay management is only there when eMMC interface is selected.
>
> 1: Static delay management: is used to provide PVT dependent static delay on the
> clock/data lines to manage setup/hold requirements of the interface. The maximum
> delay possible is 3.25ns. These delays are PVT dependent, and thus delay values
> applied are not accurate and vary across provcess voltage and temperature range.
> Due to this these delays must not be used on the very time critical paths.
>
> 2. Dynamic delay locked loop (DLL): is used to provide dynamic delay management.
> The advantage of DLL is that it provides accurate & PVT indepedent delay.
>
> The DLL is used to provide delay on the loopback clock on "Read Path" to capture
> read data reliably. On TX path the clock on which output data is transmitted is
> delayed, resulting in delay of TX data.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 58 +++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 58 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
> index 0101ae9..3443cc0 100644
> --- a/drivers/mmc/host/sdhci-st.c
> +++ b/drivers/mmc/host/sdhci-st.c
> @@ -122,6 +122,64 @@ struct st_mmc_platform_data {
>   		 ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY | \
>   		 ST_TOP_MMC_START_DLL_LOCK)
>   
> +/*
> + * For clock speeds greater than 90MHz, we need to check that the
> + * DLL procedure has finished before switching to ultra-speed modes.
> + */
> +#define	CLK_TO_CHECK_DLL_LOCK	90000000
> +
> +static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
> +{
> +	if (ioaddr) {
Maybe you could do:
     if (!ioaddr)
         return;

     writel_relaxed....
> +		writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
> +		writel_relaxed(ST_TOP_MMC_DLY_MAX,
> +				ioaddr + ST_TOP_MMC_TX_CLK_DLY);
> +	}
> +}
> +
> +static inline void st_mmcss_set_dll(void __iomem *ioaddr)
> +{
> +	if (ioaddr) {
Ditto


> +		writel_relaxed(ST_TOP_MMC_DYN_DLY_CONF,
> +			ioaddr + ST_TOP_MMC_DLY_CTRL);
> +		writel_relaxed(ST_TOP_MMC_TX_DLL_STEP_DLY_VALID,
> +			ioaddr + ST_TOP_MMC_TX_DLL_STEP_DLY);
> +	}
> +}
> +
> +static int st_mmcss_lock_dll(void __iomem *ioaddr)
> +{
> +	unsigned long curr, value;
> +	unsigned long finish = jiffies + HZ;
> +
> +	/* Checks if the DLL procedure is finished */
> +	do {
> +		curr = jiffies;
> +		value = readl(ioaddr + ST_MMC_STATUS_R);
> +		if (value & 0x1)
> +			return 0;
> +
> +		cpu_relax();
> +	} while (!time_after_eq(curr, finish));
> +
> +	return -EBUSY;
> +}
> +
> +static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
> +{
> +	int ret = 0;
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct st_mmc_platform_data *pdata = pltfm_host->priv;
> +
> +	if (host->clock > CLK_TO_CHECK_DLL_LOCK) {
> +		st_mmcss_set_dll(pdata->top_ioaddr);
> +		ret = st_mmcss_lock_dll(host->ioaddr);
> +	}
> +
> +	return ret;
> +}
> +
> +
>   static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
>   {
>   	u32 ret;

Re: [PATCH v2 3/8] mmc: sdhci-st: Add delay management functions for top registers (eMMC).

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> Due to the tight timing constriants in some UHS modes, it is required to have
s/constriant/constraints/
> some delay management in the design. Two types of delay management are supported
> in the HW: -
>
> 1) Static delay management
> 2) Dynamic delay management
>
> NB: The delay management is only there when eMMC interface is selected.
>
> 1: Static delay management: is used to provide PVT dependent static delay on the
> clock/data lines to manage setup/hold requirements of the interface. The maximum
> delay possible is 3.25ns. These delays are PVT dependent, and thus delay values
> applied are not accurate and vary across provcess voltage and temperature range.
> Due to this these delays must not be used on the very time critical paths.
>
> 2. Dynamic delay locked loop (DLL): is used to provide dynamic delay management.
> The advantage of DLL is that it provides accurate & PVT indepedent delay.
>
> The DLL is used to provide delay on the loopback clock on "Read Path" to capture
> read data reliably. On TX path the clock on which output data is transmitted is
> delayed, resulting in delay of TX data.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 58 +++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 58 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
> index 0101ae9..3443cc0 100644
> --- a/drivers/mmc/host/sdhci-st.c
> +++ b/drivers/mmc/host/sdhci-st.c
> @@ -122,6 +122,64 @@ struct st_mmc_platform_data {
>   		 ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY | \
>   		 ST_TOP_MMC_START_DLL_LOCK)
>   
> +/*
> + * For clock speeds greater than 90MHz, we need to check that the
> + * DLL procedure has finished before switching to ultra-speed modes.
> + */
> +#define	CLK_TO_CHECK_DLL_LOCK	90000000
> +
> +static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
> +{
> +	if (ioaddr) {
Maybe you could do:
     if (!ioaddr)
         return;

     writel_relaxed....
> +		writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
> +		writel_relaxed(ST_TOP_MMC_DLY_MAX,
> +				ioaddr + ST_TOP_MMC_TX_CLK_DLY);
> +	}
> +}
> +
> +static inline void st_mmcss_set_dll(void __iomem *ioaddr)
> +{
> +	if (ioaddr) {
Ditto


> +		writel_relaxed(ST_TOP_MMC_DYN_DLY_CONF,
> +			ioaddr + ST_TOP_MMC_DLY_CTRL);
> +		writel_relaxed(ST_TOP_MMC_TX_DLL_STEP_DLY_VALID,
> +			ioaddr + ST_TOP_MMC_TX_DLL_STEP_DLY);
> +	}
> +}
> +
> +static int st_mmcss_lock_dll(void __iomem *ioaddr)
> +{
> +	unsigned long curr, value;
> +	unsigned long finish = jiffies + HZ;
> +
> +	/* Checks if the DLL procedure is finished */
> +	do {
> +		curr = jiffies;
> +		value = readl(ioaddr + ST_MMC_STATUS_R);
> +		if (value & 0x1)
> +			return 0;
> +
> +		cpu_relax();
> +	} while (!time_after_eq(curr, finish));
> +
> +	return -EBUSY;
> +}
> +
> +static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
> +{
> +	int ret = 0;
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct st_mmc_platform_data *pdata = pltfm_host->priv;
> +
> +	if (host->clock > CLK_TO_CHECK_DLL_LOCK) {
> +		st_mmcss_set_dll(pdata->top_ioaddr);
> +		ret = st_mmcss_lock_dll(host->ioaddr);
> +	}
> +
> +	return ret;
> +}
> +
> +
>   static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
>   {
>   	u32 ret;

[PATCH v2 3/8] mmc: sdhci-st: Add delay management functions for top registers (eMMC).

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> Due to the tight timing constriants in some UHS modes, it is required to have
s/constriant/constraints/
> some delay management in the design. Two types of delay management are supported
> in the HW: -
>
> 1) Static delay management
> 2) Dynamic delay management
>
> NB: The delay management is only there when eMMC interface is selected.
>
> 1: Static delay management: is used to provide PVT dependent static delay on the
> clock/data lines to manage setup/hold requirements of the interface. The maximum
> delay possible is 3.25ns. These delays are PVT dependent, and thus delay values
> applied are not accurate and vary across provcess voltage and temperature range.
> Due to this these delays must not be used on the very time critical paths.
>
> 2. Dynamic delay locked loop (DLL): is used to provide dynamic delay management.
> The advantage of DLL is that it provides accurate & PVT indepedent delay.
>
> The DLL is used to provide delay on the loopback clock on "Read Path" to capture
> read data reliably. On TX path the clock on which output data is transmitted is
> delayed, resulting in delay of TX data.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 58 +++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 58 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
> index 0101ae9..3443cc0 100644
> --- a/drivers/mmc/host/sdhci-st.c
> +++ b/drivers/mmc/host/sdhci-st.c
> @@ -122,6 +122,64 @@ struct st_mmc_platform_data {
>   		 ST_TOP_MMC_DLY_CTRL_ATUNE_NOT_CFG_DLY | \
>   		 ST_TOP_MMC_START_DLL_LOCK)
>   
> +/*
> + * For clock speeds greater than 90MHz, we need to check that the
> + * DLL procedure has finished before switching to ultra-speed modes.
> + */
> +#define	CLK_TO_CHECK_DLL_LOCK	90000000
> +
> +static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
> +{
> +	if (ioaddr) {
Maybe you could do:
     if (!ioaddr)
         return;

     writel_relaxed....
> +		writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
> +		writel_relaxed(ST_TOP_MMC_DLY_MAX,
> +				ioaddr + ST_TOP_MMC_TX_CLK_DLY);
> +	}
> +}
> +
> +static inline void st_mmcss_set_dll(void __iomem *ioaddr)
> +{
> +	if (ioaddr) {
Ditto


> +		writel_relaxed(ST_TOP_MMC_DYN_DLY_CONF,
> +			ioaddr + ST_TOP_MMC_DLY_CTRL);
> +		writel_relaxed(ST_TOP_MMC_TX_DLL_STEP_DLY_VALID,
> +			ioaddr + ST_TOP_MMC_TX_DLL_STEP_DLY);
> +	}
> +}
> +
> +static int st_mmcss_lock_dll(void __iomem *ioaddr)
> +{
> +	unsigned long curr, value;
> +	unsigned long finish = jiffies + HZ;
> +
> +	/* Checks if the DLL procedure is finished */
> +	do {
> +		curr = jiffies;
> +		value = readl(ioaddr + ST_MMC_STATUS_R);
> +		if (value & 0x1)
> +			return 0;
> +
> +		cpu_relax();
> +	} while (!time_after_eq(curr, finish));
> +
> +	return -EBUSY;
> +}
> +
> +static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
> +{
> +	int ret = 0;
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct st_mmc_platform_data *pdata = pltfm_host->priv;
> +
> +	if (host->clock > CLK_TO_CHECK_DLL_LOCK) {
> +		st_mmcss_set_dll(pdata->top_ioaddr);
> +		ret = st_mmcss_lock_dll(host->ioaddr);
> +	}
> +
> +	return ret;
> +}
> +
> +
>   static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
>   {
>   	u32 ret;

Re: [PATCH v2 4/8] mmc: sdhci-st: Add st_mmcss_cconfig function to configure mmcss glue registers.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> STiH407 family SoC's have glue registers in the flashSS subsystem which
> are used to configure the Arasan HC. This patch configures these glue
> registers according to what has been specified in the DT.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 88 +++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 88 insertions(+)
>

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

Re: [PATCH v2 4/8] mmc: sdhci-st: Add st_mmcss_cconfig function to configure mmcss glue registers.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> STiH407 family SoC's have glue registers in the flashSS subsystem which
> are used to configure the Arasan HC. This patch configures these glue
> registers according to what has been specified in the DT.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 88 +++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 88 insertions(+)
>

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

[PATCH v2 4/8] mmc: sdhci-st: Add st_mmcss_cconfig function to configure mmcss glue registers.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> STiH407 family SoC's have glue registers in the flashSS subsystem which
> are used to configure the Arasan HC. This patch configures these glue
> registers according to what has been specified in the DT.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 88 +++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 88 insertions(+)
>

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

Re: [PATCH v2 5/8] mmc: sdhci-st: Add sdhci_st_set_uhs_signaling function.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> To allow UHS modes to work properly we need to provide the st specific
> set_uhs_signaling callback function. This function differs from the
> generic sdhci_set_uhs_signaling callback in that we need to configure
> the correct delay depending on the UHS mode, and also set the V18_EN
> bit.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 50 +++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 50 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
> index 11cf4e2..d53bc82 100644
> --- a/drivers/mmc/host/sdhci-st.c
> +++ b/drivers/mmc/host/sdhci-st.c
> @@ -260,6 +260,55 @@ static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
>   	return ret;
>   }
>   
> +static void sdhci_st_set_uhs_signaling(struct sdhci_host *host,
> +					unsigned int uhs)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct st_mmc_platform_data *pdata = pltfm_host->priv;
> +	u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> +	int ret = 0;
> +
> +	/* Select Bus Speed Mode for host */
> +	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
> +	switch (uhs) {
> +	/*
> +	 * Set V18_EN -- UHS modes do not work without this.
> +	 * does not change signaling voltage
> +	 */
> +
> +	case MMC_TIMING_UHS_SDR12:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180;
> +		break;
> +	case MMC_TIMING_UHS_SDR25:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180;
> +		break;
> +	case MMC_TIMING_UHS_SDR50:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
> +		ret = sdhci_st_set_dll_for_clock(host);
> +		break;
> +	case MMC_TIMING_UHS_SDR104:
> +	case MMC_TIMING_MMC_HS200:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
> +		ret =  sdhci_st_set_dll_for_clock(host);
> +		break;
> +	case MMC_TIMING_UHS_DDR50:
> +	case MMC_TIMING_MMC_DDR52:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
> +		break;
> +	}
> +
> +	if (ret)
> +		dev_warn(mmc_dev(host->mmc), "Error setting dll for clock\n");
Maybe you could  print the uhs value to know which mode it was trying to 
set?
> +
> +	dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2);
> +
> +	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
> +}
>   
>   static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
>   {
> @@ -283,6 +332,7 @@ static const struct sdhci_ops sdhci_st_ops = {
>   	.set_bus_width = sdhci_set_bus_width,
>   	.read_l = sdhci_st_readl,
>   	.reset = sdhci_reset,
> +	.set_uhs_signaling = sdhci_st_set_uhs_signaling,
>   };
>   
>   static const struct sdhci_pltfm_data sdhci_st_pdata = {

Other than that, you can add my:
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

Re: [PATCH v2 5/8] mmc: sdhci-st: Add sdhci_st_set_uhs_signaling function.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> To allow UHS modes to work properly we need to provide the st specific
> set_uhs_signaling callback function. This function differs from the
> generic sdhci_set_uhs_signaling callback in that we need to configure
> the correct delay depending on the UHS mode, and also set the V18_EN
> bit.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 50 +++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 50 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
> index 11cf4e2..d53bc82 100644
> --- a/drivers/mmc/host/sdhci-st.c
> +++ b/drivers/mmc/host/sdhci-st.c
> @@ -260,6 +260,55 @@ static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
>   	return ret;
>   }
>   
> +static void sdhci_st_set_uhs_signaling(struct sdhci_host *host,
> +					unsigned int uhs)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct st_mmc_platform_data *pdata = pltfm_host->priv;
> +	u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> +	int ret = 0;
> +
> +	/* Select Bus Speed Mode for host */
> +	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
> +	switch (uhs) {
> +	/*
> +	 * Set V18_EN -- UHS modes do not work without this.
> +	 * does not change signaling voltage
> +	 */
> +
> +	case MMC_TIMING_UHS_SDR12:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180;
> +		break;
> +	case MMC_TIMING_UHS_SDR25:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180;
> +		break;
> +	case MMC_TIMING_UHS_SDR50:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
> +		ret = sdhci_st_set_dll_for_clock(host);
> +		break;
> +	case MMC_TIMING_UHS_SDR104:
> +	case MMC_TIMING_MMC_HS200:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
> +		ret =  sdhci_st_set_dll_for_clock(host);
> +		break;
> +	case MMC_TIMING_UHS_DDR50:
> +	case MMC_TIMING_MMC_DDR52:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
> +		break;
> +	}
> +
> +	if (ret)
> +		dev_warn(mmc_dev(host->mmc), "Error setting dll for clock\n");
Maybe you could  print the uhs value to know which mode it was trying to 
set?
> +
> +	dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2);
> +
> +	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
> +}
>   
>   static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
>   {
> @@ -283,6 +332,7 @@ static const struct sdhci_ops sdhci_st_ops = {
>   	.set_bus_width = sdhci_set_bus_width,
>   	.read_l = sdhci_st_readl,
>   	.reset = sdhci_reset,
> +	.set_uhs_signaling = sdhci_st_set_uhs_signaling,
>   };
>   
>   static const struct sdhci_pltfm_data sdhci_st_pdata = {

Other than that, you can add my:
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

[PATCH v2 5/8] mmc: sdhci-st: Add sdhci_st_set_uhs_signaling function.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> To allow UHS modes to work properly we need to provide the st specific
> set_uhs_signaling callback function. This function differs from the
> generic sdhci_set_uhs_signaling callback in that we need to configure
> the correct delay depending on the UHS mode, and also set the V18_EN
> bit.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 50 +++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 50 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-st.c b/drivers/mmc/host/sdhci-st.c
> index 11cf4e2..d53bc82 100644
> --- a/drivers/mmc/host/sdhci-st.c
> +++ b/drivers/mmc/host/sdhci-st.c
> @@ -260,6 +260,55 @@ static int sdhci_st_set_dll_for_clock(struct sdhci_host *host)
>   	return ret;
>   }
>   
> +static void sdhci_st_set_uhs_signaling(struct sdhci_host *host,
> +					unsigned int uhs)
> +{
> +	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> +	struct st_mmc_platform_data *pdata = pltfm_host->priv;
> +	u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
> +	int ret = 0;
> +
> +	/* Select Bus Speed Mode for host */
> +	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
> +	switch (uhs) {
> +	/*
> +	 * Set V18_EN -- UHS modes do not work without this.
> +	 * does not change signaling voltage
> +	 */
> +
> +	case MMC_TIMING_UHS_SDR12:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR12 | SDHCI_CTRL_VDD_180;
> +		break;
> +	case MMC_TIMING_UHS_SDR25:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR25 | SDHCI_CTRL_VDD_180;
> +		break;
> +	case MMC_TIMING_UHS_SDR50:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
> +		ret = sdhci_st_set_dll_for_clock(host);
> +		break;
> +	case MMC_TIMING_UHS_SDR104:
> +	case MMC_TIMING_MMC_HS200:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
> +		ret =  sdhci_st_set_dll_for_clock(host);
> +		break;
> +	case MMC_TIMING_UHS_DDR50:
> +	case MMC_TIMING_MMC_DDR52:
> +		st_mmcss_set_static_delay(pdata->top_ioaddr);
> +		ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
> +		break;
> +	}
> +
> +	if (ret)
> +		dev_warn(mmc_dev(host->mmc), "Error setting dll for clock\n");
Maybe you could  print the uhs value to know which mode it was trying to 
set?
> +
> +	dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2);
> +
> +	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
> +}
>   
>   static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
>   {
> @@ -283,6 +332,7 @@ static const struct sdhci_ops sdhci_st_ops = {
>   	.set_bus_width = sdhci_set_bus_width,
>   	.read_l = sdhci_st_readl,
>   	.reset = sdhci_reset,
> +	.set_uhs_signaling = sdhci_st_set_uhs_signaling,
>   };
>   
>   static const struct sdhci_pltfm_data sdhci_st_pdata = {

Other than that, you can add my:
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

Re: [PATCH v2 6/8] mmc: sdhci-st: Update the quirks for this controller.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> Some additional quirks need to be enabled now we support UHS
> modes. This avoids some spurious warnings like
>
> "Got data interrupt 0x00000002 even though no data operation was in progress"
>
> Testing on stih410-b2120 board achieves the following speeds
> with HS200 eMMC card.
>
> max-frequency = 200Mhz
> /dev/mmcblk0p1:
>   Timing buffered disk reads: 270 MB in  3.02 seconds =  89.54 MB/sec
>
> max-frequency = 100Mhz
> root@debian-armhf:~# hdparm -t /dev/mmcblk0p1
> /dev/mmcblk0p1:
>   Timing buffered disk reads: 210 MB in  3.00 seconds =  70.00 MB/sec
>
> max-frequency = 50Mhz
> root@debian-armhf:~# hdparm -t /dev/mmcblk0p1
> /dev/mmcblk0p1:
>   Timing buffered disk reads: 118 MB in  3.00 seconds =  39.28 MB/sec
>
> This is better than the 3.10 kernel which achieves 77.59 MB/sec
> at 200Mhz clock (same board/soc/eMMC).
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
>

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

Re: [PATCH v2 6/8] mmc: sdhci-st: Update the quirks for this controller.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> Some additional quirks need to be enabled now we support UHS
> modes. This avoids some spurious warnings like
>
> "Got data interrupt 0x00000002 even though no data operation was in progress"
>
> Testing on stih410-b2120 board achieves the following speeds
> with HS200 eMMC card.
>
> max-frequency = 200Mhz
> /dev/mmcblk0p1:
>   Timing buffered disk reads: 270 MB in  3.02 seconds =  89.54 MB/sec
>
> max-frequency = 100Mhz
> root@debian-armhf:~# hdparm -t /dev/mmcblk0p1
> /dev/mmcblk0p1:
>   Timing buffered disk reads: 210 MB in  3.00 seconds =  70.00 MB/sec
>
> max-frequency = 50Mhz
> root@debian-armhf:~# hdparm -t /dev/mmcblk0p1
> /dev/mmcblk0p1:
>   Timing buffered disk reads: 118 MB in  3.00 seconds =  39.28 MB/sec
>
> This is better than the 3.10 kernel which achieves 77.59 MB/sec
> at 200Mhz clock (same board/soc/eMMC).
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
>

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

[PATCH v2 6/8] mmc: sdhci-st: Update the quirks for this controller.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> Some additional quirks need to be enabled now we support UHS
> modes. This avoids some spurious warnings like
>
> "Got data interrupt 0x00000002 even though no data operation was in progress"
>
> Testing on stih410-b2120 board achieves the following speeds
> with HS200 eMMC card.
>
> max-frequency = 200Mhz
> /dev/mmcblk0p1:
>   Timing buffered disk reads: 270 MB in  3.02 seconds =  89.54 MB/sec
>
> max-frequency = 100Mhz
> root at debian-armhf:~# hdparm -t /dev/mmcblk0p1
> /dev/mmcblk0p1:
>   Timing buffered disk reads: 210 MB in  3.00 seconds =  70.00 MB/sec
>
> max-frequency = 50Mhz
> root at debian-armhf:~# hdparm -t /dev/mmcblk0p1
> /dev/mmcblk0p1:
>   Timing buffered disk reads: 118 MB in  3.00 seconds =  39.28 MB/sec
>
> This is better than the 3.10 kernel which achieves 77.59 MB/sec
> at 200Mhz clock (same board/soc/eMMC).
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
> ---
>   drivers/mmc/host/sdhci-st.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
>

Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

Re: [PATCH v2 7/8] mmc: sdhci-st: Update ST SDHCI binding documentation.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> This patch updates the binding information to reflect the
> extra dt options which are now supported by the sdhci-st.c
> driver which enable support for stih407 family silicon.
>
> Stih410 SoC and later support UHS modes for eMMC, so the
STiH410
> driver now makes use of these common bindings. Examples
> are provided for both eMMC (which has additional bindings)
> and also sd slot for stih407.
STiH407
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>   Documentation/devicetree/bindings/mmc/sdhci-st.txt | 100 ++++++++++++++++++---
>   1 file changed, 90 insertions(+), 10 deletions(-)
>

Once fixed, you can add my:
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

Re: [PATCH v2 7/8] mmc: sdhci-st: Update ST SDHCI binding documentation.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> This patch updates the binding information to reflect the
> extra dt options which are now supported by the sdhci-st.c
> driver which enable support for stih407 family silicon.
>
> Stih410 SoC and later support UHS modes for eMMC, so the
STiH410
> driver now makes use of these common bindings. Examples
> are provided for both eMMC (which has additional bindings)
> and also sd slot for stih407.
STiH407
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>   Documentation/devicetree/bindings/mmc/sdhci-st.txt | 100 ++++++++++++++++++---
>   1 file changed, 90 insertions(+), 10 deletions(-)
>

Once fixed, you can add my:
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

[PATCH v2 7/8] mmc: sdhci-st: Update ST SDHCI binding documentation.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> This patch updates the binding information to reflect the
> extra dt options which are now supported by the sdhci-st.c
> driver which enable support for stih407 family silicon.
>
> Stih410 SoC and later support UHS modes for eMMC, so the
STiH410
> driver now makes use of these common bindings. Examples
> are provided for both eMMC (which has additional bindings)
> and also sd slot for stih407.
STiH407
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>   Documentation/devicetree/bindings/mmc/sdhci-st.txt | 100 ++++++++++++++++++---
>   1 file changed, 90 insertions(+), 10 deletions(-)
>

Once fixed, you can add my:
Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks,
Maxime

Re: [PATCH v2 8/8] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> The nodes have been split to allow as much commonality as possible.
> The stih407 has a silicon bug with eMMC UHS modes (with top regs)
> and as such doesn't have any of the uhs dt properties.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>   arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++
>   arch/arm/boot/dts/stih410-b2120.dts   | 10 ++++++++++
>   arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 ++++++++
>   3 files changed, 48 insertions(+)
>
>
Maybe you could also add SD/eMMC support to the b2199 too?
I can test if you don't have the hardware yet.

Kind regards,
Maxime

Re: [PATCH v2 8/8] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> The nodes have been split to allow as much commonality as possible.
> The stih407 has a silicon bug with eMMC UHS modes (with top regs)
> and as such doesn't have any of the uhs dt properties.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>   arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++
>   arch/arm/boot/dts/stih410-b2120.dts   | 10 ++++++++++
>   arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 ++++++++
>   3 files changed, 48 insertions(+)
>
>
Maybe you could also add SD/eMMC support to the b2199 too?
I can test if you don't have the hardware yet.

Kind regards,
Maxime

[PATCH v2 8/8] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

[Maxime Coquelin]

On 02/26/2015 02:10 PM, Peter Griffin wrote:
> The nodes have been split to allow as much commonality as possible.
> The stih407 has a silicon bug with eMMC UHS modes (with top regs)
> and as such doesn't have any of the uhs dt properties.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
>   arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++
>   arch/arm/boot/dts/stih410-b2120.dts   | 10 ++++++++++
>   arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 ++++++++
>   3 files changed, 48 insertions(+)
>
>
Maybe you could also add SD/eMMC support to the b2199 too?
I can test if you don't have the hardware yet.

Kind regards,
Maxime

Re: [PATCH v2 1/8] mmc: sdhci-st: Add macros for register offsets and bitfields for mmcss glue regs

[Peter Griffin]

Hi Maxime,

On Tue, 03 Mar 2015, Maxime Coquelin wrote:

> >+
> >+#define	ST_MMC_CCONFIG_REG_1		0x400
> Maybe my mail client, but I see a tab instead of a space after #define.

Yes your correct, have fixed all occurances in v3

regards,

Peter.

Re: [PATCH v2 1/8] mmc: sdhci-st: Add macros for register offsets and bitfields for mmcss glue regs

[Peter Griffin]

Hi Maxime,

On Tue, 03 Mar 2015, Maxime Coquelin wrote:

> >+
> >+#define	ST_MMC_CCONFIG_REG_1		0x400
> Maybe my mail client, but I see a tab instead of a space after #define.

Yes your correct, have fixed all occurances in v3

regards,

Peter.
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[PATCH v2 1/8] mmc: sdhci-st: Add macros for register offsets and bitfields for mmcss glue regs

[Peter Griffin]

Hi Maxime,

On Tue, 03 Mar 2015, Maxime Coquelin wrote:

> >+
> >+#define	ST_MMC_CCONFIG_REG_1		0x400
> Maybe my mail client, but I see a tab instead of a space after #define.

Yes your correct, have fixed all occurances in v3

regards,

Peter.

Re: [PATCH v2 3/8] mmc: sdhci-st: Add delay management functions for top registers (eMMC).

[Peter Griffin]

Hi Maxime,

On Tue, 03 Mar 2015, Maxime Coquelin wrote:
> 
> On 02/26/2015 02:10 PM, Peter Griffin wrote:
> >Due to the tight timing constriants in some UHS modes, it is required to have
> s/constriant/constraints/

Will fix.

<snip>
> >+
> >+static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
> >+{
> >+	if (ioaddr) {
> Maybe you could do:
>     if (!ioaddr)
>         return;

Yes good idea, I have made that change in V3.
> 
>     writel_relaxed....
> >+		writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
> >+		writel_relaxed(ST_TOP_MMC_DLY_MAX,
> >+				ioaddr + ST_TOP_MMC_TX_CLK_DLY);
> >+	}
> >+}
> >+
> >+static inline void st_mmcss_set_dll(void __iomem *ioaddr)
> >+{
> >+	if (ioaddr) {
> Ditto

regards,

Peter

[PATCH v2 3/8] mmc: sdhci-st: Add delay management functions for top registers (eMMC).

[Peter Griffin]

Hi Maxime,

On Tue, 03 Mar 2015, Maxime Coquelin wrote:
> 
> On 02/26/2015 02:10 PM, Peter Griffin wrote:
> >Due to the tight timing constriants in some UHS modes, it is required to have
> s/constriant/constraints/

Will fix.

<snip>
> >+
> >+static inline void st_mmcss_set_static_delay(void __iomem *ioaddr)
> >+{
> >+	if (ioaddr) {
> Maybe you could do:
>     if (!ioaddr)
>         return;

Yes good idea, I have made that change in V3.
> 
>     writel_relaxed....
> >+		writel_relaxed(0x0, ioaddr + ST_TOP_MMC_DLY_CTRL);
> >+		writel_relaxed(ST_TOP_MMC_DLY_MAX,
> >+				ioaddr + ST_TOP_MMC_TX_CLK_DLY);
> >+	}
> >+}
> >+
> >+static inline void st_mmcss_set_dll(void __iomem *ioaddr)
> >+{
> >+	if (ioaddr) {
> Ditto

regards,

Peter

Re: [PATCH v2 5/8] mmc: sdhci-st: Add sdhci_st_set_uhs_signaling function.

[Peter Griffin]

Hi Maxime,

On Tue, 03 Mar 2015, Maxime Coquelin wrote:
> 
> On 02/26/2015 02:10 PM, Peter Griffin wrote:
> >To allow UHS modes to work properly we need to provide the st specific
> >set_uhs_signaling callback function. This function differs from the
> >generic sdhci_set_uhs_signaling callback in that we need to configure
> >the correct delay depending on the UHS mode, and also set the V18_EN
> >bit.
<snip>
> >+	if (ret)
> >+		dev_warn(mmc_dev(host->mmc), "Error setting dll for clock\n");
> Maybe you could  print the uhs value to know which mode it was
> trying to set?

Yes good idea, I have made that change in v3.
> >+
> >+	dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2);
> >+
> >+	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
> >+}
> >  static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
> >  {
> >@@ -283,6 +332,7 @@ static const struct sdhci_ops sdhci_st_ops = {
> >  	.set_bus_width = sdhci_set_bus_width,
> >  	.read_l = sdhci_st_readl,
> >  	.reset = sdhci_reset,
> >+	.set_uhs_signaling = sdhci_st_set_uhs_signaling,
> >  };
> >  static const struct sdhci_pltfm_data sdhci_st_pdata = {
> 
> Other than that, you can add my:
> Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks, regards,

Peter.

[PATCH v2 5/8] mmc: sdhci-st: Add sdhci_st_set_uhs_signaling function.

[Peter Griffin]

Hi Maxime,

On Tue, 03 Mar 2015, Maxime Coquelin wrote:
> 
> On 02/26/2015 02:10 PM, Peter Griffin wrote:
> >To allow UHS modes to work properly we need to provide the st specific
> >set_uhs_signaling callback function. This function differs from the
> >generic sdhci_set_uhs_signaling callback in that we need to configure
> >the correct delay depending on the UHS mode, and also set the V18_EN
> >bit.
<snip>
> >+	if (ret)
> >+		dev_warn(mmc_dev(host->mmc), "Error setting dll for clock\n");
> Maybe you could  print the uhs value to know which mode it was
> trying to set?

Yes good idea, I have made that change in v3.
> >+
> >+	dev_dbg(mmc_dev(host->mmc), "uhs %d, ctrl_2 %04X\n", uhs, ctrl_2);
> >+
> >+	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
> >+}
> >  static u32 sdhci_st_readl(struct sdhci_host *host, int reg)
> >  {
> >@@ -283,6 +332,7 @@ static const struct sdhci_ops sdhci_st_ops = {
> >  	.set_bus_width = sdhci_set_bus_width,
> >  	.read_l = sdhci_st_readl,
> >  	.reset = sdhci_reset,
> >+	.set_uhs_signaling = sdhci_st_set_uhs_signaling,
> >  };
> >  static const struct sdhci_pltfm_data sdhci_st_pdata = {
> 
> Other than that, you can add my:
> Acked-by: Maxime Coquelin <maxime.coquelin@st.com>

Thanks, regards,

Peter.

Re: [PATCH v2 8/8] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

[Peter Griffin]

Hi Maxime,

On Tue, 03 Mar 2015, Maxime Coquelin wrote:

> 
> On 02/26/2015 02:10 PM, Peter Griffin wrote:
> >The nodes have been split to allow as much commonality as possible.
> >The stih407 has a silicon bug with eMMC UHS modes (with top regs)
> >and as such doesn't have any of the uhs dt properties.
> >
> >Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> >---
> >  arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++
> >  arch/arm/boot/dts/stih410-b2120.dts   | 10 ++++++++++
> >  arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 ++++++++
> >  3 files changed, 48 insertions(+)
> >
> >
> Maybe you could also add SD/eMMC support to the b2199 too?

Yes ok, I will add support for stih418-b2199 in v3.

> I can test if you don't have the hardware yet.

Yes please, as I don't have any stih418 hardware yet

regards,

Peter.

[PATCH v2 8/8] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

[Peter Griffin]

Hi Maxime,

On Tue, 03 Mar 2015, Maxime Coquelin wrote:

> 
> On 02/26/2015 02:10 PM, Peter Griffin wrote:
> >The nodes have been split to allow as much commonality as possible.
> >The stih407 has a silicon bug with eMMC UHS modes (with top regs)
> >and as such doesn't have any of the uhs dt properties.
> >
> >Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> >---
> >  arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++
> >  arch/arm/boot/dts/stih410-b2120.dts   | 10 ++++++++++
> >  arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 ++++++++
> >  3 files changed, 48 insertions(+)
> >
> >
> Maybe you could also add SD/eMMC support to the b2199 too?

Yes ok, I will add support for stih418-b2199 in v3.

> I can test if you don't have the hardware yet.

Yes please, as I don't have any stih418 hardware yet

regards,

Peter.

Re: [PATCH v2 8/8] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

[Lee Jones]

On Mon, 30 Mar 2015, Peter Griffin wrote:

> Hi Maxime,
> 
> On Tue, 03 Mar 2015, Maxime Coquelin wrote:
> 
> > 
> > On 02/26/2015 02:10 PM, Peter Griffin wrote:
> > >The nodes have been split to allow as much commonality as possible.
> > >The stih407 has a silicon bug with eMMC UHS modes (with top regs)
> > >and as such doesn't have any of the uhs dt properties.
> > >
> > >Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > >---
> > >  arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++
> > >  arch/arm/boot/dts/stih410-b2120.dts   | 10 ++++++++++
> > >  arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 ++++++++
> > >  3 files changed, 48 insertions(+)
> > >
> > >
> > Maybe you could also add SD/eMMC support to the b2199 too?
> 
> Yes ok, I will add support for stih418-b2199 in v3.

Is there any reason why this can't be actioned in a subsequent patch?

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

[PATCH v2 8/8] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

[Lee Jones]

On Mon, 30 Mar 2015, Peter Griffin wrote:

> Hi Maxime,
> 
> On Tue, 03 Mar 2015, Maxime Coquelin wrote:
> 
> > 
> > On 02/26/2015 02:10 PM, Peter Griffin wrote:
> > >The nodes have been split to allow as much commonality as possible.
> > >The stih407 has a silicon bug with eMMC UHS modes (with top regs)
> > >and as such doesn't have any of the uhs dt properties.
> > >
> > >Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> > >---
> > >  arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++
> > >  arch/arm/boot/dts/stih410-b2120.dts   | 10 ++++++++++
> > >  arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 ++++++++
> > >  3 files changed, 48 insertions(+)
> > >
> > >
> > Maybe you could also add SD/eMMC support to the b2199 too?
> 
> Yes ok, I will add support for stih418-b2199 in v3.

Is there any reason why this can't be actioned in a subsequent patch?

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

Re: [PATCH v2 8/8] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

[Maxime Coquelin]

On 03/30/2015 01:37 PM, Lee Jones wrote:
> On Mon, 30 Mar 2015, Peter Griffin wrote:
>
>> Hi Maxime,
>>
>> On Tue, 03 Mar 2015, Maxime Coquelin wrote:
>>
>>> On 02/26/2015 02:10 PM, Peter Griffin wrote:
>>>> The nodes have been split to allow as much commonality as possible.
>>>> The stih407 has a silicon bug with eMMC UHS modes (with top regs)
>>>> and as such doesn't have any of the uhs dt properties.
>>>>
>>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>>> ---
>>>>   arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++
>>>>   arch/arm/boot/dts/stih410-b2120.dts   | 10 ++++++++++
>>>>   arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 ++++++++
>>>>   3 files changed, 48 insertions(+)
>>>>
>>>>
>>> Maybe you could also add SD/eMMC support to the b2199 too?
>> Yes ok, I will add support for stih418-b2199 in v3.
> Is there any reason why this can't be actioned in a subsequent patch?
>
It could. But since the series needs a v3, it makes sense to do the 
change now.

Re: [PATCH v2 8/8] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

[Maxime Coquelin]

On 03/30/2015 01:37 PM, Lee Jones wrote:
> On Mon, 30 Mar 2015, Peter Griffin wrote:
>
>> Hi Maxime,
>>
>> On Tue, 03 Mar 2015, Maxime Coquelin wrote:
>>
>>> On 02/26/2015 02:10 PM, Peter Griffin wrote:
>>>> The nodes have been split to allow as much commonality as possible.
>>>> The stih407 has a silicon bug with eMMC UHS modes (with top regs)
>>>> and as such doesn't have any of the uhs dt properties.
>>>>
>>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>>> ---
>>>>   arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++
>>>>   arch/arm/boot/dts/stih410-b2120.dts   | 10 ++++++++++
>>>>   arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 ++++++++
>>>>   3 files changed, 48 insertions(+)
>>>>
>>>>
>>> Maybe you could also add SD/eMMC support to the b2199 too?
>> Yes ok, I will add support for stih418-b2199 in v3.
> Is there any reason why this can't be actioned in a subsequent patch?
>
It could. But since the series needs a v3, it makes sense to do the 
change now.

[PATCH v2 8/8] ARM: STi: DT: STiH407: Add dt nodes for sdhci and emmc.

[Maxime Coquelin]

On 03/30/2015 01:37 PM, Lee Jones wrote:
> On Mon, 30 Mar 2015, Peter Griffin wrote:
>
>> Hi Maxime,
>>
>> On Tue, 03 Mar 2015, Maxime Coquelin wrote:
>>
>>> On 02/26/2015 02:10 PM, Peter Griffin wrote:
>>>> The nodes have been split to allow as much commonality as possible.
>>>> The stih407 has a silicon bug with eMMC UHS modes (with top regs)
>>>> and as such doesn't have any of the uhs dt properties.
>>>>
>>>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>>>> ---
>>>>   arch/arm/boot/dts/stih407-family.dtsi | 30 ++++++++++++++++++++++++++++++
>>>>   arch/arm/boot/dts/stih410-b2120.dts   | 10 ++++++++++
>>>>   arch/arm/boot/dts/stihxxx-b2120.dtsi  |  8 ++++++++
>>>>   3 files changed, 48 insertions(+)
>>>>
>>>>
>>> Maybe you could also add SD/eMMC support to the b2199 too?
>> Yes ok, I will add support for stih418-b2199 in v3.
> Is there any reason why this can't be actioned in a subsequent patch?
>
It could. But since the series needs a v3, it makes sense to do the 
change now.