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From: Paolo Bonzini <pbonzini@redhat.com>
To: Nadav Amit <namit@cs.technion.ac.il>
Cc: kvm@vger.kernel.org
Subject: Re: [PATCH v2 1/4] KVM: x86: INIT and reset sequences are different
Date: Tue, 07 Apr 2015 15:23:11 +0200	[thread overview]
Message-ID: <5523DA3F.5070006@redhat.com> (raw)
In-Reply-To: <1427933438-12782-2-git-send-email-namit@cs.technion.ac.il>



On 02/04/2015 02:10, Nadav Amit wrote:
> x86 architecture defines differences between the reset and INIT sequences.
> INIT does not initialize the FPU (including MMX, XMM, YMM, etc.), TSC, PMU,
> MSRs (in general), MTRRs machine-check, APIC ID, APIC arbitration ID and BSP.
> 
> EFER is supposed NOT to be reset according to the SDM, but leaving the LMA and
> LME untouched causes failed VM-entry.  Therefore we reset EFER (although it is
> unclear whether the rest of EFER bits should be reset).

Do you get failed VM-entry even if LME=1, LMA=0?  LMA obviously should
be reset, but LME=1/PG=0/PAE=0 is shown as valid in Figure 4-1 of the SDM.

Paolo

  parent reply	other threads:[~2015-04-07 13:23 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-02  0:10 [PATCH v2 0/4] KVM: x86: Reset fixes Nadav Amit
2015-04-02  0:10 ` [PATCH v2 1/4] KVM: x86: INIT and reset sequences are different Nadav Amit
2015-04-02  2:17   ` Bandan Das
2015-04-07 13:23     ` Paolo Bonzini
2015-04-07 16:17       ` Bandan Das
2015-04-07 16:22         ` Paolo Bonzini
2015-04-07 16:35           ` Bandan Das
2015-04-07 13:23   ` Paolo Bonzini [this message]
2015-04-07 13:57   ` Paolo Bonzini
2015-04-02  0:10 ` [PATCH v2 2/4] KVM: x86: BSP in MSR_IA32_APICBASE is writable Nadav Amit
2015-04-02  0:10 ` [PATCH v2 3/4] KVM: x86: DR0-DR3 are not clear on reset Nadav Amit
2015-04-02  0:10 ` [PATCH v2 4/4] KVM: x86: Clear CR2 on VCPU reset Nadav Amit
2015-04-14 10:03   ` Wanpeng Li
2015-04-14 10:31     ` Nadav Amit
2015-04-07 14:01 ` [PATCH v2 0/4] KVM: x86: Reset fixes Paolo Bonzini

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