[U-Boot] [PATCH v5 0/2] i2c: sunxi: Support every i2c controller on each supported platform

[U-Boot] [PATCH v5 0/2] i2c: sunxi: Support every i2c controller on each supported platform

[Paul Kocialkowski]

Changes since v4:
* Got rid of Kconfig after all
* Only build mvtwsi when at least one controller is enabled on sunxi
* Controller 0 doesn't have to be enabled in particular

Changes since v3:
* Kconfig support for MVTWSI
* Only enable twsi0 by default for platforms that always use it for the AXP
* Remove enabling other I2C busses by default on boards that expose them on pin
  headers since those might be used for some other functionalities

Changes since v2:
* I2C/TWI busses enable for Cubietruck as well

Changes since v1:
* Kconfig option to enable I2C/TWI controllers 1-4 (when applicable)
* Following patch to enable exposed busses on a few community-supported
  single-board-computers

This series adds support for every i2c controller found on
sun4i/sun5i/sun6i/sun7i/sun8i platforms and shouldn't break support for Marvell
platforms (orion5x, kirkwood, armada xp) the driver was originally written for.

Regarding sunxi, I double-checked that this doesn't conflict with
VIDEO_LCD_PANEL_I2C.

I would be interested in having this tested on sun8i (A23), since I changed TWI0
muxing (to PH2-PH3 instead of PB0-PB1), according to the user manual and what
is being done on the upstream Linux kernel. I2C was either not working before,
or it was being muxed correctly by the bootrom, probably to communicate with the
AXP, which luckily made it work in U-Boot too, since the I/O base address was
already correct.

My use case here is that I'm writing a slave-side bitbang i2c implementation
(with an Arduino) for a school project, using a Cubieboard2 as master and
U-Boot as POC. However, only TWI1 was available through the expansion pins,
hence the need for this series.

[U-Boot] [PATCH v5 1/2] i2c: mvtwsi: Support for up to 4 different controllers

[Paul Kocialkowski]

Orion5x, Kirkwood and Armada XP platforms come with a single TWSI (I2C) MVTWSI
controller. However, other platforms using MVTWSI may come with more: this is
the case on Allwinner (sunxi) platforms, where up to 4 controllers can be found
on the same chip.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 arch/arm/include/asm/arch-sunxi/i2c.h        |   2 +-
 arch/arm/mach-kirkwood/include/mach/config.h |   2 +-
 drivers/i2c/mvtwsi.c                         | 128 +++++++++++++++++++++------
 include/configs/db-mv784mp-gp.h              |   2 +-
 include/configs/edminiv2.h                   |   2 +-
 include/configs/maxbcm.h                     |   2 +-
 6 files changed, 104 insertions(+), 34 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index dc5406b..502e3c6 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -8,7 +8,7 @@
 
 #include <asm/arch/cpu.h>
 
-#define CONFIG_I2C_MVTWSI_BASE	SUNXI_TWI0_BASE
+#define CONFIG_I2C_MVTWSI_BASE0	SUNXI_TWI0_BASE
 /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
 #define CONFIG_SYS_TCLK		24000000
 
diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h
index e77ac40..d049395 100644
--- a/arch/arm/mach-kirkwood/include/mach/config.h
+++ b/arch/arm/mach-kirkwood/include/mach/config.h
@@ -44,7 +44,7 @@
 #define CONFIG_SYS_INIT_SP_ADDR		0xC8012000
 #define CONFIG_NR_DRAM_BANKS_MAX	2
 
-#define CONFIG_I2C_MVTWSI_BASE	KW_TWSI_BASE
+#define CONFIG_I2C_MVTWSI_BASE0	KW_TWSI_BASE
 #define MV_UART_CONSOLE_BASE	KW_UART0_BASE
 #define MV_SATA_BASE		KW_SATA_BASE
 #define MV_SATA_PORT0_OFFSET	KW_SATA_PORT0_OFFSET
diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c
index 6f6edd5..f20d1b2 100644
--- a/drivers/i2c/mvtwsi.c
+++ b/drivers/i2c/mvtwsi.c
@@ -14,7 +14,7 @@
 #include <asm/io.h>
 
 /*
- * include a file that will provide CONFIG_I2C_MVTWSI_BASE
+ * include a file that will provide CONFIG_I2C_MVTWSI_BASE*
  * and possibly other settings
  */
 
@@ -91,11 +91,39 @@ struct  mvtwsi_registers {
 #define	MVTWSI_STATUS_IDLE		0xF8
 
 /*
- * The single instance of the controller we'll be dealing with
+ * MVTWSI controller base
  */
 
-static struct  mvtwsi_registers *twsi =
-	(struct  mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE;
+static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
+{
+	switch (adap->hwadapnr) {
+#ifdef CONFIG_I2C_MVTWSI_BASE0
+	case 0:
+		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE0;
+#endif
+#ifdef CONFIG_I2C_MVTWSI_BASE1
+	case 1:
+		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE1;
+#endif
+#ifdef CONFIG_I2C_MVTWSI_BASE2
+	case 2:
+		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE2;
+#endif
+#ifdef CONFIG_I2C_MVTWSI_BASE3
+	case 3:
+		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE3;
+#endif
+#ifdef CONFIG_I2C_MVTWSI_BASE4
+	case 4:
+		return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4;
+#endif
+	default:
+		printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
+		break;
+	}
+
+	return NULL;
+}
 
 /*
  * Returned statuses are 0 for success and nonzero otherwise.
@@ -117,8 +145,9 @@ static struct  mvtwsi_registers *twsi =
  * Wait for IFLG to raise, or return 'timeout'; then if status is as expected,
  * return 0 (ok) or return 'wrong status'.
  */
-static int twsi_wait(int expected_status)
+static int twsi_wait(struct i2c_adapter *adap, int expected_status)
 {
+	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	int control, status;
 	int timeout = 1000;
 
@@ -153,35 +182,40 @@ static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
  * Assert the START condition, either in a single I2C transaction
  * or inside back-to-back ones (repeated starts).
  */
-static int twsi_start(int expected_status)
+static int twsi_start(struct i2c_adapter *adap, int expected_status)
 {
+	struct mvtwsi_registers *twsi = twsi_get_base(adap);
+
 	/* globally set TWSIEN in case it was not */
 	twsi_control_flags |= MVTWSI_CONTROL_TWSIEN;
 	/* assert START */
 	writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control);
 	/* wait for controller to process START */
-	return twsi_wait(expected_status);
+	return twsi_wait(adap, expected_status);
 }
 
 /*
  * Send a byte (i2c address or data).
  */
-static int twsi_send(u8 byte, int expected_status)
+static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status)
 {
+	struct mvtwsi_registers *twsi = twsi_get_base(adap);
+
 	/* put byte in data register for sending */
 	writel(byte, &twsi->data);
 	/* clear any pending interrupt -- that'll cause sending */
 	writel(twsi_control_flags, &twsi->control);
 	/* wait for controller to receive byte and check ACK */
-	return twsi_wait(expected_status);
+	return twsi_wait(adap, expected_status);
 }
 
 /*
  * Receive a byte.
  * Global mvtwsi_control_flags variable says if we should ack or nak.
  */
-static int twsi_recv(u8 *byte)
+static int twsi_recv(struct i2c_adapter *adap, u8 *byte)
 {
+	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	int expected_status, status;
 
 	/* compute expected status based on ACK bit in global control flags */
@@ -192,7 +226,7 @@ static int twsi_recv(u8 *byte)
 	/* acknowledge *previous state* and launch receive */
 	writel(twsi_control_flags, &twsi->control);
 	/* wait for controller to receive byte and assert ACK or NAK */
-	status = twsi_wait(expected_status);
+	status = twsi_wait(adap, expected_status);
 	/* if we did receive expected byte then store it */
 	if (status == 0)
 		*byte = readl(&twsi->data);
@@ -204,8 +238,9 @@ static int twsi_recv(u8 *byte)
  * Assert the STOP condition.
  * This is also used to force the bus back in idle (SDA=SCL=1).
  */
-static int twsi_stop(int status)
+static int twsi_stop(struct i2c_adapter *adap, int status)
 {
+	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	int control, stop_status;
 	int timeout = 1000;
 
@@ -244,6 +279,7 @@ static unsigned int twsi_calc_freq(const int n, const int m)
  */
 static void twsi_reset(struct i2c_adapter *adap)
 {
+	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	/* ensure controller will be enabled by any twsi*() function */
 	twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
 	/* reset controller */
@@ -259,6 +295,7 @@ static void twsi_reset(struct i2c_adapter *adap)
 static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
 					   unsigned int requested_speed)
 {
+	struct mvtwsi_registers *twsi = twsi_get_base(adap);
 	unsigned int tmp_speed, highest_speed, n, m;
 	unsigned int baud = 0x44; /* baudrate at controller reset */
 
@@ -281,6 +318,8 @@ static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
 
 static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 {
+	struct mvtwsi_registers *twsi = twsi_get_base(adap);
+
 	/* reset controller */
 	twsi_reset(adap);
 	/* set speed */
@@ -289,7 +328,7 @@ static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
 	writel(slaveadd, &twsi->slave_address);
 	writel(0, &twsi->xtnd_slave_addr);
 	/* assert STOP but don't care for the result */
-	(void) twsi_stop(0);
+	(void) twsi_stop(adap, 0);
 }
 
 /*
@@ -297,7 +336,8 @@ static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
  * Common to i2c_probe, i2c_read and i2c_write.
  * Expected address status will derive from direction bit (bit 0) in addr.
  */
-static int i2c_begin(int expected_start_status, u8 addr)
+static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
+		     u8 addr)
 {
 	int status, expected_addr_status;
 
@@ -307,10 +347,10 @@ static int i2c_begin(int expected_start_status, u8 addr)
 	else /* writing */
 		expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
 	/* assert START */
-	status = twsi_start(expected_start_status);
+	status = twsi_start(adap, expected_start_status);
 	/* send out the address if the start went well */
 	if (status == 0)
-		status = twsi_send(addr, expected_addr_status);
+		status = twsi_send(adap, addr, expected_addr_status);
 	/* return ok or status of first failure to caller */
 	return status;
 }
@@ -325,12 +365,12 @@ static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
 	int status;
 
 	/* begin i2c read */
-	status = i2c_begin(MVTWSI_STATUS_START, (chip << 1) | 1);
+	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1);
 	/* dummy read was accepted: receive byte but NAK it. */
 	if (status == 0)
-		status = twsi_recv(&dummy_byte);
+		status = twsi_recv(adap, &dummy_byte);
 	/* Stop transaction */
-	twsi_stop(0);
+	twsi_stop(adap, 0);
 	/* return 0 or status of first failure */
 	return status;
 }
@@ -351,15 +391,15 @@ static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 	int status;
 
 	/* begin i2c write to send the address bytes */
-	status = i2c_begin(MVTWSI_STATUS_START, (chip << 1));
+	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
 	/* send addr bytes */
 	while ((status == 0) && alen--)
-		status = twsi_send(addr >> (8*alen),
+		status = twsi_send(adap, addr >> (8*alen),
 			MVTWSI_STATUS_DATA_W_ACK);
 	/* begin i2c read to receive eeprom data bytes */
 	if (status == 0)
-		status = i2c_begin(
-			MVTWSI_STATUS_REPEATED_START, (chip << 1) | 1);
+		status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
+				   (chip << 1) | 1);
 	/* prepare ACK if@least one byte must be received */
 	if (length > 0)
 		twsi_control_flags |= MVTWSI_CONTROL_ACK;
@@ -369,10 +409,10 @@ static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
 		if (length == 0)
 			twsi_control_flags &= ~MVTWSI_CONTROL_ACK;
 		/* read current byte */
-		status = twsi_recv(data++);
+		status = twsi_recv(adap, data++);
 	}
 	/* Stop transaction */
-	status = twsi_stop(status);
+	status = twsi_stop(adap, status);
 	/* return 0 or status of first failure */
 	return status;
 }
@@ -387,21 +427,51 @@ static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
 	int status;
 
 	/* begin i2c write to send the eeprom adress bytes then data bytes */
-	status = i2c_begin(MVTWSI_STATUS_START, (chip << 1));
+	status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
 	/* send addr bytes */
 	while ((status == 0) && alen--)
-		status = twsi_send(addr >> (8*alen),
+		status = twsi_send(adap, addr >> (8*alen),
 			MVTWSI_STATUS_DATA_W_ACK);
 	/* send data bytes */
 	while ((status == 0) && (length-- > 0))
-		status = twsi_send(*(data++), MVTWSI_STATUS_DATA_W_ACK);
+		status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK);
 	/* Stop transaction */
-	status = twsi_stop(status);
+	status = twsi_stop(adap, status);
 	/* return 0 or status of first failure */
 	return status;
 }
 
+#ifdef CONFIG_I2C_MVTWSI_BASE0
 U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
 			 twsi_i2c_read, twsi_i2c_write,
 			 twsi_i2c_set_bus_speed,
 			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
+#endif
+#ifdef CONFIG_I2C_MVTWSI_BASE1
+U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
+			 twsi_i2c_read, twsi_i2c_write,
+			 twsi_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
+
+#endif
+#ifdef CONFIG_I2C_MVTWSI_BASE2
+U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
+			 twsi_i2c_read, twsi_i2c_write,
+			 twsi_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
+
+#endif
+#ifdef CONFIG_I2C_MVTWSI_BASE3
+U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
+			 twsi_i2c_read, twsi_i2c_write,
+			 twsi_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
+
+#endif
+#ifdef CONFIG_I2C_MVTWSI_BASE4
+U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
+			 twsi_i2c_read, twsi_i2c_write,
+			 twsi_i2c_set_bus_speed,
+			 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
+
+#endif
diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h
index 1683a15..4dd7b11 100644
--- a/include/configs/db-mv784mp-gp.h
+++ b/include/configs/db-mv784mp-gp.h
@@ -37,7 +37,7 @@
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MVTWSI
-#define CONFIG_I2C_MVTWSI_BASE		MVEBU_TWSI_BASE
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
 #define CONFIG_SYS_I2C_SLAVE		0x0
 #define CONFIG_SYS_I2C_SPEED		100000
 
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index 5ce01fb..bd08740 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -208,7 +208,7 @@
 #ifdef CONFIG_CMD_I2C
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MVTWSI
-#define CONFIG_I2C_MVTWSI_BASE		ORION5X_TWSI_BASE
+#define CONFIG_I2C_MVTWSI_BASE0		ORION5X_TWSI_BASE
 #define CONFIG_SYS_I2C_SLAVE		0x0
 #define CONFIG_SYS_I2C_SPEED		100000
 #endif
diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h
index 5999d60..e909623 100644
--- a/include/configs/maxbcm.h
+++ b/include/configs/maxbcm.h
@@ -35,7 +35,7 @@
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MVTWSI
-#define CONFIG_I2C_MVTWSI_BASE		MVEBU_TWSI_BASE
+#define CONFIG_I2C_MVTWSI_BASE0		MVEBU_TWSI_BASE
 #define CONFIG_SYS_I2C_SLAVE		0x0
 #define CONFIG_SYS_I2C_SPEED		100000
 
-- 
1.9.1

[U-Boot] [PATCH v5 2/2] sunxi: Complete i2c support for each supported platform

[Paul Kocialkowski]

Sunxi platforms come with at least 3 TWI (I2C) controllers and some platforms
even have up to 5. This adds support for every controller on each supported
platform, which is especially useful when using expansion ports on single-board-
computers.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
 arch/arm/include/asm/arch-sunxi/cpu_sun4i.h |  7 +++
 arch/arm/include/asm/arch-sunxi/gpio.h      | 15 +++++-
 arch/arm/include/asm/arch-sunxi/i2c.h       | 15 ++++++
 board/sunxi/Kconfig                         | 38 ++++++++++++++
 board/sunxi/board.c                         | 77 ++++++++++++++++++++++++++++-
 include/configs/sunxi-common.h              |  4 ++
 6 files changed, 153 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
index dae6069..f403742 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
@@ -94,6 +94,13 @@
 #define SUNXI_TWI0_BASE			0x01c2ac00
 #define SUNXI_TWI1_BASE			0x01c2b000
 #define SUNXI_TWI2_BASE			0x01c2b400
+#ifdef CONFIG_MACH_SUN6I
+#define SUNXI_TWI3_BASE			0x01c0b800
+#endif
+#ifdef CONFIG_MACH_SUN7I
+#define SUNXI_TWI3_BASE			0x01c2b800
+#define SUNXI_TWI4_BASE			0x01c2c000
+#endif
 
 #define SUNXI_CAN_BASE			0x01c2bc00
 
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index f227044..ae7cbb7 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -148,7 +148,11 @@ enum sunxi_gpio_number {
 #define SUN6I_GPA_SDC2		5
 #define SUN6I_GPA_SDC3		4
 
-#define SUNXI_GPB_TWI0		2
+#define SUN4I_GPB_TWI0		2
+#define SUN4I_GPB_TWI1		2
+#define SUN5I_GPB_TWI1		2
+#define SUN4I_GPB_TWI2		2
+#define SUN5I_GPB_TWI2		2
 #define SUN4I_GPB_UART0		2
 #define SUN5I_GPB_UART0		2
 
@@ -160,6 +164,7 @@ enum sunxi_gpio_number {
 #define SUNXI_GPD_LVDS0		3
 
 #define SUN5I_GPE_SDC2		3
+#define SUN8I_GPE_TWI2		3
 
 #define SUNXI_GPF_SDC0		2
 #define SUNXI_GPF_UART0		4
@@ -169,12 +174,20 @@ enum sunxi_gpio_number {
 #define SUN5I_GPG_SDC1		2
 #define SUN6I_GPG_SDC1		2
 #define SUN8I_GPG_SDC1		2
+#define SUN6I_GPG_TWI3		2
 #define SUN5I_GPG_UART1		4
 
 #define SUN4I_GPH_SDC1		5
+#define SUN6I_GPH_TWI0		2
+#define SUN8I_GPH_TWI0		2
+#define SUN6I_GPH_TWI1		2
+#define SUN8I_GPH_TWI1		2
+#define SUN6I_GPH_TWI2		2
 #define SUN6I_GPH_UART0		2
 
 #define SUNXI_GPI_SDC3		2
+#define SUN7I_GPI_TWI3		3
+#define SUN7I_GPI_TWI4		3
 
 #define SUN6I_GPL0_R_P2WI_SCK	3
 #define SUN6I_GPL1_R_P2WI_SDA	3
diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h
index 502e3c6..561cd2b 100644
--- a/arch/arm/include/asm/arch-sunxi/i2c.h
+++ b/arch/arm/include/asm/arch-sunxi/i2c.h
@@ -8,7 +8,22 @@
 
 #include <asm/arch/cpu.h>
 
+#ifdef CONFIG_I2C0_ENABLE
 #define CONFIG_I2C_MVTWSI_BASE0	SUNXI_TWI0_BASE
+#endif
+#ifdef CONFIG_I2C1_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE1	SUNXI_TWI1_BASE
+#endif
+#ifdef CONFIG_I2C2_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE2	SUNXI_TWI2_BASE
+#endif
+#ifdef CONFIG_I2C3_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE3	SUNXI_TWI3_BASE
+#endif
+#ifdef CONFIG_I2C4_ENABLE
+#define CONFIG_I2C_MVTWSI_BASE4	SUNXI_TWI4_BASE
+#endif
+
 /* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
 #define CONFIG_SYS_TCLK		24000000
 
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index ccc2080..88e3358 100644
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -269,6 +269,44 @@ config USB2_VBUS_PIN
 	---help---
 	See USB1_VBUS_PIN help text.
 
+config I2C0_ENABLE
+	bool "Enable I2C/TWI controller 0"
+	default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+	default n if MACH_SUN6I || MACH_SUN8I
+	---help---
+	This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
+	its clock and setting up the bus. This is especially useful on devices
+	with slaves connected to the bus or with pins exposed through e.g. an
+	expansion port/header.
+
+config I2C1_ENABLE
+	bool "Enable I2C/TWI controller 1"
+	default n
+	---help---
+	See I2C0_ENABLE help text.
+
+config I2C2_ENABLE
+	bool "Enable I2C/TWI controller 2"
+	default n
+	---help---
+	See I2C0_ENABLE help text.
+
+if MACH_SUN6I || MACH_SUN7I
+config I2C3_ENABLE
+	bool "Enable I2C/TWI controller 3"
+	default n
+	---help---
+	See I2C0_ENABLE help text.
+endif
+
+if MACH_SUN7I
+config I2C4_ENABLE
+	bool "Enable I2C/TWI controller 4"
+	default n
+	---help---
+	See I2C0_ENABLE help text.
+endif
+
 config VIDEO
 	boolean "Enable graphical uboot console on HDMI, LCD or VGA"
 	default y
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 986261a..1034c1b 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -276,9 +276,82 @@ int board_mmc_init(bd_t *bis)
 
 void i2c_init_board(void)
 {
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB_TWI0);
-	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB_TWI0);
+#ifdef CONFIG_I2C0_ENABLE
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
 	clock_twi_onoff(0, 1);
+#elif defined(CONFIG_MACH_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
+	clock_twi_onoff(0, 1);
+#elif defined(CONFIG_MACH_SUN8I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
+	clock_twi_onoff(0, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C1_ENABLE
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
+	clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN5I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
+	clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
+	clock_twi_onoff(1, 1);
+#elif defined(CONFIG_MACH_SUN8I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
+	clock_twi_onoff(1, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C2_ENABLE
+#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
+	clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN5I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
+	clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
+	clock_twi_onoff(2, 1);
+#elif defined(CONFIG_MACH_SUN8I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
+	sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
+	clock_twi_onoff(2, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C3_ENABLE
+#if defined(CONFIG_MACH_SUN6I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
+	sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
+	clock_twi_onoff(3, 1);
+#elif defined(CONFIG_MACH_SUN7I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
+	sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
+	clock_twi_onoff(3, 1);
+#endif
+#endif
+
+#ifdef CONFIG_I2C4_ENABLE
+#if defined(CONFIG_MACH_SUN7I)
+	sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
+	sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
+	clock_twi_onoff(4, 1);
+#endif
+#endif
+
 #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
 	soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
 	soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index b9bb971..ad7b760 100644
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -197,7 +197,11 @@
 #endif
 
 #define CONFIG_SYS_I2C
+#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \
+    defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \
+    defined CONFIG_I2C4_ENABLE
 #define CONFIG_SYS_I2C_MVTWSI
+#endif
 #define CONFIG_SYS_I2C_SPEED		400000
 #define CONFIG_SYS_I2C_SLAVE		0x7f
 
-- 
1.9.1

[U-Boot] [PATCH v5 0/2] i2c: sunxi: Support every i2c controller on each supported platform

[Paul Kocialkowski]

This version is ready for merging by the way.

I didn't use Kconfig after all, since all the Marvell boards are
including this through config.h and I didn't feel like moving it all to
Kconfig. Moreover, this doesn't use DM and apparently, only I2C drivers
that use DM are in Kconfig now.

Also, I don't think it makes sense to make twsi0 more privileged than
the other controllers. Users might just need to enable, say, controller
1, without enabling controller 0 on sunxi.

Le vendredi 10 avril 2015 ? 23:09 +0200, Paul Kocialkowski a ?crit :
> Changes since v4:
> * Got rid of Kconfig after all
> * Only build mvtwsi when at least one controller is enabled on sunxi
> * Controller 0 doesn't have to be enabled in particular
> 
> Changes since v3:
> * Kconfig support for MVTWSI
> * Only enable twsi0 by default for platforms that always use it for the AXP
> * Remove enabling other I2C busses by default on boards that expose them on pin
>   headers since those might be used for some other functionalities
> 
> Changes since v2:
> * I2C/TWI busses enable for Cubietruck as well
> 
> Changes since v1:
> * Kconfig option to enable I2C/TWI controllers 1-4 (when applicable)
> * Following patch to enable exposed busses on a few community-supported
>   single-board-computers
> 
> This series adds support for every i2c controller found on
> sun4i/sun5i/sun6i/sun7i/sun8i platforms and shouldn't break support for Marvell
> platforms (orion5x, kirkwood, armada xp) the driver was originally written for.
> 
> Regarding sunxi, I double-checked that this doesn't conflict with
> VIDEO_LCD_PANEL_I2C.
> 
> I would be interested in having this tested on sun8i (A23), since I changed TWI0
> muxing (to PH2-PH3 instead of PB0-PB1), according to the user manual and what
> is being done on the upstream Linux kernel. I2C was either not working before,
> or it was being muxed correctly by the bootrom, probably to communicate with the
> AXP, which luckily made it work in U-Boot too, since the I/O base address was
> already correct.
> 
> My use case here is that I'm writing a slave-side bitbang i2c implementation
> (with an Arduino) for a school project, using a Cubieboard2 as master and
> U-Boot as POC. However, only TWI1 was available through the expansion pins,
> hence the need for this series.

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[U-Boot] [PATCH v5 0/2] i2c: sunxi: Support every i2c controller on each supported platform

[Hans de Goede]

Hi,

On 10-04-15 23:09, Paul Kocialkowski wrote:
> Changes since v4:
> * Got rid of Kconfig after all
> * Only build mvtwsi when at least one controller is enabled on sunxi
> * Controller 0 doesn't have to be enabled in particular
>
> Changes since v3:
> * Kconfig support for MVTWSI
> * Only enable twsi0 by default for platforms that always use it for the AXP
> * Remove enabling other I2C busses by default on boards that expose them on pin
>    headers since those might be used for some other functionalities
>
> Changes since v2:
> * I2C/TWI busses enable for Cubietruck as well
>
> Changes since v1:
> * Kconfig option to enable I2C/TWI controllers 1-4 (when applicable)
> * Following patch to enable exposed busses on a few community-supported
>    single-board-computers
>
> This series adds support for every i2c controller found on
> sun4i/sun5i/sun6i/sun7i/sun8i platforms and shouldn't break support for Marvell
> platforms (orion5x, kirkwood, armada xp) the driver was originally written for.
>
> Regarding sunxi, I double-checked that this doesn't conflict with
> VIDEO_LCD_PANEL_I2C.
>
> I would be interested in having this tested on sun8i (A23), since I changed TWI0
> muxing (to PH2-PH3 instead of PB0-PB1), according to the user manual and what
> is being done on the upstream Linux kernel. I2C was either not working before,
> or it was being muxed correctly by the bootrom, probably to communicate with the
> AXP, which luckily made it work in U-Boot too, since the I/O base address was
> already correct.
>
> My use case here is that I'm writing a slave-side bitbang i2c implementation
> (with an Arduino) for a school project, using a Cubieboard2 as master and
> U-Boot as POC. However, only TWI1 was available through the expansion pins,
> hence the need for this series.
>

Thanks, merged into u-boot-sunxi/next with Heiko's ack for the first patch,

Regards,

Hans