* [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu
@ 2015-04-23 22:57 minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 01/17] Add a base IPMI interface minyard
` (17 more replies)
0 siblings, 18 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel
The major changes from last time are:
* Don't use callbacks for adding firmware tables, provide binary
blobs instead.
* Add the SSDT as a separate table.
* Modify the BIOS tests to test for the IPMI tables.
-corey
^ permalink raw reply [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 01/17] Add a base IPMI interface
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
@ 2015-04-23 22:57 ` minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure minyard
` (16 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
Add the basic IPMI types and infrastructure to QEMU. Low-level
interfaces and simulation interfaces will register with this; it's
kind of the go-between to tie them together.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/Makefile.objs | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi.c | 135 +++++++++++++++++++++++
hw/ipmi/ipmi.h | 215 +++++++++++++++++++++++++++++++++++++
qemu-doc.texi | 2 +
7 files changed, 356 insertions(+)
create mode 100644 hw/ipmi/Makefile.objs
create mode 100644 hw/ipmi/ipmi.c
create mode 100644 hw/ipmi/ipmi.h
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 6a74e00..ab1a552 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -8,6 +8,7 @@ CONFIG_VGA_ISA=y
CONFIG_VGA_CIRRUS=y
CONFIG_VMWARE_VGA=y
CONFIG_VMMOUSE=y
+CONFIG_IPMI=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 46b87dd..82bafcc 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -8,6 +8,7 @@ CONFIG_VGA_ISA=y
CONFIG_VGA_CIRRUS=y
CONFIG_VMWARE_VGA=y
CONFIG_VMMOUSE=y
+CONFIG_IPMI=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/hw/Makefile.objs b/hw/Makefile.objs
index 73afa41..ba021b8 100644
--- a/hw/Makefile.objs
+++ b/hw/Makefile.objs
@@ -13,6 +13,7 @@ devices-dirs-$(CONFIG_SOFTMMU) += ide/
devices-dirs-$(CONFIG_SOFTMMU) += input/
devices-dirs-$(CONFIG_SOFTMMU) += intc/
devices-dirs-$(CONFIG_IPACK) += ipack/
+devices-dirs-$(CONFIG_SOFTMMU) += ipmi/
devices-dirs-$(CONFIG_SOFTMMU) += isa/
devices-dirs-$(CONFIG_SOFTMMU) += misc/
devices-dirs-$(CONFIG_SOFTMMU) += net/
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
new file mode 100644
index 0000000..65bde11
--- /dev/null
+++ b/hw/ipmi/Makefile.objs
@@ -0,0 +1 @@
+common-obj-$(CONFIG_IPMI) += ipmi.o
diff --git a/hw/ipmi/ipmi.c b/hw/ipmi/ipmi.c
new file mode 100644
index 0000000..b046517
--- /dev/null
+++ b/hw/ipmi/ipmi.c
@@ -0,0 +1,135 @@
+/*
+ * QEMU IPMI emulation
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "hw/hw.h"
+#include "ipmi.h"
+#include "sysemu/sysemu.h"
+#include "qmp-commands.h"
+
+static int ipmi_do_hw_op(IPMIInterface *s, enum ipmi_op op, int checkonly)
+{
+ switch (op) {
+ case IPMI_RESET_CHASSIS:
+ if (checkonly) {
+ return 0;
+ }
+ qemu_system_reset_request();
+ return 0;
+
+ case IPMI_POWEROFF_CHASSIS:
+ if (checkonly) {
+ return 0;
+ }
+ qemu_system_powerdown_request();
+ return 0;
+
+ case IPMI_SEND_NMI:
+ if (checkonly) {
+ return 0;
+ }
+ qemu_mutex_lock_iothread();
+ qmp_inject_nmi(NULL);
+ qemu_mutex_unlock_iothread();
+ return 0;
+
+ case IPMI_POWERCYCLE_CHASSIS:
+ case IPMI_PULSE_DIAG_IRQ:
+ case IPMI_SHUTDOWN_VIA_ACPI_OVERTEMP:
+ case IPMI_POWERON_CHASSIS:
+ default:
+ return IPMI_CC_COMMAND_NOT_SUPPORTED;
+ }
+}
+
+static void ipmi_set_irq_enable(IPMIInterface *s, int val)
+{
+ s->irqs_enabled = val;
+}
+
+void ipmi_interface_reset(IPMIInterface *s)
+{
+ IPMIBmcClass *bk = IPMI_BMC_GET_CLASS(s->bmc);
+
+ if (bk->handle_reset) {
+ bk->handle_reset(s->bmc);
+ }
+}
+
+void ipmi_interface_init(IPMIInterface *s, Error **errp)
+{
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ if (k->init) {
+ k->init(s, errp);
+ if (*errp) {
+ return;
+ }
+ }
+
+ if (!s->slave_addr) {
+ s->slave_addr = 0x20;
+ }
+}
+
+static void ipmi_interface_class_init(ObjectClass *class, void *data)
+{
+ IPMIInterfaceClass *ik = IPMI_INTERFACE_CLASS(class);
+
+ ik->do_hw_op = ipmi_do_hw_op;
+ ik->set_irq_enable = ipmi_set_irq_enable;
+}
+
+static TypeInfo ipmi_interface_type_info = {
+ .name = TYPE_IPMI_INTERFACE,
+ .parent = TYPE_OBJECT,
+ .instance_size = sizeof(IPMIInterface),
+ .abstract = true,
+ .class_size = sizeof(IPMIInterfaceClass),
+ .class_init = ipmi_interface_class_init,
+};
+
+void ipmi_bmc_init(IPMIBmc *s, Error **errp)
+{
+ IPMIBmcClass *k = IPMI_BMC_GET_CLASS(s);
+
+ if (k->init) {
+ k->init(s, errp);
+ }
+}
+
+static TypeInfo ipmi_bmc_type_info = {
+ .name = TYPE_IPMI_BMC,
+ .parent = TYPE_OBJECT,
+ .instance_size = sizeof(IPMIBmc),
+ .abstract = true,
+ .class_size = sizeof(IPMIBmcClass),
+};
+
+static void ipmi_register_types(void)
+{
+ type_register_static(&ipmi_interface_type_info);
+ type_register_static(&ipmi_bmc_type_info);
+}
+
+type_init(ipmi_register_types)
diff --git a/hw/ipmi/ipmi.h b/hw/ipmi/ipmi.h
new file mode 100644
index 0000000..6b2a3e9
--- /dev/null
+++ b/hw/ipmi/ipmi.h
@@ -0,0 +1,215 @@
+/*
+ * IPMI base class
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef HW_IPMI_H
+#define HW_IPMI_H
+
+#include "exec/memory.h"
+#include "qemu-common.h"
+#include "hw/qdev.h"
+
+#define MAX_IPMI_MSG_SIZE 300
+
+enum ipmi_op {
+ IPMI_RESET_CHASSIS,
+ IPMI_POWEROFF_CHASSIS,
+ IPMI_POWERON_CHASSIS,
+ IPMI_POWERCYCLE_CHASSIS,
+ IPMI_PULSE_DIAG_IRQ,
+ IPMI_SHUTDOWN_VIA_ACPI_OVERTEMP,
+ IPMI_SEND_NMI
+};
+
+#define IPMI_CC_INVALID_CMD 0xc1
+#define IPMI_CC_COMMAND_INVALID_FOR_LUN 0xc2
+#define IPMI_CC_TIMEOUT 0xc3
+#define IPMI_CC_OUT_OF_SPACE 0xc4
+#define IPMI_CC_INVALID_RESERVATION 0xc5
+#define IPMI_CC_REQUEST_DATA_TRUNCATED 0xc6
+#define IPMI_CC_REQUEST_DATA_LENGTH_INVALID 0xc7
+#define IPMI_CC_PARM_OUT_OF_RANGE 0xc9
+#define IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES 0xca
+#define IPMI_CC_REQ_ENTRY_NOT_PRESENT 0xcb
+#define IPMI_CC_INVALID_DATA_FIELD 0xcc
+#define IPMI_CC_BMC_INIT_IN_PROGRESS 0xd2
+#define IPMI_CC_COMMAND_NOT_SUPPORTED 0xd5
+
+#define IPMI_NETFN_APP 0x06
+
+#define IPMI_DEBUG 1
+
+/* Specified in the SMBIOS spec. */
+#define IPMI_SMBIOS_KCS 0x01
+#define IPMI_SMBIOS_SMIC 0x02
+#define IPMI_SMBIOS_BT 0x03
+#define IPMI_SMBIOS_SSIF 0x04
+
+/* IPMI Interface types (KCS, SMIC, BT) are prefixed with this */
+#define TYPE_IPMI_INTERFACE_PREFIX "ipmi-interface-"
+
+typedef struct IPMIBmc IPMIBmc;
+
+/*
+ * An IPMI Interface, the interface for talking between the target
+ * and the BMC.
+ */
+#define TYPE_IPMI_INTERFACE "ipmi-interface"
+#define IPMI_INTERFACE(obj) \
+ OBJECT_CHECK(IPMIInterface, (obj), TYPE_IPMI_INTERFACE)
+#define IPMI_INTERFACE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(IPMIInterfaceClass, (klass), TYPE_IPMI_INTERFACE)
+#define IPMI_INTERFACE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(IPMIInterfaceClass, (obj), TYPE_IPMI_INTERFACE)
+
+typedef struct IPMIInterface {
+ Object parent_obj;
+
+ IPMIBmc *bmc;
+
+ bool do_wake;
+
+ qemu_irq irq;
+
+ unsigned long io_base;
+ unsigned long io_length;
+ MemoryRegion io;
+
+ unsigned char slave_addr;
+
+ bool obf_irq_set;
+ bool atn_irq_set;
+ bool use_irq;
+ bool irqs_enabled;
+
+ uint8_t outmsg[MAX_IPMI_MSG_SIZE];
+ uint32_t outpos;
+ uint32_t outlen;
+
+ uint8_t inmsg[MAX_IPMI_MSG_SIZE];
+ uint32_t inlen;
+ bool write_end;
+} IPMIInterface;
+
+typedef struct IPMIInterfaceClass {
+ ObjectClass parent_class;
+
+ unsigned int smbios_type;
+
+ void (*init)(struct IPMIInterface *s, Error **errp);
+
+ /*
+ * Perform various operations on the hardware. If checkonly is
+ * true, it will return if the operation can be performed, but it
+ * will not do the operation.
+ */
+ int (*do_hw_op)(struct IPMIInterface *s, enum ipmi_op op, int checkonly);
+
+ /*
+ * Enable/disable irqs on the interface when the BMC requests this.
+ */
+ void (*set_irq_enable)(struct IPMIInterface *s, int val);
+
+ /*
+ * Handle an event that occurred on the interface, generally the.
+ * target writing to a register.
+ */
+ void (*handle_if_event)(struct IPMIInterface *s);
+
+ /*
+ * The interfaces use this to perform certain ops
+ */
+ void (*set_atn)(struct IPMIInterface *s, int val, int irq);
+
+ /*
+ * Got an IPMI warm/cold reset.
+ */
+ void (*reset)(struct IPMIInterface *s, bool is_cold);
+
+ /*
+ * Handle a response from the bmc.
+ */
+ void (*handle_rsp)(struct IPMIInterface *s, uint8_t msg_id,
+ unsigned char *rsp, unsigned int rsp_len);
+} IPMIInterfaceClass;
+
+void ipmi_interface_init(IPMIInterface *s, Error **errp);
+void ipmi_interface_reset(IPMIInterface *s);
+
+/*
+ * Define a BMC simulator (or perhaps a connection to a real BMC)
+ */
+#define TYPE_IPMI_BMC "ipmi-bmc"
+#define IPMI_BMC(obj) \
+ OBJECT_CHECK(IPMIBmc, (obj), TYPE_IPMI_BMC)
+#define IPMI_BMC_CLASS(klass) \
+ OBJECT_CLASS_CHECK(IPMIBmcClass, (klass), TYPE_IPMI_BMC)
+#define IPMI_BMC_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(IPMIBmcClass, (obj), TYPE_IPMI_BMC)
+
+#define TYPE_IPMI_BMC_EXTERN "ipmi-bmc-extern"
+#define TYPE_IPMI_BMC_SIMULATOR "ipmi-bmc-sim"
+
+static inline void ipmi_signal(IPMIInterface *s)
+{
+ s->do_wake = 1;
+ while (s->do_wake) {
+ s->do_wake = 0;
+ (IPMI_INTERFACE_GET_CLASS(s))->handle_if_event(s);
+ }
+}
+
+struct IPMIBmc {
+ Object parent_obj;
+
+ IPMIInterface *intf;
+ CharDriverState *chr;
+};
+
+typedef struct IPMIBmcClass {
+ ObjectClass parent_class;
+
+ void (*init)(IPMIBmc *s, Error **errp);
+
+ /* Called when the system resets to report to the bmc. */
+ void (*handle_reset)(struct IPMIBmc *s);
+
+ /*
+ * Handle a command to the bmc.
+ */
+ void (*handle_command)(struct IPMIBmc *s,
+ uint8_t *cmd, unsigned int cmd_len,
+ unsigned int max_cmd_len,
+ uint8_t msg_id);
+} IPMIBmcClass;
+
+void ipmi_bmc_init(IPMIBmc *s, Error **errp);
+
+#ifdef IPMI_DEBUG
+#define ipmi_debug(fs, ...) \
+ fprintf(stderr, "IPMI (%s): " fs, __func__, ##__VA_ARGS__)
+#else
+#define ipmi_debug(fs, ...)
+#endif
+
+#endif
diff --git a/qemu-doc.texi b/qemu-doc.texi
index 0125bc7..80a22a4 100644
--- a/qemu-doc.texi
+++ b/qemu-doc.texi
@@ -195,6 +195,8 @@ PCI and ISA network adapters
@item
Serial ports
@item
+IPMI BMC, either and internal or external one
+@item
Creative SoundBlaster 16 sound card
@item
ENSONIQ AudioPCI ES1370 sound card
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 01/17] Add a base IPMI interface minyard
@ 2015-04-23 22:57 ` minyard
2015-04-26 8:58 ` Michael S. Tsirkin
2015-04-26 9:05 ` Michael S. Tsirkin
2015-04-23 22:57 ` [Qemu-devel] [PATCH 03/17] ipmi: Add a KCS low-level interface minyard
` (15 subsequent siblings)
17 siblings, 2 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
This provides the base infrastructure to tie IPMI low-level
interfaces into a PC ISA bus.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/isa_ipmi.c | 144 +++++++++++++++++++++++++++++++++++++
include/hw/nvram/fw_cfg.h | 11 ++-
5 files changed, 157 insertions(+), 1 deletion(-)
create mode 100644 hw/ipmi/isa_ipmi.c
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index ab1a552..1c3153b 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -9,6 +9,7 @@ CONFIG_VGA_CIRRUS=y
CONFIG_VMWARE_VGA=y
CONFIG_VMMOUSE=y
CONFIG_IPMI=y
+CONFIG_ISA_IPMI=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 82bafcc..6b57430 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -9,6 +9,7 @@ CONFIG_VGA_CIRRUS=y
CONFIG_VMWARE_VGA=y
CONFIG_VMMOUSE=y
CONFIG_IPMI=y
+CONFIG_ISA_IPMI=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
index 65bde11..1518216 100644
--- a/hw/ipmi/Makefile.objs
+++ b/hw/ipmi/Makefile.objs
@@ -1 +1,2 @@
+common-obj-$(CONFIG_ISA_IPMI) += isa_ipmi.o
common-obj-$(CONFIG_IPMI) += ipmi.o
diff --git a/hw/ipmi/isa_ipmi.c b/hw/ipmi/isa_ipmi.c
new file mode 100644
index 0000000..1c1ab8d
--- /dev/null
+++ b/hw/ipmi/isa_ipmi.c
@@ -0,0 +1,144 @@
+/*
+ * QEMU ISA IPMI emulation
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw/hw.h"
+#include "hw/isa/isa.h"
+#include "hw/i386/pc.h"
+#include "qemu/timer.h"
+#include "sysemu/char.h"
+#include "sysemu/sysemu.h"
+#include "ipmi.h"
+
+/* This is the type the user specifies on the -device command line */
+#define TYPE_ISA_IPMI "isa-ipmi"
+#define ISA_IPMI(obj) OBJECT_CHECK(ISAIPMIDevice, (obj), TYPE_ISA_IPMI)
+
+typedef struct ISAIPMIDevice {
+ ISADevice dev;
+ char *interface;
+ uint32_t iobase;
+ int32 isairq;
+ uint8_t slave_addr;
+ CharDriverState *chr;
+ IPMIInterface *intf;
+} ISAIPMIDevice;
+
+static void ipmi_isa_realizefn(DeviceState *dev, Error **errp)
+{
+ ISADevice *isadev = ISA_DEVICE(dev);
+ ISAIPMIDevice *ipmi = ISA_IPMI(dev);
+ char typename[20];
+ Object *intfobj;
+ IPMIInterface *intf;
+ Object *bmcobj;
+ IPMIBmc *bmc;
+
+ if (!ipmi->interface) {
+ ipmi->interface = g_strdup("kcs");
+ }
+
+ if (ipmi->chr) {
+ bmcobj = object_new(TYPE_IPMI_BMC_EXTERN);
+ } else {
+ bmcobj = object_new(TYPE_IPMI_BMC_SIMULATOR);
+ }
+ bmc = IPMI_BMC(bmcobj);
+ bmc->chr = ipmi->chr;
+ snprintf(typename, sizeof(typename),
+ TYPE_IPMI_INTERFACE_PREFIX "%s", ipmi->interface);
+ intfobj = object_new(typename);
+ intf = IPMI_INTERFACE(intfobj);
+ bmc->intf = intf;
+ intf->bmc = bmc;
+ intf->io_base = ipmi->iobase;
+ intf->slave_addr = ipmi->slave_addr;
+ ipmi_interface_init(intf, errp);
+ if (*errp) {
+ return;
+ }
+ ipmi_bmc_init(bmc, errp);
+ if (*errp) {
+ return;
+ }
+
+ /* These may be set by the interface. */
+ ipmi->iobase = intf->io_base;
+ ipmi->slave_addr = intf->slave_addr;
+
+ if (ipmi->isairq > 0) {
+ isa_init_irq(isadev, &intf->irq, ipmi->isairq);
+ intf->use_irq = 1;
+ }
+
+ ipmi->intf = intf;
+ object_property_add_child(OBJECT(isadev), "intf", OBJECT(intf), errp);
+ if (*errp) {
+ return;
+ }
+ object_property_add_child(OBJECT(isadev), "bmc", OBJECT(bmc), errp);
+ if (*errp) {
+ return;
+ }
+
+ qdev_set_legacy_instance_id(dev, intf->io_base, intf->io_length);
+
+ isa_register_ioport(isadev, &intf->io, intf->io_base);
+}
+
+static void ipmi_isa_reset(DeviceState *qdev)
+{
+ ISAIPMIDevice *isa = ISA_IPMI(qdev);
+
+ ipmi_interface_reset(isa->intf);
+}
+
+static Property ipmi_isa_properties[] = {
+ DEFINE_PROP_STRING("interface", ISAIPMIDevice, interface),
+ DEFINE_PROP_UINT32("iobase", ISAIPMIDevice, iobase, 0),
+ DEFINE_PROP_INT32("irq", ISAIPMIDevice, isairq, 5),
+ DEFINE_PROP_UINT8("slave_addr", ISAIPMIDevice, slave_addr, 0),
+ DEFINE_PROP_CHR("chardev", ISAIPMIDevice, chr),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ipmi_isa_class_initfn(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->realize = ipmi_isa_realizefn;
+ dc->reset = ipmi_isa_reset;
+ dc->props = ipmi_isa_properties;
+}
+
+static const TypeInfo ipmi_isa_info = {
+ .name = TYPE_ISA_IPMI,
+ .parent = TYPE_ISA_DEVICE,
+ .instance_size = sizeof(ISAIPMIDevice),
+ .class_init = ipmi_isa_class_initfn,
+};
+
+static void ipmi_register_types(void)
+{
+ type_register_static(&ipmi_isa_info);
+}
+
+type_init(ipmi_register_types)
diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index 6d8a8ac..cac3a34 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -38,7 +38,16 @@
#define FW_CFG_FILE_FIRST 0x20
#define FW_CFG_FILE_SLOTS 0x10
-#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
+
+#define FW_CFG_IPMI_INTERFACE 0x30
+#define FW_CFG_IPMI_BASE_ADDR 0x31
+#define FW_CFG_IPMI_REG_SPACE 0x32
+#define FW_CFG_IPMI_REG_SPACING 0x33
+#define FW_CFG_IPMI_SLAVE_ADDR 0x34
+#define FW_CFG_IPMI_IRQ 0x35
+#define FW_CFG_IPMI_VERSION 0x36
+
+#define FW_CFG_MAX_ENTRY (FW_CFG_IPMI_VERSION + 1)
#define FW_CFG_WRITE_CHANNEL 0x4000
#define FW_CFG_ARCH_LOCAL 0x8000
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 03/17] ipmi: Add a KCS low-level interface
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 01/17] Add a base IPMI interface minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure minyard
@ 2015-04-23 22:57 ` minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 04/17] ipmi: Add a BT " minyard
` (14 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
This provides the simulation of the KCS hardware interface.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_kcs.c | 337 +++++++++++++++++++++++++++++++++++++
4 files changed, 340 insertions(+)
create mode 100644 hw/ipmi/ipmi_kcs.c
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 1c3153b..845ecca 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -10,6 +10,7 @@ CONFIG_VMWARE_VGA=y
CONFIG_VMMOUSE=y
CONFIG_IPMI=y
CONFIG_ISA_IPMI=y
+CONFIG_IPMI_KCS=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 6b57430..0db658b 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -10,6 +10,7 @@ CONFIG_VMWARE_VGA=y
CONFIG_VMMOUSE=y
CONFIG_IPMI=y
CONFIG_ISA_IPMI=y
+CONFIG_IPMI_KCS=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
index 1518216..fec5812 100644
--- a/hw/ipmi/Makefile.objs
+++ b/hw/ipmi/Makefile.objs
@@ -1,2 +1,3 @@
common-obj-$(CONFIG_ISA_IPMI) += isa_ipmi.o
common-obj-$(CONFIG_IPMI) += ipmi.o
+common-obj-$(CONFIG_IPMI_KCS) += ipmi_kcs.o
diff --git a/hw/ipmi/ipmi_kcs.c b/hw/ipmi/ipmi_kcs.c
new file mode 100644
index 0000000..411799e
--- /dev/null
+++ b/hw/ipmi/ipmi_kcs.c
@@ -0,0 +1,337 @@
+/*
+ * QEMU IPMI KCS emulation
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw/hw.h"
+#include "ipmi.h"
+
+#define TYPE_IPMI_INTERFACE_KCS TYPE_IPMI_INTERFACE_PREFIX "kcs"
+#define IPMI_INTERFACE_KCS(obj) OBJECT_CHECK(IPMIKcsInterface, (obj), \
+ TYPE_IPMI_INTERFACE_KCS)
+
+#define IPMI_KCS_OBF_BIT 0
+#define IPMI_KCS_IBF_BIT 1
+#define IPMI_KCS_SMS_ATN_BIT 2
+#define IPMI_KCS_CD_BIT 3
+
+#define IPMI_KCS_OBF_MASK (1 << IPMI_KCS_OBF_BIT)
+#define IPMI_KCS_GET_OBF(d) (((d) >> IPMI_KCS_OBF_BIT) & 0x1)
+#define IPMI_KCS_SET_OBF(d, v) (d) = (((d) & ~IPMI_KCS_OBF_MASK) | \
+ (((v) & 1) << IPMI_KCS_OBF_BIT))
+#define IPMI_KCS_IBF_MASK (1 << IPMI_KCS_IBF_BIT)
+#define IPMI_KCS_GET_IBF(d) (((d) >> IPMI_KCS_IBF_BIT) & 0x1)
+#define IPMI_KCS_SET_IBF(d, v) (d) = (((d) & ~IPMI_KCS_IBF_MASK) | \
+ (((v) & 1) << IPMI_KCS_IBF_BIT))
+#define IPMI_KCS_SMS_ATN_MASK (1 << IPMI_KCS_SMS_ATN_BIT)
+#define IPMI_KCS_GET_SMS_ATN(d) (((d) >> IPMI_KCS_SMS_ATN_BIT) & 0x1)
+#define IPMI_KCS_SET_SMS_ATN(d, v) (d) = (((d) & ~IPMI_KCS_SMS_ATN_MASK) | \
+ (((v) & 1) << IPMI_KCS_SMS_ATN_BIT))
+#define IPMI_KCS_CD_MASK (1 << IPMI_KCS_CD_BIT)
+#define IPMI_KCS_GET_CD(d) (((d) >> IPMI_KCS_CD_BIT) & 0x1)
+#define IPMI_KCS_SET_CD(d, v) (d) = (((d) & ~IPMI_KCS_CD_MASK) | \
+ (((v) & 1) << IPMI_KCS_CD_BIT))
+
+#define IPMI_KCS_IDLE_STATE 0
+#define IPMI_KCS_READ_STATE 1
+#define IPMI_KCS_WRITE_STATE 2
+#define IPMI_KCS_ERROR_STATE 3
+
+#define IPMI_KCS_GET_STATE(d) (((d) >> 6) & 0x3)
+#define IPMI_KCS_SET_STATE(d, v) ((d) = ((d) & ~0xc0) | (((v) & 0x3) << 6))
+
+#define IPMI_KCS_ABORT_STATUS_CMD 0x60
+#define IPMI_KCS_WRITE_START_CMD 0x61
+#define IPMI_KCS_WRITE_END_CMD 0x62
+#define IPMI_KCS_READ_CMD 0x68
+
+#define IPMI_KCS_STATUS_NO_ERR 0x00
+#define IPMI_KCS_STATUS_ABORTED_ERR 0x01
+#define IPMI_KCS_STATUS_BAD_CC_ERR 0x02
+#define IPMI_KCS_STATUS_LENGTH_ERR 0x06
+
+typedef struct IPMIKcsInterface {
+ IPMIInterface intf;
+
+ uint8_t status_reg;
+ uint8_t data_out_reg;
+
+ int16_t data_in_reg; /* -1 means not written */
+ int16_t cmd_reg;
+
+ /*
+ * This is a response number that we send with the command to make
+ * sure that the response matches the command.
+ */
+ uint8_t waiting_rsp;
+} IPMIKcsInterface;
+
+#define SET_OBF() \
+ do { \
+ IPMI_KCS_SET_OBF(kcs->status_reg, 1); \
+ if (s->use_irq && s->irqs_enabled && !s->obf_irq_set) { \
+ s->obf_irq_set = 1; \
+ if (!s->atn_irq_set) { \
+ qemu_irq_raise(s->irq); \
+ } \
+ } \
+ } while (0)
+
+static void ipmi_kcs_handle_event(IPMIInterface *s)
+{
+ IPMIKcsInterface *kcs = IPMI_INTERFACE_KCS(s);
+
+ if (kcs->cmd_reg == IPMI_KCS_ABORT_STATUS_CMD) {
+ if (IPMI_KCS_GET_STATE(kcs->status_reg) != IPMI_KCS_ERROR_STATE) {
+ kcs->waiting_rsp++; /* Invalidate the message */
+ s->outmsg[0] = IPMI_KCS_STATUS_ABORTED_ERR;
+ s->outlen = 1;
+ s->outpos = 0;
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_ERROR_STATE);
+ SET_OBF();
+ }
+ goto out;
+ }
+
+ switch (IPMI_KCS_GET_STATE(kcs->status_reg)) {
+ case IPMI_KCS_IDLE_STATE:
+ if (kcs->cmd_reg == IPMI_KCS_WRITE_START_CMD) {
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_WRITE_STATE);
+ kcs->cmd_reg = -1;
+ s->write_end = 0;
+ s->inlen = 0;
+ SET_OBF();
+ }
+ break;
+
+ case IPMI_KCS_READ_STATE:
+ handle_read:
+ if (s->outpos >= s->outlen) {
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_IDLE_STATE);
+ SET_OBF();
+ } else if (kcs->data_in_reg == IPMI_KCS_READ_CMD) {
+ kcs->data_out_reg = s->outmsg[s->outpos];
+ s->outpos++;
+ SET_OBF();
+ } else {
+ s->outmsg[0] = IPMI_KCS_STATUS_BAD_CC_ERR;
+ s->outlen = 1;
+ s->outpos = 0;
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_ERROR_STATE);
+ SET_OBF();
+ goto out;
+ }
+ break;
+
+ case IPMI_KCS_WRITE_STATE:
+ if (kcs->data_in_reg != -1) {
+ /*
+ * Don't worry about input overrun here, that will be
+ * handled in the BMC.
+ */
+ if (s->inlen < sizeof(s->inmsg)) {
+ s->inmsg[s->inlen] = kcs->data_in_reg;
+ }
+ s->inlen++;
+ }
+ if (s->write_end) {
+ IPMIBmcClass *bk = IPMI_BMC_GET_CLASS(s->bmc);
+ s->outlen = 0;
+ s->write_end = 0;
+ s->outpos = 0;
+ bk->handle_command(s->bmc, s->inmsg, s->inlen, sizeof(s->inmsg),
+ kcs->waiting_rsp);
+ goto out_noibf;
+ } else if (kcs->cmd_reg == IPMI_KCS_WRITE_END_CMD) {
+ kcs->cmd_reg = -1;
+ s->write_end = 1;
+ }
+ SET_OBF();
+ break;
+
+ case IPMI_KCS_ERROR_STATE:
+ if (kcs->data_in_reg != -1) {
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_READ_STATE);
+ kcs->data_in_reg = IPMI_KCS_READ_CMD;
+ goto handle_read;
+ }
+ break;
+ }
+
+ if (kcs->cmd_reg != -1) {
+ /* Got an invalid command */
+ s->outmsg[0] = IPMI_KCS_STATUS_BAD_CC_ERR;
+ s->outlen = 1;
+ s->outpos = 0;
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_ERROR_STATE);
+ }
+
+ out:
+ kcs->cmd_reg = -1;
+ kcs->data_in_reg = -1;
+ IPMI_KCS_SET_IBF(kcs->status_reg, 0);
+ out_noibf:
+ return;
+}
+
+static void ipmi_kcs_handle_rsp(IPMIInterface *s, uint8_t msg_id,
+ unsigned char *rsp, unsigned int rsp_len)
+{
+ IPMIKcsInterface *kcs = IPMI_INTERFACE_KCS(s);
+
+ if (kcs->waiting_rsp == msg_id) {
+ kcs->waiting_rsp++;
+ if (rsp_len > sizeof(s->outmsg)) {
+ s->outmsg[0] = rsp[0];
+ s->outmsg[1] = rsp[1];
+ s->outmsg[2] = IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES;
+ s->outlen = 3;
+ } else {
+ memcpy(s->outmsg, rsp, rsp_len);
+ s->outlen = rsp_len;
+ }
+ IPMI_KCS_SET_STATE(kcs->status_reg, IPMI_KCS_READ_STATE);
+ kcs->data_in_reg = IPMI_KCS_READ_CMD;
+ ipmi_signal(&kcs->intf);
+ }
+}
+
+
+static uint64_t ipmi_kcs_ioport_read(void *opaque, hwaddr addr, unsigned size)
+{
+ IPMIKcsInterface *kcs = opaque;
+ uint32_t ret;
+
+ switch (addr & 1) {
+ case 0:
+ ret = kcs->data_out_reg;
+ IPMI_KCS_SET_OBF(kcs->status_reg, 0);
+ if (kcs->intf.obf_irq_set) {
+ kcs->intf.obf_irq_set = 0;
+ if (!kcs->intf.atn_irq_set) {
+ qemu_irq_lower(kcs->intf.irq);
+ }
+ }
+ break;
+ case 1:
+ ret = kcs->status_reg;
+ if (kcs->intf.atn_irq_set) {
+ kcs->intf.atn_irq_set = 0;
+ if (!kcs->intf.obf_irq_set) {
+ qemu_irq_lower(kcs->intf.irq);
+ }
+ }
+ break;
+ }
+ return ret;
+}
+
+static void ipmi_kcs_ioport_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ IPMIKcsInterface *kcs = opaque;
+ IPMIInterface *s = &kcs->intf;
+
+ if (IPMI_KCS_GET_IBF(kcs->status_reg)) {
+ return;
+ }
+
+ switch (addr & 1) {
+ case 0:
+ kcs->data_in_reg = val;
+ break;
+
+ case 1:
+ kcs->cmd_reg = val;
+ break;
+ }
+ IPMI_KCS_SET_IBF(kcs->status_reg, 1);
+ ipmi_signal(s);
+}
+
+const MemoryRegionOps ipmi_kcs_io_ops = {
+ .read = ipmi_kcs_ioport_read,
+ .write = ipmi_kcs_ioport_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void ipmi_kcs_set_atn(IPMIInterface *s, int val, int irq)
+{
+ IPMIKcsInterface *kcs = IPMI_INTERFACE_KCS(s);
+
+ IPMI_KCS_SET_SMS_ATN(kcs->status_reg, val);
+ if (val) {
+ if (irq && !s->atn_irq_set && s->use_irq && s->irqs_enabled) {
+ s->atn_irq_set = 1;
+ if (!s->obf_irq_set) {
+ qemu_irq_raise(s->irq);
+ }
+ }
+ } else {
+ if (s->atn_irq_set) {
+ s->atn_irq_set = 0;
+ if (!s->obf_irq_set) {
+ qemu_irq_lower(s->irq);
+ }
+ }
+ }
+}
+
+static void ipmi_kcs_init(IPMIInterface *s, Error **errp)
+{
+ IPMIKcsInterface *kcs = IPMI_INTERFACE_KCS(s);
+
+ if (!s->io_base) {
+ s->io_base = 0xca2;
+ }
+ s->io_length = 2;
+
+ memory_region_init_io(&s->io, NULL, &ipmi_kcs_io_ops, kcs, "ipmi-kcs", 2);
+}
+
+static void ipmi_kcs_class_init(ObjectClass *class, void *data)
+{
+ IPMIInterfaceClass *k = IPMI_INTERFACE_CLASS(class);
+
+ k->init = ipmi_kcs_init;
+ k->smbios_type = IPMI_SMBIOS_KCS;
+ k->set_atn = ipmi_kcs_set_atn;
+ k->handle_rsp = ipmi_kcs_handle_rsp;
+ k->handle_if_event = ipmi_kcs_handle_event;
+}
+
+static const TypeInfo ipmi_kcs_type = {
+ .name = TYPE_IPMI_INTERFACE_KCS,
+ .parent = TYPE_IPMI_INTERFACE,
+ .instance_size = sizeof(IPMIKcsInterface),
+ .class_init = ipmi_kcs_class_init,
+};
+
+static void ipmi_kcs_register_types(void)
+{
+ type_register_static(&ipmi_kcs_type);
+}
+
+type_init(ipmi_kcs_register_types)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 04/17] ipmi: Add a BT low-level interface
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (2 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 03/17] ipmi: Add a KCS low-level interface minyard
@ 2015-04-23 22:57 ` minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 05/17] ipmi: Add a local BMC simulation minyard
` (13 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
This provides the simulation of the BT hardware interface for
IPMI.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_bt.c | 374 +++++++++++++++++++++++++++++++++++++
4 files changed, 377 insertions(+)
create mode 100644 hw/ipmi/ipmi_bt.c
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 845ecca..7037185 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -11,6 +11,7 @@ CONFIG_VMMOUSE=y
CONFIG_IPMI=y
CONFIG_ISA_IPMI=y
CONFIG_IPMI_KCS=y
+CONFIG_IPMI_BT=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 0db658b..c5c234f 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -11,6 +11,7 @@ CONFIG_VMMOUSE=y
CONFIG_IPMI=y
CONFIG_ISA_IPMI=y
CONFIG_IPMI_KCS=y
+CONFIG_IPMI_BT=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
index fec5812..98c34ca 100644
--- a/hw/ipmi/Makefile.objs
+++ b/hw/ipmi/Makefile.objs
@@ -1,3 +1,4 @@
common-obj-$(CONFIG_ISA_IPMI) += isa_ipmi.o
common-obj-$(CONFIG_IPMI) += ipmi.o
common-obj-$(CONFIG_IPMI_KCS) += ipmi_kcs.o
+common-obj-$(CONFIG_IPMI_BT) += ipmi_bt.o
diff --git a/hw/ipmi/ipmi_bt.c b/hw/ipmi/ipmi_bt.c
new file mode 100644
index 0000000..95beb71
--- /dev/null
+++ b/hw/ipmi/ipmi_bt.c
@@ -0,0 +1,374 @@
+/*
+ * QEMU IPMI BT emulation
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+#include "hw/hw.h"
+#include "ipmi.h"
+
+#define TYPE_IPMI_INTERFACE_BT TYPE_IPMI_INTERFACE_PREFIX "bt"
+#define IPMI_INTERFACE_BT(obj) OBJECT_CHECK(IPMIBtInterface, (obj), \
+ TYPE_IPMI_INTERFACE_BT)
+
+/* Control register */
+#define IPMI_BT_CLR_WR_BIT 0
+#define IPMI_BT_CLR_RD_BIT 1
+#define IPMI_BT_H2B_ATN_BIT 2
+#define IPMI_BT_B2H_ATN_BIT 3
+#define IPMI_BT_SMS_ATN_BIT 4
+#define IPMI_BT_HBUSY_BIT 6
+#define IPMI_BT_BBUSY_BIT 7
+
+#define IPMI_BT_CLR_WR_MASK (1 << IPMI_BT_CLR_WR_BIT)
+#define IPMI_BT_GET_CLR_WR(d) (((d) >> IPMI_BT_CLR_WR_BIT) & 0x1)
+#define IPMI_BT_SET_CLR_WR(d, v) (d) = (((d) & ~IPMI_BT_CLR_WR_MASK) | \
+ (((v & 1) << IPMI_BT_CLR_WR_BIT)))
+
+#define IPMI_BT_CLR_RD_MASK (1 << IPMI_BT_CLR_RD_BIT)
+#define IPMI_BT_GET_CLR_RD(d) (((d) >> IPMI_BT_CLR_RD_BIT) & 0x1)
+#define IPMI_BT_SET_CLR_RD(d, v) (d) = (((d) & ~IPMI_BT_CLR_RD_MASK) | \
+ (((v & 1) << IPMI_BT_CLR_RD_BIT)))
+
+#define IPMI_BT_H2B_ATN_MASK (1 << IPMI_BT_H2B_ATN_BIT)
+#define IPMI_BT_GET_H2B_ATN(d) (((d) >> IPMI_BT_H2B_ATN_BIT) & 0x1)
+#define IPMI_BT_SET_H2B_ATN(d, v) (d) = (((d) & ~IPMI_BT_H2B_ATN_MASK) | \
+ (((v & 1) << IPMI_BT_H2B_ATN_BIT)))
+
+#define IPMI_BT_B2H_ATN_MASK (1 << IPMI_BT_B2H_ATN_BIT)
+#define IPMI_BT_GET_B2H_ATN(d) (((d) >> IPMI_BT_B2H_ATN_BIT) & 0x1)
+#define IPMI_BT_SET_B2H_ATN(d, v) (d) = (((d) & ~IPMI_BT_B2H_ATN_MASK) | \
+ (((v & 1) << IPMI_BT_B2H_ATN_BIT)))
+
+#define IPMI_BT_SMS_ATN_MASK (1 << IPMI_BT_SMS_ATN_BIT)
+#define IPMI_BT_GET_SMS_ATN(d) (((d) >> IPMI_BT_SMS_ATN_BIT) & 0x1)
+#define IPMI_BT_SET_SMS_ATN(d, v) (d) = (((d) & ~IPMI_BT_SMS_ATN_MASK) | \
+ (((v & 1) << IPMI_BT_SMS_ATN_BIT)))
+
+#define IPMI_BT_HBUSY_MASK (1 << IPMI_BT_HBUSY_BIT)
+#define IPMI_BT_GET_HBUSY(d) (((d) >> IPMI_BT_HBUSY_BIT) & 0x1)
+#define IPMI_BT_SET_HBUSY(d, v) (d) = (((d) & ~IPMI_BT_HBUSY_MASK) | \
+ (((v & 1) << IPMI_BT_HBUSY_BIT)))
+
+#define IPMI_BT_BBUSY_MASK (1 << IPMI_BT_BBUSY_BIT)
+#define IPMI_BT_GET_BBUSY(d) (((d) >> IPMI_BT_BBUSY_BIT) & 0x1)
+#define IPMI_BT_SET_BBUSY(d, v) (d) = (((d) & ~IPMI_BT_BBUSY_MASK) | \
+ (((v & 1) << IPMI_BT_BBUSY_BIT)))
+
+
+/* Mask register */
+#define IPMI_BT_B2H_IRQ_EN_BIT 0
+#define IPMI_BT_B2H_IRQ_BIT 1
+
+#define IPMI_BT_B2H_IRQ_EN_MASK (1 << IPMI_BT_B2H_IRQ_EN_BIT)
+#define IPMI_BT_GET_B2H_IRQ_EN(d) (((d) >> IPMI_BT_B2H_IRQ_EN_BIT) & 0x1)
+#define IPMI_BT_SET_B2H_IRQ_EN(d, v) (d) = (((d) & ~IPMI_BT_B2H_IRQ_EN_MASK) | \
+ (((v & 1) << IPMI_BT_B2H_IRQ_EN_BIT)))
+
+#define IPMI_BT_B2H_IRQ_MASK (1 << IPMI_BT_B2H_IRQ_BIT)
+#define IPMI_BT_GET_B2H_IRQ(d) (((d) >> IPMI_BT_B2H_IRQ_BIT) & 0x1)
+#define IPMI_BT_SET_B2H_IRQ(d, v) (d) = (((d) & ~IPMI_BT_B2H_IRQ_MASK) | \
+ (((v & 1) << IPMI_BT_B2H_IRQ_BIT)))
+
+typedef struct IPMIBtInterface {
+ IPMIInterface intf;
+
+ uint8_t control_reg;
+ uint8_t mask_reg;
+
+ /*
+ * This is a response number that we send with the command to make
+ * sure that the response matches the command.
+ */
+ uint8_t waiting_rsp;
+ uint8_t waiting_seq;
+} IPMIBtInterface;
+
+#define IPMI_CMD_GET_BT_INTF_CAP 0x36
+
+static void ipmi_bt_handle_event(IPMIInterface *s)
+{
+ IPMIBtInterface *bt = IPMI_INTERFACE_BT(s);
+
+ if (s->inlen < 4) {
+ goto out;
+ }
+ /* Note that overruns are handled by handle_command */
+ if (s->inmsg[0] != (s->inlen - 1)) {
+ /* Length mismatch, just ignore. */
+ IPMI_BT_SET_BBUSY(bt->control_reg, 1);
+ s->inlen = 0;
+ goto out;
+ }
+ if ((s->inmsg[1] == (IPMI_NETFN_APP << 2)) &&
+ (s->inmsg[3] == IPMI_CMD_GET_BT_INTF_CAP)) {
+ /* We handle this one ourselves. */
+ s->outmsg[0] = 9;
+ s->outmsg[1] = s->inmsg[1] | 0x04;
+ s->outmsg[2] = s->inmsg[2];
+ s->outmsg[3] = s->inmsg[3];
+ s->outmsg[4] = 0;
+ s->outmsg[5] = 1; /* Only support 1 outstanding request. */
+ if (sizeof(s->inmsg) > 0xff) { /* Input buffer size */
+ s->outmsg[6] = 0xff;
+ } else {
+ s->outmsg[6] = (unsigned char) sizeof(s->inmsg);
+ }
+ if (sizeof(s->outmsg) > 0xff) { /* Output buffer size */
+ s->outmsg[7] = 0xff;
+ } else {
+ s->outmsg[7] = (unsigned char) sizeof(s->outmsg);
+ }
+ s->outmsg[8] = 10; /* Max request to response time */
+ s->outmsg[9] = 0; /* Don't recommend retries */
+ s->outlen = 10;
+ IPMI_BT_SET_BBUSY(bt->control_reg, 0);
+ IPMI_BT_SET_B2H_ATN(bt->control_reg, 1);
+ if (s->use_irq && s->irqs_enabled &&
+ !IPMI_BT_GET_B2H_IRQ(bt->mask_reg) &&
+ IPMI_BT_GET_B2H_IRQ_EN(bt->mask_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 1);
+ qemu_irq_raise(s->irq);
+ }
+ goto out;
+ }
+ bt->waiting_seq = s->inmsg[2];
+ s->inmsg[2] = s->inmsg[1];
+ {
+ IPMIBmcClass *bk = IPMI_BMC_GET_CLASS(s->bmc);
+ bk->handle_command(s->bmc, s->inmsg + 2, s->inlen - 2, sizeof(s->inmsg),
+ bt->waiting_rsp);
+ }
+ out:
+ return;
+}
+
+static void ipmi_bt_handle_rsp(IPMIInterface *s, uint8_t msg_id,
+ unsigned char *rsp, unsigned int rsp_len)
+{
+ IPMIBtInterface *bt = IPMI_INTERFACE_BT(s);
+
+ if (bt->waiting_rsp == msg_id) {
+ bt->waiting_rsp++;
+ if (rsp_len > (sizeof(s->outmsg) - 2)) {
+ s->outmsg[0] = 4;
+ s->outmsg[1] = rsp[0];
+ s->outmsg[2] = bt->waiting_seq;
+ s->outmsg[3] = rsp[1];
+ s->outmsg[4] = IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES;
+ s->outlen = 5;
+ } else {
+ s->outmsg[0] = rsp_len + 1;
+ s->outmsg[1] = rsp[0];
+ s->outmsg[2] = bt->waiting_seq;
+ memcpy(s->outmsg + 3, rsp + 1, rsp_len - 1);
+ s->outlen = rsp_len + 2;
+ }
+ IPMI_BT_SET_BBUSY(bt->control_reg, 0);
+ IPMI_BT_SET_B2H_ATN(bt->control_reg, 1);
+ if (s->use_irq && s->irqs_enabled &&
+ !IPMI_BT_GET_B2H_IRQ(bt->mask_reg) &&
+ IPMI_BT_GET_B2H_IRQ_EN(bt->mask_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 1);
+ qemu_irq_raise(s->irq);
+ }
+ }
+}
+
+
+static uint64_t ipmi_bt_ioport_read(void *opaque, hwaddr addr, unsigned size)
+{
+ IPMIBtInterface *bt = opaque;
+ IPMIInterface *s = &bt->intf;
+ uint32_t ret = 0xff;
+
+ switch (addr & 3) {
+ case 0:
+ ret = bt->control_reg;
+ break;
+ case 1:
+ if (s->outpos < s->outlen) {
+ ret = s->outmsg[s->outpos];
+ s->outpos++;
+ if (s->outpos == s->outlen) {
+ s->outpos = 0;
+ s->outlen = 0;
+ }
+ } else {
+ ret = 0xff;
+ }
+ break;
+ case 2:
+ ret = bt->mask_reg;
+ break;
+ }
+ return ret;
+}
+
+static void ipmi_bt_ioport_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned size)
+{
+ IPMIBtInterface *bt = opaque;
+ IPMIInterface *s = &bt->intf;
+
+ switch (addr & 3) {
+ case 0:
+ if (IPMI_BT_GET_CLR_WR(val)) {
+ s->inlen = 0;
+ }
+ if (IPMI_BT_GET_CLR_RD(val)) {
+ s->outpos = 0;
+ }
+ if (IPMI_BT_GET_B2H_ATN(val)) {
+ IPMI_BT_SET_B2H_ATN(bt->control_reg, 0);
+ }
+ if (IPMI_BT_GET_SMS_ATN(val)) {
+ IPMI_BT_SET_SMS_ATN(bt->control_reg, 0);
+ }
+ if (IPMI_BT_GET_HBUSY(val)) {
+ /* Toggle */
+ IPMI_BT_SET_HBUSY(bt->control_reg,
+ !IPMI_BT_GET_HBUSY(bt->control_reg));
+ }
+ if (IPMI_BT_GET_H2B_ATN(val)) {
+ IPMI_BT_SET_BBUSY(bt->control_reg, 1);
+ ipmi_signal(s);
+ }
+ break;
+
+ case 1:
+ if (s->inlen < sizeof(s->inmsg)) {
+ s->inmsg[s->inlen] = val;
+ }
+ s->inlen++;
+ break;
+
+ case 2:
+ if (IPMI_BT_GET_B2H_IRQ_EN(val) !=
+ IPMI_BT_GET_B2H_IRQ_EN(bt->mask_reg)) {
+ if (IPMI_BT_GET_B2H_IRQ_EN(val)) {
+ if (IPMI_BT_GET_B2H_ATN(bt->control_reg) ||
+ IPMI_BT_GET_SMS_ATN(bt->control_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 1);
+ qemu_irq_raise(s->irq);
+ }
+ IPMI_BT_SET_B2H_IRQ_EN(bt->mask_reg, 1);
+ } else {
+ if (IPMI_BT_GET_B2H_IRQ(bt->mask_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 0);
+ qemu_irq_lower(s->irq);
+ }
+ IPMI_BT_SET_B2H_IRQ_EN(bt->mask_reg, 0);
+ }
+ }
+ if (IPMI_BT_GET_B2H_IRQ(val) && IPMI_BT_GET_B2H_IRQ(bt->mask_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 0);
+ qemu_irq_lower(s->irq);
+ }
+ break;
+ }
+}
+
+static const MemoryRegionOps ipmi_bt_io_ops = {
+ .read = ipmi_bt_ioport_read,
+ .write = ipmi_bt_ioport_write,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static void ipmi_bt_set_atn(IPMIInterface *s, int val, int irq)
+{
+ IPMIBtInterface *bt = IPMI_INTERFACE_BT(s);
+
+ if (!!val == IPMI_BT_GET_SMS_ATN(bt->control_reg)) {
+ return;
+ }
+
+ IPMI_BT_SET_SMS_ATN(bt->control_reg, val);
+ if (val) {
+ if (irq && s->use_irq && s->irqs_enabled &&
+ !IPMI_BT_GET_B2H_ATN(bt->control_reg) &&
+ IPMI_BT_GET_B2H_IRQ_EN(bt->mask_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 1);
+ qemu_irq_raise(s->irq);
+ }
+ } else {
+ if (!IPMI_BT_GET_B2H_ATN(bt->control_reg) &&
+ IPMI_BT_GET_B2H_IRQ(bt->mask_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 0);
+ qemu_irq_lower(s->irq);
+ }
+ }
+}
+
+static void ipmi_bt_handle_reset(IPMIInterface *s, bool is_cold)
+{
+ IPMIBtInterface *bt = IPMI_INTERFACE_BT(s);
+
+ if (is_cold) {
+ /* Disable the BT interrupt on reset */
+ if (IPMI_BT_GET_B2H_IRQ(bt->mask_reg)) {
+ IPMI_BT_SET_B2H_IRQ(bt->mask_reg, 0);
+ qemu_irq_lower(s->irq);
+ }
+ IPMI_BT_SET_B2H_IRQ_EN(bt->mask_reg, 0);
+ }
+}
+
+static void ipmi_bt_init(IPMIInterface *s, Error **errp)
+{
+ IPMIBtInterface *bt = IPMI_INTERFACE_BT(s);
+
+ if (!s->io_base) {
+ s->io_base = 0xe4;
+ }
+ s->io_length = 3;
+
+ memory_region_init_io(&s->io, NULL, &ipmi_bt_io_ops, bt, "ipmi-bt", 3);
+}
+
+static void ipmi_bt_class_init(ObjectClass *klass, void *data)
+{
+ IPMIInterfaceClass *k = IPMI_INTERFACE_CLASS(klass);
+
+ k->init = ipmi_bt_init;
+ k->smbios_type = IPMI_SMBIOS_BT;
+ k->set_atn = ipmi_bt_set_atn;
+ k->handle_rsp = ipmi_bt_handle_rsp;
+ k->handle_if_event = ipmi_bt_handle_event;
+ k->reset = ipmi_bt_handle_reset;
+}
+
+static const TypeInfo ipmi_bt_type = {
+ .name = TYPE_IPMI_INTERFACE_BT,
+ .parent = TYPE_IPMI_INTERFACE,
+ .instance_size = sizeof(IPMIBtInterface),
+ .class_init = ipmi_bt_class_init,
+};
+
+static void ipmi_bt_register_types(void)
+{
+ type_register_static(&ipmi_bt_type);
+}
+
+type_init(ipmi_bt_register_types)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 05/17] ipmi: Add a local BMC simulation
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (3 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 04/17] ipmi: Add a BT " minyard
@ 2015-04-23 22:57 ` minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 06/17] ipmi: Add an external connection simulation interface minyard
` (12 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
This provides a minimal local BMC, basically enough to comply with the
spec and provide a complete watchdog timer (including a sensor, SDR,
and event).
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_sim.c | 1730 ++++++++++++++++++++++++++++++++++++
4 files changed, 1733 insertions(+)
create mode 100644 hw/ipmi/ipmi_sim.c
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 7037185..5d8ad39 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -12,6 +12,7 @@ CONFIG_IPMI=y
CONFIG_ISA_IPMI=y
CONFIG_IPMI_KCS=y
CONFIG_IPMI_BT=y
+CONFIG_IPMI_LOCAL=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index c5c234f..7b83314 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -12,6 +12,7 @@ CONFIG_IPMI=y
CONFIG_ISA_IPMI=y
CONFIG_IPMI_KCS=y
CONFIG_IPMI_BT=y
+CONFIG_IPMI_LOCAL=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
index 98c34ca..d30a84e 100644
--- a/hw/ipmi/Makefile.objs
+++ b/hw/ipmi/Makefile.objs
@@ -2,3 +2,4 @@ common-obj-$(CONFIG_ISA_IPMI) += isa_ipmi.o
common-obj-$(CONFIG_IPMI) += ipmi.o
common-obj-$(CONFIG_IPMI_KCS) += ipmi_kcs.o
common-obj-$(CONFIG_IPMI_BT) += ipmi_bt.o
+common-obj-$(CONFIG_IPMI_LOCAL) += ipmi_sim.o
diff --git a/hw/ipmi/ipmi_sim.c b/hw/ipmi/ipmi_sim.c
new file mode 100644
index 0000000..d5b0600
--- /dev/null
+++ b/hw/ipmi/ipmi_sim.c
@@ -0,0 +1,1730 @@
+/*
+ * IPMI BMC emulation
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <stdint.h>
+#include "qemu/timer.h"
+#include "ipmi.h"
+
+#define IPMI_NETFN_CHASSIS 0x00
+#define IPMI_NETFN_CHASSIS_MAXCMD 0x03
+
+#define IPMI_CMD_GET_CHASSIS_CAPABILITIES 0x00
+#define IPMI_CMD_GET_CHASSIS_STATUS 0x01
+#define IPMI_CMD_CHASSIS_CONTROL 0x02
+
+#define IPMI_NETFN_SENSOR_EVENT 0x04
+#define IPMI_NETFN_SENSOR_EVENT_MAXCMD 0x2e
+
+#define IPMI_CMD_SET_SENSOR_EVT_ENABLE 0x28
+#define IPMI_CMD_GET_SENSOR_EVT_ENABLE 0x29
+#define IPMI_CMD_REARM_SENSOR_EVTS 0x2a
+#define IPMI_CMD_GET_SENSOR_EVT_STATUS 0x2b
+#define IPMI_CMD_GET_SENSOR_READING 0x2d
+
+/* #define IPMI_NETFN_APP 0x06 In ipmi.h */
+#define IPMI_NETFN_APP_MAXCMD 0x36
+
+#define IPMI_CMD_GET_DEVICE_ID 0x01
+#define IPMI_CMD_COLD_RESET 0x02
+#define IPMI_CMD_WARM_RESET 0x03
+#define IPMI_CMD_RESET_WATCHDOG_TIMER 0x22
+#define IPMI_CMD_SET_WATCHDOG_TIMER 0x24
+#define IPMI_CMD_GET_WATCHDOG_TIMER 0x25
+#define IPMI_CMD_SET_BMC_GLOBAL_ENABLES 0x2e
+#define IPMI_CMD_GET_BMC_GLOBAL_ENABLES 0x2f
+#define IPMI_CMD_CLR_MSG_FLAGS 0x30
+#define IPMI_CMD_GET_MSG_FLAGS 0x31
+#define IPMI_CMD_GET_MSG 0x33
+#define IPMI_CMD_SEND_MSG 0x34
+#define IPMI_CMD_READ_EVT_MSG_BUF 0x35
+
+#define IPMI_NETFN_STORAGE 0x0a
+#define IPMI_NETFN_STORAGE_MAXCMD 0x4a
+
+#define IPMI_CMD_GET_SDR_REP_INFO 0x20
+#define IPMI_CMD_GET_SDR_REP_ALLOC_INFO 0x21
+#define IPMI_CMD_RESERVE_SDR_REP 0x22
+#define IPMI_CMD_GET_SDR 0x23
+#define IPMI_CMD_ADD_SDR 0x24
+#define IPMI_CMD_PARTIAL_ADD_SDR 0x25
+#define IPMI_CMD_DELETE_SDR 0x26
+#define IPMI_CMD_CLEAR_SDR_REP 0x27
+#define IPMI_CMD_GET_SDR_REP_TIME 0x28
+#define IPMI_CMD_SET_SDR_REP_TIME 0x29
+#define IPMI_CMD_ENTER_SDR_REP_UPD_MODE 0x2A
+#define IPMI_CMD_EXIT_SDR_REP_UPD_MODE 0x2B
+#define IPMI_CMD_RUN_INIT_AGENT 0x2C
+#define IPMI_CMD_GET_SEL_INFO 0x40
+#define IPMI_CMD_GET_SEL_ALLOC_INFO 0x41
+#define IPMI_CMD_RESERVE_SEL 0x42
+#define IPMI_CMD_GET_SEL_ENTRY 0x43
+#define IPMI_CMD_ADD_SEL_ENTRY 0x44
+#define IPMI_CMD_PARTIAL_ADD_SEL_ENTRY 0x45
+#define IPMI_CMD_DELETE_SEL_ENTRY 0x46
+#define IPMI_CMD_CLEAR_SEL 0x47
+#define IPMI_CMD_GET_SEL_TIME 0x48
+#define IPMI_CMD_SET_SEL_TIME 0x49
+
+
+/* Same as a timespec struct. */
+struct ipmi_time {
+ long tv_sec;
+ long tv_nsec;
+};
+
+#define MAX_SEL_SIZE 128
+
+typedef struct IPMISel {
+ uint8_t sel[MAX_SEL_SIZE][16];
+ unsigned int next_free;
+ long time_offset;
+ uint16_t reservation;
+ uint8_t last_addition[4];
+ uint8_t last_clear[4];
+ uint8_t overflow;
+} IPMISel;
+
+#define MAX_SDR_SIZE 16384
+
+typedef struct IPMISdr {
+ uint8_t sdr[MAX_SDR_SIZE];
+ unsigned int next_free;
+ uint16_t next_rec_id;
+ uint16_t reservation;
+ uint8_t last_addition[4];
+ uint8_t last_clear[4];
+ uint8_t overflow;
+} IPMISdr;
+
+typedef struct IPMISensor {
+ uint8_t status;
+ uint8_t reading;
+ uint16_t states_suppt;
+ uint16_t assert_suppt;
+ uint16_t deassert_suppt;
+ uint16_t states;
+ uint16_t assert_states;
+ uint16_t deassert_states;
+ uint16_t assert_enable;
+ uint16_t deassert_enable;
+ uint8_t sensor_type;
+ uint8_t evt_reading_type_code;
+} IPMISensor;
+#define IPMI_SENSOR_GET_PRESENT(s) ((s)->status & 0x01)
+#define IPMI_SENSOR_SET_PRESENT(s, v) ((s)->status = (s->status & ~0x01) | \
+ !!(v))
+#define IPMI_SENSOR_GET_SCAN_ON(s) ((s)->status & 0x40)
+#define IPMI_SENSOR_SET_SCAN_ON(s, v) ((s)->status = (s->status & ~0x40) | \
+ ((!!(v)) << 6))
+#define IPMI_SENSOR_GET_EVENTS_ON(s) ((s)->status & 0x80)
+#define IPMI_SENSOR_SET_EVENTS_ON(s, v) ((s)->status = (s->status & ~0x80) | \
+ ((!!(v)) << 7))
+#define IPMI_SENSOR_GET_RET_STATUS(s) ((s)->status & 0xc0)
+#define IPMI_SENSOR_SET_RET_STATUS(s, v) ((s)->status = (s->status & ~0xc0) | \
+ (v & 0xc0))
+#define IPMI_SENSOR_IS_DISCRETE(s) ((s)->evt_reading_type_code != 1)
+
+#define MAX_SENSORS 20
+#define IPMI_WATCHDOG_SENSOR 0
+
+typedef struct IPMISimBmc IPMISimBmc;
+
+#define MAX_NETFNS 64
+typedef void (*IPMICmdHandler)(IPMISimBmc *s,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len);
+typedef struct IPMINetfn {
+ unsigned int cmd_nums;
+ const IPMICmdHandler *cmd_handlers;
+} IPMINetfn;
+
+typedef struct IPMIRcvBufEntry {
+ QTAILQ_ENTRY(IPMIRcvBufEntry) entry;
+ uint8_t len;
+ uint8_t buf[MAX_IPMI_MSG_SIZE];
+} IPMIRcvBufEntry;
+
+#define IPMI_BMC_SIMULATOR(obj) OBJECT_CHECK(IPMISimBmc, (obj), \
+ TYPE_IPMI_BMC_SIMULATOR)
+struct IPMISimBmc {
+ IPMIBmc parent;
+
+ QEMUTimer *timer;
+
+ uint8_t bmc_global_enables;
+ uint8_t msg_flags;
+
+ bool watchdog_initialized;
+ uint8_t watchdog_use;
+ uint8_t watchdog_action;
+ uint8_t watchdog_pretimeout; /* In seconds */
+ bool watchdog_expired;
+ uint16_t watchdog_timeout; /* in 100's of milliseconds */
+
+ bool watchdog_running;
+ bool watchdog_preaction_ran;
+ int64_t watchdog_expiry;
+
+ uint8_t device_id;
+ uint8_t ipmi_version;
+ uint8_t device_rev;
+ uint8_t fwrev1;
+ uint8_t fwrev2;
+ uint8_t mfg_id[3];
+ uint8_t product_id[2];
+
+ IPMISel sel;
+ IPMISdr sdr;
+ IPMISensor sensors[MAX_SENSORS];
+
+ /* Odd netfns are for responses, so we only need the even ones. */
+ const IPMINetfn *netfns[MAX_NETFNS / 2];
+
+ QemuMutex lock;
+ /* We allow one event in the buffer */
+ uint8_t evtbuf[16];
+
+ QTAILQ_HEAD(, IPMIRcvBufEntry) rcvbufs;
+};
+
+#define IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK (1 << 3)
+#define IPMI_BMC_MSG_FLAG_EVT_BUF_FULL (1 << 1)
+#define IPMI_BMC_MSG_FLAG_RCV_MSG_QUEUE (1 << 0)
+#define IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK_SET(s) \
+ (IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK & (s)->msg_flags)
+#define IPMI_BMC_MSG_FLAG_EVT_BUF_FULL_SET(s) \
+ (IPMI_BMC_MSG_FLAG_EVT_BUF_FULL & (s)->msg_flags)
+#define IPMI_BMC_MSG_FLAG_RCV_MSG_QUEUE_SET(s) \
+ (IPMI_BMC_MSG_FLAG_RCV_MSG_QUEUE & (s)->msg_flags)
+
+#define IPMI_BMC_RCV_MSG_QUEUE_INT_BIT 0
+#define IPMI_BMC_EVBUF_FULL_INT_BIT 1
+#define IPMI_BMC_EVENT_MSG_BUF_BIT 2
+#define IPMI_BMC_EVENT_LOG_BIT 3
+#define IPMI_BMC_MSG_INTS_ON(s) ((s)->bmc_global_enables & \
+ (1 << IPMI_BMC_RCV_MSG_QUEUE_INT_BIT))
+#define IPMI_BMC_EVBUF_FULL_INT_ENABLED(s) ((s)->bmc_global_enables & \
+ (1 << IPMI_BMC_EVBUF_FULL_INT_BIT))
+#define IPMI_BMC_EVENT_LOG_ENABLED(s) ((s)->bmc_global_enables & \
+ (1 << IPMI_BMC_EVENT_LOG_BIT))
+#define IPMI_BMC_EVENT_MSG_BUF_ENABLED(s) ((s)->bmc_global_enables & \
+ (1 << IPMI_BMC_EVENT_MSG_BUF_BIT))
+
+#define IPMI_BMC_WATCHDOG_USE_MASK 0xc7
+#define IPMI_BMC_WATCHDOG_ACTION_MASK 0x77
+#define IPMI_BMC_WATCHDOG_GET_USE(s) ((s)->watchdog_use & 0x7)
+#define IPMI_BMC_WATCHDOG_GET_DONT_LOG(s) (((s)->watchdog_use >> 7) & 0x1)
+#define IPMI_BMC_WATCHDOG_GET_DONT_STOP(s) (((s)->watchdog_use >> 6) & 0x1)
+#define IPMI_BMC_WATCHDOG_GET_PRE_ACTION(s) (((s)->watchdog_action >> 4) & 0x7)
+#define IPMI_BMC_WATCHDOG_PRE_NONE 0
+#define IPMI_BMC_WATCHDOG_PRE_SMI 1
+#define IPMI_BMC_WATCHDOG_PRE_NMI 2
+#define IPMI_BMC_WATCHDOG_PRE_MSG_INT 3
+#define IPMI_BMC_WATCHDOG_GET_ACTION(s) ((s)->watchdog_action & 0x7)
+#define IPMI_BMC_WATCHDOG_ACTION_NONE 0
+#define IPMI_BMC_WATCHDOG_ACTION_RESET 1
+#define IPMI_BMC_WATCHDOG_ACTION_POWER_DOWN 2
+#define IPMI_BMC_WATCHDOG_ACTION_POWER_CYCLE 3
+
+
+/* Add a byte to the response. */
+#define IPMI_ADD_RSP_DATA(b) \
+ do { \
+ if (*rsp_len >= max_rsp_len) { \
+ rsp[2] = IPMI_CC_REQUEST_DATA_TRUNCATED; \
+ goto out; \
+ } \
+ rsp[(*rsp_len)++] = (b); \
+ } while (0)
+
+/* Verify that the received command is a certain length. */
+#define IPMI_CHECK_CMD_LEN(l) \
+ if (cmd_len < l) { \
+ rsp[2] = IPMI_CC_REQUEST_DATA_LENGTH_INVALID; \
+ goto out; \
+ }
+
+/* Check that the reservation in the command is valid. */
+#define IPMI_CHECK_RESERVATION(off, r) \
+ do { \
+ if ((cmd[off] | (cmd[off + 1] << 8)) != r) { \
+ rsp[2] = IPMI_CC_INVALID_RESERVATION; \
+ goto out; \
+ } \
+ } while (0)
+
+
+static void ipmi_sim_handle_timeout(IPMISimBmc *ss);
+
+static void ipmi_gettime(struct ipmi_time *time)
+{
+ int64_t stime;
+
+ stime = qemu_clock_get_ns(QEMU_CLOCK_HOST);
+ time->tv_sec = stime / 1000000000LL;
+ time->tv_nsec = stime % 1000000000LL;
+}
+
+static int64_t ipmi_getmonotime(void)
+{
+ return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+}
+
+static void ipmi_timeout(void *opaque)
+{
+ IPMISimBmc *ss = opaque;
+
+ ipmi_sim_handle_timeout(ss);
+}
+
+static void set_timestamp(IPMISimBmc *ss, uint8_t *ts)
+{
+ unsigned int val;
+ struct ipmi_time now;
+
+ ipmi_gettime(&now);
+ val = now.tv_sec + ss->sel.time_offset;
+ ts[0] = val & 0xff;
+ ts[1] = (val >> 8) & 0xff;
+ ts[2] = (val >> 16) & 0xff;
+ ts[3] = (val >> 24) & 0xff;
+}
+
+static void sdr_inc_reservation(IPMISdr *sdr)
+{
+ sdr->reservation++;
+ if (sdr->reservation == 0) {
+ sdr->reservation = 1;
+ }
+}
+
+static int sdr_add_entry(IPMISimBmc *ss, const uint8_t *entry,
+ unsigned int len, uint16_t *recid)
+{
+ if ((len < 5) || (len > 255)) {
+ return 1;
+ }
+
+ if (entry[ss->sdr.next_free + 4] != len) {
+ return 1;
+ }
+
+ if (ss->sdr.next_free + len > MAX_SDR_SIZE) {
+ ss->sdr.overflow = 1;
+ return 1;
+ }
+
+ memcpy(ss->sdr.sdr + ss->sdr.next_free, entry, len);
+ ss->sdr.sdr[ss->sdr.next_free] = ss->sdr.next_rec_id & 0xff;
+ ss->sdr.sdr[ss->sdr.next_free+1] = (ss->sdr.next_rec_id >> 8) & 0xff;
+ ss->sdr.sdr[ss->sdr.next_free+2] = 0x51; /* Conform to IPMI 1.5 spec */
+
+ if (recid) {
+ *recid = ss->sdr.next_rec_id;
+ }
+ ss->sdr.next_rec_id++;
+ set_timestamp(ss, ss->sdr.last_addition);
+ ss->sdr.next_free += len;
+ sdr_inc_reservation(&ss->sdr);
+ return 0;
+}
+
+static int sdr_find_entry(IPMISdr *sdr, uint16_t recid,
+ unsigned int *retpos, uint16_t *nextrec)
+{
+ unsigned int pos = *retpos;
+
+ while (pos < sdr->next_free) {
+ uint16_t trec = sdr->sdr[pos] | (sdr->sdr[pos + 1] << 8);
+ unsigned int nextpos = pos + sdr->sdr[pos + 4];
+
+ if (trec == recid) {
+ if (nextrec) {
+ if (nextpos >= sdr->next_free) {
+ *nextrec = 0xffff;
+ } else {
+ *nextrec = (sdr->sdr[nextpos] |
+ (sdr->sdr[nextpos + 1] << 8));
+ }
+ }
+ *retpos = pos;
+ return 0;
+ }
+ pos = nextpos;
+ }
+ return 1;
+}
+
+static void sel_inc_reservation(IPMISel *sel)
+{
+ sel->reservation++;
+ if (sel->reservation == 0) {
+ sel->reservation = 1;
+ }
+}
+
+/* Returns 1 if the SEL is full and can't hold the event. */
+static int sel_add_event(IPMISimBmc *ss, uint8_t *event)
+{
+ event[0] = 0xff;
+ event[1] = 0xff;
+ set_timestamp(ss, event + 3);
+ if (ss->sel.next_free == MAX_SEL_SIZE) {
+ ss->sel.overflow = 1;
+ return 1;
+ }
+ event[0] = ss->sel.next_free & 0xff;
+ event[1] = (ss->sel.next_free >> 8) & 0xff;
+ memcpy(ss->sel.last_addition, event + 3, 4);
+ memcpy(ss->sel.sel[ss->sel.next_free], event, 16);
+ ss->sel.next_free++;
+ sel_inc_reservation(&ss->sel);
+ return 0;
+}
+
+static int attn_set(IPMISimBmc *ss)
+{
+ return IPMI_BMC_MSG_FLAG_RCV_MSG_QUEUE_SET(ss)
+ || IPMI_BMC_MSG_FLAG_EVT_BUF_FULL_SET(ss)
+ || IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK_SET(ss);
+}
+
+static int attn_irq_enabled(IPMISimBmc *ss)
+{
+ return (IPMI_BMC_MSG_INTS_ON(ss) && IPMI_BMC_MSG_FLAG_RCV_MSG_QUEUE_SET(ss))
+ || (IPMI_BMC_EVBUF_FULL_INT_ENABLED(ss) &&
+ IPMI_BMC_MSG_FLAG_EVT_BUF_FULL_SET(ss));
+}
+
+static void gen_event(IPMISimBmc *ss, unsigned int sens_num, uint8_t deassert,
+ uint8_t evd1, uint8_t evd2, uint8_t evd3)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ uint8_t evt[16];
+ IPMISensor *sens = ss->sensors + sens_num;
+
+ if (!IPMI_BMC_EVENT_MSG_BUF_ENABLED(ss)) {
+ return;
+ }
+ if (!IPMI_SENSOR_GET_EVENTS_ON(sens)) {
+ return;
+ }
+
+ evt[2] = 0x2; /* System event record */
+ evt[7] = s->slave_addr;
+ evt[8] = 0;
+ evt[9] = 0x04; /* Format version */
+ evt[10] = sens->sensor_type;
+ evt[11] = sens_num;
+ evt[12] = sens->evt_reading_type_code | (!!deassert << 7);
+ evt[13] = evd1;
+ evt[14] = evd2;
+ evt[15] = evd3;
+
+ if (IPMI_BMC_EVENT_LOG_ENABLED(ss)) {
+ sel_add_event(ss, evt);
+ }
+
+ if (ss->msg_flags & IPMI_BMC_MSG_FLAG_EVT_BUF_FULL) {
+ goto out;
+ }
+
+ memcpy(ss->evtbuf, evt, 16);
+ ss->msg_flags |= IPMI_BMC_MSG_FLAG_EVT_BUF_FULL;
+ k->set_atn(s, 1, attn_irq_enabled(ss));
+ out:
+ return;
+}
+
+static void sensor_set_discrete_bit(IPMISimBmc *ss, unsigned int sensor,
+ unsigned int bit, unsigned int val,
+ uint8_t evd1, uint8_t evd2, uint8_t evd3)
+{
+ IPMISensor *sens;
+ uint16_t mask;
+
+ if (sensor >= MAX_SENSORS) {
+ return;
+ }
+ if (bit >= 16) {
+ return;
+ }
+
+ mask = (1 << bit);
+ sens = ss->sensors + sensor;
+ if (val) {
+ sens->states |= mask & sens->states_suppt;
+ if (sens->assert_states & mask) {
+ return; /* Already asserted */
+ }
+ sens->assert_states |= mask & sens->assert_suppt;
+ if (sens->assert_enable & mask & sens->assert_states) {
+ /* Send an event on assert */
+ gen_event(ss, sensor, 0, evd1, evd2, evd3);
+ }
+ } else {
+ sens->states &= ~(mask & sens->states_suppt);
+ if (sens->deassert_states & mask) {
+ return; /* Already deasserted */
+ }
+ sens->deassert_states |= mask & sens->deassert_suppt;
+ if (sens->deassert_enable & mask & sens->deassert_states) {
+ /* Send an event on deassert */
+ gen_event(ss, sensor, 1, evd1, evd2, evd3);
+ }
+ }
+}
+
+static void ipmi_init_sensors_from_sdrs(IPMISimBmc *s)
+{
+ unsigned int i, pos;
+ IPMISensor *sens;
+
+ for (i = 0; i < MAX_SENSORS; i++) {
+ memset(s->sensors + i, 0, sizeof(*sens));
+ }
+
+ pos = 0;
+ for (i = 0; !sdr_find_entry(&s->sdr, i, &pos, NULL); i++) {
+ uint8_t *sdr = s->sdr.sdr + pos;
+ unsigned int len = sdr[4];
+
+ if (len < 20) {
+ continue;
+ }
+ if ((sdr[3] < 1) || (sdr[3] > 2)) {
+ continue; /* Not a sensor SDR we set from */
+ }
+
+ if (sdr[7] > MAX_SENSORS) {
+ continue;
+ }
+ sens = s->sensors + sdr[7];
+
+ IPMI_SENSOR_SET_PRESENT(sens, 1);
+ IPMI_SENSOR_SET_SCAN_ON(sens, (sdr[10] >> 6) & 1);
+ IPMI_SENSOR_SET_EVENTS_ON(sens, (sdr[10] >> 5) & 1);
+ sens->assert_suppt = sdr[14] | (sdr[15] << 8);
+ sens->deassert_suppt = sdr[16] | (sdr[17] << 8);
+ sens->states_suppt = sdr[18] | (sdr[19] << 8);
+ sens->sensor_type = sdr[12];
+ sens->evt_reading_type_code = sdr[13] & 0x7f;
+
+ /* Enable all the events that are supported. */
+ sens->assert_enable = sens->assert_suppt;
+ sens->deassert_enable = sens->deassert_suppt;
+ }
+}
+
+static int ipmi_register_netfn(IPMISimBmc *s, unsigned int netfn,
+ const IPMINetfn *netfnd)
+{
+ if ((netfn & 1) || (netfn > MAX_NETFNS) || (s->netfns[netfn / 2])) {
+ return -1;
+ }
+ s->netfns[netfn / 2] = netfnd;
+ return 0;
+}
+
+static void next_timeout(IPMISimBmc *ss)
+{
+ int64_t next;
+ if (ss->watchdog_running) {
+ next = ss->watchdog_expiry;
+ } else {
+ /* Wait a minute */
+ next = ipmi_getmonotime() + 60 * 1000000000LL;
+ }
+ timer_mod_ns(ss->timer, next);
+}
+
+static void ipmi_sim_handle_command(IPMIBmc *b,
+ uint8_t *cmd, unsigned int cmd_len,
+ unsigned int max_cmd_len,
+ uint8_t msg_id)
+{
+ IPMISimBmc *ss = IPMI_BMC_SIMULATOR(b);
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ unsigned int netfn;
+ uint8_t rsp[MAX_IPMI_MSG_SIZE];
+ unsigned int rsp_len_holder = 0;
+ unsigned int *rsp_len = &rsp_len_holder;
+ unsigned int max_rsp_len = sizeof(rsp);
+
+ /* Set up the response, set the low bit of NETFN. */
+ /* Note that max_rsp_len must be at least 3 */
+ IPMI_ADD_RSP_DATA(cmd[0] | 0x04);
+ IPMI_ADD_RSP_DATA(cmd[1]);
+ IPMI_ADD_RSP_DATA(0); /* Assume success */
+
+ /* If it's too short or it was truncated, return an error. */
+ if (cmd_len < 2) {
+ rsp[2] = IPMI_CC_REQUEST_DATA_LENGTH_INVALID;
+ goto out;
+ }
+ if (cmd_len > max_cmd_len) {
+ rsp[2] = IPMI_CC_REQUEST_DATA_TRUNCATED;
+ goto out;
+ }
+
+ if ((cmd[0] & 0x03) != 0) {
+ /* Only have stuff on LUN 0 */
+ rsp[2] = IPMI_CC_COMMAND_INVALID_FOR_LUN;
+ goto out;
+ }
+
+ netfn = cmd[0] >> 2;
+
+ /* Odd netfns are not valid, make sure the command is registered */
+ if ((netfn & 1) || !ss->netfns[netfn / 2] ||
+ (cmd[1] >= ss->netfns[netfn / 2]->cmd_nums) ||
+ (!ss->netfns[netfn / 2]->cmd_handlers[cmd[1]])) {
+ rsp[2] = IPMI_CC_INVALID_CMD;
+ goto out;
+ }
+
+ ss->netfns[netfn / 2]->cmd_handlers[cmd[1]](ss, cmd, cmd_len, rsp, rsp_len,
+ max_rsp_len);
+
+ out:
+ k->handle_rsp(s, msg_id, rsp, *rsp_len);
+
+ next_timeout(ss);
+}
+
+static void ipmi_sim_handle_timeout(IPMISimBmc *ss)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ if (!ss->watchdog_running) {
+ goto out;
+ }
+
+ if (!ss->watchdog_preaction_ran) {
+ switch (IPMI_BMC_WATCHDOG_GET_PRE_ACTION(ss)) {
+ case IPMI_BMC_WATCHDOG_PRE_NMI:
+ ss->msg_flags |= IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK;
+ k->do_hw_op(s, IPMI_SEND_NMI, 0);
+ sensor_set_discrete_bit(ss, IPMI_WATCHDOG_SENSOR, 8, 1,
+ 0xc8, (2 << 4) | 0xf, 0xff);
+ break;
+
+ case IPMI_BMC_WATCHDOG_PRE_MSG_INT:
+ ss->msg_flags |= IPMI_BMC_MSG_FLAG_WATCHDOG_TIMEOUT_MASK;
+ k->set_atn(s, 1, attn_irq_enabled(ss));
+ sensor_set_discrete_bit(ss, IPMI_WATCHDOG_SENSOR, 8, 1,
+ 0xc8, (3 << 4) | 0xf, 0xff);
+ break;
+
+ default:
+ goto do_full_expiry;
+ }
+
+ ss->watchdog_preaction_ran = 1;
+ /* Issued the pretimeout, do the rest of the timeout now. */
+ ss->watchdog_expiry = ipmi_getmonotime();
+ ss->watchdog_expiry += ss->watchdog_pretimeout * 1000000000LL;
+ goto out;
+ }
+
+ do_full_expiry:
+ ss->watchdog_running = 0; /* Stop the watchdog on a timeout */
+ ss->watchdog_expired |= (1 << IPMI_BMC_WATCHDOG_GET_USE(ss));
+ switch (IPMI_BMC_WATCHDOG_GET_ACTION(ss)) {
+ case IPMI_BMC_WATCHDOG_ACTION_NONE:
+ sensor_set_discrete_bit(ss, IPMI_WATCHDOG_SENSOR, 0, 1,
+ 0xc0, ss->watchdog_use & 0xf, 0xff);
+ break;
+
+ case IPMI_BMC_WATCHDOG_ACTION_RESET:
+ sensor_set_discrete_bit(ss, IPMI_WATCHDOG_SENSOR, 1, 1,
+ 0xc1, ss->watchdog_use & 0xf, 0xff);
+ k->do_hw_op(s, IPMI_RESET_CHASSIS, 0);
+ break;
+
+ case IPMI_BMC_WATCHDOG_ACTION_POWER_DOWN:
+ sensor_set_discrete_bit(ss, IPMI_WATCHDOG_SENSOR, 2, 1,
+ 0xc2, ss->watchdog_use & 0xf, 0xff);
+ k->do_hw_op(s, IPMI_POWEROFF_CHASSIS, 0);
+ break;
+
+ case IPMI_BMC_WATCHDOG_ACTION_POWER_CYCLE:
+ sensor_set_discrete_bit(ss, IPMI_WATCHDOG_SENSOR, 2, 1,
+ 0xc3, ss->watchdog_use & 0xf, 0xff);
+ k->do_hw_op(s, IPMI_POWERCYCLE_CHASSIS, 0);
+ break;
+ }
+
+ out:
+ next_timeout(ss);
+}
+
+static void chassis_capabilities(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+
+ IPMI_ADD_RSP_DATA(0);
+ IPMI_ADD_RSP_DATA(s->slave_addr);
+ IPMI_ADD_RSP_DATA(s->slave_addr);
+ IPMI_ADD_RSP_DATA(s->slave_addr);
+ IPMI_ADD_RSP_DATA(s->slave_addr);
+ out:
+ return;
+}
+
+static void chassis_status(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(0x61); /* Unknown power restore, power is on */
+ IPMI_ADD_RSP_DATA(0);
+ IPMI_ADD_RSP_DATA(0);
+ IPMI_ADD_RSP_DATA(0);
+ out:
+ return;
+}
+
+static void chassis_control(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ IPMI_CHECK_CMD_LEN(3);
+ switch (cmd[2] & 0xf) {
+ case 0: /* power down */
+ rsp[2] = k->do_hw_op(s, IPMI_POWEROFF_CHASSIS, 0);
+ break;
+ case 1: /* power up */
+ rsp[2] = k->do_hw_op(s, IPMI_POWERON_CHASSIS, 0);
+ break;
+ case 2: /* power cycle */
+ rsp[2] = k->do_hw_op(s, IPMI_POWERCYCLE_CHASSIS, 0);
+ break;
+ case 3: /* hard reset */
+ rsp[2] = k->do_hw_op(s, IPMI_RESET_CHASSIS, 0);
+ break;
+ case 4: /* pulse diagnostic interrupt */
+ rsp[2] = k->do_hw_op(s, IPMI_PULSE_DIAG_IRQ, 0);
+ break;
+ case 5: /* soft shutdown via ACPI by overtemp emulation */
+ rsp[2] = k->do_hw_op(s,
+ IPMI_SHUTDOWN_VIA_ACPI_OVERTEMP, 0);
+ break;
+ default:
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ out:
+ return;
+}
+
+static void get_device_id(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(ss->device_id);
+ IPMI_ADD_RSP_DATA(ss->device_rev & 0xf);
+ IPMI_ADD_RSP_DATA(ss->fwrev1 & 0x7f);
+ IPMI_ADD_RSP_DATA(ss->fwrev2);
+ IPMI_ADD_RSP_DATA(ss->ipmi_version);
+ IPMI_ADD_RSP_DATA(0x07); /* sensor, SDR, and SEL. */
+ IPMI_ADD_RSP_DATA(ss->mfg_id[0]);
+ IPMI_ADD_RSP_DATA(ss->mfg_id[1]);
+ IPMI_ADD_RSP_DATA(ss->mfg_id[2]);
+ IPMI_ADD_RSP_DATA(ss->product_id[0]);
+ IPMI_ADD_RSP_DATA(ss->product_id[1]);
+ out:
+ return;
+}
+
+static void set_global_enables(IPMISimBmc *ss, uint8_t val)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ bool irqs_on;
+
+ ss->bmc_global_enables = val;
+
+ irqs_on = val & (IPMI_BMC_EVBUF_FULL_INT_BIT |
+ IPMI_BMC_RCV_MSG_QUEUE_INT_BIT);
+
+ k->set_irq_enable(s, irqs_on);
+}
+
+static void cold_reset(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ /* Disable all interrupts */
+ set_global_enables(ss, 1 << IPMI_BMC_EVENT_LOG_BIT);
+
+ if (k->reset) {
+ k->reset(s, true);
+ }
+}
+
+static void warm_reset(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ if (k->reset) {
+ k->reset(s, false);
+ }
+}
+
+static void set_bmc_global_enables(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_CHECK_CMD_LEN(3);
+ set_global_enables(ss, cmd[2]);
+ out:
+ return;
+}
+
+static void get_bmc_global_enables(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(ss->bmc_global_enables);
+ out:
+ return;
+}
+
+static void clr_msg_flags(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ IPMI_CHECK_CMD_LEN(3);
+ ss->msg_flags &= ~cmd[2];
+ k->set_atn(s, attn_set(ss), attn_irq_enabled(ss));
+ out:
+ return;
+}
+
+static void get_msg_flags(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(ss->msg_flags);
+ out:
+ return;
+}
+
+static void read_evt_msg_buf(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ unsigned int i;
+
+ if (!(ss->msg_flags & IPMI_BMC_MSG_FLAG_EVT_BUF_FULL)) {
+ rsp[2] = 0x80;
+ goto out;
+ }
+ for (i = 0; i < 16; i++) {
+ IPMI_ADD_RSP_DATA(ss->evtbuf[i]);
+ }
+ ss->msg_flags &= ~IPMI_BMC_MSG_FLAG_EVT_BUF_FULL;
+ k->set_atn(s, attn_set(ss), attn_irq_enabled(ss));
+ out:
+ return;
+}
+
+static void get_msg(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIRcvBufEntry *msg;
+
+ qemu_mutex_lock(&ss->lock);
+ if (QTAILQ_EMPTY(&ss->rcvbufs)) {
+ rsp[2] = 0x80; /* Queue empty */
+ goto out;
+ }
+ rsp[3] = 0; /* Channel 0 */
+ *rsp_len += 1;
+ msg = QTAILQ_FIRST(&ss->rcvbufs);
+ memcpy(rsp + 4, msg->buf, msg->len);
+ *rsp_len += msg->len;
+ QTAILQ_REMOVE(&ss->rcvbufs, msg, entry);
+ g_free(msg);
+
+ if (QTAILQ_EMPTY(&ss->rcvbufs)) {
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ ss->msg_flags &= ~IPMI_BMC_MSG_FLAG_RCV_MSG_QUEUE;
+ k->set_atn(s, attn_set(ss), attn_irq_enabled(ss));
+ }
+
+ out:
+ qemu_mutex_unlock(&ss->lock);
+ return;
+}
+
+static unsigned char
+ipmb_checksum(unsigned char *data, int size, unsigned char csum)
+{
+ for (; size > 0; size--, data++) {
+ csum += *data;
+ }
+
+ return -csum;
+}
+
+static void send_msg(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ IPMIRcvBufEntry *msg;
+ uint8_t *buf;
+ uint8_t netfn, rqLun, rsLun, rqSeq;
+
+ IPMI_CHECK_CMD_LEN(3);
+
+ if (cmd[2] != 0) {
+ /* We only handle channel 0 with no options */
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+
+ IPMI_CHECK_CMD_LEN(10);
+ if (cmd[3] != 0x40) {
+ /* We only emulate a MC at address 0x40. */
+ rsp[2] = 0x83; /* NAK on write */
+ goto out;
+ }
+
+ cmd += 3; /* Skip the header. */
+ cmd_len -= 3;
+
+ /*
+ * At this point we "send" the message successfully. Any error will
+ * be returned in the response.
+ */
+ if (ipmb_checksum(cmd, cmd_len, 0) != 0 ||
+ cmd[3] != 0x20) { /* Improper response address */
+ goto out; /* No response */
+ }
+
+ netfn = cmd[1] >> 2;
+ rqLun = cmd[4] & 0x3;
+ rsLun = cmd[1] & 0x3;
+ rqSeq = cmd[4] >> 2;
+
+ if (rqLun != 2) {
+ /* We only support LUN 2 coming back to us. */
+ goto out;
+ }
+
+ msg = g_malloc(sizeof(*msg));
+ msg->buf[0] = ((netfn | 1) << 2) | rqLun; /* NetFN, and make a response */
+ msg->buf[1] = ipmb_checksum(msg->buf, 1, 0);
+ msg->buf[2] = cmd[0]; /* rsSA */
+ msg->buf[3] = (rqSeq << 2) | rsLun;
+ msg->buf[4] = cmd[5]; /* Cmd */
+ msg->buf[5] = 0; /* Completion Code */
+ msg->len = 6;
+
+ if ((cmd[1] >> 2) != IPMI_NETFN_APP || cmd[5] != IPMI_CMD_GET_DEVICE_ID) {
+ /* Not a command we handle. */
+ msg->buf[5] = IPMI_CC_INVALID_CMD;
+ goto end_msg;
+ }
+
+ buf = msg->buf + msg->len; /* After the CC */
+ buf[0] = 0;
+ buf[1] = 0;
+ buf[2] = 0;
+ buf[3] = 0;
+ buf[4] = 0x51;
+ buf[5] = 0;
+ buf[6] = 0;
+ buf[7] = 0;
+ buf[8] = 0;
+ buf[9] = 0;
+ buf[10] = 0;
+ msg->len += 11;
+
+ end_msg:
+ msg->buf[msg->len] = ipmb_checksum(msg->buf, msg->len, 0);
+ msg->len++;
+ qemu_mutex_lock(&ss->lock);
+ QTAILQ_INSERT_TAIL(&ss->rcvbufs, msg, entry);
+ ss->msg_flags |= IPMI_BMC_MSG_FLAG_RCV_MSG_QUEUE;
+ k->set_atn(s, 1, attn_irq_enabled(ss));
+ qemu_mutex_unlock(&ss->lock);
+
+ out:
+ return;
+}
+
+static void do_watchdog_reset(IPMISimBmc *ss)
+{
+ if (IPMI_BMC_WATCHDOG_GET_ACTION(ss) ==
+ IPMI_BMC_WATCHDOG_ACTION_NONE) {
+ ss->watchdog_running = 0;
+ return;
+ }
+ ss->watchdog_preaction_ran = 0;
+
+
+ /* Timeout is in tenths of a second, offset is in seconds */
+ ss->watchdog_expiry = ipmi_getmonotime();
+ ss->watchdog_expiry += ss->watchdog_timeout * 100000000LL;
+ if (IPMI_BMC_WATCHDOG_GET_PRE_ACTION(ss) != IPMI_BMC_WATCHDOG_PRE_NONE) {
+ ss->watchdog_expiry -= ss->watchdog_pretimeout * 1000000000LL;
+ }
+ ss->watchdog_running = 1;
+}
+
+static void reset_watchdog_timer(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ if (!ss->watchdog_initialized) {
+ rsp[2] = 0x80;
+ goto out;
+ }
+ do_watchdog_reset(ss);
+ out:
+ return;
+}
+
+static void set_watchdog_timer(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMIInterface *s = ss->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ unsigned int val;
+
+ IPMI_CHECK_CMD_LEN(8);
+ val = cmd[2] & 0x7; /* Validate use */
+ if (val == 0 || val > 5) {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ val = cmd[3] & 0x7; /* Validate action */
+ switch (val) {
+ case IPMI_BMC_WATCHDOG_ACTION_NONE:
+ break;
+
+ case IPMI_BMC_WATCHDOG_ACTION_RESET:
+ rsp[2] = k->do_hw_op(s, IPMI_RESET_CHASSIS, 1);
+ break;
+
+ case IPMI_BMC_WATCHDOG_ACTION_POWER_DOWN:
+ rsp[2] = k->do_hw_op(s, IPMI_POWEROFF_CHASSIS, 1);
+ break;
+
+ case IPMI_BMC_WATCHDOG_ACTION_POWER_CYCLE:
+ rsp[2] = k->do_hw_op(s, IPMI_POWERCYCLE_CHASSIS, 1);
+ break;
+
+ default:
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ }
+ if (rsp[2]) {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+
+ val = (cmd[3] >> 4) & 0x7; /* Validate preaction */
+ switch (val) {
+ case IPMI_BMC_WATCHDOG_PRE_MSG_INT:
+ case IPMI_BMC_WATCHDOG_PRE_NONE:
+ break;
+
+ case IPMI_BMC_WATCHDOG_PRE_NMI:
+ if (!k->do_hw_op(s, IPMI_SEND_NMI, 1)) {
+ /* NMI not supported. */
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ default:
+ /* We don't support PRE_SMI */
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+
+ ss->watchdog_initialized = 1;
+ ss->watchdog_use = cmd[2] & IPMI_BMC_WATCHDOG_USE_MASK;
+ ss->watchdog_action = cmd[3] & IPMI_BMC_WATCHDOG_ACTION_MASK;
+ ss->watchdog_pretimeout = cmd[4];
+ ss->watchdog_expired &= ~cmd[5];
+ ss->watchdog_timeout = cmd[6] | (((uint16_t) cmd[7]) << 8);
+ if (ss->watchdog_running & IPMI_BMC_WATCHDOG_GET_DONT_STOP(ss)) {
+ do_watchdog_reset(ss);
+ } else {
+ ss->watchdog_running = 0;
+ }
+ out:
+ return;
+}
+
+static void get_watchdog_timer(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(ss->watchdog_use);
+ IPMI_ADD_RSP_DATA(ss->watchdog_action);
+ IPMI_ADD_RSP_DATA(ss->watchdog_pretimeout);
+ IPMI_ADD_RSP_DATA(ss->watchdog_expired);
+ if (ss->watchdog_running) {
+ long timeout;
+ timeout = ((ss->watchdog_expiry - ipmi_getmonotime() + 50000000)
+ / 100000000);
+ IPMI_ADD_RSP_DATA(timeout & 0xff);
+ IPMI_ADD_RSP_DATA((timeout >> 8) & 0xff);
+ } else {
+ IPMI_ADD_RSP_DATA(0);
+ IPMI_ADD_RSP_DATA(0);
+ }
+ out:
+ return;
+}
+
+static void get_sdr_rep_info(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ unsigned int i;
+
+ IPMI_ADD_RSP_DATA(0x51); /* Conform to IPMI 1.5 spec */
+ IPMI_ADD_RSP_DATA(ss->sdr.next_rec_id & 0xff);
+ IPMI_ADD_RSP_DATA((ss->sdr.next_rec_id >> 8) & 0xff);
+ IPMI_ADD_RSP_DATA((MAX_SDR_SIZE - ss->sdr.next_free) & 0xff);
+ IPMI_ADD_RSP_DATA(((MAX_SDR_SIZE - ss->sdr.next_free) >> 8) & 0xff);
+ for (i = 0; i < 4; i++) {
+ IPMI_ADD_RSP_DATA(ss->sdr.last_addition[i]);
+ }
+ for (i = 0; i < 4; i++) {
+ IPMI_ADD_RSP_DATA(ss->sdr.last_clear[i]);
+ }
+ /* Only modal support, reserve supported */
+ IPMI_ADD_RSP_DATA((ss->sdr.overflow << 7) | 0x22);
+ out:
+ return;
+}
+
+static void reserve_sdr_rep(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(ss->sdr.reservation & 0xff);
+ IPMI_ADD_RSP_DATA((ss->sdr.reservation >> 8) & 0xff);
+ out:
+ return;
+}
+
+static void get_sdr(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ unsigned int pos;
+ uint16_t nextrec;
+
+ IPMI_CHECK_CMD_LEN(8);
+ if (cmd[6]) {
+ IPMI_CHECK_RESERVATION(2, ss->sdr.reservation);
+ }
+ pos = 0;
+ if (sdr_find_entry(&ss->sdr, cmd[4] | (cmd[5] << 8),
+ &pos, &nextrec)) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ if (cmd[6] > (ss->sdr.sdr[pos + 4])) {
+ rsp[2] = IPMI_CC_PARM_OUT_OF_RANGE;
+ goto out;
+ }
+
+ IPMI_ADD_RSP_DATA(nextrec & 0xff);
+ IPMI_ADD_RSP_DATA((nextrec >> 8) & 0xff);
+
+ if (cmd[7] == 0xff) {
+ cmd[7] = ss->sdr.sdr[pos + 4] - cmd[6];
+ }
+
+ if ((cmd[7] + *rsp_len) > max_rsp_len) {
+ rsp[2] = IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES;
+ goto out;
+ }
+ memcpy(rsp + *rsp_len, ss->sdr.sdr + pos + cmd[6], cmd[7]);
+ *rsp_len += cmd[7];
+ out:
+ return;
+}
+
+static void add_sdr(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ uint16_t recid;
+
+ if (sdr_add_entry(ss, cmd + 2, cmd_len - 2, &recid)) {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ IPMI_ADD_RSP_DATA(recid & 0xff);
+ IPMI_ADD_RSP_DATA((recid >> 8) & 0xff);
+ out:
+ return;
+}
+
+static void clear_sdr_rep(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_CHECK_CMD_LEN(8);
+ IPMI_CHECK_RESERVATION(2, ss->sdr.reservation);
+ if (cmd[4] != 'C' || cmd[5] != 'L' || cmd[6] != 'R') {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ if (cmd[7] == 0xaa) {
+ ss->sdr.next_free = 0;
+ ss->sdr.overflow = 0;
+ set_timestamp(ss, ss->sdr.last_clear);
+ IPMI_ADD_RSP_DATA(1); /* Erasure complete */
+ sdr_inc_reservation(&ss->sdr);
+ } else if (cmd[7] == 0) {
+ IPMI_ADD_RSP_DATA(1); /* Erasure complete */
+ } else {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ out:
+ return;
+}
+
+static void get_sel_info(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ unsigned int i, val;
+
+ IPMI_ADD_RSP_DATA(0x51); /* Conform to IPMI 1.5 */
+ IPMI_ADD_RSP_DATA(ss->sel.next_free & 0xff);
+ IPMI_ADD_RSP_DATA((ss->sel.next_free >> 8) & 0xff);
+ val = (MAX_SEL_SIZE - ss->sel.next_free) * 16;
+ IPMI_ADD_RSP_DATA(val & 0xff);
+ IPMI_ADD_RSP_DATA((val >> 8) & 0xff);
+ for (i = 0; i < 4; i++) {
+ IPMI_ADD_RSP_DATA(ss->sel.last_addition[i]);
+ }
+ for (i = 0; i < 4; i++) {
+ IPMI_ADD_RSP_DATA(ss->sel.last_clear[i]);
+ }
+ /* Only support Reserve SEL */
+ IPMI_ADD_RSP_DATA((ss->sel.overflow << 7) | 0x02);
+ out:
+ return;
+}
+
+static void reserve_sel(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_ADD_RSP_DATA(ss->sel.reservation & 0xff);
+ IPMI_ADD_RSP_DATA((ss->sel.reservation >> 8) & 0xff);
+ out:
+ return;
+}
+
+static void get_sel_entry(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ unsigned int val;
+
+ IPMI_CHECK_CMD_LEN(8);
+ if (cmd[6]) {
+ IPMI_CHECK_RESERVATION(2, ss->sel.reservation);
+ }
+ if (ss->sel.next_free == 0) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ if (cmd[6] > 15) {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ if (cmd[7] == 0xff) {
+ cmd[7] = 16;
+ } else if ((cmd[7] + cmd[6]) > 16) {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ } else {
+ cmd[7] += cmd[6];
+ }
+
+ val = cmd[4] | (cmd[5] << 8);
+ if (val == 0xffff) {
+ val = ss->sel.next_free - 1;
+ } else if (val >= ss->sel.next_free) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ if ((val + 1) == ss->sel.next_free) {
+ IPMI_ADD_RSP_DATA(0xff);
+ IPMI_ADD_RSP_DATA(0xff);
+ } else {
+ IPMI_ADD_RSP_DATA((val + 1) & 0xff);
+ IPMI_ADD_RSP_DATA(((val + 1) >> 8) & 0xff);
+ }
+ for (; cmd[6] < cmd[7]; cmd[6]++) {
+ IPMI_ADD_RSP_DATA(ss->sel.sel[val][cmd[6]]);
+ }
+ out:
+ return;
+}
+
+static void add_sel_entry(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_CHECK_CMD_LEN(18);
+ if (sel_add_event(ss, cmd + 2)) {
+ rsp[2] = IPMI_CC_OUT_OF_SPACE;
+ goto out;
+ }
+ /* sel_add_event fills in the record number. */
+ IPMI_ADD_RSP_DATA(cmd[2]);
+ IPMI_ADD_RSP_DATA(cmd[3]);
+ out:
+ return;
+}
+
+static void clear_sel(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMI_CHECK_CMD_LEN(8);
+ IPMI_CHECK_RESERVATION(2, ss->sel.reservation);
+ if (cmd[4] != 'C' || cmd[5] != 'L' || cmd[6] != 'R') {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ if (cmd[7] == 0xaa) {
+ ss->sel.next_free = 0;
+ ss->sel.overflow = 0;
+ set_timestamp(ss, ss->sdr.last_clear);
+ IPMI_ADD_RSP_DATA(1); /* Erasure complete */
+ sel_inc_reservation(&ss->sel);
+ } else if (cmd[7] == 0) {
+ IPMI_ADD_RSP_DATA(1); /* Erasure complete */
+ } else {
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ out:
+ return;
+}
+
+static void get_sel_time(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ uint32_t val;
+ struct ipmi_time now;
+
+ ipmi_gettime(&now);
+ val = now.tv_sec + ss->sel.time_offset;
+ IPMI_ADD_RSP_DATA(val & 0xff);
+ IPMI_ADD_RSP_DATA((val >> 8) & 0xff);
+ IPMI_ADD_RSP_DATA((val >> 16) & 0xff);
+ IPMI_ADD_RSP_DATA((val >> 24) & 0xff);
+ out:
+ return;
+}
+
+static void set_sel_time(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ uint32_t val;
+ struct ipmi_time now;
+
+ IPMI_CHECK_CMD_LEN(6);
+ val = cmd[2] | (cmd[3] << 8) | (cmd[4] << 16) | (cmd[5] << 24);
+ ipmi_gettime(&now);
+ ss->sel.time_offset = now.tv_sec - ((long) val);
+ out:
+ return;
+}
+
+static void set_sensor_evt_enable(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMISensor *sens;
+
+ IPMI_CHECK_CMD_LEN(4);
+ if ((cmd[2] > MAX_SENSORS) ||
+ !IPMI_SENSOR_GET_PRESENT(ss->sensors + cmd[2])) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ sens = ss->sensors + cmd[2];
+ switch ((cmd[3] >> 4) & 0x3) {
+ case 0: /* Do not change */
+ break;
+ case 1: /* Enable bits */
+ if (cmd_len > 4) {
+ sens->assert_enable |= cmd[4];
+ }
+ if (cmd_len > 5) {
+ sens->assert_enable |= cmd[5] << 8;
+ }
+ if (cmd_len > 6) {
+ sens->deassert_enable |= cmd[6];
+ }
+ if (cmd_len > 7) {
+ sens->deassert_enable |= cmd[7] << 8;
+ }
+ break;
+ case 2: /* Disable bits */
+ if (cmd_len > 4) {
+ sens->assert_enable &= ~cmd[4];
+ }
+ if (cmd_len > 5) {
+ sens->assert_enable &= ~(cmd[5] << 8);
+ }
+ if (cmd_len > 6) {
+ sens->deassert_enable &= ~cmd[6];
+ }
+ if (cmd_len > 7) {
+ sens->deassert_enable &= ~(cmd[7] << 8);
+ }
+ break;
+ case 3:
+ rsp[2] = IPMI_CC_INVALID_DATA_FIELD;
+ goto out;
+ }
+ IPMI_SENSOR_SET_RET_STATUS(sens, cmd[3]);
+ out:
+ return;
+}
+
+static void get_sensor_evt_enable(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMISensor *sens;
+
+ IPMI_CHECK_CMD_LEN(3);
+ if ((cmd[2] > MAX_SENSORS) ||
+ !IPMI_SENSOR_GET_PRESENT(ss->sensors + cmd[2])) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ sens = ss->sensors + cmd[2];
+ IPMI_ADD_RSP_DATA(IPMI_SENSOR_GET_RET_STATUS(sens));
+ IPMI_ADD_RSP_DATA(sens->assert_enable & 0xff);
+ IPMI_ADD_RSP_DATA((sens->assert_enable >> 8) & 0xff);
+ IPMI_ADD_RSP_DATA(sens->deassert_enable & 0xff);
+ IPMI_ADD_RSP_DATA((sens->deassert_enable >> 8) & 0xff);
+ out:
+ return;
+}
+
+static void rearm_sensor_evts(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMISensor *sens;
+
+ IPMI_CHECK_CMD_LEN(4);
+ if ((cmd[2] > MAX_SENSORS) ||
+ !IPMI_SENSOR_GET_PRESENT(ss->sensors + cmd[2])) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ sens = ss->sensors + cmd[2];
+
+ if ((cmd[3] & 0x80) == 0) {
+ /* Just clear everything */
+ sens->states = 0;
+ goto out;
+ }
+ out:
+ return;
+}
+
+static void get_sensor_evt_status(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMISensor *sens;
+
+ IPMI_CHECK_CMD_LEN(3);
+ if ((cmd[2] > MAX_SENSORS) ||
+ !IPMI_SENSOR_GET_PRESENT(ss->sensors + cmd[2])) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ sens = ss->sensors + cmd[2];
+ IPMI_ADD_RSP_DATA(sens->reading);
+ IPMI_ADD_RSP_DATA(IPMI_SENSOR_GET_RET_STATUS(sens));
+ IPMI_ADD_RSP_DATA(sens->assert_states & 0xff);
+ IPMI_ADD_RSP_DATA((sens->assert_states >> 8) & 0xff);
+ IPMI_ADD_RSP_DATA(sens->deassert_states & 0xff);
+ IPMI_ADD_RSP_DATA((sens->deassert_states >> 8) & 0xff);
+ out:
+ return;
+}
+
+static void get_sensor_reading(IPMISimBmc *ss,
+ uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len,
+ unsigned int max_rsp_len)
+{
+ IPMISensor *sens;
+
+ IPMI_CHECK_CMD_LEN(3);
+ if ((cmd[2] > MAX_SENSORS) ||
+ !IPMI_SENSOR_GET_PRESENT(ss->sensors + cmd[2])) {
+ rsp[2] = IPMI_CC_REQ_ENTRY_NOT_PRESENT;
+ goto out;
+ }
+ sens = ss->sensors + cmd[2];
+ IPMI_ADD_RSP_DATA(sens->reading);
+ IPMI_ADD_RSP_DATA(IPMI_SENSOR_GET_RET_STATUS(sens));
+ IPMI_ADD_RSP_DATA(sens->states & 0xff);
+ if (IPMI_SENSOR_IS_DISCRETE(sens)) {
+ IPMI_ADD_RSP_DATA((sens->states >> 8) & 0xff);
+ }
+ out:
+ return;
+}
+
+static const IPMICmdHandler chassis_cmds[IPMI_NETFN_CHASSIS_MAXCMD] = {
+ [IPMI_CMD_GET_CHASSIS_CAPABILITIES] = chassis_capabilities,
+ [IPMI_CMD_GET_CHASSIS_STATUS] = chassis_status,
+ [IPMI_CMD_CHASSIS_CONTROL] = chassis_control
+};
+static const IPMINetfn chassis_netfn = {
+ .cmd_nums = IPMI_NETFN_CHASSIS_MAXCMD,
+ .cmd_handlers = chassis_cmds
+};
+
+static const IPMICmdHandler
+sensor_event_cmds[IPMI_NETFN_SENSOR_EVENT_MAXCMD] = {
+ [IPMI_CMD_SET_SENSOR_EVT_ENABLE] = set_sensor_evt_enable,
+ [IPMI_CMD_GET_SENSOR_EVT_ENABLE] = get_sensor_evt_enable,
+ [IPMI_CMD_REARM_SENSOR_EVTS] = rearm_sensor_evts,
+ [IPMI_CMD_GET_SENSOR_EVT_STATUS] = get_sensor_evt_status,
+ [IPMI_CMD_GET_SENSOR_READING] = get_sensor_reading
+};
+static const IPMINetfn sensor_event_netfn = {
+ .cmd_nums = IPMI_NETFN_SENSOR_EVENT_MAXCMD,
+ .cmd_handlers = sensor_event_cmds
+};
+
+static const IPMICmdHandler app_cmds[IPMI_NETFN_APP_MAXCMD] = {
+ [IPMI_CMD_GET_DEVICE_ID] = get_device_id,
+ [IPMI_CMD_COLD_RESET] = cold_reset,
+ [IPMI_CMD_WARM_RESET] = warm_reset,
+ [IPMI_CMD_SET_BMC_GLOBAL_ENABLES] = set_bmc_global_enables,
+ [IPMI_CMD_GET_BMC_GLOBAL_ENABLES] = get_bmc_global_enables,
+ [IPMI_CMD_CLR_MSG_FLAGS] = clr_msg_flags,
+ [IPMI_CMD_GET_MSG_FLAGS] = get_msg_flags,
+ [IPMI_CMD_GET_MSG] = get_msg,
+ [IPMI_CMD_SEND_MSG] = send_msg,
+ [IPMI_CMD_READ_EVT_MSG_BUF] = read_evt_msg_buf,
+ [IPMI_CMD_RESET_WATCHDOG_TIMER] = reset_watchdog_timer,
+ [IPMI_CMD_SET_WATCHDOG_TIMER] = set_watchdog_timer,
+ [IPMI_CMD_GET_WATCHDOG_TIMER] = get_watchdog_timer,
+};
+static const IPMINetfn app_netfn = {
+ .cmd_nums = IPMI_NETFN_APP_MAXCMD,
+ .cmd_handlers = app_cmds
+};
+
+static const IPMICmdHandler storage_cmds[IPMI_NETFN_STORAGE_MAXCMD] = {
+ [IPMI_CMD_GET_SDR_REP_INFO] = get_sdr_rep_info,
+ [IPMI_CMD_RESERVE_SDR_REP] = reserve_sdr_rep,
+ [IPMI_CMD_GET_SDR] = get_sdr,
+ [IPMI_CMD_ADD_SDR] = add_sdr,
+ [IPMI_CMD_CLEAR_SDR_REP] = clear_sdr_rep,
+ [IPMI_CMD_GET_SEL_INFO] = get_sel_info,
+ [IPMI_CMD_RESERVE_SEL] = reserve_sel,
+ [IPMI_CMD_GET_SEL_ENTRY] = get_sel_entry,
+ [IPMI_CMD_ADD_SEL_ENTRY] = add_sel_entry,
+ [IPMI_CMD_CLEAR_SEL] = clear_sel,
+ [IPMI_CMD_GET_SEL_TIME] = get_sel_time,
+ [IPMI_CMD_SET_SEL_TIME] = set_sel_time,
+};
+
+static const IPMINetfn storage_netfn = {
+ .cmd_nums = IPMI_NETFN_STORAGE_MAXCMD,
+ .cmd_handlers = storage_cmds
+};
+
+static void register_cmds(IPMISimBmc *s)
+{
+ ipmi_register_netfn(s, IPMI_NETFN_CHASSIS, &chassis_netfn);
+ ipmi_register_netfn(s, IPMI_NETFN_SENSOR_EVENT, &sensor_event_netfn);
+ ipmi_register_netfn(s, IPMI_NETFN_APP, &app_netfn);
+ ipmi_register_netfn(s, IPMI_NETFN_STORAGE, &storage_netfn);
+}
+
+static const uint8_t init_sdrs[] = {
+ /* Watchdog device */
+ 0x00, 0x00, 0x51, 0x02, 40, 0x20, 0x00, 0x00,
+ 0x23, 0x01, 0x63, 0x00, 0x23, 0x6f, 0x0f, 0x01,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8,
+ 'W', 'a', 't', 'c', 'h', 'd', 'o', 'g',
+ /* End */
+ 0xff, 0xff, 0x00, 0x00, 0x00
+};
+
+static void ipmi_sim_init(IPMIBmc *b, Error **errp)
+{
+ unsigned int i;
+ unsigned int next_recid, recid;
+ IPMISimBmc *ss = IPMI_BMC_SIMULATOR(b);
+
+ qemu_mutex_init(&ss->lock);
+ QTAILQ_INIT(&ss->rcvbufs);
+
+ ss->bmc_global_enables = (1 << IPMI_BMC_EVENT_LOG_BIT);
+ ss->device_id = 0x20;
+ ss->ipmi_version = 0x02; /* IPMI 2.0 */
+ for (i = 0; i < 4; i++) {
+ ss->sel.last_addition[i] = 0xff;
+ ss->sel.last_clear[i] = 0xff;
+ ss->sdr.last_addition[i] = 0xff;
+ ss->sdr.last_clear[i] = 0xff;
+ }
+
+ next_recid = 0;
+ for (i = 0;;) {
+ int len;
+ if ((i + 5) > sizeof(init_sdrs)) {
+ error_setg(errp, "Problem with recid 0x%4.4x\n", i);
+ return;
+ }
+ len = init_sdrs[i + 4];
+ recid = init_sdrs[i] | (init_sdrs[i + 1] << 8);
+ if (recid == 0xffff) {
+ break;
+ }
+ if ((i + len) > sizeof(init_sdrs)) {
+ error_setg(errp, "Problem with recid 0x%4.4x\n", i);
+ return;
+ }
+ if (recid != next_recid) {
+ error_setg(errp, "Problem with recid 0x%4.4x\n", i);
+ return;
+ }
+ sdr_add_entry(ss, init_sdrs + i, len, NULL);
+ i += len;
+ }
+
+ ipmi_init_sensors_from_sdrs(ss);
+ register_cmds(ss);
+
+ ss->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ipmi_timeout, ss);
+}
+
+static void ipmi_sim_class_init(ObjectClass *klass, void *data)
+{
+ IPMIBmcClass *bk = IPMI_BMC_CLASS(klass);
+
+ bk->init = ipmi_sim_init;
+ bk->handle_command = ipmi_sim_handle_command;
+}
+
+static const TypeInfo ipmi_sim_type = {
+ .name = TYPE_IPMI_BMC_SIMULATOR,
+ .parent = TYPE_IPMI_BMC,
+ .instance_size = sizeof(IPMISimBmc),
+ .class_init = ipmi_sim_class_init,
+};
+
+static void ipmi_sim_register_types(void)
+{
+ type_register_static(&ipmi_sim_type);
+}
+
+type_init(ipmi_sim_register_types)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 06/17] ipmi: Add an external connection simulation interface
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (4 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 05/17] ipmi: Add a local BMC simulation minyard
@ 2015-04-23 22:57 ` minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 07/17] ipmi: Add tests minyard
` (11 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
This adds an interface for IPMI that connects to a remote
BMC over a chardev (generally a TCP socket). The OpenIPMI
lanserv simulator describes this interface, see that for
interface details.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_extern.c | 457 +++++++++++++++++++++++++++++++++++++
4 files changed, 460 insertions(+)
create mode 100644 hw/ipmi/ipmi_extern.c
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 5d8ad39..2448543 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -13,6 +13,7 @@ CONFIG_ISA_IPMI=y
CONFIG_IPMI_KCS=y
CONFIG_IPMI_BT=y
CONFIG_IPMI_LOCAL=y
+CONFIG_IPMI_EXTERN=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 7b83314..3ed8877 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -13,6 +13,7 @@ CONFIG_ISA_IPMI=y
CONFIG_IPMI_KCS=y
CONFIG_IPMI_BT=y
CONFIG_IPMI_LOCAL=y
+CONFIG_IPMI_EXTERN=y
CONFIG_SERIAL=y
CONFIG_PARALLEL=y
CONFIG_I8254=y
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
index d30a84e..abfa827 100644
--- a/hw/ipmi/Makefile.objs
+++ b/hw/ipmi/Makefile.objs
@@ -3,3 +3,4 @@ common-obj-$(CONFIG_IPMI) += ipmi.o
common-obj-$(CONFIG_IPMI_KCS) += ipmi_kcs.o
common-obj-$(CONFIG_IPMI_BT) += ipmi_bt.o
common-obj-$(CONFIG_IPMI_LOCAL) += ipmi_sim.o
+common-obj-$(CONFIG_IPMI_EXTERN) += ipmi_extern.o
diff --git a/hw/ipmi/ipmi_extern.c b/hw/ipmi/ipmi_extern.c
new file mode 100644
index 0000000..b59ff8a
--- /dev/null
+++ b/hw/ipmi/ipmi_extern.c
@@ -0,0 +1,457 @@
+/*
+ * IPMI BMC external connection
+ *
+ * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+/*
+ * This is designed to connect with OpenIPMI's lanserv serial interface
+ * using the "VM" connection type. See that for details.
+ */
+
+#include <stdint.h>
+#include "qemu/timer.h"
+#include "sysemu/char.h"
+#include "ipmi.h"
+
+#define VM_MSG_CHAR 0xA0 /* Marks end of message */
+#define VM_CMD_CHAR 0xA1 /* Marks end of a command */
+#define VM_ESCAPE_CHAR 0xAA /* Set bit 4 from the next byte to 0 */
+
+#define VM_PROTOCOL_VERSION 1
+#define VM_CMD_VERSION 0xff /* A version number byte follows */
+#define VM_CMD_NOATTN 0x00
+#define VM_CMD_ATTN 0x01
+#define VM_CMD_ATTN_IRQ 0x02
+#define VM_CMD_POWEROFF 0x03
+#define VM_CMD_RESET 0x04
+#define VM_CMD_ENABLE_IRQ 0x05 /* Enable/disable the messaging irq */
+#define VM_CMD_DISABLE_IRQ 0x06
+#define VM_CMD_SEND_NMI 0x07
+#define VM_CMD_CAPABILITIES 0x08
+#define VM_CAPABILITIES_POWER 0x01
+#define VM_CAPABILITIES_RESET 0x02
+#define VM_CAPABILITIES_IRQ 0x04
+#define VM_CAPABILITIES_NMI 0x08
+#define VM_CAPABILITIES_ATTN 0x10
+
+#define IPMI_BMC_EXTERN(obj) OBJECT_CHECK(IPMIExternBmc, (obj), \
+ TYPE_IPMI_BMC_EXTERN)
+typedef struct IPMIExternBmc {
+ IPMIBmc parent;
+
+ int connected;
+ int is_listen;
+
+ unsigned char inbuf[MAX_IPMI_MSG_SIZE + 2];
+ unsigned int inpos;
+ int in_escape;
+ int in_too_many;
+ int waiting_rsp;
+ int sending_cmd;
+
+ unsigned char outbuf[(MAX_IPMI_MSG_SIZE + 2) * 2 + 1];
+ unsigned int outpos;
+ unsigned int outlen;
+
+ struct QEMUTimer *extern_timer;
+
+ /* A reset event is pending to be sent upstream. */
+ bool send_reset;
+} IPMIExternBmc;
+
+static int can_receive(void *opaque);
+static void receive(void *opaque, const uint8_t *buf, int size);
+static void chr_event(void *opaque, int event);
+
+static unsigned char
+ipmb_checksum(const unsigned char *data, int size, unsigned char start)
+{
+ unsigned char csum = start;
+
+ for (; size > 0; size--, data++) {
+ csum += *data;
+ }
+ return csum;
+}
+
+static void continue_send(IPMIExternBmc *es)
+{
+ if (es->outlen == 0) {
+ goto check_reset;
+ }
+ send:
+ es->outpos += qemu_chr_fe_write(es->parent.chr, es->outbuf + es->outpos,
+ es->outlen - es->outpos);
+ if (es->outpos < es->outlen) {
+ /* Not fully transmitted, try again in a 10ms */
+ timer_mod_ns(es->extern_timer,
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 10000000);
+ } else {
+ /* Sent */
+ es->outlen = 0;
+ es->outpos = 0;
+ if (!es->sending_cmd) {
+ es->waiting_rsp = 1;
+ } else {
+ es->sending_cmd = 0;
+ }
+ check_reset:
+ if (es->connected && es->send_reset) {
+ /* Send the reset */
+ es->outbuf[0] = VM_CMD_RESET;
+ es->outbuf[1] = VM_CMD_CHAR;
+ es->outlen = 2;
+ es->outpos = 0;
+ es->send_reset = 0;
+ es->sending_cmd = 1;
+ goto send;
+ }
+
+ if (es->waiting_rsp) {
+ /* Make sure we get a response within 4 seconds. */
+ timer_mod_ns(es->extern_timer,
+ qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 4000000000ULL);
+ }
+ }
+ return;
+}
+
+static void extern_timeout(void *opaque)
+{
+ IPMIExternBmc *es = opaque;
+ IPMIInterface *s = es->parent.intf;
+
+ if (es->connected) {
+ if (es->waiting_rsp && (es->outlen == 0)) {
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ /* The message response timed out, return an error. */
+ es->waiting_rsp = 0;
+ es->inbuf[1] = es->outbuf[1] | 0x04;
+ es->inbuf[2] = es->outbuf[2];
+ es->inbuf[3] = IPMI_CC_TIMEOUT;
+ k->handle_rsp(s, es->outbuf[0], es->inbuf + 1, 3);
+ } else {
+ continue_send(es);
+ }
+ }
+}
+
+static void addchar(IPMIExternBmc *es, unsigned char ch)
+{
+ switch (ch) {
+ case VM_MSG_CHAR:
+ case VM_CMD_CHAR:
+ case VM_ESCAPE_CHAR:
+ es->outbuf[es->outlen] = VM_ESCAPE_CHAR;
+ es->outlen++;
+ ch |= 0x10;
+ /* No break */
+
+ default:
+ es->outbuf[es->outlen] = ch;
+ es->outlen++;
+ }
+}
+
+static void ipmi_extern_handle_command(IPMIBmc *b,
+ uint8_t *cmd, unsigned int cmd_len,
+ unsigned int max_cmd_len,
+ uint8_t msg_id)
+{
+ IPMIExternBmc *es = IPMI_BMC_EXTERN(b);
+ IPMIInterface *s = es->parent.intf;
+ uint8_t err = 0, csum;
+ unsigned int i;
+
+ if (es->outlen) {
+ /* We already have a command queued. Shouldn't ever happen. */
+ fprintf(stderr, "IPMI KCS: Got command when not finished with the"
+ " previous commmand\n");
+ abort();
+ }
+
+ /* If it's too short or it was truncated, return an error. */
+ if (cmd_len < 2) {
+ err = IPMI_CC_REQUEST_DATA_LENGTH_INVALID;
+ } else if ((cmd_len > max_cmd_len) || (cmd_len > MAX_IPMI_MSG_SIZE)) {
+ err = IPMI_CC_REQUEST_DATA_TRUNCATED;
+ } else if (!es->connected) {
+ err = IPMI_CC_BMC_INIT_IN_PROGRESS;
+ }
+ if (err) {
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ unsigned char rsp[3];
+ rsp[0] = cmd[0] | 0x04;
+ rsp[1] = cmd[1];
+ rsp[2] = err;
+ es->waiting_rsp = 0;
+ k->handle_rsp(s, msg_id, rsp, 3);
+ goto out;
+ }
+
+ addchar(es, msg_id);
+ for (i = 0; i < cmd_len; i++) {
+ addchar(es, cmd[i]);
+ }
+ csum = ipmb_checksum(&msg_id, 1, 0);
+ addchar(es, -ipmb_checksum(cmd, cmd_len, csum));
+
+ es->outbuf[es->outlen] = VM_MSG_CHAR;
+ es->outlen++;
+
+ /* Start the transmit */
+ continue_send(es);
+
+ out:
+ return;
+}
+
+static void handle_hw_op(IPMIExternBmc *es, unsigned char hw_op)
+{
+ IPMIInterface *s = es->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ switch (hw_op) {
+ case VM_CMD_VERSION:
+ /* We only support one version at this time. */
+ break;
+
+ case VM_CMD_NOATTN:
+ k->set_atn(s, 0, 0);
+ break;
+
+ case VM_CMD_ATTN:
+ k->set_atn(s, 1, 0);
+ break;
+
+ case VM_CMD_ATTN_IRQ:
+ k->set_atn(s, 1, 1);
+ break;
+
+ case VM_CMD_POWEROFF:
+ k->do_hw_op(s, IPMI_POWEROFF_CHASSIS, 0);
+ break;
+
+ case VM_CMD_RESET:
+ k->do_hw_op(s, IPMI_RESET_CHASSIS, 0);
+ break;
+
+ case VM_CMD_ENABLE_IRQ:
+ k->set_irq_enable(s, 1);
+ break;
+
+ case VM_CMD_DISABLE_IRQ:
+ k->set_irq_enable(s, 0);
+ break;
+
+ case VM_CMD_SEND_NMI:
+ k->do_hw_op(s, IPMI_SEND_NMI, 0);
+ break;
+ }
+}
+
+static void handle_msg(IPMIExternBmc *es)
+{
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(es->parent.intf);
+
+ if (es->in_escape) {
+ ipmi_debug("msg escape not ended\n");
+ return;
+ }
+ if (es->inpos < 5) {
+ ipmi_debug("msg too short\n");
+ return;
+ }
+ if (es->in_too_many) {
+ es->inbuf[3] = IPMI_CC_REQUEST_DATA_TRUNCATED;
+ es->inpos = 4;
+ } else if (ipmb_checksum(es->inbuf, es->inpos, 0) != 0) {
+ ipmi_debug("msg checksum failure\n");
+ return;
+ } else {
+ es->inpos--; /* Remove checkum */
+ }
+
+ timer_del(es->extern_timer);
+ es->waiting_rsp = 0;
+ k->handle_rsp(es->parent.intf, es->inbuf[0], es->inbuf + 1, es->inpos - 1);
+}
+
+static int can_receive(void *opaque)
+{
+ return 1;
+}
+
+static void receive(void *opaque, const uint8_t *buf, int size)
+{
+ IPMIExternBmc *es = opaque;
+ int i;
+ unsigned char hw_op;
+
+ for (i = 0; i < size; i++) {
+ unsigned char ch = buf[i];
+
+ switch (ch) {
+ case VM_MSG_CHAR:
+ handle_msg(es);
+ es->in_too_many = 0;
+ es->inpos = 0;
+ break;
+
+ case VM_CMD_CHAR:
+ if (es->in_too_many) {
+ ipmi_debug("cmd in too many\n");
+ es->in_too_many = 0;
+ es->inpos = 0;
+ break;
+ }
+ if (es->in_escape) {
+ ipmi_debug("cmd in escape\n");
+ es->in_too_many = 0;
+ es->inpos = 0;
+ es->in_escape = 0;
+ break;
+ }
+ es->in_too_many = 0;
+ if (es->inpos < 1) {
+ break;
+ }
+ hw_op = es->inbuf[0];
+ es->inpos = 0;
+ goto out_hw_op;
+ break;
+
+ case VM_ESCAPE_CHAR:
+ es->in_escape = 1;
+ break;
+
+ default:
+ if (es->in_escape) {
+ ch &= ~0x10;
+ es->in_escape = 0;
+ }
+ if (es->in_too_many) {
+ break;
+ }
+ if (es->inpos >= sizeof(es->inbuf)) {
+ es->in_too_many = 1;
+ break;
+ }
+ es->inbuf[es->inpos] = ch;
+ es->inpos++;
+ break;
+ }
+ }
+ return;
+
+ out_hw_op:
+ handle_hw_op(es, hw_op);
+}
+
+static void chr_event(void *opaque, int event)
+{
+ IPMIExternBmc *es = opaque;
+ IPMIInterface *s = es->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+ unsigned char v;
+
+ switch (event) {
+ case CHR_EVENT_OPENED:
+ es->connected = 1;
+ es->outpos = 0;
+ es->outlen = 0;
+ addchar(es, VM_CMD_VERSION);
+ addchar(es, VM_PROTOCOL_VERSION);
+ es->outbuf[es->outlen] = VM_CMD_CHAR;
+ es->outlen++;
+ addchar(es, VM_CMD_CAPABILITIES);
+ v = VM_CAPABILITIES_IRQ | VM_CAPABILITIES_ATTN;
+ if (k->do_hw_op(es->parent.intf, IPMI_POWEROFF_CHASSIS, 1) == 0) {
+ v |= VM_CAPABILITIES_POWER;
+ }
+ if (k->do_hw_op(es->parent.intf, IPMI_RESET_CHASSIS, 1) == 0) {
+ v |= VM_CAPABILITIES_RESET;
+ }
+ if (k->do_hw_op(es->parent.intf, IPMI_SEND_NMI, 1) == 0) {
+ v |= VM_CAPABILITIES_NMI;
+ }
+ addchar(es, v);
+ es->outbuf[es->outlen] = VM_CMD_CHAR;
+ es->outlen++;
+ es->sending_cmd = 0;
+ continue_send(es);
+ break;
+
+ case CHR_EVENT_CLOSED:
+ if (!es->connected) {
+ return;
+ }
+ es->connected = 0;
+ if (es->waiting_rsp) {
+ es->waiting_rsp = 0;
+ es->inbuf[1] = es->outbuf[1] | 0x04;
+ es->inbuf[2] = es->outbuf[2];
+ es->inbuf[3] = IPMI_CC_BMC_INIT_IN_PROGRESS;
+ k->handle_rsp(s, es->outbuf[0], es->inbuf + 1, 3);
+ }
+ break;
+ }
+}
+
+static void ipmi_extern_handle_reset(IPMIBmc *b)
+{
+ IPMIExternBmc *es = IPMI_BMC_EXTERN(b);
+
+ es->send_reset = 1;
+ continue_send(es);
+}
+
+static void ipmi_extern_init(IPMIBmc *b, Error **errp)
+{
+ IPMIExternBmc *es = IPMI_BMC_EXTERN(b);
+
+ es->extern_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, extern_timeout, es);
+ qemu_chr_add_handlers(es->parent.chr, can_receive, receive, chr_event, es);
+}
+
+static void ipmi_extern_class_init(ObjectClass *klass, void *data)
+{
+ IPMIBmcClass *bk = IPMI_BMC_CLASS(klass);
+
+ bk->init = ipmi_extern_init;
+ bk->handle_command = ipmi_extern_handle_command;
+ bk->handle_reset = ipmi_extern_handle_reset;
+}
+
+static const TypeInfo ipmi_extern_type = {
+ .name = TYPE_IPMI_BMC_EXTERN,
+ .parent = TYPE_IPMI_BMC,
+ .instance_size = sizeof(IPMIExternBmc),
+ .class_init = ipmi_extern_class_init,
+};
+
+static void ipmi_extern_register_types(void)
+{
+ type_register_static(&ipmi_extern_type);
+}
+
+type_init(ipmi_extern_register_types)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 07/17] ipmi: Add tests
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (5 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 06/17] ipmi: Add an external connection simulation interface minyard
@ 2015-04-23 22:57 ` minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 08/17] ipmi: Add documentation minyard
` (10 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
Test the KCS interface with a local BMC and a BT interface with an
external BMC.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
tests/Makefile | 4 +
tests/ipmi-bt-test.c | 440 ++++++++++++++++++++++++++++++++++++++++++++++++++
tests/ipmi-kcs-test.c | 294 +++++++++++++++++++++++++++++++++
3 files changed, 738 insertions(+)
create mode 100644 tests/ipmi-bt-test.c
create mode 100644 tests/ipmi-kcs-test.c
diff --git a/tests/Makefile b/tests/Makefile
index 55aa745..404547c 100644
--- a/tests/Makefile
+++ b/tests/Makefile
@@ -146,6 +146,8 @@ gcov-files-i386-y += hw/block/hd-geometry.c
check-qtest-i386-y += tests/boot-order-test$(EXESUF)
check-qtest-i386-y += tests/bios-tables-test$(EXESUF)
check-qtest-i386-y += tests/rtc-test$(EXESUF)
+check-qtest-i386-y += tests/ipmi-kcs-test$(EXESUF)
+check-qtest-i386-y += tests/ipmi-bt-test$(EXESUF)
check-qtest-i386-y += tests/i440fx-test$(EXESUF)
check-qtest-i386-y += tests/fw_cfg-test$(EXESUF)
check-qtest-i386-y += tests/drive_del-test$(EXESUF)
@@ -326,6 +328,8 @@ tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y)
tests/fdc-test$(EXESUF): tests/fdc-test.o
tests/ide-test$(EXESUF): tests/ide-test.o $(libqos-pc-obj-y)
tests/ahci-test$(EXESUF): tests/ahci-test.o $(libqos-pc-obj-y)
+tests/ipmi-kcs-test$(EXESUF): tests/ipmi-kcs-test.o
+tests/ipmi-bt-test$(EXESUF): tests/ipmi-bt-test.o
tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o
tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y)
tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o $(libqos-obj-y)
diff --git a/tests/ipmi-bt-test.c b/tests/ipmi-bt-test.c
new file mode 100644
index 0000000..c1da325
--- /dev/null
+++ b/tests/ipmi-bt-test.c
@@ -0,0 +1,440 @@
+/*
+ * IPMI BT test cases, using the external interface for checking
+ *
+ * Copyright (c) 2012 Corey Minyard <cminyard@mvista.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+
+#include <sys/socket.h>
+#include <netinet/in.h>
+#include <netinet/ip.h>
+#include <netinet/tcp.h>
+
+#include <glib.h>
+
+#include "libqtest.h"
+#include "qemu-common.h"
+
+#define IPMI_IRQ 5
+
+#define IPMI_BT_BASE 0xe4
+
+#define IPMI_BT_CTLREG_CLR_WR_PTR 0
+#define IPMI_BT_CTLREG_CLR_RD_PTR 1
+#define IPMI_BT_CTLREG_H2B_ATN 2
+#define IPMI_BT_CTLREG_B2H_ATN 3
+#define IPMI_BT_CTLREG_SMS_ATN 4
+#define IPMI_BT_CTLREG_H_BUSY 6
+#define IPMI_BT_CTLREG_B_BUSY 7
+
+#define IPMI_BT_CTLREG_GET(b) ((bt_get_ctrlreg() >> (b)) & 1)
+#define IPMI_BT_CTLREG_GET_H2B_ATN() IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_H2B_ATN)
+#define IPMI_BT_CTLREG_GET_B2H_ATN() IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_B2H_ATN)
+#define IPMI_BT_CTLREG_GET_SMS_ATN() IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_SMS_ATN)
+#define IPMI_BT_CTLREG_GET_H_BUSY() IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_H_BUSY)
+#define IPMI_BT_CTLREG_GET_B_BUSY() IPMI_BT_CTLREG_GET(IPMI_BT_CTLREG_B_BUSY)
+
+#define IPMI_BT_CTLREG_SET(b) bt_write_ctrlreg(1 << (b))
+#define IPMI_BT_CTLREG_SET_CLR_WR_PTR() IPMI_BT_CTLREG_SET( \
+ IPMI_BT_CTLREG_CLR_WR_PTR)
+#define IPMI_BT_CTLREG_SET_CLR_RD_PTR() IPMI_BT_CTLREG_SET( \
+ IPMI_BT_CTLREG_CLR_RD_PTR)
+#define IPMI_BT_CTLREG_SET_H2B_ATN() IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_H2B_ATN)
+#define IPMI_BT_CTLREG_SET_B2H_ATN() IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_B2H_ATN)
+#define IPMI_BT_CTLREG_SET_SMS_ATN() IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_SMS_ATN)
+#define IPMI_BT_CTLREG_SET_H_BUSY() IPMI_BT_CTLREG_SET(IPMI_BT_CTLREG_H_BUSY)
+
+static int bt_ints_enabled;
+
+static uint8_t bt_get_ctrlreg(void)
+{
+ return inb(IPMI_BT_BASE);
+}
+
+static void bt_write_ctrlreg(uint8_t val)
+{
+ outb(IPMI_BT_BASE, val);
+}
+
+static uint8_t bt_get_buf(void)
+{
+ return inb(IPMI_BT_BASE + 1);
+}
+
+static void bt_write_buf(uint8_t val)
+{
+ outb(IPMI_BT_BASE + 1, val);
+}
+
+static uint8_t bt_get_irqreg(void)
+{
+ return inb(IPMI_BT_BASE + 2);
+}
+
+static void bt_write_irqreg(uint8_t val)
+{
+ outb(IPMI_BT_BASE + 2, val);
+}
+
+static void bt_wait_b_busy(void)
+{
+ unsigned int count = 1000;
+ while (IPMI_BT_CTLREG_GET_B_BUSY() != 0) {
+ g_assert(--count != 0);
+ }
+}
+
+static void bt_wait_b2h_atn(void)
+{
+ unsigned int count = 1000;
+ while (IPMI_BT_CTLREG_GET_B2H_ATN() == 0) {
+ g_assert(--count != 0);
+ }
+}
+
+
+static int emu_lfd;
+static int emu_fd;
+static in_port_t emu_port;
+static uint8_t inbuf[100];
+static unsigned int inbuf_len;
+static unsigned int inbuf_pos;
+static int last_was_aa;
+
+static void read_emu_data(void)
+{
+ fd_set readfds;
+ int rv;
+ struct timeval tv;
+
+ FD_ZERO(&readfds);
+ FD_SET(emu_fd, &readfds);
+ tv.tv_sec = 10;
+ tv.tv_usec = 0;
+ rv = select(emu_fd + 1, &readfds, NULL, NULL, &tv);
+ if (rv == -1) {
+ perror("select");
+ }
+ g_assert(rv == 1);
+ rv = read(emu_fd, inbuf, sizeof(inbuf));
+ if (rv == -1) {
+ perror("read");
+ }
+ g_assert(rv > 0);
+ inbuf_len = rv;
+ inbuf_pos = 0;
+}
+
+static void write_emu_msg(uint8_t *msg, unsigned int len)
+{
+ int rv;
+
+#ifdef DEBUG_TEST
+ {
+ unsigned int i;
+ printf("sending:");
+ for (i = 0; i < len; i++) {
+ printf(" %2.2x", msg[i]);
+ }
+ printf("\n");
+ }
+#endif
+ rv = write(emu_fd, msg, len);
+ g_assert(rv == len);
+}
+
+static void get_emu_msg(uint8_t *msg, unsigned int *len)
+{
+ unsigned int outpos = 0;
+
+ for (;;) {
+ while (inbuf_pos < inbuf_len) {
+ uint8_t ch = inbuf[inbuf_pos++];
+
+ g_assert(outpos < *len);
+ if (last_was_aa) {
+ assert(ch & 0x10);
+ msg[outpos++] = ch & ~0x10;
+ last_was_aa = 0;
+ } else if (ch == 0xaa) {
+ last_was_aa = 1;
+ } else {
+ msg[outpos++] = ch;
+ if ((ch == 0xa0) || (ch == 0xa1)) {
+ /* Message complete */
+ *len = outpos;
+ goto done;
+ }
+ }
+ }
+ read_emu_data();
+ }
+ done:
+#ifdef DEBUG_TEST
+ {
+ unsigned int i;
+ printf("Msg:");
+ for (i = 0; i < outpos; i++) {
+ printf(" %2.2x", msg[i]);
+ }
+ printf("\n");
+ }
+#endif
+ return;
+}
+
+static uint8_t
+ipmb_checksum(const unsigned char *data, int size, unsigned char start)
+{
+ unsigned char csum = start;
+
+ for (; size > 0; size--, data++) {
+ csum += *data;
+ }
+ return csum;
+}
+
+static uint8_t get_dev_id_cmd[] = { 0x18, 0x01 };
+static uint8_t get_dev_id_rsp[] = { 0x1c, 0x01, 0x00, 0x20, 0x00, 0x00, 0x00,
+ 0x02, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+static uint8_t set_bmc_globals_cmd[] = { 0x18, 0x2e, 0x0f };
+static uint8_t set_bmc_globals_rsp[] = { 0x1c, 0x2e, 0x00 };
+static uint8_t enable_irq_cmd[] = { 0x05, 0xa1 };
+
+static void emu_msg_handler(void)
+{
+ uint8_t msg[100];
+ unsigned int msg_len = sizeof(msg);
+
+ get_emu_msg(msg, &msg_len);
+ g_assert(msg_len >= 5);
+ g_assert(msg[msg_len - 1] == 0xa0);
+ msg_len--;
+ g_assert(ipmb_checksum(msg, msg_len, 0) == 0);
+ msg_len--;
+ if ((msg[1] == get_dev_id_cmd[0]) && (msg[2] == get_dev_id_cmd[1])) {
+ memcpy(msg + 1, get_dev_id_rsp, sizeof(get_dev_id_rsp));
+ msg_len = sizeof(get_dev_id_rsp) + 1;
+ msg[msg_len] = -ipmb_checksum(msg, msg_len, 0);
+ msg_len++;
+ msg[msg_len++] = 0xa0;
+ write_emu_msg(msg, msg_len);
+ } else if ((msg[1] == set_bmc_globals_cmd[0]) &&
+ (msg[2] == set_bmc_globals_cmd[1])) {
+ memcpy(msg + 1, set_bmc_globals_rsp, sizeof(set_bmc_globals_rsp));
+ msg_len = sizeof(set_bmc_globals_rsp) + 1;
+ msg[msg_len] = -ipmb_checksum(msg, msg_len, 0);
+ msg_len++;
+ msg[msg_len++] = 0xa0;
+ write_emu_msg(msg, msg_len);
+ write_emu_msg(enable_irq_cmd, sizeof(enable_irq_cmd));
+ } else {
+ g_assert(0);
+ }
+}
+
+static void bt_cmd(uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len)
+{
+ unsigned int i, len, j = 0;
+ uint8_t seq = 5;
+
+ /* Should be idle */
+ g_assert(bt_get_ctrlreg() == 0);
+
+ bt_wait_b_busy();
+ IPMI_BT_CTLREG_SET_CLR_WR_PTR();
+ bt_write_buf(cmd_len + 1);
+ bt_write_buf(cmd[0]);
+ bt_write_buf(seq);
+ for (i = 1; i < cmd_len; i++) {
+ bt_write_buf(cmd[i]);
+ }
+ IPMI_BT_CTLREG_SET_H2B_ATN();
+
+ emu_msg_handler(); /* We should get a message on the socket here. */
+
+ bt_wait_b2h_atn();
+ if (bt_ints_enabled) {
+ g_assert((bt_get_irqreg() & 0x02) == 0x02);
+ g_assert(get_irq(IPMI_IRQ));
+ bt_write_irqreg(0x03);
+ } else {
+ g_assert(!get_irq(IPMI_IRQ));
+ }
+ IPMI_BT_CTLREG_SET_H_BUSY();
+ IPMI_BT_CTLREG_SET_B2H_ATN();
+ IPMI_BT_CTLREG_SET_CLR_RD_PTR();
+ len = bt_get_buf();
+ g_assert(len >= 4);
+ rsp[0] = bt_get_buf();
+ assert(bt_get_buf() == seq);
+ len--;
+ for (j = 1; j < len; j++) {
+ rsp[j] = bt_get_buf();
+ }
+ IPMI_BT_CTLREG_SET_H_BUSY();
+ *rsp_len = j;
+}
+
+
+/*
+ * We should get a connect request and a short message with capabilities.
+ */
+static void test_connect(void)
+{
+ fd_set readfds;
+ int rv;
+ int val;
+ struct timeval tv;
+ uint8_t msg[100];
+ unsigned int msglen;
+ static uint8_t exp1[] = { 0xff, 0x01, 0xa1 }; /* A protocol version */
+ static uint8_t exp2[] = { 0x08, 0x1f, 0xa1 }; /* A capabilities cmd */
+ static uint8_t exp3[] = { 0x04, 0xa1 }; /* A reset is reported */
+
+ FD_ZERO(&readfds);
+ FD_SET(emu_lfd, &readfds);
+ tv.tv_sec = 10;
+ tv.tv_usec = 0;
+ rv = select(emu_lfd + 1, &readfds, NULL, NULL, &tv);
+ g_assert(rv == 1);
+ emu_fd = accept(emu_lfd, NULL, 0);
+ if (emu_fd < 0) {
+ perror("accept");
+ }
+ g_assert(emu_fd >= 0);
+
+ val = 1;
+ rv = setsockopt(emu_fd, IPPROTO_TCP, TCP_NODELAY, &val, sizeof(val));
+ g_assert(rv != -1);
+
+ /* Report our version */
+ write_emu_msg(exp1, sizeof(exp1));
+
+ /* Validate that we get the info we expect. */
+ msglen = sizeof(msg);
+ get_emu_msg(msg, &msglen);
+ g_assert(msglen == sizeof(exp1));
+ g_assert(memcmp(msg, exp1, msglen) == 0);
+ msglen = sizeof(msg);
+ get_emu_msg(msg, &msglen);
+ g_assert(msglen == sizeof(exp2));
+ g_assert(memcmp(msg, exp2, msglen) == 0);
+ msglen = sizeof(msg);
+ get_emu_msg(msg, &msglen);
+ g_assert(msglen == sizeof(exp3));
+ g_assert(memcmp(msg, exp3, msglen) == 0);
+}
+
+/*
+ * Send a get_device_id to do a basic test.
+ */
+static void test_bt_base(void)
+{
+ uint8_t rsp[20];
+ unsigned int rsplen = sizeof(rsp);
+
+ bt_cmd(get_dev_id_cmd, sizeof(get_dev_id_cmd), rsp, &rsplen);
+ g_assert(rsplen == sizeof(get_dev_id_rsp));
+ g_assert(memcmp(get_dev_id_rsp, rsp, rsplen) == 0);
+}
+
+/*
+ * Enable IRQs for the interface.
+ */
+static void test_enable_irq(void)
+{
+ uint8_t rsp[20];
+ unsigned int rsplen = sizeof(rsp);
+
+ bt_cmd(set_bmc_globals_cmd, sizeof(set_bmc_globals_cmd), rsp, &rsplen);
+ g_assert(rsplen == sizeof(set_bmc_globals_rsp));
+ g_assert(memcmp(set_bmc_globals_rsp, rsp, rsplen) == 0);
+ bt_write_irqreg(0x01);
+ bt_ints_enabled = 1;
+}
+
+/*
+ * Create a local TCP socket with any port, then save off the port we got.
+ */
+static void open_socket(void)
+{
+ struct sockaddr_in myaddr;
+ socklen_t addrlen;
+
+ myaddr.sin_family = AF_INET;
+ myaddr.sin_addr.s_addr = htonl(INADDR_LOOPBACK);
+ myaddr.sin_port = 0;
+ emu_lfd = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP);
+ if (emu_lfd == -1) {
+ perror("socket");
+ exit(1);
+ }
+ if (bind(emu_lfd, (struct sockaddr *) &myaddr, sizeof(myaddr)) == -1) {
+ perror("bind");
+ exit(1);
+ }
+ addrlen = sizeof(myaddr);
+ if (getsockname(emu_lfd, (struct sockaddr *) &myaddr , &addrlen) == -1) {
+ perror("getsockname");
+ exit(1);
+ }
+ emu_port = ntohs(myaddr.sin_port);
+ assert(listen(emu_lfd, 1) != -1);
+}
+
+int main(int argc, char **argv)
+{
+ const char *arch = qtest_get_arch();
+ char *cmdline;
+ int ret;
+
+ /* Check architecture */
+ if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
+ g_test_message("Skipping test for non-x86\n");
+ return 0;
+ }
+
+ open_socket();
+
+ /* Run the tests */
+ g_test_init(&argc, &argv, NULL);
+
+ cmdline = g_strdup_printf("-vnc none"
+ " -chardev socket,id=ipmi0,host=localhost,port=%d,reconnect=10"
+ " -device isa-ipmi,interface=bt,chardev=ipmi0", emu_port);
+ qtest_start(cmdline);
+ qtest_irq_intercept_in(global_qtest, "ioapic");
+ qtest_add_func("/ipmi/extern/connect", test_connect);
+ qtest_add_func("/ipmi/extern/bt_base", test_bt_base);
+ qtest_add_func("/ipmi/extern/bt_enable_irq", test_enable_irq);
+ qtest_add_func("/ipmi/extern/bt_base_irq", test_bt_base);
+ ret = g_test_run();
+ qtest_quit(global_qtest);
+
+ return ret;
+}
diff --git a/tests/ipmi-kcs-test.c b/tests/ipmi-kcs-test.c
new file mode 100644
index 0000000..e2e1bdb
--- /dev/null
+++ b/tests/ipmi-kcs-test.c
@@ -0,0 +1,294 @@
+/*
+ * IPMI KCS test cases, using the local interface.
+ *
+ * Copyright (c) 2012 Corey Minyard <cminyard@mvista.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <stdio.h>
+
+#include <glib.h>
+
+#include "libqtest.h"
+
+#define IPMI_IRQ 5
+
+#define IPMI_KCS_BASE 0xca2
+
+#define IPMI_KCS_STATUS_ABORT 0x60
+#define IPMI_KCS_CMD_WRITE_START 0x61
+#define IPMI_KCS_CMD_WRITE_END 0x62
+#define IPMI_KCS_CMD_READ 0x68
+
+#define IPMI_KCS_ABORTED_BY_CMD 0x01
+
+#define IPMI_KCS_CMDREG_GET_STATE() ((kcs_get_cmdreg() >> 6) & 3)
+#define IPMI_KCS_STATE_IDLE 0
+#define IPMI_KCS_STATE_READ 1
+#define IPMI_KCS_STATE_WRITE 2
+#define IPMI_KCS_STATE_ERROR 3
+#define IPMI_KCS_CMDREG_GET_CD() ((kcs_get_cmdreg() >> 3) & 1)
+#define IPMI_KCS_CMDREG_GET_ATN() ((kcs_get_cmdreg() >> 2) & 1)
+#define IPMI_KCS_CMDREG_GET_IBF() ((kcs_get_cmdreg() >> 1) & 1)
+#define IPMI_KCS_CMDREG_GET_OBF() ((kcs_get_cmdreg() >> 0) & 1)
+
+static int kcs_ints_enabled;
+
+static uint8_t kcs_get_cmdreg(void)
+{
+ return inb(IPMI_KCS_BASE + 1);
+}
+
+static void kcs_write_cmdreg(uint8_t val)
+{
+ outb(IPMI_KCS_BASE + 1, val);
+}
+
+static uint8_t kcs_get_datareg(void)
+{
+ return inb(IPMI_KCS_BASE);
+}
+
+static void kcs_write_datareg(uint8_t val)
+{
+ outb(IPMI_KCS_BASE, val);
+}
+
+static void kcs_wait_ibf(void)
+{
+ unsigned int count = 1000;
+ while (IPMI_KCS_CMDREG_GET_IBF() != 0) {
+ g_assert(--count != 0);
+ }
+}
+
+static void kcs_wait_obf(void)
+{
+ unsigned int count = 1000;
+ while (IPMI_KCS_CMDREG_GET_OBF() == 0) {
+ g_assert(--count != 0);
+ }
+}
+
+static void kcs_clear_obf(void)
+{
+ if (kcs_ints_enabled) {
+ g_assert(get_irq(IPMI_IRQ));
+ } else {
+ g_assert(!get_irq(IPMI_IRQ));
+ }
+ g_assert(IPMI_KCS_CMDREG_GET_OBF() == 1);
+ kcs_get_datareg();
+ g_assert(IPMI_KCS_CMDREG_GET_OBF() == 0);
+ g_assert(!get_irq(IPMI_IRQ));
+}
+
+static void kcs_check_state(uint8_t state)
+{
+ g_assert(IPMI_KCS_CMDREG_GET_STATE() == state);
+}
+
+static void kcs_cmd(uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len)
+{
+ unsigned int i, j = 0;
+
+ /* Should be idle */
+ g_assert(kcs_get_cmdreg() == 0);
+
+ kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_START);
+ kcs_wait_ibf();
+ kcs_check_state(IPMI_KCS_STATE_WRITE);
+ kcs_clear_obf();
+ for (i = 0; i < cmd_len; i++) {
+ kcs_write_datareg(cmd[i]);
+ kcs_wait_ibf();
+ kcs_check_state(IPMI_KCS_STATE_WRITE);
+ kcs_clear_obf();
+ }
+ kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_END);
+ kcs_wait_ibf();
+ kcs_check_state(IPMI_KCS_STATE_WRITE);
+ kcs_clear_obf();
+ kcs_write_datareg(0);
+ next_read_byte:
+ kcs_wait_ibf();
+ switch (IPMI_KCS_CMDREG_GET_STATE()) {
+ case IPMI_KCS_STATE_READ:
+ kcs_wait_obf();
+ g_assert(j < *rsp_len);
+ rsp[j++] = kcs_get_datareg();
+ kcs_write_datareg(IPMI_KCS_CMD_READ);
+ goto next_read_byte;
+ break;
+
+ case IPMI_KCS_STATE_IDLE:
+ kcs_wait_obf();
+ kcs_get_datareg();
+ break;
+
+ default:
+ g_assert(0);
+ }
+ *rsp_len = j;
+}
+
+static void kcs_abort(uint8_t *cmd, unsigned int cmd_len,
+ uint8_t *rsp, unsigned int *rsp_len)
+{
+ unsigned int i, j = 0;
+ unsigned int retries = 4;
+
+ /* Should be idle */
+ g_assert(kcs_get_cmdreg() == 0);
+
+ kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_START);
+ kcs_wait_ibf();
+ kcs_check_state(IPMI_KCS_STATE_WRITE);
+ kcs_clear_obf();
+ for (i = 0; i < cmd_len; i++) {
+ kcs_write_datareg(cmd[i]);
+ kcs_wait_ibf();
+ kcs_check_state(IPMI_KCS_STATE_WRITE);
+ kcs_clear_obf();
+ }
+ kcs_write_cmdreg(IPMI_KCS_CMD_WRITE_END);
+ kcs_wait_ibf();
+ kcs_check_state(IPMI_KCS_STATE_WRITE);
+ kcs_clear_obf();
+ kcs_write_datareg(0);
+ kcs_wait_ibf();
+ switch (IPMI_KCS_CMDREG_GET_STATE()) {
+ case IPMI_KCS_STATE_READ:
+ kcs_wait_obf();
+ g_assert(j < *rsp_len);
+ rsp[j++] = kcs_get_datareg();
+ kcs_write_datareg(IPMI_KCS_CMD_READ);
+ break;
+
+ default:
+ g_assert(0);
+ }
+
+ /* Start the abort here */
+ retry_abort:
+ g_assert(retries > 0);
+
+ kcs_wait_ibf();
+ kcs_write_cmdreg(IPMI_KCS_STATUS_ABORT);
+ kcs_wait_ibf();
+ kcs_clear_obf();
+ kcs_write_datareg(0);
+ kcs_wait_ibf();
+ if (IPMI_KCS_CMDREG_GET_STATE() != IPMI_KCS_STATE_READ) {
+ retries--;
+ goto retry_abort;
+ }
+ kcs_wait_obf();
+ rsp[0] = kcs_get_datareg();
+ kcs_write_datareg(IPMI_KCS_CMD_READ);
+ kcs_wait_ibf();
+ if (IPMI_KCS_CMDREG_GET_STATE() != IPMI_KCS_STATE_IDLE) {
+ retries--;
+ goto retry_abort;
+ }
+ kcs_wait_obf();
+ kcs_clear_obf();
+
+ *rsp_len = j;
+}
+
+
+static uint8_t get_dev_id_cmd[] = { 0x18, 0x01 };
+static uint8_t get_dev_id_rsp[] = { 0x1c, 0x01, 0x00, 0x20, 0x00, 0x00, 0x00,
+ 0x02, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+/*
+ * Send a get_device_id to do a basic test.
+ */
+static void test_kcs_base(void)
+{
+ uint8_t rsp[20];
+ unsigned int rsplen = sizeof(rsp);
+
+ kcs_cmd(get_dev_id_cmd, sizeof(get_dev_id_cmd), rsp, &rsplen);
+ g_assert(rsplen == sizeof(get_dev_id_rsp));
+ g_assert(memcmp(get_dev_id_rsp, rsp, rsplen) == 0);
+}
+
+/*
+ * Abort a kcs operation while reading
+ */
+static void test_kcs_abort(void)
+{
+ uint8_t rsp[20];
+ unsigned int rsplen = sizeof(rsp);
+
+ kcs_abort(get_dev_id_cmd, sizeof(get_dev_id_cmd), rsp, &rsplen);
+ g_assert(rsp[0] == IPMI_KCS_ABORTED_BY_CMD);
+}
+
+static uint8_t set_bmc_globals_cmd[] = { 0x18, 0x2e, 0x0f };
+static uint8_t set_bmc_globals_rsp[] = { 0x1c, 0x2e, 0x00 };
+
+/*
+ * Enable interrupts
+ */
+static void test_enable_irq(void)
+{
+ uint8_t rsp[20];
+ unsigned int rsplen = sizeof(rsp);
+
+ kcs_cmd(set_bmc_globals_cmd, sizeof(set_bmc_globals_cmd), rsp, &rsplen);
+ g_assert(rsplen == sizeof(set_bmc_globals_rsp));
+ g_assert(memcmp(set_bmc_globals_rsp, rsp, rsplen) == 0);
+ kcs_ints_enabled = 1;
+}
+
+int main(int argc, char **argv)
+{
+ const char *arch = qtest_get_arch();
+ char *cmdline;
+ int ret;
+
+ /* Check architecture */
+ if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
+ g_test_message("Skipping test for non-x86\n");
+ return 0;
+ }
+
+ /* Run the tests */
+ g_test_init(&argc, &argv, NULL);
+
+ cmdline = g_strdup_printf("-vnc none -device isa-ipmi");
+ qtest_start(cmdline);
+ qtest_irq_intercept_in(global_qtest, "ioapic");
+ qtest_add_func("/ipmi/local/kcs_base", test_kcs_base);
+ qtest_add_func("/ipmi/local/kcs_abort", test_kcs_abort);
+ qtest_add_func("/ipmi/local/kcs_enable_irq", test_enable_irq);
+ qtest_add_func("/ipmi/local/kcs_base_irq", test_kcs_base);
+ qtest_add_func("/ipmi/local/kcs_abort_irq", test_kcs_abort);
+ ret = g_test_run();
+ qtest_quit(global_qtest);
+
+ return ret;
+}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 08/17] ipmi: Add documentation
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (6 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 07/17] ipmi: Add tests minyard
@ 2015-04-23 22:57 ` minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 09/17] ipmi: Add migration capability to the IPMI device minyard
` (9 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
Add some basic documentation for the IPMI device.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
qemu-options.hx | 38 ++++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/qemu-options.hx b/qemu-options.hx
index 319d971..598c631 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -373,6 +373,44 @@ Add device @var{driver}. @var{prop}=@var{value} sets driver
properties. Valid properties depend on the driver. To get help on
possible drivers and properties, use @code{-device help} and
@code{-device @var{driver},help}.
+
+Some drivers are:
+@item -device isa-ipmi[,interface=kcs|bt][,iobase=@var{val}][,irq=@var{val}][,slave_addr=@var{val}][,chardev=name]
+
+Add an IPMI device. This also adds a corresponding ACPI and SMBIOS entries,
+if appropriate. The following options are handled:
+@table @option
+@item interface=kcs|bt
+Define the interface type to use. Currently the IPMI-defined KCS and
+BT interfaces are handled. The default is KCS.
+@item iobase=@var{val}
+Define the I/O address of the interface. The default is 0xca0 for KCS
+and 0xe4 for BT.
+@item irq=@var{val}
+Define the interrupt to use. The default is 5. To disable interrupts,
+set this to 0.
+@item slave_addr=@var{val}
+The IPMI slave address to use for the BMC. The default is 0x20.
+This address is the BMC's address on the I2C network of management
+controllers. If you don't know what this means, it is safe to ignore
+it.
+@item chardev=name
+If a chardev is not specified, the IPMI driver uses a built-in baseboard
+management controller (BMC) simulator. It provides a basic BMC with a
+watchdog timer and associated sensor.
+
+If a chardev is specified, A connection is made to an external BMC
+simulator. If you do this, it is strongly recommended that you use
+the "reconnect=" chardev option to reconnect to the simulator if the
+connection is lost. Note that if this is not used carefully, it can
+be a security issue, as the interface has the ability to send resets,
+NMIs, and power off the VM. It's best if QEMU makes a connection to
+an external simulator running on a secure port on localhost, so
+neither the simulator nor QEMU is exposed to any outside network.
+
+See the "lanserv/README.vm" file in the OpenIPMI library for more
+details on the external interface.
+@end table
ETEXI
DEF("name", HAS_ARG, QEMU_OPTION_name,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 09/17] ipmi: Add migration capability to the IPMI device.
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (7 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 08/17] ipmi: Add documentation minyard
@ 2015-04-23 22:57 ` minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 10/17] ipmi: Add a firmware configuration repository minyard
` (8 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Corey Minyard <cminyard@mvista.com
---
hw/ipmi/ipmi.c | 17 +++++++++++++++++
hw/ipmi/ipmi.h | 2 ++
hw/ipmi/ipmi_bt.c | 14 ++++++++++++++
hw/ipmi/ipmi_extern.c | 42 ++++++++++++++++++++++++++++++++++++++----
hw/ipmi/ipmi_kcs.c | 15 +++++++++++++++
hw/ipmi/ipmi_sim.c | 30 ++++++++++++++++++++++++++++++
hw/ipmi/isa_ipmi.c | 12 ++++++++++++
7 files changed, 128 insertions(+), 4 deletions(-)
diff --git a/hw/ipmi/ipmi.c b/hw/ipmi/ipmi.c
index b046517..f3e5e9e 100644
--- a/hw/ipmi/ipmi.c
+++ b/hw/ipmi/ipmi.c
@@ -118,6 +118,23 @@ void ipmi_bmc_init(IPMIBmc *s, Error **errp)
}
}
+const VMStateDescription vmstate_IPMIInterface = {
+ .name = TYPE_IPMI_INTERFACE,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_BOOL(obf_irq_set, IPMIInterface),
+ VMSTATE_BOOL(atn_irq_set, IPMIInterface),
+ VMSTATE_BOOL(use_irq, IPMIInterface),
+ VMSTATE_BOOL(irqs_enabled, IPMIInterface),
+ VMSTATE_UINT32(outpos, IPMIInterface),
+ VMSTATE_UINT32(outlen, IPMIInterface),
+ VMSTATE_VBUFFER_UINT32(inmsg, IPMIInterface, 1, NULL, 0, inlen),
+ VMSTATE_BOOL(write_end, IPMIInterface),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static TypeInfo ipmi_bmc_type_info = {
.name = TYPE_IPMI_BMC,
.parent = TYPE_OBJECT,
diff --git a/hw/ipmi/ipmi.h b/hw/ipmi/ipmi.h
index 6b2a3e9..56cb423 100644
--- a/hw/ipmi/ipmi.h
+++ b/hw/ipmi/ipmi.h
@@ -153,6 +153,8 @@ typedef struct IPMIInterfaceClass {
unsigned char *rsp, unsigned int rsp_len);
} IPMIInterfaceClass;
+extern const VMStateDescription vmstate_IPMIInterface;
+
void ipmi_interface_init(IPMIInterface *s, Error **errp);
void ipmi_interface_reset(IPMIInterface *s);
diff --git a/hw/ipmi/ipmi_bt.c b/hw/ipmi/ipmi_bt.c
index 95beb71..105b978 100644
--- a/hw/ipmi/ipmi_bt.c
+++ b/hw/ipmi/ipmi_bt.c
@@ -335,6 +335,19 @@ static void ipmi_bt_handle_reset(IPMIInterface *s, bool is_cold)
}
}
+static const VMStateDescription vmstate_ipmi_bt = {
+ .name = TYPE_IPMI_INTERFACE_BT,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(control_reg, IPMIBtInterface),
+ VMSTATE_UINT8(mask_reg, IPMIBtInterface),
+ VMSTATE_UINT8(waiting_rsp, IPMIBtInterface),
+ VMSTATE_UINT8(waiting_seq, IPMIBtInterface),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void ipmi_bt_init(IPMIInterface *s, Error **errp)
{
IPMIBtInterface *bt = IPMI_INTERFACE_BT(s);
@@ -345,6 +358,7 @@ static void ipmi_bt_init(IPMIInterface *s, Error **errp)
s->io_length = 3;
memory_region_init_io(&s->io, NULL, &ipmi_bt_io_ops, bt, "ipmi-bt", 3);
+ vmstate_register(NULL, 0, &vmstate_ipmi_bt, bt);
}
static void ipmi_bt_class_init(ObjectClass *klass, void *data)
diff --git a/hw/ipmi/ipmi_extern.c b/hw/ipmi/ipmi_extern.c
index b59ff8a..aace0b3 100644
--- a/hw/ipmi/ipmi_extern.c
+++ b/hw/ipmi/ipmi_extern.c
@@ -63,10 +63,10 @@ typedef struct IPMIExternBmc {
unsigned char inbuf[MAX_IPMI_MSG_SIZE + 2];
unsigned int inpos;
- int in_escape;
- int in_too_many;
- int waiting_rsp;
- int sending_cmd;
+ bool in_escape;
+ bool in_too_many;
+ bool waiting_rsp;
+ bool sending_cmd;
unsigned char outbuf[(MAX_IPMI_MSG_SIZE + 2) * 2 + 1];
unsigned int outpos;
@@ -425,12 +425,46 @@ static void ipmi_extern_handle_reset(IPMIBmc *b)
continue_send(es);
}
+static int ipmi_extern_post_migrate(void *opaque, int version_id)
+{
+ IPMIExternBmc *es = opaque;
+
+ /*
+ * We don't directly restore waiting_rsp, Instead, we return an
+ * error on the interface if a response was being waited for.
+ */
+ if (es->waiting_rsp) {
+ IPMIInterface *s = es->parent.intf;
+ IPMIInterfaceClass *k = IPMI_INTERFACE_GET_CLASS(s);
+
+ es->waiting_rsp = 0;
+ es->inbuf[1] = es->outbuf[1] | 0x04;
+ es->inbuf[2] = es->outbuf[2];
+ es->inbuf[3] = IPMI_CC_BMC_INIT_IN_PROGRESS;
+ k->handle_rsp(s, es->outbuf[0], es->inbuf + 1, 3);
+ }
+ return 0;
+}
+
+static const VMStateDescription vmstate_ipmi_extern = {
+ .name = TYPE_IPMI_BMC_EXTERN,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .post_load = ipmi_extern_post_migrate,
+ .fields = (VMStateField[]) {
+ VMSTATE_BOOL(send_reset, IPMIExternBmc),
+ VMSTATE_BOOL(waiting_rsp, IPMIExternBmc),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void ipmi_extern_init(IPMIBmc *b, Error **errp)
{
IPMIExternBmc *es = IPMI_BMC_EXTERN(b);
es->extern_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, extern_timeout, es);
qemu_chr_add_handlers(es->parent.chr, can_receive, receive, chr_event, es);
+ vmstate_register(NULL, 0, &vmstate_ipmi_extern, es);
}
static void ipmi_extern_class_init(ObjectClass *klass, void *data)
diff --git a/hw/ipmi/ipmi_kcs.c b/hw/ipmi/ipmi_kcs.c
index 411799e..e3af39e 100644
--- a/hw/ipmi/ipmi_kcs.c
+++ b/hw/ipmi/ipmi_kcs.c
@@ -299,6 +299,20 @@ static void ipmi_kcs_set_atn(IPMIInterface *s, int val, int irq)
}
}
+static const VMStateDescription vmstate_ipmi_kcs = {
+ .name = TYPE_IPMI_INTERFACE_KCS,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(status_reg, IPMIKcsInterface),
+ VMSTATE_UINT8(data_out_reg, IPMIKcsInterface),
+ VMSTATE_INT16(data_in_reg, IPMIKcsInterface),
+ VMSTATE_INT16(cmd_reg, IPMIKcsInterface),
+ VMSTATE_UINT8(waiting_rsp, IPMIKcsInterface),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void ipmi_kcs_init(IPMIInterface *s, Error **errp)
{
IPMIKcsInterface *kcs = IPMI_INTERFACE_KCS(s);
@@ -309,6 +323,7 @@ static void ipmi_kcs_init(IPMIInterface *s, Error **errp)
s->io_length = 2;
memory_region_init_io(&s->io, NULL, &ipmi_kcs_io_ops, kcs, "ipmi-kcs", 2);
+ vmstate_register(NULL, 0, &vmstate_ipmi_kcs, kcs);
}
static void ipmi_kcs_class_init(ObjectClass *class, void *data)
diff --git a/hw/ipmi/ipmi_sim.c b/hw/ipmi/ipmi_sim.c
index d5b0600..62c3ce9 100644
--- a/hw/ipmi/ipmi_sim.c
+++ b/hw/ipmi/ipmi_sim.c
@@ -1658,6 +1658,34 @@ static const uint8_t init_sdrs[] = {
0xff, 0xff, 0x00, 0x00, 0x00
};
+static const VMStateDescription vmstate_ipmi_sim = {
+ .name = TYPE_IPMI_BMC_SIMULATOR,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(bmc_global_enables, IPMISimBmc),
+ VMSTATE_UINT8(msg_flags, IPMISimBmc),
+ VMSTATE_BOOL(watchdog_initialized, IPMISimBmc),
+ VMSTATE_UINT8(watchdog_use, IPMISimBmc),
+ VMSTATE_UINT8(watchdog_action, IPMISimBmc),
+ VMSTATE_UINT8(watchdog_pretimeout, IPMISimBmc),
+ VMSTATE_BOOL(watchdog_expired, IPMISimBmc),
+ VMSTATE_UINT16(watchdog_timeout, IPMISimBmc),
+ VMSTATE_BOOL(watchdog_running, IPMISimBmc),
+ VMSTATE_BOOL(watchdog_preaction_ran, IPMISimBmc),
+ VMSTATE_INT64(watchdog_expiry, IPMISimBmc),
+ VMSTATE_UINT8_ARRAY(evtbuf, IPMISimBmc, 16),
+ VMSTATE_UINT8(sensors[IPMI_WATCHDOG_SENSOR].status, IPMISimBmc),
+ VMSTATE_UINT8(sensors[IPMI_WATCHDOG_SENSOR].reading, IPMISimBmc),
+ VMSTATE_UINT16(sensors[IPMI_WATCHDOG_SENSOR].states, IPMISimBmc),
+ VMSTATE_UINT16(sensors[IPMI_WATCHDOG_SENSOR].assert_states, IPMISimBmc),
+ VMSTATE_UINT16(sensors[IPMI_WATCHDOG_SENSOR].deassert_states,
+ IPMISimBmc),
+ VMSTATE_UINT16(sensors[IPMI_WATCHDOG_SENSOR].assert_enable, IPMISimBmc),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void ipmi_sim_init(IPMIBmc *b, Error **errp)
{
unsigned int i;
@@ -1705,6 +1733,8 @@ static void ipmi_sim_init(IPMIBmc *b, Error **errp)
register_cmds(ss);
ss->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, ipmi_timeout, ss);
+
+ vmstate_register(NULL, 0, &vmstate_ipmi_sim, ss);
}
static void ipmi_sim_class_init(ObjectClass *klass, void *data)
diff --git a/hw/ipmi/isa_ipmi.c b/hw/ipmi/isa_ipmi.c
index 1c1ab8d..e62f744 100644
--- a/hw/ipmi/isa_ipmi.c
+++ b/hw/ipmi/isa_ipmi.c
@@ -121,11 +121,23 @@ static Property ipmi_isa_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static const VMStateDescription vmstate_isa_ipmi = {
+ .name = TYPE_ISA_IPMI,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_POINTER(intf, ISAIPMIDevice, vmstate_IPMIInterface,
+ IPMIInterface),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static void ipmi_isa_class_initfn(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
dc->realize = ipmi_isa_realizefn;
dc->reset = ipmi_isa_reset;
+ dc->vmsd = &vmstate_isa_ipmi;
dc->props = ipmi_isa_properties;
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 10/17] ipmi: Add a firmware configuration repository
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (8 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 09/17] ipmi: Add migration capability to the IPMI device minyard
@ 2015-04-23 22:57 ` minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 12/17] smbios: Add a function to directly add an entry minyard
` (7 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
Add a way for IPMI devices to register their firmware information
with the IPMI subsystem so that various firmware entities can pull
that information later for adding to firmware tables.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
hw/ipmi/ipmi.c | 25 +++++++++++++++++++++++++
hw/ipmi/ipmi.h | 36 ++++++++++++++++++++++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/hw/ipmi/ipmi.c b/hw/ipmi/ipmi.c
index f3e5e9e..c43c844 100644
--- a/hw/ipmi/ipmi.c
+++ b/hw/ipmi/ipmi.c
@@ -150,3 +150,28 @@ static void ipmi_register_types(void)
}
type_init(ipmi_register_types)
+
+struct fw_entry_handlers {
+ IPMIFwHandler handler;
+ void *opaque;
+ QSLIST_ENTRY(fw_entry_handlers) next;
+};
+static QSLIST_HEAD(, fw_entry_handlers) fw_entries;
+
+void ipmi_add_fwinfo(IPMIFwInfo *info)
+{
+ struct fw_entry_handlers *e;
+
+ QSLIST_FOREACH(e, &fw_entries, next) {
+ e->handler(info, e->opaque);
+ }
+}
+
+void ipmi_register_fwinfo_handler(IPMIFwHandler handler, void *opaque)
+{
+ struct fw_entry_handlers *e = g_malloc(sizeof(*e));
+
+ e->handler = handler;
+ e->opaque = opaque;
+ QSLIST_INSERT_HEAD(&fw_entries, e, next);
+}
diff --git a/hw/ipmi/ipmi.h b/hw/ipmi/ipmi.h
index 56cb423..62b757a 100644
--- a/hw/ipmi/ipmi.h
+++ b/hw/ipmi/ipmi.h
@@ -25,6 +25,7 @@
#ifndef HW_IPMI_H
#define HW_IPMI_H
+#include <qemu/queue.h>
#include "exec/memory.h"
#include "qemu-common.h"
#include "hw/qdev.h"
@@ -207,6 +208,41 @@ typedef struct IPMIBmcClass {
void ipmi_bmc_init(IPMIBmc *s, Error **errp);
+/*
+ * Used for transferring information to interfaces that add
+ * entries to firmware tables.
+ */
+typedef struct IPMIFwInfo {
+ const char *interface_name;
+ int interface_type;
+ uint8_t ipmi_spec_major_revision;
+ uint8_t ipmi_spec_minor_revision;
+ uint8_t i2c_slave_address;
+
+ uint64_t base_address;
+ uint64_t register_length;
+ uint8_t register_spacing;
+ enum {
+ IPMI_MEMSPACE_IO,
+ IPMI_MEMSPACE_MEM32,
+ IPMI_MEMSPACE_MEM64,
+ IPMI_MEMSPACE_SMBUS
+ } memspace;
+
+ int interrupt_number;
+ enum {
+ IPMI_LEVEL_IRQ,
+ IPMI_EDGE_IRQ
+ } irq_type;
+
+ const char *acpi_parent;
+} IPMIFwInfo;
+
+typedef void (*IPMIFwHandler)(IPMIFwInfo *info, void *opaque);
+
+void ipmi_add_fwinfo(IPMIFwInfo *info);
+void ipmi_register_fwinfo_handler(IPMIFwHandler handler, void *opaque);
+
#ifdef IPMI_DEBUG
#define ipmi_debug(fs, ...) \
fprintf(stderr, "IPMI (%s): " fs, __func__, ##__VA_ARGS__)
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 12/17] smbios: Add a function to directly add an entry
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (9 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 10/17] ipmi: Add a firmware configuration repository minyard
@ 2015-04-23 22:57 ` minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 13/17] pc: Postpone SMBIOS table installation to post machine init minyard
` (6 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
There was no way to directly add a table entry to the SMBIOS table,
even though the BIOS supports this. So add a function to do this.
This is in preparation for the IPMI handler adding it's SMBIOS table
entry.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
hw/i386/smbios.c | 153 +++++++++++++++++++++++++++++++----------------
include/hw/i386/smbios.h | 8 +++
2 files changed, 109 insertions(+), 52 deletions(-)
diff --git a/hw/i386/smbios.c b/hw/i386/smbios.c
index 1341e02..ac97c6b 100644
--- a/hw/i386/smbios.c
+++ b/hw/i386/smbios.c
@@ -831,6 +831,92 @@ static void smbios_entry_point_setup(void)
ep.structure_table_address = cpu_to_le32(0);
}
+struct smbios_table_entry {
+ void *data;
+ int size;
+ bool append_zeros;
+ QSLIST_ENTRY(smbios_table_entry) next;
+};
+
+static QSLIST_HEAD(, smbios_table_entry) table_entries;
+
+void smbios_add_table_entry(void *data, int size, bool append_zeros)
+{
+ struct smbios_table_entry *e = g_malloc(sizeof(*e));
+
+ e->data = g_malloc(size);
+ memcpy(e->data, data, size);
+ e->size = size;
+ e->append_zeros = append_zeros;
+ QSLIST_INSERT_HEAD(&table_entries, e, next);
+}
+
+static void smbios_table_entry_append(void *data, int size, bool append_zeros)
+{
+ struct smbios_structure_header *header;
+ struct smbios_table *table; /* legacy mode only */
+
+ /*
+ * NOTE: standard double '\0' terminator expected, per smbios spec.
+ * (except in legacy mode, where the second '\0' is implicit and
+ * will be inserted by the BIOS).
+ */
+ if (append_zeros) {
+ size += 2;
+ }
+ smbios_tables = g_realloc(smbios_tables, smbios_tables_len + size);
+ header = (struct smbios_structure_header *)(smbios_tables +
+ smbios_tables_len);
+
+ memcpy(header, data, size);
+ if (append_zeros) {
+ memset(smbios_tables + smbios_tables_len + size - 2, 0, 2);
+ }
+
+ if (test_bit(header->type, have_fields_bitmap)) {
+ error_report("can't load type %d struct, fields already specified!",
+ header->type);
+ exit(1);
+ }
+ set_bit(header->type, have_binfile_bitmap);
+
+ if (header->type == 4) {
+ smbios_type4_count++;
+ }
+
+ smbios_tables_len += size;
+ if (size > smbios_table_max) {
+ smbios_table_max = size;
+ }
+ smbios_table_cnt++;
+
+ /* add a copy of the newly loaded blob to legacy smbios_entries */
+ /* NOTE: This code runs before smbios_set_defaults(), so we don't
+ * yet know which mode (legacy vs. aggregate-table) will be
+ * required. We therefore add the binary blob to both legacy
+ * (smbios_entries) and aggregate (smbios_tables) tables, and
+ * delete the one we don't need from smbios_set_defaults(),
+ * once we know which machine version has been requested.
+ */
+ if (!smbios_entries) {
+ smbios_entries_len = sizeof(uint16_t);
+ smbios_entries = g_malloc0(smbios_entries_len);
+ }
+ if (append_zeros) {
+ size -= 1; /* The BIOS adds the second zero in legacy mode. */
+ }
+ smbios_entries = g_realloc(smbios_entries, smbios_entries_len +
+ size + sizeof(*table));
+ table = (struct smbios_table *)(smbios_entries + smbios_entries_len);
+ table->header.type = SMBIOS_TABLE_ENTRY;
+ table->header.length = cpu_to_le16(sizeof(*table) + size);
+ memcpy(table->data, header, size);
+ smbios_entries_len += sizeof(*table) + size;
+ (*(uint16_t *)smbios_entries) =
+ cpu_to_le16(le16_to_cpu(*(uint16_t *)smbios_entries) + 1);
+ /* end: add a copy of the newly loaded blob to legacy smbios_entries */
+}
+
void smbios_get_tables(uint8_t **tables, size_t *tables_len,
uint8_t **anchor, size_t *anchor_len)
{
@@ -875,6 +961,16 @@ void smbios_get_tables(uint8_t **tables, size_t *tables_len,
}
smbios_build_type_32_table();
+
+ while (!QSLIST_EMPTY(&table_entries)) {
+ struct smbios_table_entry *e = QSLIST_FIRST(&table_entries);
+
+ QSLIST_REMOVE_HEAD(&table_entries, next);
+ smbios_table_entry_append(e->data, e->size, e->append_zeros);
+ g_free(e->data);
+ g_free(e);
+ }
+
smbios_build_type_127_table();
smbios_validate_table();
@@ -907,9 +1003,8 @@ void smbios_entry_add(QemuOpts *opts)
val = qemu_opt_get(opts, "file");
if (val) {
- struct smbios_structure_header *header;
int size;
- struct smbios_table *table; /* legacy mode only */
+ uint8_t *data;
qemu_opts_validate(opts, qemu_smbios_file_opts, &local_err);
if (local_err) {
@@ -923,60 +1018,14 @@ void smbios_entry_add(QemuOpts *opts)
exit(1);
}
- /*
- * NOTE: standard double '\0' terminator expected, per smbios spec.
- * (except in legacy mode, where the second '\0' is implicit and
- * will be inserted by the BIOS).
- */
- smbios_tables = g_realloc(smbios_tables, smbios_tables_len + size);
- header = (struct smbios_structure_header *)(smbios_tables +
- smbios_tables_len);
-
- if (load_image(val, (uint8_t *)header) != size) {
+ data = g_malloc(size);
+ if (load_image(val, data) != size) {
error_report("Failed to load SMBIOS file %s", val);
exit(1);
}
- if (test_bit(header->type, have_fields_bitmap)) {
- error_report("can't load type %d struct, fields already specified!",
- header->type);
- exit(1);
- }
- set_bit(header->type, have_binfile_bitmap);
-
- if (header->type == 4) {
- smbios_type4_count++;
- }
-
- smbios_tables_len += size;
- if (size > smbios_table_max) {
- smbios_table_max = size;
- }
- smbios_table_cnt++;
-
- /* add a copy of the newly loaded blob to legacy smbios_entries */
- /* NOTE: This code runs before smbios_set_defaults(), so we don't
- * yet know which mode (legacy vs. aggregate-table) will be
- * required. We therefore add the binary blob to both legacy
- * (smbios_entries) and aggregate (smbios_tables) tables, and
- * delete the one we don't need from smbios_set_defaults(),
- * once we know which machine version has been requested.
- */
- if (!smbios_entries) {
- smbios_entries_len = sizeof(uint16_t);
- smbios_entries = g_malloc0(smbios_entries_len);
- }
- smbios_entries = g_realloc(smbios_entries, smbios_entries_len +
- size + sizeof(*table));
- table = (struct smbios_table *)(smbios_entries + smbios_entries_len);
- table->header.type = SMBIOS_TABLE_ENTRY;
- table->header.length = cpu_to_le16(sizeof(*table) + size);
- memcpy(table->data, header, size);
- smbios_entries_len += sizeof(*table) + size;
- (*(uint16_t *)smbios_entries) =
- cpu_to_le16(le16_to_cpu(*(uint16_t *)smbios_entries) + 1);
- /* end: add a copy of the newly loaded blob to legacy smbios_entries */
-
+ smbios_table_entry_append(data, size, false);
+ g_free(data);
return;
}
diff --git a/include/hw/i386/smbios.h b/include/hw/i386/smbios.h
index d2850be..9f3e920 100644
--- a/include/hw/i386/smbios.h
+++ b/include/hw/i386/smbios.h
@@ -27,6 +27,14 @@ void smbios_get_tables(uint8_t **tables, size_t *tables_len,
uint8_t **anchor, size_t *anchor_len);
/*
+ * Add an external entry to the SMBIOS table. Can only be called
+ * from a registered device table handler. This will store the
+ * given data in a queue and append it when the SMBIOS table is
+ * built.
+ */
+void smbios_add_table_entry(void *data, int size, bool append_zeros);
+
+/*
* SMBIOS spec defined tables
*/
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 13/17] pc: Postpone SMBIOS table installation to post machine init
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (10 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 12/17] smbios: Add a function to directly add an entry minyard
@ 2015-04-23 22:57 ` minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 14/17] ipmi: Add SMBIOS table entry minyard
` (5 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
This is the same place that the ACPI SSDT table gets added, so that
devices can add themselves to the SMBIOS table.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
hw/i386/pc.c | 35 ++++++++++++++++++-----------------
1 file changed, 18 insertions(+), 17 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index a8e6be1..efe3c2f 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -680,8 +680,6 @@ static unsigned int pc_apic_id_limit(unsigned int max_cpus)
static FWCfgState *bochs_bios_init(void)
{
FWCfgState *fw_cfg;
- uint8_t *smbios_tables, *smbios_anchor;
- size_t smbios_tables_len, smbios_anchor_len;
uint64_t *numa_fw_cfg;
int i, j;
unsigned int apic_id_limit = pc_apic_id_limit(max_cpus);
@@ -707,21 +705,6 @@ static FWCfgState *bochs_bios_init(void)
acpi_tables, acpi_tables_len);
fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
- smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
- if (smbios_tables) {
- fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
- smbios_tables, smbios_tables_len);
- }
-
- smbios_get_tables(&smbios_tables, &smbios_tables_len,
- &smbios_anchor, &smbios_anchor_len);
- if (smbios_anchor) {
- fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
- smbios_tables, smbios_tables_len);
- fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
- smbios_anchor, smbios_anchor_len);
- }
-
fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE,
&e820_reserve, sizeof(e820_reserve));
fw_cfg_add_file(fw_cfg, "etc/e820", e820_table,
@@ -1119,7 +1102,25 @@ void pc_guest_info_machine_done(Notifier *notifier, void *data)
PcGuestInfoState *guest_info_state = container_of(notifier,
PcGuestInfoState,
machine_done);
+ uint8_t *smbios_tables, *smbios_anchor;
+ size_t smbios_tables_len, smbios_anchor_len;
+ FWCfgState *fw_cfg = guest_info_state->info.fw_cfg;
+
acpi_setup(&guest_info_state->info);
+
+ smbios_tables = smbios_get_table_legacy(&smbios_tables_len);
+ if (smbios_tables) {
+ fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
+ smbios_tables, smbios_tables_len);
+ }
+ smbios_get_tables(&smbios_tables, &smbios_tables_len,
+ &smbios_anchor, &smbios_anchor_len);
+ if (smbios_anchor) {
+ fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables",
+ smbios_tables, smbios_tables_len);
+ fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor",
+ smbios_anchor, smbios_anchor_len);
+ }
}
PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 14/17] ipmi: Add SMBIOS table entry
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (11 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 13/17] pc: Postpone SMBIOS table installation to post machine init minyard
@ 2015-04-23 22:57 ` minyard
2015-04-26 8:36 ` Michael S. Tsirkin
2015-04-23 22:57 ` [Qemu-devel] [PATCH 15/17] acpi: Add a way for devices to add ACPI tables minyard
` (4 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
Add an IPMI table entry to the SMBIOS.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
default-configs/i386-softmmu.mak | 1 +
default-configs/x86_64-softmmu.mak | 1 +
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_smbios.c | 89 ++++++++++++++++++++++++++++++++++++++
4 files changed, 92 insertions(+)
create mode 100644 hw/ipmi/ipmi_smbios.c
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 2448543..15c0b70 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -20,6 +20,7 @@ CONFIG_I8254=y
CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
+CONFIG_SMBIOS=y
CONFIG_ACPI=y
CONFIG_APM=y
CONFIG_I8257=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 3ed8877..dac877a 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -20,6 +20,7 @@ CONFIG_I8254=y
CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
+CONFIG_SMBIOS=y
CONFIG_ACPI=y
CONFIG_APM=y
CONFIG_I8257=y
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
index abfa827..d0129cf 100644
--- a/hw/ipmi/Makefile.objs
+++ b/hw/ipmi/Makefile.objs
@@ -4,3 +4,4 @@ common-obj-$(CONFIG_IPMI_KCS) += ipmi_kcs.o
common-obj-$(CONFIG_IPMI_BT) += ipmi_bt.o
common-obj-$(CONFIG_IPMI_LOCAL) += ipmi_sim.o
common-obj-$(CONFIG_IPMI_EXTERN) += ipmi_extern.o
+common-obj-$(call land,$(CONFIG_IPMI),$(CONFIG_SMBIOS)) += ipmi_smbios.o
diff --git a/hw/ipmi/ipmi_smbios.c b/hw/ipmi/ipmi_smbios.c
new file mode 100644
index 0000000..b818f5b
--- /dev/null
+++ b/hw/ipmi/ipmi_smbios.c
@@ -0,0 +1,89 @@
+/*
+ * IPMI SMBIOS firmware handling
+ *
+ * Copyright (c) 2015 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "ipmi.h"
+#include <hw/i386/smbios.h>
+#include <qemu/error-report.h>
+
+/* SMBIOS type 38 - IPMI */
+struct smbios_type_38 {
+ struct smbios_structure_header header;
+ uint8_t interface_type;
+ uint8_t ipmi_spec_revision;
+ uint8_t i2c_slave_address;
+ uint8_t nv_storage_device_address;
+ uint64_t base_address;
+ uint8_t base_address_modifier;
+ uint8_t interrupt_number;
+} QEMU_PACKED;
+
+static void ipmi_encode_one_smbios(IPMIFwInfo *info, void *opaque)
+{
+ struct smbios_type_38 smb38;
+ uint64_t baseaddr = info->base_address;
+
+ smb38.header.type = 38;
+ smb38.header.length = sizeof(smb38);
+ smb38.header.handle = cpu_to_le16(0x3000);
+ smb38.interface_type = info->interface_type;
+ smb38.ipmi_spec_revision = ((info->ipmi_spec_major_revision << 4)
+ | info->ipmi_spec_minor_revision);
+ smb38.i2c_slave_address = info->i2c_slave_address;
+ smb38.nv_storage_device_address = 0;
+
+ /* or 1 to set it to I/O space */
+ switch (info->memspace) {
+ case IPMI_MEMSPACE_IO: baseaddr |= 1; break;
+ case IPMI_MEMSPACE_MEM32: break;
+ case IPMI_MEMSPACE_MEM64: break;
+ case IPMI_MEMSPACE_SMBUS: baseaddr <<= 1; break;
+ }
+
+ smb38.base_address = cpu_to_le64(baseaddr);
+
+ smb38.base_address_modifier = 0;
+ if (info->irq_type == IPMI_LEVEL_IRQ) {
+ smb38.base_address_modifier |= 1;
+ }
+ switch (info->register_spacing) {
+ case 1: break;
+ case 4: smb38.base_address_modifier |= 1 << 6; break;
+ case 16: smb38.base_address_modifier |= 2 << 6; break;
+ default:
+ error_report("IPMI register spacing %d is not compatible with"
+ " SMBIOS, ignoring this entry.", info->register_spacing);
+ return;
+ }
+ smb38.interrupt_number = info->interrupt_number;
+
+ smbios_add_table_entry((struct smbios_structure_header *) &smb38,
+ sizeof(smb38), true);
+}
+
+static void smbios_init(void)
+{
+ ipmi_register_fwinfo_handler(ipmi_encode_one_smbios, NULL);
+}
+
+type_init(smbios_init);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 15/17] acpi: Add a way for devices to add ACPI tables
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (12 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 14/17] ipmi: Add SMBIOS table entry minyard
@ 2015-04-23 22:57 ` minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 16/17] ipmi: Add ACPI table entries minyard
` (3 subsequent siblings)
17 siblings, 0 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
Some devices, like IPMI, need to add ACPI table entries to report
their presence. Add a method for adding these entries.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
hw/acpi/Makefile.objs | 1 +
hw/acpi/acpi-dev-tables.c | 80 +++++++++++++++++++++++++++++++++++++++
hw/i386/acpi-build.c | 17 +++++++++
include/hw/acpi/acpi-dev-tables.h | 38 +++++++++++++++++++
4 files changed, 136 insertions(+)
create mode 100644 hw/acpi/acpi-dev-tables.c
create mode 100644 include/hw/acpi/acpi-dev-tables.h
diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
index b9fefa7..2b84f08 100644
--- a/hw/acpi/Makefile.objs
+++ b/hw/acpi/Makefile.objs
@@ -3,3 +3,4 @@ common-obj-$(CONFIG_ACPI) += memory_hotplug.o
common-obj-$(CONFIG_ACPI) += acpi_interface.o
common-obj-$(CONFIG_ACPI) += bios-linker-loader.o
common-obj-$(CONFIG_ACPI) += aml-build.o
+common-obj-$(CONFIG_ACPI) += acpi-dev-tables.o
diff --git a/hw/acpi/acpi-dev-tables.c b/hw/acpi/acpi-dev-tables.c
new file mode 100644
index 0000000..7f07a3d
--- /dev/null
+++ b/hw/acpi/acpi-dev-tables.c
@@ -0,0 +1,80 @@
+/*
+ * Add and get ACPI tables registered by devices.
+ *
+ * Copyright (c) 2015 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <string.h>
+#include <hw/acpi/acpi-dev-tables.h>
+#include <qemu/queue.h>
+
+struct acpi_dev_table {
+ void *data;
+ int size;
+ const char *sig;
+ uint8_t rev;
+ QSLIST_ENTRY(acpi_dev_table) next;
+};
+
+static QSLIST_HEAD(, acpi_dev_table) acpi_table_entries;
+
+void
+add_acpi_dev_table(void *data, int size, const char *sig, uint8_t rev)
+{
+ struct acpi_dev_table *e = g_malloc(sizeof(*e));
+
+ e->data = g_malloc(size);
+ memcpy(e->data, data, size);
+ e->size = size;
+ e->sig = sig;
+ e->rev = rev;
+ QSLIST_INSERT_HEAD(&acpi_table_entries, e, next);
+}
+
+struct acpi_dev_table *acpi_dev_table_first(void)
+{
+ return QSLIST_FIRST(&acpi_table_entries);
+}
+
+struct acpi_dev_table *acpi_dev_table_next(struct acpi_dev_table *current)
+{
+ return QSLIST_NEXT(current, next);
+}
+
+uint8_t *acpi_dev_table_data(struct acpi_dev_table *e)
+{
+ return e->data;
+}
+
+unsigned acpi_dev_table_len(struct acpi_dev_table *e)
+{
+ return e->size;
+}
+
+const char *acpi_dev_table_sig(struct acpi_dev_table *e)
+{
+ return e->sig;
+}
+
+uint8_t acpi_dev_table_rev(struct acpi_dev_table *e)
+{
+ return e->rev;
+}
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index e761005..0b4d195 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -35,6 +35,7 @@
#include "hw/timer/hpet.h"
#include "hw/i386/acpi-defs.h"
#include "hw/acpi/acpi.h"
+#include "hw/acpi/acpi-dev-tables.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/acpi/bios-linker-loader.h"
#include "hw/loader.h"
@@ -1377,6 +1378,7 @@ void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
AcpiMcfgInfo mcfg;
PcPciInfo pci;
uint8_t *u;
+ struct acpi_dev_table *dt;
size_t aml_len = 0;
GArray *tables_blob = tables->table_data;
@@ -1448,6 +1450,21 @@ void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
build_dmar_q35(tables_blob, tables->linker);
}
+ /* Add tables from devices. */
+ for (dt = acpi_dev_table_first(); dt; dt = acpi_dev_table_next(dt)) {
+ unsigned len = acpi_dev_table_len(dt);
+ void *data = acpi_dev_table_data(dt);
+
+ acpi_add_table(table_offsets, tables_blob);
+ acpi_data_push(tables_blob, sizeof(AcpiTableHeader));
+ g_array_append_vals(tables_blob, data, len);
+ build_header(tables->linker, tables_blob,
+ (void *)(tables_blob->data + tables_blob->len -
+ len - sizeof(AcpiTableHeader)),
+ acpi_dev_table_sig(dt), len + sizeof(AcpiTableHeader),
+ acpi_dev_table_rev(dt));
+ }
+
/* Add tables supplied by user (if any) */
for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
unsigned len = acpi_table_len(u);
diff --git a/include/hw/acpi/acpi-dev-tables.h b/include/hw/acpi/acpi-dev-tables.h
new file mode 100644
index 0000000..6dd18a5
--- /dev/null
+++ b/include/hw/acpi/acpi-dev-tables.h
@@ -0,0 +1,38 @@
+/*
+ * Add and get ACPI tables registered by devices.
+ *
+ * Copyright (C) 2015 Corey Minyard <cminyard@mvista.com>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+
+#ifndef QEMU_HW_ACPI_HOOKS_H
+#define QEMU_HW_ACPI_HOOKS_H
+
+#include <hw/acpi/aml-build.h>
+
+void add_acpi_dev_table(void *data, int size, const char *sig, uint8_t rev);
+
+struct acpi_dev_table;
+
+struct acpi_dev_table *acpi_dev_table_first(void);
+struct acpi_dev_table *acpi_dev_table_next(struct acpi_dev_table *current);
+uint8_t *acpi_dev_table_data(struct acpi_dev_table *);
+unsigned acpi_dev_table_len(struct acpi_dev_table *);
+const char *acpi_dev_table_sig(struct acpi_dev_table *);
+uint8_t acpi_dev_table_rev(struct acpi_dev_table *);
+
+#endif /* QEMU_HW_ACPI_HOOKS_H */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 16/17] ipmi: Add ACPI table entries
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (13 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 15/17] acpi: Add a way for devices to add ACPI tables minyard
@ 2015-04-23 22:57 ` minyard
2015-04-26 8:36 ` Michael S. Tsirkin
2015-04-23 22:57 ` [Qemu-devel] [PATCH 17/17] bios: Add tests for the IPMI ACPI and SMBIOS entries minyard
` (2 subsequent siblings)
17 siblings, 1 reply; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
Use the new ACPI table construction tools to create an ACPI
entry for IPMI.
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
hw/ipmi/Makefile.objs | 1 +
hw/ipmi/ipmi_acpi.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++++++
hw/ipmi/isa_ipmi.c | 4 ++
3 files changed, 127 insertions(+)
create mode 100644 hw/ipmi/ipmi_acpi.c
diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
index d0129cf..17ca09f 100644
--- a/hw/ipmi/Makefile.objs
+++ b/hw/ipmi/Makefile.objs
@@ -5,3 +5,4 @@ common-obj-$(CONFIG_IPMI_BT) += ipmi_bt.o
common-obj-$(CONFIG_IPMI_LOCAL) += ipmi_sim.o
common-obj-$(CONFIG_IPMI_EXTERN) += ipmi_extern.o
common-obj-$(call land,$(CONFIG_IPMI),$(CONFIG_SMBIOS)) += ipmi_smbios.o
+common-obj-$(call land,$(CONFIG_IPMI),$(CONFIG_ACPI)) += ipmi_acpi.o
diff --git a/hw/ipmi/ipmi_acpi.c b/hw/ipmi/ipmi_acpi.c
new file mode 100644
index 0000000..e014da7
--- /dev/null
+++ b/hw/ipmi/ipmi_acpi.c
@@ -0,0 +1,122 @@
+/*
+ * IPMI ACPI firmware handling
+ *
+ * Copyright (c) 2015 Corey Minyard, MontaVista Software, LLC
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "ipmi.h"
+#include "hw/acpi/aml-build.h"
+#include "hw/acpi/acpi.h"
+#include "hw/acpi/acpi-dev-tables.h"
+#include <qemu/error-report.h>
+
+static Aml *aml_ipmi_crs(IPMIFwInfo *info)
+{
+ Aml *crs = aml_resource_template();
+ uint8_t regspacing = info->register_spacing;
+
+ if (regspacing == 1) {
+ regspacing = 0;
+ }
+
+ switch (info->memspace) {
+ case IPMI_MEMSPACE_IO:
+ aml_append(crs, aml_io(aml_decode16, info->base_address,
+ info->base_address + info->register_length - 1,
+ regspacing, info->register_length));
+ break;
+ case IPMI_MEMSPACE_MEM32:
+ aml_append(crs,
+ aml_dword_memory(aml_pos_decode,
+ aml_min_fixed, aml_max_fixed,
+ aml_non_cacheable, aml_ReadWrite,
+ 0xffffffff,
+ info->base_address,
+ info->base_address + info->register_length - 1,
+ regspacing, info->register_length));
+ break;
+ case IPMI_MEMSPACE_MEM64:
+ aml_append(crs,
+ aml_qword_memory(aml_pos_decode,
+ aml_min_fixed, aml_max_fixed,
+ aml_non_cacheable, aml_ReadWrite,
+ 0xffffffffffffffffULL,
+ info->base_address,
+ info->base_address + info->register_length - 1,
+ regspacing, info->register_length));
+ break;
+ case IPMI_MEMSPACE_SMBUS:
+ aml_append(crs, aml_return(aml_int(info->base_address)));
+ break;
+ }
+
+ if (info->interrupt_number) {
+ aml_append(crs, aml_irq_no_flags(info->interrupt_number));
+ }
+
+ return crs;
+}
+
+static void
+ipmi_encode_one_acpi(IPMIFwInfo *info, void *opaque)
+{
+ Aml *ssdt, *scope, *dev, *method;
+ char *name;
+ int version = ((info->ipmi_spec_major_revision << 8)
+ | (info->ipmi_spec_minor_revision << 4));
+
+ if (!info->acpi_parent) {
+ ipmi_debug("device %s not compatible with ACPI, no parent given.",
+ info->interface_name);
+ return;
+ }
+
+ ssdt = init_aml_allocator();
+
+ scope = aml_scope("%s", info->acpi_parent);
+ name = g_strdup_printf("ipmi_%s", info->interface_name);
+
+ dev = aml_device("MI0");
+ aml_append(dev, aml_name_decl("_HID", aml_eisaid("IPI0001")));
+ aml_append(dev, aml_name_decl("_STR", aml_string("%s", name)));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+ aml_append(dev, aml_name_decl("_CRS", aml_ipmi_crs(info)));
+ method = aml_method("_IFT", 0);
+ aml_append(method, aml_return(aml_int(info->interface_type)));
+ aml_append(dev, method);
+ method = aml_method("_SRV", 0);
+ aml_append(method, aml_return(aml_int(version)));
+ aml_append(dev, method);
+
+ aml_append(scope, dev);
+
+ aml_append(ssdt, scope);
+
+ add_acpi_dev_table(ssdt->buf->data, ssdt->buf->len, "SSDT", 1);
+ free_aml_allocator();
+}
+
+static void ipmi_acpi_init(void)
+{
+ ipmi_register_fwinfo_handler(ipmi_encode_one_acpi, NULL);
+}
+
+type_init(ipmi_acpi_init);
diff --git a/hw/ipmi/isa_ipmi.c b/hw/ipmi/isa_ipmi.c
index da86247..ae6d3c8 100644
--- a/hw/ipmi/isa_ipmi.c
+++ b/hw/ipmi/isa_ipmi.c
@@ -37,6 +37,8 @@ typedef struct ISAIPMIDevice {
ISADevice dev;
char *interface;
uint32_t iobase;
+ uint32_t iolength;
+ uint8_t regspacing;
int32 isairq;
uint8_t slave_addr;
CharDriverState *chr;
@@ -73,12 +75,14 @@ static void ipmi_isa_realizefn(DeviceState *dev, Error **errp)
intfk = IPMI_INTERFACE_GET_CLASS(intf);
bmc->intf = intf;
intf->bmc = bmc;
+ ipmi->regspacing = 1;
intf->io_base = ipmi->iobase;
intf->slave_addr = ipmi->slave_addr;
ipmi_interface_init(intf, errp);
if (*errp) {
return;
}
+ ipmi->iolength = intf->io_length;
ipmi_bmc_init(bmc, errp);
if (*errp) {
return;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* [Qemu-devel] [PATCH 17/17] bios: Add tests for the IPMI ACPI and SMBIOS entries
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (14 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 16/17] ipmi: Add ACPI table entries minyard
@ 2015-04-23 22:57 ` minyard
2015-04-23 23:11 ` [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu Eric Blake
2015-04-24 9:38 ` Paolo Bonzini
17 siblings, 0 replies; 38+ messages in thread
From: minyard @ 2015-04-23 22:57 UTC (permalink / raw)
To: qemu-devel; +Cc: Corey Minyard
From: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Corey Minyard <cminyard@mvista.com>
---
tests/bios-tables-test.c | 112 ++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 107 insertions(+), 5 deletions(-)
diff --git a/tests/bios-tables-test.c b/tests/bios-tables-test.c
index 735ac61..35d20fc 100644
--- a/tests/bios-tables-test.c
+++ b/tests/bios-tables-test.c
@@ -51,6 +51,10 @@ typedef struct {
GArray *tables;
uint32_t smbios_ep_addr;
struct smbios_entry_point smbios_ep_table;
+ uint8_t *ssdt_compare;
+ int ssdt_compare_len;
+ uint8_t *required_struct_types;
+ int required_struct_types_len;
} test_data;
#define LOW(x) ((x) & 0xff)
@@ -105,6 +109,12 @@ typedef struct {
ACPI_READ_FIELD((table)->asl_compiler_revision, addr); \
} while (0);
+static bool acpi_cmp32(uint32_t actual, const char *expected)
+{
+ actual = cpu_to_le32(actual);
+ return memcmp(&actual, expected, 4) == 0;
+}
+
#define ACPI_ASSERT_CMP(actual, expected) do { \
uint32_t ACPI_ASSERT_CMP_le = cpu_to_le32(actual); \
char ACPI_ASSERT_CMP_str[5] = {}; \
@@ -376,15 +386,28 @@ static void test_acpi_tables(test_data *data)
{
int tables_nr = data->rsdt_tables_nr - 1; /* fadt is first */
int i;
+ bool match_found = !data->ssdt_compare;
for (i = 0; i < tables_nr; i++) {
AcpiSdtTable ssdt_table;
- memset(&ssdt_table, 0 , sizeof(ssdt_table));
+ memset(&ssdt_table, 0, sizeof(ssdt_table));
uint32_t addr = data->rsdt_tables_addr[i + 1]; /* fadt is first */
test_dst_table(&ssdt_table, addr);
- g_array_append_val(data->tables, ssdt_table);
+
+ if (data->ssdt_compare &&
+ acpi_cmp32(ssdt_table.header.signature, "SSDT") &&
+ data->ssdt_compare_len == ssdt_table.aml_len &&
+ memcmp(data->ssdt_compare, ssdt_table.aml,
+ ssdt_table.aml_len) == 0) {
+ match_found = true;
+ g_free(ssdt_table.aml);
+ } else {
+ g_array_append_val(data->tables, ssdt_table);
+ }
}
+
+ g_assert(match_found);
}
static void dump_aml_files(test_data *data, bool rebuild)
@@ -672,7 +695,6 @@ static void test_smbios_structs(test_data *data)
uint32_t addr = ep_table->structure_table_address;
int i, len, max_len = 0;
uint8_t type, prv, crt;
- uint8_t required_struct_types[] = {0, 1, 3, 4, 16, 17, 19, 32, 127};
/* walk the smbios tables */
for (i = 0; i < ep_table->number_of_structures; i++) {
@@ -712,8 +734,8 @@ static void test_smbios_structs(test_data *data)
g_assert_cmpuint(ep_table->max_structure_size, ==, max_len);
/* required struct types must all be present */
- for (i = 0; i < ARRAY_SIZE(required_struct_types); i++) {
- g_assert(test_bit(required_struct_types[i], struct_bitmap));
+ for (i = 0; i < data->required_struct_types_len; i++) {
+ g_assert(test_bit(data->required_struct_types[i], struct_bitmap));
}
}
@@ -775,6 +797,9 @@ static void test_acpi_one(const char *params, test_data *data)
g_free(args);
}
+static uint8_t base_required_struct_types[] =
+ {0, 1, 3, 4, 16, 17, 19, 32, 127};
+
static void test_acpi_piix4_tcg(void)
{
test_data data;
@@ -784,6 +809,8 @@ static void test_acpi_piix4_tcg(void)
*/
memset(&data, 0, sizeof(data));
data.machine = MACHINE_PC;
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
test_acpi_one("-machine accel=tcg", &data);
free_test_data(&data);
}
@@ -795,6 +822,8 @@ static void test_acpi_piix4_tcg_bridge(void)
memset(&data, 0, sizeof(data));
data.machine = MACHINE_PC;
data.variant = ".bridge";
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
test_acpi_one("-machine accel=tcg -device pci-bridge,chassis_nr=1", &data);
free_test_data(&data);
}
@@ -805,6 +834,8 @@ static void test_acpi_q35_tcg(void)
memset(&data, 0, sizeof(data));
data.machine = MACHINE_Q35;
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
test_acpi_one("-machine q35,accel=tcg", &data);
free_test_data(&data);
}
@@ -816,11 +847,80 @@ static void test_acpi_q35_tcg_bridge(void)
memset(&data, 0, sizeof(data));
data.machine = MACHINE_Q35;
data.variant = ".bridge";
+ data.required_struct_types = base_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types);
test_acpi_one("-machine q35,accel=tcg -device pci-bridge,chassis_nr=1",
&data);
free_test_data(&data);
}
+static uint8_t ipmi_ssdt_bt_irq5[] = {
+ 0x10, 0x42, 0x06, 0x5c, 0x2f, 0x03, 0x5f, 0x53,
+ 0x42, 0x5f, 0x50, 0x43, 0x49, 0x30, 0x49, 0x53,
+ 0x41, 0x5f, 0x5b, 0x82, 0x4f, 0x04, 0x4d, 0x49,
+ 0x30, 0x5f, 0x08, 0x5f, 0x48, 0x49, 0x44, 0x0c,
+ 0x26, 0x09, 0x00, 0x01, 0x08, 0x5f, 0x53, 0x54,
+ 0x52, 0x0d, 0x69, 0x70, 0x6d, 0x69, 0x5f, 0x62,
+ 0x74, 0x00, 0x08, 0x5f, 0x55, 0x49, 0x44, 0x00,
+ 0x08, 0x5f, 0x43, 0x52, 0x53, 0x11, 0x10, 0x0a,
+ 0x0d, 0x47, 0x01, 0xe4, 0x00, 0xe6, 0x00, 0x00,
+ 0x03, 0x22, 0x20, 0x00, 0x79, 0x00, 0x14, 0x09,
+ 0x5f, 0x49, 0x46, 0x54, 0x00, 0xa4, 0x0a, 0x03,
+ 0x14, 0x0a, 0x5f, 0x53, 0x52, 0x56, 0x00, 0xa4,
+ 0x0b, 0x00, 0x02
+};
+
+static uint8_t ipmi_ssdt_kcs_irq0[] = {
+ 0x10, 0x4f, 0x05, 0x5c, 0x2f, 0x03, 0x5f, 0x53,
+ 0x42, 0x5f, 0x50, 0x43, 0x49, 0x30, 0x49, 0x53,
+ 0x41, 0x5f, 0x5b, 0x82, 0x4c, 0x04, 0x4d, 0x49,
+ 0x30, 0x5f, 0x08, 0x5f, 0x48, 0x49, 0x44, 0x0c,
+ 0x26, 0x09, 0x00, 0x01, 0x08, 0x5f, 0x53, 0x54,
+ 0x52, 0x0d, 0x69, 0x70, 0x6d, 0x69, 0x5f, 0x6b,
+ 0x63, 0x73, 0x00, 0x08, 0x5f, 0x55, 0x49, 0x44,
+ 0x00, 0x08, 0x5f, 0x43, 0x52, 0x53, 0x11, 0x0d,
+ 0x0a, 0x0a, 0x47, 0x01, 0xa2, 0x0c, 0xa3, 0x0c,
+ 0x00, 0x02, 0x79, 0x00, 0x14, 0x08, 0x5f, 0x49,
+ 0x46, 0x54, 0x00, 0xa4, 0x01, 0x14, 0x0a, 0x5f,
+ 0x53, 0x52, 0x56, 0x00, 0xa4, 0x0b, 0x00, 0x02
+};
+
+static uint8_t ipmi_required_struct_types[] =
+ {0, 1, 3, 4, 16, 17, 19, 32, 38, 127};
+
+static void test_acpi_q35_tcg_ipmi(void)
+{
+ test_data data;
+
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_Q35;
+ data.ssdt_compare = ipmi_ssdt_bt_irq5;
+ data.ssdt_compare_len = sizeof(ipmi_ssdt_bt_irq5);
+ data.required_struct_types = ipmi_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types);
+ test_acpi_one("-machine q35,accel=tcg -device isa-ipmi,interface=bt",
+ &data);
+ free_test_data(&data);
+}
+
+static void test_acpi_piix4_tcg_ipmi(void)
+{
+ test_data data;
+
+ /* Supplying -machine accel argument overrides the default (qtest).
+ * This is to make guest actually run.
+ */
+ memset(&data, 0, sizeof(data));
+ data.machine = MACHINE_PC;
+ data.ssdt_compare = ipmi_ssdt_kcs_irq0;
+ data.ssdt_compare_len = sizeof(ipmi_ssdt_kcs_irq0);
+ data.required_struct_types = ipmi_required_struct_types;
+ data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types);
+ test_acpi_one("-machine accel=tcg -device isa-ipmi,interface=kcs,irq=0",
+ &data);
+ free_test_data(&data);
+}
+
int main(int argc, char *argv[])
{
const char *arch = qtest_get_arch();
@@ -841,6 +941,8 @@ int main(int argc, char *argv[])
qtest_add_func("acpi/piix4/tcg/bridge", test_acpi_piix4_tcg_bridge);
qtest_add_func("acpi/q35/tcg", test_acpi_q35_tcg);
qtest_add_func("acpi/q35/tcg/bridge", test_acpi_q35_tcg_bridge);
+ qtest_add_func("acpi/piix4/tcg/ipmi", test_acpi_piix4_tcg_ipmi);
+ qtest_add_func("acpi/q35/tcg/ipmi", test_acpi_q35_tcg_ipmi);
}
ret = g_test_run();
unlink(disk);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (15 preceding siblings ...)
2015-04-23 22:57 ` [Qemu-devel] [PATCH 17/17] bios: Add tests for the IPMI ACPI and SMBIOS entries minyard
@ 2015-04-23 23:11 ` Eric Blake
2015-04-26 11:39 ` Andreas Färber
2015-04-24 9:38 ` Paolo Bonzini
17 siblings, 1 reply; 38+ messages in thread
From: Eric Blake @ 2015-04-23 23:11 UTC (permalink / raw)
To: minyard, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1083 bytes --]
On 04/23/2015 04:57 PM, minyard@acm.org wrote:
> The major changes from last time are:
That says this series should probably be named v2 (git
format-patch/send-email -v2) or later, as part of the subject line. If
the previous version is more than a couple weeks ago, it's also nice
(but not required) to provide a URL to the archives of the previous
discussion.
>
> * Don't use callbacks for adding firmware tables, provide binary
> blobs instead.
>
> * Add the SSDT as a separate table.
>
> * Modify the BIOS tests to test for the IPMI tables.
>
Also, you might want to use git format-patch --cover-letter, which helps
form a 00/17 letter with a diffstat pre-filled; the diffstat gives
reviewers a quick glance at what files are touched, and how many lines
of code are being impacted, which makes it easier to decide when to
schedule a review for the series.
More patch submission hints at: http://wiki.qemu.org/Contribute/SubmitAPatch
--
Eric Blake eblake redhat com +1-919-301-3266
Libvirt virtualization library http://libvirt.org
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 604 bytes --]
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
` (16 preceding siblings ...)
2015-04-23 23:11 ` [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu Eric Blake
@ 2015-04-24 9:38 ` Paolo Bonzini
2015-04-24 13:07 ` Corey Minyard
17 siblings, 1 reply; 38+ messages in thread
From: Paolo Bonzini @ 2015-04-24 9:38 UTC (permalink / raw)
To: minyard, qemu-devel, Michael S. Tsirkin
On 24/04/2015 00:57, minyard@acm.org wrote:
> The major changes from last time are:
>
> * Don't use callbacks for adding firmware tables, provide binary
> blobs instead.
>
> * Add the SSDT as a separate table.
>
> * Modify the BIOS tests to test for the IPMI tables.
I disagree with both of the first two changes, but thanks for doing them
nevertheless. Michael, is this okay with you now?
Paolo
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu
2015-04-24 9:38 ` Paolo Bonzini
@ 2015-04-24 13:07 ` Corey Minyard
0 siblings, 0 replies; 38+ messages in thread
From: Corey Minyard @ 2015-04-24 13:07 UTC (permalink / raw)
To: Paolo Bonzini, qemu-devel, Michael S. Tsirkin
On 04/24/2015 04:38 AM, Paolo Bonzini wrote:
>
> On 24/04/2015 00:57, minyard@acm.org wrote:
>> The major changes from last time are:
>>
>> * Don't use callbacks for adding firmware tables, provide binary
>> blobs instead.
>>
>> * Add the SSDT as a separate table.
>>
>> * Modify the BIOS tests to test for the IPMI tables.
> I disagree with both of the first two changes, but thanks for doing them
> nevertheless. Michael, is this okay with you now?
To me it was not a big deal either way. The change made the code a
bit more consistent with what was already there, and having the SSDT
as a separate table made the testing a lot easier, as Michael said it
would.
-corey
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 16/17] ipmi: Add ACPI table entries
2015-04-23 22:57 ` [Qemu-devel] [PATCH 16/17] ipmi: Add ACPI table entries minyard
@ 2015-04-26 8:36 ` Michael S. Tsirkin
0 siblings, 0 replies; 38+ messages in thread
From: Michael S. Tsirkin @ 2015-04-26 8:36 UTC (permalink / raw)
To: minyard; +Cc: Corey Minyard, qemu-devel
On Thu, Apr 23, 2015 at 05:57:57PM -0500, minyard@acm.org wrote:
> From: Corey Minyard <cminyard@mvista.com>
>
> Use the new ACPI table construction tools to create an ACPI
> entry for IPMI.
>
> Signed-off-by: Corey Minyard <cminyard@mvista.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/ipmi/Makefile.objs | 1 +
> hw/ipmi/ipmi_acpi.c | 122 ++++++++++++++++++++++++++++++++++++++++++++++++++
> hw/ipmi/isa_ipmi.c | 4 ++
> 3 files changed, 127 insertions(+)
> create mode 100644 hw/ipmi/ipmi_acpi.c
>
> diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
> index d0129cf..17ca09f 100644
> --- a/hw/ipmi/Makefile.objs
> +++ b/hw/ipmi/Makefile.objs
> @@ -5,3 +5,4 @@ common-obj-$(CONFIG_IPMI_BT) += ipmi_bt.o
> common-obj-$(CONFIG_IPMI_LOCAL) += ipmi_sim.o
> common-obj-$(CONFIG_IPMI_EXTERN) += ipmi_extern.o
> common-obj-$(call land,$(CONFIG_IPMI),$(CONFIG_SMBIOS)) += ipmi_smbios.o
> +common-obj-$(call land,$(CONFIG_IPMI),$(CONFIG_ACPI)) += ipmi_acpi.o
> diff --git a/hw/ipmi/ipmi_acpi.c b/hw/ipmi/ipmi_acpi.c
> new file mode 100644
> index 0000000..e014da7
> --- /dev/null
> +++ b/hw/ipmi/ipmi_acpi.c
> @@ -0,0 +1,122 @@
> +/*
> + * IPMI ACPI firmware handling
> + *
> + * Copyright (c) 2015 Corey Minyard, MontaVista Software, LLC
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "ipmi.h"
> +#include "hw/acpi/aml-build.h"
> +#include "hw/acpi/acpi.h"
> +#include "hw/acpi/acpi-dev-tables.h"
> +#include <qemu/error-report.h>
> +
> +static Aml *aml_ipmi_crs(IPMIFwInfo *info)
> +{
> + Aml *crs = aml_resource_template();
> + uint8_t regspacing = info->register_spacing;
> +
> + if (regspacing == 1) {
> + regspacing = 0;
> + }
> +
> + switch (info->memspace) {
> + case IPMI_MEMSPACE_IO:
> + aml_append(crs, aml_io(aml_decode16, info->base_address,
> + info->base_address + info->register_length - 1,
> + regspacing, info->register_length));
> + break;
> + case IPMI_MEMSPACE_MEM32:
> + aml_append(crs,
> + aml_dword_memory(aml_pos_decode,
> + aml_min_fixed, aml_max_fixed,
> + aml_non_cacheable, aml_ReadWrite,
> + 0xffffffff,
> + info->base_address,
> + info->base_address + info->register_length - 1,
> + regspacing, info->register_length));
> + break;
> + case IPMI_MEMSPACE_MEM64:
> + aml_append(crs,
> + aml_qword_memory(aml_pos_decode,
> + aml_min_fixed, aml_max_fixed,
> + aml_non_cacheable, aml_ReadWrite,
> + 0xffffffffffffffffULL,
> + info->base_address,
> + info->base_address + info->register_length - 1,
> + regspacing, info->register_length));
> + break;
> + case IPMI_MEMSPACE_SMBUS:
> + aml_append(crs, aml_return(aml_int(info->base_address)));
> + break;
> + }
> +
> + if (info->interrupt_number) {
> + aml_append(crs, aml_irq_no_flags(info->interrupt_number));
> + }
> +
> + return crs;
> +}
> +
> +static void
> +ipmi_encode_one_acpi(IPMIFwInfo *info, void *opaque)
> +{
> + Aml *ssdt, *scope, *dev, *method;
> + char *name;
> + int version = ((info->ipmi_spec_major_revision << 8)
> + | (info->ipmi_spec_minor_revision << 4));
> +
> + if (!info->acpi_parent) {
> + ipmi_debug("device %s not compatible with ACPI, no parent given.",
> + info->interface_name);
> + return;
> + }
> +
> + ssdt = init_aml_allocator();
> +
> + scope = aml_scope("%s", info->acpi_parent);
> + name = g_strdup_printf("ipmi_%s", info->interface_name);
> +
> + dev = aml_device("MI0");
> + aml_append(dev, aml_name_decl("_HID", aml_eisaid("IPI0001")));
> + aml_append(dev, aml_name_decl("_STR", aml_string("%s", name)));
> + aml_append(dev, aml_name_decl("_UID", aml_int(0)));
> + aml_append(dev, aml_name_decl("_CRS", aml_ipmi_crs(info)));
> + method = aml_method("_IFT", 0);
> + aml_append(method, aml_return(aml_int(info->interface_type)));
> + aml_append(dev, method);
> + method = aml_method("_SRV", 0);
> + aml_append(method, aml_return(aml_int(version)));
> + aml_append(dev, method);
> +
> + aml_append(scope, dev);
> +
> + aml_append(ssdt, scope);
> +
> + add_acpi_dev_table(ssdt->buf->data, ssdt->buf->len, "SSDT", 1);
> + free_aml_allocator();
> +}
> +
> +static void ipmi_acpi_init(void)
> +{
> + ipmi_register_fwinfo_handler(ipmi_encode_one_acpi, NULL);
> +}
> +
> +type_init(ipmi_acpi_init);
> diff --git a/hw/ipmi/isa_ipmi.c b/hw/ipmi/isa_ipmi.c
> index da86247..ae6d3c8 100644
> --- a/hw/ipmi/isa_ipmi.c
> +++ b/hw/ipmi/isa_ipmi.c
> @@ -37,6 +37,8 @@ typedef struct ISAIPMIDevice {
> ISADevice dev;
> char *interface;
> uint32_t iobase;
> + uint32_t iolength;
> + uint8_t regspacing;
> int32 isairq;
> uint8_t slave_addr;
> CharDriverState *chr;
> @@ -73,12 +75,14 @@ static void ipmi_isa_realizefn(DeviceState *dev, Error **errp)
> intfk = IPMI_INTERFACE_GET_CLASS(intf);
> bmc->intf = intf;
> intf->bmc = bmc;
> + ipmi->regspacing = 1;
> intf->io_base = ipmi->iobase;
> intf->slave_addr = ipmi->slave_addr;
> ipmi_interface_init(intf, errp);
> if (*errp) {
> return;
> }
> + ipmi->iolength = intf->io_length;
> ipmi_bmc_init(bmc, errp);
> if (*errp) {
> return;
> --
> 1.8.3.1
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 14/17] ipmi: Add SMBIOS table entry
2015-04-23 22:57 ` [Qemu-devel] [PATCH 14/17] ipmi: Add SMBIOS table entry minyard
@ 2015-04-26 8:36 ` Michael S. Tsirkin
0 siblings, 0 replies; 38+ messages in thread
From: Michael S. Tsirkin @ 2015-04-26 8:36 UTC (permalink / raw)
To: minyard; +Cc: Corey Minyard, qemu-devel
On Thu, Apr 23, 2015 at 05:57:55PM -0500, minyard@acm.org wrote:
> From: Corey Minyard <cminyard@mvista.com>
>
> Add an IPMI table entry to the SMBIOS.
>
> Signed-off-by: Corey Minyard <cminyard@mvista.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> default-configs/i386-softmmu.mak | 1 +
> default-configs/x86_64-softmmu.mak | 1 +
> hw/ipmi/Makefile.objs | 1 +
> hw/ipmi/ipmi_smbios.c | 89 ++++++++++++++++++++++++++++++++++++++
> 4 files changed, 92 insertions(+)
> create mode 100644 hw/ipmi/ipmi_smbios.c
>
> diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
> index 2448543..15c0b70 100644
> --- a/default-configs/i386-softmmu.mak
> +++ b/default-configs/i386-softmmu.mak
> @@ -20,6 +20,7 @@ CONFIG_I8254=y
> CONFIG_PCSPK=y
> CONFIG_PCKBD=y
> CONFIG_FDC=y
> +CONFIG_SMBIOS=y
> CONFIG_ACPI=y
> CONFIG_APM=y
> CONFIG_I8257=y
> diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
> index 3ed8877..dac877a 100644
> --- a/default-configs/x86_64-softmmu.mak
> +++ b/default-configs/x86_64-softmmu.mak
> @@ -20,6 +20,7 @@ CONFIG_I8254=y
> CONFIG_PCSPK=y
> CONFIG_PCKBD=y
> CONFIG_FDC=y
> +CONFIG_SMBIOS=y
> CONFIG_ACPI=y
> CONFIG_APM=y
> CONFIG_I8257=y
> diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
> index abfa827..d0129cf 100644
> --- a/hw/ipmi/Makefile.objs
> +++ b/hw/ipmi/Makefile.objs
> @@ -4,3 +4,4 @@ common-obj-$(CONFIG_IPMI_KCS) += ipmi_kcs.o
> common-obj-$(CONFIG_IPMI_BT) += ipmi_bt.o
> common-obj-$(CONFIG_IPMI_LOCAL) += ipmi_sim.o
> common-obj-$(CONFIG_IPMI_EXTERN) += ipmi_extern.o
> +common-obj-$(call land,$(CONFIG_IPMI),$(CONFIG_SMBIOS)) += ipmi_smbios.o
> diff --git a/hw/ipmi/ipmi_smbios.c b/hw/ipmi/ipmi_smbios.c
> new file mode 100644
> index 0000000..b818f5b
> --- /dev/null
> +++ b/hw/ipmi/ipmi_smbios.c
> @@ -0,0 +1,89 @@
> +/*
> + * IPMI SMBIOS firmware handling
> + *
> + * Copyright (c) 2015 Corey Minyard, MontaVista Software, LLC
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "ipmi.h"
> +#include <hw/i386/smbios.h>
> +#include <qemu/error-report.h>
> +
> +/* SMBIOS type 38 - IPMI */
> +struct smbios_type_38 {
> + struct smbios_structure_header header;
> + uint8_t interface_type;
> + uint8_t ipmi_spec_revision;
> + uint8_t i2c_slave_address;
> + uint8_t nv_storage_device_address;
> + uint64_t base_address;
> + uint8_t base_address_modifier;
> + uint8_t interrupt_number;
> +} QEMU_PACKED;
> +
> +static void ipmi_encode_one_smbios(IPMIFwInfo *info, void *opaque)
> +{
> + struct smbios_type_38 smb38;
> + uint64_t baseaddr = info->base_address;
> +
> + smb38.header.type = 38;
> + smb38.header.length = sizeof(smb38);
> + smb38.header.handle = cpu_to_le16(0x3000);
> + smb38.interface_type = info->interface_type;
> + smb38.ipmi_spec_revision = ((info->ipmi_spec_major_revision << 4)
> + | info->ipmi_spec_minor_revision);
> + smb38.i2c_slave_address = info->i2c_slave_address;
> + smb38.nv_storage_device_address = 0;
> +
> + /* or 1 to set it to I/O space */
> + switch (info->memspace) {
> + case IPMI_MEMSPACE_IO: baseaddr |= 1; break;
> + case IPMI_MEMSPACE_MEM32: break;
> + case IPMI_MEMSPACE_MEM64: break;
> + case IPMI_MEMSPACE_SMBUS: baseaddr <<= 1; break;
> + }
> +
> + smb38.base_address = cpu_to_le64(baseaddr);
> +
> + smb38.base_address_modifier = 0;
> + if (info->irq_type == IPMI_LEVEL_IRQ) {
> + smb38.base_address_modifier |= 1;
> + }
> + switch (info->register_spacing) {
> + case 1: break;
> + case 4: smb38.base_address_modifier |= 1 << 6; break;
> + case 16: smb38.base_address_modifier |= 2 << 6; break;
> + default:
> + error_report("IPMI register spacing %d is not compatible with"
> + " SMBIOS, ignoring this entry.", info->register_spacing);
> + return;
> + }
> + smb38.interrupt_number = info->interrupt_number;
> +
> + smbios_add_table_entry((struct smbios_structure_header *) &smb38,
> + sizeof(smb38), true);
> +}
> +
> +static void smbios_init(void)
> +{
> + ipmi_register_fwinfo_handler(ipmi_encode_one_smbios, NULL);
> +}
> +
> +type_init(smbios_init);
> --
> 1.8.3.1
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-04-23 22:57 ` [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure minyard
@ 2015-04-26 8:58 ` Michael S. Tsirkin
2015-04-26 9:07 ` Michael S. Tsirkin
2015-05-08 21:16 ` Corey Minyard
2015-04-26 9:05 ` Michael S. Tsirkin
1 sibling, 2 replies; 38+ messages in thread
From: Michael S. Tsirkin @ 2015-04-26 8:58 UTC (permalink / raw)
To: minyard; +Cc: Corey Minyard, andreas.faerber, qemu-devel
On Thu, Apr 23, 2015 at 05:57:43PM -0500, minyard@acm.org wrote:
> From: Corey Minyard <cminyard@mvista.com>
>
> This provides the base infrastructure to tie IPMI low-level
> interfaces into a PC ISA bus.
>
> Signed-off-by: Corey Minyard <cminyard@mvista.com>
> ---
> default-configs/i386-softmmu.mak | 1 +
> default-configs/x86_64-softmmu.mak | 1 +
> hw/ipmi/Makefile.objs | 1 +
> hw/ipmi/isa_ipmi.c | 144 +++++++++++++++++++++++++++++++++++++
> include/hw/nvram/fw_cfg.h | 11 ++-
> 5 files changed, 157 insertions(+), 1 deletion(-)
> create mode 100644 hw/ipmi/isa_ipmi.c
>
> diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
> index ab1a552..1c3153b 100644
> --- a/default-configs/i386-softmmu.mak
> +++ b/default-configs/i386-softmmu.mak
> @@ -9,6 +9,7 @@ CONFIG_VGA_CIRRUS=y
> CONFIG_VMWARE_VGA=y
> CONFIG_VMMOUSE=y
> CONFIG_IPMI=y
> +CONFIG_ISA_IPMI=y
> CONFIG_SERIAL=y
> CONFIG_PARALLEL=y
> CONFIG_I8254=y
> diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
> index 82bafcc..6b57430 100644
> --- a/default-configs/x86_64-softmmu.mak
> +++ b/default-configs/x86_64-softmmu.mak
> @@ -9,6 +9,7 @@ CONFIG_VGA_CIRRUS=y
> CONFIG_VMWARE_VGA=y
> CONFIG_VMMOUSE=y
> CONFIG_IPMI=y
> +CONFIG_ISA_IPMI=y
> CONFIG_SERIAL=y
> CONFIG_PARALLEL=y
> CONFIG_I8254=y
> diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
> index 65bde11..1518216 100644
> --- a/hw/ipmi/Makefile.objs
> +++ b/hw/ipmi/Makefile.objs
> @@ -1 +1,2 @@
> +common-obj-$(CONFIG_ISA_IPMI) += isa_ipmi.o
> common-obj-$(CONFIG_IPMI) += ipmi.o
> diff --git a/hw/ipmi/isa_ipmi.c b/hw/ipmi/isa_ipmi.c
> new file mode 100644
> index 0000000..1c1ab8d
> --- /dev/null
> +++ b/hw/ipmi/isa_ipmi.c
> @@ -0,0 +1,144 @@
> +/*
> + * QEMU ISA IPMI emulation
> + *
> + * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +#include "hw/hw.h"
> +#include "hw/isa/isa.h"
> +#include "hw/i386/pc.h"
> +#include "qemu/timer.h"
> +#include "sysemu/char.h"
> +#include "sysemu/sysemu.h"
> +#include "ipmi.h"
> +
> +/* This is the type the user specifies on the -device command line */
> +#define TYPE_ISA_IPMI "isa-ipmi"
> +#define ISA_IPMI(obj) OBJECT_CHECK(ISAIPMIDevice, (obj), TYPE_ISA_IPMI)
> +
> +typedef struct ISAIPMIDevice {
> + ISADevice dev;
> + char *interface;
> + uint32_t iobase;
> + int32 isairq;
> + uint8_t slave_addr;
> + CharDriverState *chr;
> + IPMIInterface *intf;
> +} ISAIPMIDevice;
> +
> +static void ipmi_isa_realizefn(DeviceState *dev, Error **errp)
> +{
> + ISADevice *isadev = ISA_DEVICE(dev);
> + ISAIPMIDevice *ipmi = ISA_IPMI(dev);
> + char typename[20];
> + Object *intfobj;
> + IPMIInterface *intf;
> + Object *bmcobj;
> + IPMIBmc *bmc;
> +
> + if (!ipmi->interface) {
> + ipmi->interface = g_strdup("kcs");
> + }
> +
> + if (ipmi->chr) {
> + bmcobj = object_new(TYPE_IPMI_BMC_EXTERN);
> + } else {
> + bmcobj = object_new(TYPE_IPMI_BMC_SIMULATOR);
> + }
> + bmc = IPMI_BMC(bmcobj);
> + bmc->chr = ipmi->chr;
> + snprintf(typename, sizeof(typename),
> + TYPE_IPMI_INTERFACE_PREFIX "%s", ipmi->interface);
> + intfobj = object_new(typename);
I wonder what Andreas thinks about this.
There are only 3 legal types, correct?
I think it would be cleaner to avoid the prefix trick,
and just do a plain
if (!ipmi->interface)) {
typename = TYPE_IPMI_INTERFACE_KCS
} else if (!strcmp(ipmi->interface, "kcs")) {
typename = TYPE_IPMI_INTERFACE_KCS
} else if ....
etc
> + intf = IPMI_INTERFACE(intfobj);
> + bmc->intf = intf;
> + intf->bmc = bmc;
> + intf->io_base = ipmi->iobase;
> + intf->slave_addr = ipmi->slave_addr;
> + ipmi_interface_init(intf, errp);
> + if (*errp) {
> + return;
> + }
> + ipmi_bmc_init(bmc, errp);
> + if (*errp) {
> + return;
> + }
> +
> + /* These may be set by the interface. */
> + ipmi->iobase = intf->io_base;
> + ipmi->slave_addr = intf->slave_addr;
> +
> + if (ipmi->isairq > 0) {
> + isa_init_irq(isadev, &intf->irq, ipmi->isairq);
> + intf->use_irq = 1;
> + }
> +
> + ipmi->intf = intf;
> + object_property_add_child(OBJECT(isadev), "intf", OBJECT(intf), errp);
> + if (*errp) {
> + return;
> + }
> + object_property_add_child(OBJECT(isadev), "bmc", OBJECT(bmc), errp);
> + if (*errp) {
> + return;
> + }
> +
Should the created object be destroyed before return?
> + qdev_set_legacy_instance_id(dev, intf->io_base, intf->io_length);
> +
> + isa_register_ioport(isadev, &intf->io, intf->io_base);
> +}
> +
> +static void ipmi_isa_reset(DeviceState *qdev)
> +{
> + ISAIPMIDevice *isa = ISA_IPMI(qdev);
> +
> + ipmi_interface_reset(isa->intf);
> +}
> +
> +static Property ipmi_isa_properties[] = {
> + DEFINE_PROP_STRING("interface", ISAIPMIDevice, interface),
> + DEFINE_PROP_UINT32("iobase", ISAIPMIDevice, iobase, 0),
> + DEFINE_PROP_INT32("irq", ISAIPMIDevice, isairq, 5),
> + DEFINE_PROP_UINT8("slave_addr", ISAIPMIDevice, slave_addr, 0),
> + DEFINE_PROP_CHR("chardev", ISAIPMIDevice, chr),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ipmi_isa_class_initfn(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + dc->realize = ipmi_isa_realizefn;
> + dc->reset = ipmi_isa_reset;
> + dc->props = ipmi_isa_properties;
> +}
> +
> +static const TypeInfo ipmi_isa_info = {
> + .name = TYPE_ISA_IPMI,
> + .parent = TYPE_ISA_DEVICE,
> + .instance_size = sizeof(ISAIPMIDevice),
> + .class_init = ipmi_isa_class_initfn,
> +};
> +
> +static void ipmi_register_types(void)
> +{
> + type_register_static(&ipmi_isa_info);
> +}
> +
> +type_init(ipmi_register_types)
> diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
> index 6d8a8ac..cac3a34 100644
> --- a/include/hw/nvram/fw_cfg.h
> +++ b/include/hw/nvram/fw_cfg.h
> @@ -38,7 +38,16 @@
>
> #define FW_CFG_FILE_FIRST 0x20
> #define FW_CFG_FILE_SLOTS 0x10
> -#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
> +
> +#define FW_CFG_IPMI_INTERFACE 0x30
> +#define FW_CFG_IPMI_BASE_ADDR 0x31
> +#define FW_CFG_IPMI_REG_SPACE 0x32
> +#define FW_CFG_IPMI_REG_SPACING 0x33
> +#define FW_CFG_IPMI_SLAVE_ADDR 0x34
> +#define FW_CFG_IPMI_IRQ 0x35
> +#define FW_CFG_IPMI_VERSION 0x36
> +
> +#define FW_CFG_MAX_ENTRY (FW_CFG_IPMI_VERSION + 1)
>
> #define FW_CFG_WRITE_CHANNEL 0x4000
> #define FW_CFG_ARCH_LOCAL 0x8000
> --
> 1.8.3.1
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-04-23 22:57 ` [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure minyard
2015-04-26 8:58 ` Michael S. Tsirkin
@ 2015-04-26 9:05 ` Michael S. Tsirkin
2015-04-26 17:03 ` Paolo Bonzini
1 sibling, 1 reply; 38+ messages in thread
From: Michael S. Tsirkin @ 2015-04-26 9:05 UTC (permalink / raw)
To: minyard; +Cc: Corey Minyard, qemu-devel
On Thu, Apr 23, 2015 at 05:57:43PM -0500, minyard@acm.org wrote:
> From: Corey Minyard <cminyard@mvista.com>
>
> This provides the base infrastructure to tie IPMI low-level
> interfaces into a PC ISA bus.
>
> Signed-off-by: Corey Minyard <cminyard@mvista.com>
> ---
> default-configs/i386-softmmu.mak | 1 +
> default-configs/x86_64-softmmu.mak | 1 +
> hw/ipmi/Makefile.objs | 1 +
> hw/ipmi/isa_ipmi.c | 144 +++++++++++++++++++++++++++++++++++++
> include/hw/nvram/fw_cfg.h | 11 ++-
> 5 files changed, 157 insertions(+), 1 deletion(-)
> create mode 100644 hw/ipmi/isa_ipmi.c
>
> diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
> index ab1a552..1c3153b 100644
> --- a/default-configs/i386-softmmu.mak
> +++ b/default-configs/i386-softmmu.mak
> @@ -9,6 +9,7 @@ CONFIG_VGA_CIRRUS=y
> CONFIG_VMWARE_VGA=y
> CONFIG_VMMOUSE=y
> CONFIG_IPMI=y
> +CONFIG_ISA_IPMI=y
> CONFIG_SERIAL=y
> CONFIG_PARALLEL=y
> CONFIG_I8254=y
> diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
> index 82bafcc..6b57430 100644
> --- a/default-configs/x86_64-softmmu.mak
> +++ b/default-configs/x86_64-softmmu.mak
> @@ -9,6 +9,7 @@ CONFIG_VGA_CIRRUS=y
> CONFIG_VMWARE_VGA=y
> CONFIG_VMMOUSE=y
> CONFIG_IPMI=y
> +CONFIG_ISA_IPMI=y
> CONFIG_SERIAL=y
> CONFIG_PARALLEL=y
> CONFIG_I8254=y
> diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
> index 65bde11..1518216 100644
> --- a/hw/ipmi/Makefile.objs
> +++ b/hw/ipmi/Makefile.objs
> @@ -1 +1,2 @@
> +common-obj-$(CONFIG_ISA_IPMI) += isa_ipmi.o
> common-obj-$(CONFIG_IPMI) += ipmi.o
> diff --git a/hw/ipmi/isa_ipmi.c b/hw/ipmi/isa_ipmi.c
> new file mode 100644
> index 0000000..1c1ab8d
> --- /dev/null
> +++ b/hw/ipmi/isa_ipmi.c
> @@ -0,0 +1,144 @@
> +/*
> + * QEMU ISA IPMI emulation
> + *
> + * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +#include "hw/hw.h"
> +#include "hw/isa/isa.h"
> +#include "hw/i386/pc.h"
> +#include "qemu/timer.h"
> +#include "sysemu/char.h"
> +#include "sysemu/sysemu.h"
> +#include "ipmi.h"
> +
> +/* This is the type the user specifies on the -device command line */
> +#define TYPE_ISA_IPMI "isa-ipmi"
> +#define ISA_IPMI(obj) OBJECT_CHECK(ISAIPMIDevice, (obj), TYPE_ISA_IPMI)
> +
> +typedef struct ISAIPMIDevice {
> + ISADevice dev;
> + char *interface;
> + uint32_t iobase;
> + int32 isairq;
> + uint8_t slave_addr;
> + CharDriverState *chr;
> + IPMIInterface *intf;
> +} ISAIPMIDevice;
> +
> +static void ipmi_isa_realizefn(DeviceState *dev, Error **errp)
> +{
> + ISADevice *isadev = ISA_DEVICE(dev);
> + ISAIPMIDevice *ipmi = ISA_IPMI(dev);
> + char typename[20];
> + Object *intfobj;
> + IPMIInterface *intf;
> + Object *bmcobj;
> + IPMIBmc *bmc;
> +
> + if (!ipmi->interface) {
> + ipmi->interface = g_strdup("kcs");
> + }
> +
> + if (ipmi->chr) {
> + bmcobj = object_new(TYPE_IPMI_BMC_EXTERN);
> + } else {
> + bmcobj = object_new(TYPE_IPMI_BMC_SIMULATOR);
> + }
> + bmc = IPMI_BMC(bmcobj);
> + bmc->chr = ipmi->chr;
> + snprintf(typename, sizeof(typename),
> + TYPE_IPMI_INTERFACE_PREFIX "%s", ipmi->interface);
> + intfobj = object_new(typename);
> + intf = IPMI_INTERFACE(intfobj);
> + bmc->intf = intf;
> + intf->bmc = bmc;
> + intf->io_base = ipmi->iobase;
> + intf->slave_addr = ipmi->slave_addr;
> + ipmi_interface_init(intf, errp);
> + if (*errp) {
> + return;
> + }
> + ipmi_bmc_init(bmc, errp);
> + if (*errp) {
> + return;
> + }
> +
> + /* These may be set by the interface. */
> + ipmi->iobase = intf->io_base;
> + ipmi->slave_addr = intf->slave_addr;
> +
> + if (ipmi->isairq > 0) {
> + isa_init_irq(isadev, &intf->irq, ipmi->isairq);
> + intf->use_irq = 1;
> + }
> +
> + ipmi->intf = intf;
> + object_property_add_child(OBJECT(isadev), "intf", OBJECT(intf), errp);
> + if (*errp) {
> + return;
> + }
> + object_property_add_child(OBJECT(isadev), "bmc", OBJECT(bmc), errp);
> + if (*errp) {
> + return;
> + }
> +
> + qdev_set_legacy_instance_id(dev, intf->io_base, intf->io_length);
> +
> + isa_register_ioport(isadev, &intf->io, intf->io_base);
> +}
> +
> +static void ipmi_isa_reset(DeviceState *qdev)
> +{
> + ISAIPMIDevice *isa = ISA_IPMI(qdev);
> +
> + ipmi_interface_reset(isa->intf);
> +}
> +
> +static Property ipmi_isa_properties[] = {
> + DEFINE_PROP_STRING("interface", ISAIPMIDevice, interface),
> + DEFINE_PROP_UINT32("iobase", ISAIPMIDevice, iobase, 0),
> + DEFINE_PROP_INT32("irq", ISAIPMIDevice, isairq, 5),
> + DEFINE_PROP_UINT8("slave_addr", ISAIPMIDevice, slave_addr, 0),
> + DEFINE_PROP_CHR("chardev", ISAIPMIDevice, chr),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ipmi_isa_class_initfn(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + dc->realize = ipmi_isa_realizefn;
> + dc->reset = ipmi_isa_reset;
> + dc->props = ipmi_isa_properties;
> +}
> +
> +static const TypeInfo ipmi_isa_info = {
> + .name = TYPE_ISA_IPMI,
> + .parent = TYPE_ISA_DEVICE,
> + .instance_size = sizeof(ISAIPMIDevice),
> + .class_init = ipmi_isa_class_initfn,
> +};
> +
> +static void ipmi_register_types(void)
> +{
> + type_register_static(&ipmi_isa_info);
> +}
> +
> +type_init(ipmi_register_types)
> diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
> index 6d8a8ac..cac3a34 100644
> --- a/include/hw/nvram/fw_cfg.h
> +++ b/include/hw/nvram/fw_cfg.h
> @@ -38,7 +38,16 @@
>
> #define FW_CFG_FILE_FIRST 0x20
> #define FW_CFG_FILE_SLOTS 0x10
> -#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
> +
> +#define FW_CFG_IPMI_INTERFACE 0x30
> +#define FW_CFG_IPMI_BASE_ADDR 0x31
> +#define FW_CFG_IPMI_REG_SPACE 0x32
> +#define FW_CFG_IPMI_REG_SPACING 0x33
> +#define FW_CFG_IPMI_SLAVE_ADDR 0x34
> +#define FW_CFG_IPMI_IRQ 0x35
> +#define FW_CFG_IPMI_VERSION 0x36
> +
> +#define FW_CFG_MAX_ENTRY (FW_CFG_IPMI_VERSION + 1)
>
> #define FW_CFG_WRITE_CHANNEL 0x4000
> #define FW_CFG_ARCH_LOCAL 0x8000
Can IPMI use fw cfg file interface?
This is, generally, preferred.
> --
> 1.8.3.1
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-04-26 8:58 ` Michael S. Tsirkin
@ 2015-04-26 9:07 ` Michael S. Tsirkin
2015-05-08 21:16 ` Corey Minyard
1 sibling, 0 replies; 38+ messages in thread
From: Michael S. Tsirkin @ 2015-04-26 9:07 UTC (permalink / raw)
To: minyard; +Cc: Corey Minyard, andreas.faerber, qemu-devel
On Sun, Apr 26, 2015 at 10:58:56AM +0200, Michael S. Tsirkin wrote:
> On Thu, Apr 23, 2015 at 05:57:43PM -0500, minyard@acm.org wrote:
> > From: Corey Minyard <cminyard@mvista.com>
> >
> > This provides the base infrastructure to tie IPMI low-level
> > interfaces into a PC ISA bus.
> >
> > Signed-off-by: Corey Minyard <cminyard@mvista.com>
BTW can you version patches please?
recent git format-patch has a -v flag, older
ones let you use --subject-prefix='PATCH vX'.
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu
2015-04-23 23:11 ` [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu Eric Blake
@ 2015-04-26 11:39 ` Andreas Färber
2015-04-26 16:52 ` Paolo Bonzini
2015-04-27 13:19 ` Corey Minyard
0 siblings, 2 replies; 38+ messages in thread
From: Andreas Färber @ 2015-04-26 11:39 UTC (permalink / raw)
To: minyard, qemu-devel; +Cc: Peter Maydell, Michael S. Tsirkin
[-- Attachment #1: Type: text/plain, Size: 965 bytes --]
Am 24.04.2015 um 01:11 schrieb Eric Blake:
> On 04/23/2015 04:57 PM, minyard@acm.org wrote:
>> The major changes from last time are:
>
> That says this series should probably be named v2 (git
> format-patch/send-email -v2) or later, as part of the subject line. If
> the previous version is more than a couple weeks ago, it's also nice
> (but not required) to provide a URL to the archives of the previous
> discussion.
Even worse, I don't see any update on the licensing questions previously
raised... did Intel ever get back to you?
> Also, you might want to use git format-patch --cover-letter, which helps
> form a 00/17 letter with a diffstat pre-filled; the diffstat gives
> reviewers a quick glance at what files are touched, [...]
+1.
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Jennifer Guild, Dilip Upmanyu,
Graham Norton; HRB 21284 (AG Nürnberg)
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu
2015-04-26 11:39 ` Andreas Färber
@ 2015-04-26 16:52 ` Paolo Bonzini
2015-04-27 13:19 ` Corey Minyard
1 sibling, 0 replies; 38+ messages in thread
From: Paolo Bonzini @ 2015-04-26 16:52 UTC (permalink / raw)
To: Andreas Färber, minyard, qemu-devel
Cc: Peter Maydell, Michael S. Tsirkin
On 26/04/2015 13:39, Andreas Färber wrote:
>> That says this series should probably be named v2 (git
>> format-patch/send-email -v2) or later, as part of the subject
>> line. If the previous version is more than a couple weeks ago,
>> it's also nice (but not required) to provide a URL to the
>> archives of the previous discussion.
>
> Even worse, I don't see any update on the licensing questions
> previously raised... did Intel ever get back to you?
A reminder for the lazy and/or uninformed?
Paolo
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-04-26 9:05 ` Michael S. Tsirkin
@ 2015-04-26 17:03 ` Paolo Bonzini
2015-05-08 20:59 ` Corey Minyard
0 siblings, 1 reply; 38+ messages in thread
From: Paolo Bonzini @ 2015-04-26 17:03 UTC (permalink / raw)
To: Michael S. Tsirkin, minyard; +Cc: Corey Minyard, qemu-devel
On 26/04/2015 11:05, Michael S. Tsirkin wrote:
>> +
>> +#define FW_CFG_IPMI_INTERFACE 0x30
>> +#define FW_CFG_IPMI_BASE_ADDR 0x31
>> +#define FW_CFG_IPMI_REG_SPACE 0x32
>> +#define FW_CFG_IPMI_REG_SPACING 0x33
>> +#define FW_CFG_IPMI_SLAVE_ADDR 0x34
>> +#define FW_CFG_IPMI_IRQ 0x35
>> +#define FW_CFG_IPMI_VERSION 0x36
>> +
>> +#define FW_CFG_MAX_ENTRY (FW_CFG_IPMI_VERSION + 1)
Also, what is this used for? I haven't seen firmware patches, maybe
it's obsoleted by SMBIOS support in QEMU?
Paolo
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu
2015-04-26 11:39 ` Andreas Färber
2015-04-26 16:52 ` Paolo Bonzini
@ 2015-04-27 13:19 ` Corey Minyard
1 sibling, 0 replies; 38+ messages in thread
From: Corey Minyard @ 2015-04-27 13:19 UTC (permalink / raw)
To: Andreas Färber, qemu-devel
Cc: Bret Ketchum, Peter Maydell, Michael S. Tsirkin
On 04/26/2015 06:39 AM, Andreas Färber wrote:
> Am 24.04.2015 um 01:11 schrieb Eric Blake:
>> On 04/23/2015 04:57 PM, minyard@acm.org wrote:
>>> The major changes from last time are:
>> That says this series should probably be named v2 (git
>> format-patch/send-email -v2) or later, as part of the subject line. If
>> the previous version is more than a couple weeks ago, it's also nice
>> (but not required) to provide a URL to the archives of the previous
>> discussion.
> Even worse, I don't see any update on the licensing questions previously
> raised... did Intel ever get back to you?
This is the last update I received from Bret Ketchum. From what he says
we will get nothing from Intel on this and everything seems ok:
From my understanding you'll not be receiving anything official from
Intel. My understanding from Tom is that there are open source KCS/BT
drivers existing in the wild with no IPMI adopters asserting IP on those
drivers. The specification places requirement son VMC but does not do
the same for software.
The Adotpers Agreement may be looked at as benign/beneficial. At one
level the agreement limits the extent that fellow Adopters can assert IP
claims against other signers.
I only bring this up (again) in that I've a request for the update
to these patches I mentioned on the mailing list.
Another option may be for some other than yourself to post these
patches which would absolve you from any recompense.
On Thu, Mar 6, 2014 at 6:48 PM, Corey Minyard <minyard@acm.org
<mailto:minyard@acm.org>> wrote:
On 03/06/2014 06:02 AM, Bret Ketchum wrote:
>
>
> What needs to be done to unstick the IPMI patches? Are you waiting
> on something from Intel legal? My email exchanges with Tom Slaight and
> Akkiah_Maddukuri do not suggest a legal issue with regards to a shim
> protocol that facilitates a IPMI client talking to an IPMI server.
>
I'm waiting for something from Intel. I don't have contact info for
anyone at Intel. And email from Tom Slaight would probably be good
enough
It's more than just a shim protocol, too. There is an implementation of
simulated KCS and BT hardware and a small simulated BMC that provides
basic function and a watchdog. We could lose the BMC, but not the
hardware simulations.
Thanks,
-corey
>
> On Tue, Mar 4, 2014 at 6:38 PM, <minyard@acm.org
<mailto:minyard@acm.org>
> <mailto:minyard@acm.org <mailto:minyard@acm.org>>> wrote:
>
> This patch set was part of the IPMI patches, but people have asked
> it to be
> separated out because it's useful by itself and the IPMI patches
> are stuck
> in legal limbo.
>
> I have left the patch to move allocating CharDriverState in
one place
> (patch 1). I didn't get much opinion either way, but I think
it is
> an improvement and a net reduction in code. I also added a patch
> (patch 6)
> that goes another step there, it makes the error handling in
> qmp_chardev_add() consistent and is also a net reduction in code.
>
> The main patches to add the feature are patch 2 and patch 3.
>
> The rest are little possible bug fixes that I noticed while
> working in the
> code.
>
> I went through all the comments and I believe I fixed everything.
>
> Thanks to everyone that reviewed this before.
>
>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-04-26 17:03 ` Paolo Bonzini
@ 2015-05-08 20:59 ` Corey Minyard
0 siblings, 0 replies; 38+ messages in thread
From: Corey Minyard @ 2015-05-08 20:59 UTC (permalink / raw)
To: Paolo Bonzini, Michael S. Tsirkin; +Cc: Corey Minyard, qemu-devel
On 04/26/2015 12:03 PM, Paolo Bonzini wrote:
>
> On 26/04/2015 11:05, Michael S. Tsirkin wrote:
>>> +
>>> +#define FW_CFG_IPMI_INTERFACE 0x30
>>> +#define FW_CFG_IPMI_BASE_ADDR 0x31
>>> +#define FW_CFG_IPMI_REG_SPACE 0x32
>>> +#define FW_CFG_IPMI_REG_SPACING 0x33
>>> +#define FW_CFG_IPMI_SLAVE_ADDR 0x34
>>> +#define FW_CFG_IPMI_IRQ 0x35
>>> +#define FW_CFG_IPMI_VERSION 0x36
>>> +
>>> +#define FW_CFG_MAX_ENTRY (FW_CFG_IPMI_VERSION + 1)
> Also, what is this used for? I haven't seen firmware patches, maybe
> it's obsoleted by SMBIOS support in QEMU?
>
> Paolo
Finally back on this. This is bogus, it was left over from something
else, and I missed it because it was at the end of the file.
-corey
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-04-26 8:58 ` Michael S. Tsirkin
2015-04-26 9:07 ` Michael S. Tsirkin
@ 2015-05-08 21:16 ` Corey Minyard
2015-05-11 14:21 ` Paolo Bonzini
2015-05-11 17:26 ` Andreas Färber
1 sibling, 2 replies; 38+ messages in thread
From: Corey Minyard @ 2015-05-08 21:16 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: Corey Minyard, andreas.faerber, qemu-devel
On 04/26/2015 03:58 AM, Michael S. Tsirkin wrote:
> On Thu, Apr 23, 2015 at 05:57:43PM -0500, minyard@acm.org wrote:
>> From: Corey Minyard <cminyard@mvista.com>
>>
>> This provides the base infrastructure to tie IPMI low-level
>> interfaces into a PC ISA bus.
>>
>> Signed-off-by: Corey Minyard <cminyard@mvista.com>
>> ---
>> default-configs/i386-softmmu.mak | 1 +
>> default-configs/x86_64-softmmu.mak | 1 +
>> hw/ipmi/Makefile.objs | 1 +
>> hw/ipmi/isa_ipmi.c | 144 +++++++++++++++++++++++++++++++++++++
>> include/hw/nvram/fw_cfg.h | 11 ++-
>> 5 files changed, 157 insertions(+), 1 deletion(-)
>> create mode 100644 hw/ipmi/isa_ipmi.c
>>
>> diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
>> index ab1a552..1c3153b 100644
>> --- a/default-configs/i386-softmmu.mak
>> +++ b/default-configs/i386-softmmu.mak
>> @@ -9,6 +9,7 @@ CONFIG_VGA_CIRRUS=y
>> CONFIG_VMWARE_VGA=y
>> CONFIG_VMMOUSE=y
>> CONFIG_IPMI=y
>> +CONFIG_ISA_IPMI=y
>> CONFIG_SERIAL=y
>> CONFIG_PARALLEL=y
>> CONFIG_I8254=y
>> diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
>> index 82bafcc..6b57430 100644
>> --- a/default-configs/x86_64-softmmu.mak
>> +++ b/default-configs/x86_64-softmmu.mak
>> @@ -9,6 +9,7 @@ CONFIG_VGA_CIRRUS=y
>> CONFIG_VMWARE_VGA=y
>> CONFIG_VMMOUSE=y
>> CONFIG_IPMI=y
>> +CONFIG_ISA_IPMI=y
>> CONFIG_SERIAL=y
>> CONFIG_PARALLEL=y
>> CONFIG_I8254=y
>> diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
>> index 65bde11..1518216 100644
>> --- a/hw/ipmi/Makefile.objs
>> +++ b/hw/ipmi/Makefile.objs
>> @@ -1 +1,2 @@
>> +common-obj-$(CONFIG_ISA_IPMI) += isa_ipmi.o
>> common-obj-$(CONFIG_IPMI) += ipmi.o
>> diff --git a/hw/ipmi/isa_ipmi.c b/hw/ipmi/isa_ipmi.c
>> new file mode 100644
>> index 0000000..1c1ab8d
>> --- /dev/null
>> +++ b/hw/ipmi/isa_ipmi.c
>> @@ -0,0 +1,144 @@
>> +/*
>> + * QEMU ISA IPMI emulation
>> + *
>> + * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>> + * of this software and associated documentation files (the "Software"), to deal
>> + * in the Software without restriction, including without limitation the rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +#include "hw/hw.h"
>> +#include "hw/isa/isa.h"
>> +#include "hw/i386/pc.h"
>> +#include "qemu/timer.h"
>> +#include "sysemu/char.h"
>> +#include "sysemu/sysemu.h"
>> +#include "ipmi.h"
>> +
>> +/* This is the type the user specifies on the -device command line */
>> +#define TYPE_ISA_IPMI "isa-ipmi"
>> +#define ISA_IPMI(obj) OBJECT_CHECK(ISAIPMIDevice, (obj), TYPE_ISA_IPMI)
>> +
>> +typedef struct ISAIPMIDevice {
>> + ISADevice dev;
>> + char *interface;
>> + uint32_t iobase;
>> + int32 isairq;
>> + uint8_t slave_addr;
>> + CharDriverState *chr;
>> + IPMIInterface *intf;
>> +} ISAIPMIDevice;
>> +
>> +static void ipmi_isa_realizefn(DeviceState *dev, Error **errp)
>> +{
>> + ISADevice *isadev = ISA_DEVICE(dev);
>> + ISAIPMIDevice *ipmi = ISA_IPMI(dev);
>> + char typename[20];
>> + Object *intfobj;
>> + IPMIInterface *intf;
>> + Object *bmcobj;
>> + IPMIBmc *bmc;
>> +
>> + if (!ipmi->interface) {
>> + ipmi->interface = g_strdup("kcs");
>> + }
>> +
>> + if (ipmi->chr) {
>> + bmcobj = object_new(TYPE_IPMI_BMC_EXTERN);
>> + } else {
>> + bmcobj = object_new(TYPE_IPMI_BMC_SIMULATOR);
>> + }
>> + bmc = IPMI_BMC(bmcobj);
>> + bmc->chr = ipmi->chr;
>> + snprintf(typename, sizeof(typename),
>> + TYPE_IPMI_INTERFACE_PREFIX "%s", ipmi->interface);
>> + intfobj = object_new(typename);
>
> I wonder what Andreas thinks about this.
> There are only 3 legal types, correct?
> I think it would be cleaner to avoid the prefix trick,
> and just do a plain
> if (!ipmi->interface)) {
> typename = TYPE_IPMI_INTERFACE_KCS
> } else if (!strcmp(ipmi->interface, "kcs")) {
> typename = TYPE_IPMI_INTERFACE_KCS
> } else if ....
>
>
> etc
Well, I'm fine either way. The way I had it seems clear enough to me,
but I wrote it :).
If Andreas or you want it changed, not a problem. Just say so.
>
>
>
>> + intf = IPMI_INTERFACE(intfobj);
>> + bmc->intf = intf;
>> + intf->bmc = bmc;
>> + intf->io_base = ipmi->iobase;
>> + intf->slave_addr = ipmi->slave_addr;
>> + ipmi_interface_init(intf, errp);
>> + if (*errp) {
>> + return;
>> + }
>> + ipmi_bmc_init(bmc, errp);
>> + if (*errp) {
>> + return;
>> + }
>> +
>> + /* These may be set by the interface. */
>> + ipmi->iobase = intf->io_base;
>> + ipmi->slave_addr = intf->slave_addr;
>> +
>> + if (ipmi->isairq > 0) {
>> + isa_init_irq(isadev, &intf->irq, ipmi->isairq);
>> + intf->use_irq = 1;
>> + }
>> +
>> + ipmi->intf = intf;
>> + object_property_add_child(OBJECT(isadev), "intf", OBJECT(intf), errp);
>> + if (*errp) {
>> + return;
>> + }
>> + object_property_add_child(OBJECT(isadev), "bmc", OBJECT(bmc), errp);
>> + if (*errp) {
>> + return;
>> + }
>> +
> Should the created object be destroyed before return?
Returning an error from the realize here appears to result in an error
being printed and qemu being terminated, as far as I can tell. So it
shouldn't matter here, right?
-corey
>> + qdev_set_legacy_instance_id(dev, intf->io_base, intf->io_length);
>> +
>> + isa_register_ioport(isadev, &intf->io, intf->io_base);
>> +}
>> +
>> +static void ipmi_isa_reset(DeviceState *qdev)
>> +{
>> + ISAIPMIDevice *isa = ISA_IPMI(qdev);
>> +
>> + ipmi_interface_reset(isa->intf);
>> +}
>> +
>> +static Property ipmi_isa_properties[] = {
>> + DEFINE_PROP_STRING("interface", ISAIPMIDevice, interface),
>> + DEFINE_PROP_UINT32("iobase", ISAIPMIDevice, iobase, 0),
>> + DEFINE_PROP_INT32("irq", ISAIPMIDevice, isairq, 5),
>> + DEFINE_PROP_UINT8("slave_addr", ISAIPMIDevice, slave_addr, 0),
>> + DEFINE_PROP_CHR("chardev", ISAIPMIDevice, chr),
>> + DEFINE_PROP_END_OF_LIST(),
>> +};
>> +
>> +static void ipmi_isa_class_initfn(ObjectClass *klass, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(klass);
>> + dc->realize = ipmi_isa_realizefn;
>> + dc->reset = ipmi_isa_reset;
>> + dc->props = ipmi_isa_properties;
>> +}
>> +
>> +static const TypeInfo ipmi_isa_info = {
>> + .name = TYPE_ISA_IPMI,
>> + .parent = TYPE_ISA_DEVICE,
>> + .instance_size = sizeof(ISAIPMIDevice),
>> + .class_init = ipmi_isa_class_initfn,
>> +};
>> +
>> +static void ipmi_register_types(void)
>> +{
>> + type_register_static(&ipmi_isa_info);
>> +}
>> +
>> +type_init(ipmi_register_types)
>> diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
>> index 6d8a8ac..cac3a34 100644
>> --- a/include/hw/nvram/fw_cfg.h
>> +++ b/include/hw/nvram/fw_cfg.h
>> @@ -38,7 +38,16 @@
>>
>> #define FW_CFG_FILE_FIRST 0x20
>> #define FW_CFG_FILE_SLOTS 0x10
>> -#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
>> +
>> +#define FW_CFG_IPMI_INTERFACE 0x30
>> +#define FW_CFG_IPMI_BASE_ADDR 0x31
>> +#define FW_CFG_IPMI_REG_SPACE 0x32
>> +#define FW_CFG_IPMI_REG_SPACING 0x33
>> +#define FW_CFG_IPMI_SLAVE_ADDR 0x34
>> +#define FW_CFG_IPMI_IRQ 0x35
>> +#define FW_CFG_IPMI_VERSION 0x36
>> +
>> +#define FW_CFG_MAX_ENTRY (FW_CFG_IPMI_VERSION + 1)
>>
>> #define FW_CFG_WRITE_CHANNEL 0x4000
>> #define FW_CFG_ARCH_LOCAL 0x8000
>> --
>> 1.8.3.1
>>
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-05-08 21:16 ` Corey Minyard
@ 2015-05-11 14:21 ` Paolo Bonzini
2015-05-11 17:26 ` Andreas Färber
1 sibling, 0 replies; 38+ messages in thread
From: Paolo Bonzini @ 2015-05-11 14:21 UTC (permalink / raw)
To: minyard, Michael S. Tsirkin; +Cc: Corey Minyard, andreas.faerber, qemu-devel
On 08/05/2015 23:16, Corey Minyard wrote:
>>> >> + ipmi->intf = intf;
>>> >> + object_property_add_child(OBJECT(isadev), "intf", OBJECT(intf), errp);
>>> >> + if (*errp) {
>>> >> + return;
>>> >> + }
>>> >> + object_property_add_child(OBJECT(isadev), "bmc", OBJECT(bmc), errp);
>>> >> + if (*errp) {
>>> >> + return;
>>> >> + }
>>> >> +
>> > Should the created object be destroyed before return?
> Returning an error from the realize here appears to result in an error
> being printed and qemu being terminated, as far as I can tell. So it
> shouldn't matter here, right?
I would just use &error_abort and ignore error handling.
Paolo
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-05-08 21:16 ` Corey Minyard
2015-05-11 14:21 ` Paolo Bonzini
@ 2015-05-11 17:26 ` Andreas Färber
2015-05-11 19:42 ` Paolo Bonzini
1 sibling, 1 reply; 38+ messages in thread
From: Andreas Färber @ 2015-05-11 17:26 UTC (permalink / raw)
To: minyard, Michael S. Tsirkin; +Cc: Corey Minyard, qemu-devel
Am 08.05.2015 um 23:16 schrieb Corey Minyard:
> On 04/26/2015 03:58 AM, Michael S. Tsirkin wrote:
>> On Thu, Apr 23, 2015 at 05:57:43PM -0500, minyard@acm.org wrote:
>>> From: Corey Minyard <cminyard@mvista.com>
>>>
>>> This provides the base infrastructure to tie IPMI low-level
>>> interfaces into a PC ISA bus.
>>>
>>> Signed-off-by: Corey Minyard <cminyard@mvista.com>
>>> ---
>>> default-configs/i386-softmmu.mak | 1 +
>>> default-configs/x86_64-softmmu.mak | 1 +
>>> hw/ipmi/Makefile.objs | 1 +
>>> hw/ipmi/isa_ipmi.c | 144 +++++++++++++++++++++++++++++++++++++
>>> include/hw/nvram/fw_cfg.h | 11 ++-
>>> 5 files changed, 157 insertions(+), 1 deletion(-)
>>> create mode 100644 hw/ipmi/isa_ipmi.c
>>>
>>> diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
>>> index ab1a552..1c3153b 100644
>>> --- a/default-configs/i386-softmmu.mak
>>> +++ b/default-configs/i386-softmmu.mak
>>> @@ -9,6 +9,7 @@ CONFIG_VGA_CIRRUS=y
>>> CONFIG_VMWARE_VGA=y
>>> CONFIG_VMMOUSE=y
>>> CONFIG_IPMI=y
>>> +CONFIG_ISA_IPMI=y
>>> CONFIG_SERIAL=y
>>> CONFIG_PARALLEL=y
>>> CONFIG_I8254=y
>>> diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
>>> index 82bafcc..6b57430 100644
>>> --- a/default-configs/x86_64-softmmu.mak
>>> +++ b/default-configs/x86_64-softmmu.mak
>>> @@ -9,6 +9,7 @@ CONFIG_VGA_CIRRUS=y
>>> CONFIG_VMWARE_VGA=y
>>> CONFIG_VMMOUSE=y
>>> CONFIG_IPMI=y
>>> +CONFIG_ISA_IPMI=y
>>> CONFIG_SERIAL=y
>>> CONFIG_PARALLEL=y
>>> CONFIG_I8254=y
>>> diff --git a/hw/ipmi/Makefile.objs b/hw/ipmi/Makefile.objs
>>> index 65bde11..1518216 100644
>>> --- a/hw/ipmi/Makefile.objs
>>> +++ b/hw/ipmi/Makefile.objs
>>> @@ -1 +1,2 @@
>>> +common-obj-$(CONFIG_ISA_IPMI) += isa_ipmi.o
>>> common-obj-$(CONFIG_IPMI) += ipmi.o
>>> diff --git a/hw/ipmi/isa_ipmi.c b/hw/ipmi/isa_ipmi.c
>>> new file mode 100644
>>> index 0000000..1c1ab8d
>>> --- /dev/null
>>> +++ b/hw/ipmi/isa_ipmi.c
>>> @@ -0,0 +1,144 @@
>>> +/*
>>> + * QEMU ISA IPMI emulation
>>> + *
>>> + * Copyright (c) 2012 Corey Minyard, MontaVista Software, LLC
>>> + *
>>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>>> + * of this software and associated documentation files (the "Software"), to deal
>>> + * in the Software without restriction, including without limitation the rights
>>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>>> + * copies of the Software, and to permit persons to whom the Software is
>>> + * furnished to do so, subject to the following conditions:
>>> + *
>>> + * The above copyright notice and this permission notice shall be included in
>>> + * all copies or substantial portions of the Software.
>>> + *
>>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>>> + * THE SOFTWARE.
>>> + */
>>> +#include "hw/hw.h"
>>> +#include "hw/isa/isa.h"
>>> +#include "hw/i386/pc.h"
>>> +#include "qemu/timer.h"
>>> +#include "sysemu/char.h"
>>> +#include "sysemu/sysemu.h"
>>> +#include "ipmi.h"
>>> +
>>> +/* This is the type the user specifies on the -device command line */
>>> +#define TYPE_ISA_IPMI "isa-ipmi"
>>> +#define ISA_IPMI(obj) OBJECT_CHECK(ISAIPMIDevice, (obj), TYPE_ISA_IPMI)
>>> +
>>> +typedef struct ISAIPMIDevice {
>>> + ISADevice dev;
>>> + char *interface;
>>> + uint32_t iobase;
>>> + int32 isairq;
>>> + uint8_t slave_addr;
>>> + CharDriverState *chr;
>>> + IPMIInterface *intf;
>>> +} ISAIPMIDevice;
>>> +
>>> +static void ipmi_isa_realizefn(DeviceState *dev, Error **errp)
>>> +{
>>> + ISADevice *isadev = ISA_DEVICE(dev);
>>> + ISAIPMIDevice *ipmi = ISA_IPMI(dev);
>>> + char typename[20];
>>> + Object *intfobj;
>>> + IPMIInterface *intf;
>>> + Object *bmcobj;
>>> + IPMIBmc *bmc;
>>> +
>>> + if (!ipmi->interface) {
>>> + ipmi->interface = g_strdup("kcs");
>>> + }
>>> +
>>> + if (ipmi->chr) {
>>> + bmcobj = object_new(TYPE_IPMI_BMC_EXTERN);
>>> + } else {
>>> + bmcobj = object_new(TYPE_IPMI_BMC_SIMULATOR);
>>> + }
>>> + bmc = IPMI_BMC(bmcobj);
>>> + bmc->chr = ipmi->chr;
>>> + snprintf(typename, sizeof(typename),
>>> + TYPE_IPMI_INTERFACE_PREFIX "%s", ipmi->interface);
>>> + intfobj = object_new(typename);
>>
>> I wonder what Andreas thinks about this.
>> There are only 3 legal types, correct?
>> I think it would be cleaner to avoid the prefix trick,
>> and just do a plain
>> if (!ipmi->interface)) {
>> typename = TYPE_IPMI_INTERFACE_KCS
>> } else if (!strcmp(ipmi->interface, "kcs")) {
>> typename = TYPE_IPMI_INTERFACE_KCS
>> } else if ....
>>
>>
>> etc
>
> Well, I'm fine either way. The way I had it seems clear enough to me,
> but I wrote it :).
>
> If Andreas or you want it changed, not a problem. Just say so.
I do prefer mst's suggestion. You are right that your code is clear, but
it's duplicated and thus makes refactorings harder. For clarity I would
even propose to skip bmcobj in favor of bmc. Same for the other objects.
OBJECT() is cheap, unlike other casts.
Another problem is that you're using object_new() in realize at all,
which means that it's too late for any management interface to tweak
properties on the new device. One possible solution would be to create
the object in a property setter, before realizing the object. Did you
look at how some of the other backends are implemented, such as rng?
>>> + intf = IPMI_INTERFACE(intfobj);
>>> + bmc->intf = intf;
>>> + intf->bmc = bmc;
>>> + intf->io_base = ipmi->iobase;
>>> + intf->slave_addr = ipmi->slave_addr;
>>> + ipmi_interface_init(intf, errp);
>>> + if (*errp) {
>>> + return;
>>> + }
>>> + ipmi_bmc_init(bmc, errp);
>>> + if (*errp) {
>>> + return;
>>> + }
>>> +
>>> + /* These may be set by the interface. */
>>> + ipmi->iobase = intf->io_base;
>>> + ipmi->slave_addr = intf->slave_addr;
>>> +
>>> + if (ipmi->isairq > 0) {
>>> + isa_init_irq(isadev, &intf->irq, ipmi->isairq);
>>> + intf->use_irq = 1;
>>> + }
>>> +
>>> + ipmi->intf = intf;
>>> + object_property_add_child(OBJECT(isadev), "intf", OBJECT(intf), errp);
>>> + if (*errp) {
>>> + return;
>>> + }
>>> + object_property_add_child(OBJECT(isadev), "bmc", OBJECT(bmc), errp);
>>> + if (*errp) {
>>> + return;
>>> + }
>>> +
>> Should the created object be destroyed before return?
>
> Returning an error from the realize here appears to result in an error
> being printed and qemu being terminated, as far as I can tell. So it
> shouldn't matter here, right?
Negative, this is a property setter that has nothing to do with what its
callers do. For one, you cannot rely on errp != NULL, so you need to use
a local Error *err = NULL; and call error_propagate() when necessary.
Also keep in mind that this realized property is publicly accessible.
When set to false and re-set to true those will definitely fail as I see
no unrealize implementation ever deleting these properties. In that
case, with your guest running, terminating QEMU is not desired.
>>> + qdev_set_legacy_instance_id(dev, intf->io_base, intf->io_length);
>>> +
>>> + isa_register_ioport(isadev, &intf->io, intf->io_base);
>>> +}
>>> +
>>> +static void ipmi_isa_reset(DeviceState *qdev)
>>> +{
>>> + ISAIPMIDevice *isa = ISA_IPMI(qdev);
>>> +
>>> + ipmi_interface_reset(isa->intf);
>>> +}
>>> +
>>> +static Property ipmi_isa_properties[] = {
>>> + DEFINE_PROP_STRING("interface", ISAIPMIDevice, interface),
>>> + DEFINE_PROP_UINT32("iobase", ISAIPMIDevice, iobase, 0),
>>> + DEFINE_PROP_INT32("irq", ISAIPMIDevice, isairq, 5),
>>> + DEFINE_PROP_UINT8("slave_addr", ISAIPMIDevice, slave_addr, 0),
>>> + DEFINE_PROP_CHR("chardev", ISAIPMIDevice, chr),
>>> + DEFINE_PROP_END_OF_LIST(),
>>> +};
>>> +
>>> +static void ipmi_isa_class_initfn(ObjectClass *klass, void *data)
s/klass/oc/ preferred.
>>> +{
>>> + DeviceClass *dc = DEVICE_CLASS(klass);
>>> + dc->realize = ipmi_isa_realizefn;
>>> + dc->reset = ipmi_isa_reset;
>>> + dc->props = ipmi_isa_properties;
>>> +}
>>> +
>>> +static const TypeInfo ipmi_isa_info = {
>>> + .name = TYPE_ISA_IPMI,
>>> + .parent = TYPE_ISA_DEVICE,
>>> + .instance_size = sizeof(ISAIPMIDevice),
>>> + .class_init = ipmi_isa_class_initfn,
>>> +};
>>> +
>>> +static void ipmi_register_types(void)
>>> +{
>>> + type_register_static(&ipmi_isa_info);
>>> +}
>>> +
>>> +type_init(ipmi_register_types)
>>> diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
>>> index 6d8a8ac..cac3a34 100644
>>> --- a/include/hw/nvram/fw_cfg.h
>>> +++ b/include/hw/nvram/fw_cfg.h
>>> @@ -38,7 +38,16 @@
>>>
>>> #define FW_CFG_FILE_FIRST 0x20
>>> #define FW_CFG_FILE_SLOTS 0x10
>>> -#define FW_CFG_MAX_ENTRY (FW_CFG_FILE_FIRST+FW_CFG_FILE_SLOTS)
>>> +
>>> +#define FW_CFG_IPMI_INTERFACE 0x30
>>> +#define FW_CFG_IPMI_BASE_ADDR 0x31
>>> +#define FW_CFG_IPMI_REG_SPACE 0x32
>>> +#define FW_CFG_IPMI_REG_SPACING 0x33
>>> +#define FW_CFG_IPMI_SLAVE_ADDR 0x34
>>> +#define FW_CFG_IPMI_IRQ 0x35
>>> +#define FW_CFG_IPMI_VERSION 0x36
Do we really need all those fw_cfg entries for an optional device?
>>> +
>>> +#define FW_CFG_MAX_ENTRY (FW_CFG_IPMI_VERSION + 1)
>>>
>>> #define FW_CFG_WRITE_CHANNEL 0x4000
>>> #define FW_CFG_ARCH_LOCAL 0x8000
>>> --
>>> 1.8.3.1
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Dilip Upmanyu, Graham Norton; HRB
21284 (AG Nürnberg)
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-05-11 17:26 ` Andreas Färber
@ 2015-05-11 19:42 ` Paolo Bonzini
2015-05-11 19:58 ` Corey Minyard
0 siblings, 1 reply; 38+ messages in thread
From: Paolo Bonzini @ 2015-05-11 19:42 UTC (permalink / raw)
To: Andreas Färber, minyard, Michael S. Tsirkin
Cc: Corey Minyard, qemu-devel
On 11/05/2015 19:26, Andreas Färber wrote:
> Another problem is that you're using object_new() in realize at all,
> which means that it's too late for any management interface to tweak
> properties on the new device. One possible solution would be to create
> the object in a property setter, before realizing the object. Did you
> look at how some of the other backends are implemented, such as rng?
Note that this is not exactly a backend. It's a different guest-visible
I/O interface. But there are no properties on the interface, so it's
okay to create it at realize time.
Paolo
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-05-11 19:42 ` Paolo Bonzini
@ 2015-05-11 19:58 ` Corey Minyard
2015-05-13 14:52 ` Paolo Bonzini
0 siblings, 1 reply; 38+ messages in thread
From: Corey Minyard @ 2015-05-11 19:58 UTC (permalink / raw)
To: Paolo Bonzini, Andreas Färber, Michael S. Tsirkin
Cc: Corey Minyard, qemu-devel
On 05/11/2015 02:42 PM, Paolo Bonzini wrote:
>
> On 11/05/2015 19:26, Andreas Färber wrote:
>> Another problem is that you're using object_new() in realize at all,
>> which means that it's too late for any management interface to tweak
>> properties on the new device. One possible solution would be to create
>> the object in a property setter, before realizing the object. Did you
>> look at how some of the other backends are implemented, such as rng?
> Note that this is not exactly a backend. It's a different guest-visible
> I/O interface. But there are no properties on the interface, so it's
> okay to create it at realize time.
>
> Paolo
I've debated this in my mind since I've been learning more about qemu.
Some of
the bmc properties are being passed in to the interface and passed on to
the bmc.
Plus some IPMI systems have multiple interfaces that point to the same
bmc. It
might be best to have the user create a bmc device then tie an interface
device to it.
If I do this, what is the acceptable way to look up another object this
way? I hunted
a bit and didn't come up with anything clean.
Thanks,
-corey
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-05-11 19:58 ` Corey Minyard
@ 2015-05-13 14:52 ` Paolo Bonzini
2015-05-16 1:48 ` Corey Minyard
0 siblings, 1 reply; 38+ messages in thread
From: Paolo Bonzini @ 2015-05-13 14:52 UTC (permalink / raw)
To: minyard, Andreas Färber, Michael S. Tsirkin
Cc: Corey Minyard, qemu-devel
On 11/05/2015 21:58, Corey Minyard wrote:
> I've debated this in my mind since I've been learning more about
> qemu. Some of the bmc properties are being passed in to the interface
> and passed on to the bmc. Plus some IPMI systems have multiple
> interfaces that point to the same bmc. It might be best to have the
> user create a bmc device then tie an interface device to it.
>
> If I do this, what is the acceptable way to look up another object
> this way? I hunted a bit and didn't come up with anything clean.
Yes, you're right indeed!!! I think you want something like
-object ipmi-bmc-extern,id=bmc0,chardev=foo
-device isa-ipmi-kcs,bmc=bmc0
vs.
-object ipmi-bmc,id=bmc0
-device isa-ipmi-bt,bmc=bmc0
ipmi-bmc would be a subclass of Object like the one that you have, but
it needs to implement the UserCreatable interface; see backends/rng.c
for an example.
Then ipmi-isa-kcs would be your usual ISA device, so a subclass of
TYPE_ISA_DEVICE; however it would implement IPMIInterface, which would
be an interface rather than an abstract class. For an example of
interface boilerplate, see hw/core/hotplug.c. For an example of how to
implement the "bmc" property, see hw/mem/pc-dimm.c.
Paolo
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-05-13 14:52 ` Paolo Bonzini
@ 2015-05-16 1:48 ` Corey Minyard
2015-05-16 13:47 ` Paolo Bonzini
0 siblings, 1 reply; 38+ messages in thread
From: Corey Minyard @ 2015-05-16 1:48 UTC (permalink / raw)
To: Paolo Bonzini, Andreas Färber, Michael S. Tsirkin
Cc: Corey Minyard, qemu-devel
On 05/13/2015 09:52 AM, Paolo Bonzini wrote:
>
> On 11/05/2015 21:58, Corey Minyard wrote:
>> I've debated this in my mind since I've been learning more about
>> qemu. Some of the bmc properties are being passed in to the interface
>> and passed on to the bmc. Plus some IPMI systems have multiple
>> interfaces that point to the same bmc. It might be best to have the
>> user create a bmc device then tie an interface device to it.
>>
>> If I do this, what is the acceptable way to look up another object
>> this way? I hunted a bit and didn't come up with anything clean.
> Yes, you're right indeed!!! I think you want something like
>
> -object ipmi-bmc-extern,id=bmc0,chardev=foo
> -device isa-ipmi-kcs,bmc=bmc0
>
> vs.
>
> -object ipmi-bmc,id=bmc0
> -device isa-ipmi-bt,bmc=bmc0
>
> ipmi-bmc would be a subclass of Object like the one that you have, but
> it needs to implement the UserCreatable interface; see backends/rng.c
> for an example.
>
> Then ipmi-isa-kcs would be your usual ISA device, so a subclass of
> TYPE_ISA_DEVICE; however it would implement IPMIInterface, which would
> be an interface rather than an abstract class. For an example of
> interface boilerplate, see hw/core/hotplug.c. For an example of how to
> implement the "bmc" property, see hw/mem/pc-dimm.c.
>
> Paolo
I've been trying to piece this together, and the problem is that BT and
KCS can sit on different kinds of busses, not just ISA. There are PCI
and memory based implementations. I'd prefer to have one implementation
for all, so I'm trying to figure out a way to piece all these things
together.
What I've come up with is the following class structure:
IPMIBmc (abstract subclass of Device)
Implements the base BMC handling
IPMIBmcInternal (subclass of IPMIBmc)
An internal BMC
IPMIBmcExternal (subclass of IPMIBmc)
A connection to an external BMC
BusDevice (subclass of Interface)
An interface where a device can connect to a bus and do I/O and
interrupts.
BusDeviceISA (subclass of ISADevice, implements BusDevice)
An ISA interface for BusDevice
IPMIInterface (subclass of Interface)
An Interface that connects between a BMC and a physical IPMI interface
(BT, KCS, SMBus)
IPMIDevice (abstract subclass of Device, implements IPMIInterface)
The base class for the various IPMI devices. This code finds the IPMIBmc
and the BusDevice objects and plugs them in to the subclasses of this
class.
IPMIDevKCS (subclass of IPMIDevice)
KCS interface
IPMIDevBT (subclass of IPMIDevice)
BT interface
So on the command line, you would say:
-device isadev,irq=5,id=ipmiisadev,addr=0xca2 -device
ipmi-bmc-internal,id=bmc1
-device ipmi-kcs,bmc=bmc1,busdev=ipmiisadev
This seems rather complicated, but it seem like the only way to break
this up. And
I don't know if object_property_add_link() works on interfaces, but that
should be easy
to fix if it doesn't.
Does this sound plausible?
Thanks,
-corey
^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure
2015-05-16 1:48 ` Corey Minyard
@ 2015-05-16 13:47 ` Paolo Bonzini
0 siblings, 0 replies; 38+ messages in thread
From: Paolo Bonzini @ 2015-05-16 13:47 UTC (permalink / raw)
To: minyard, Andreas Färber, Michael S. Tsirkin
Cc: Corey Minyard, qemu-devel
On 16/05/2015 03:48, Corey Minyard wrote:
> On 05/13/2015 09:52 AM, Paolo Bonzini wrote:
>>
>> On 11/05/2015 21:58, Corey Minyard wrote:
>>> I've debated this in my mind since I've been learning more about
>>> qemu. Some of the bmc properties are being passed in to the interface
>>> and passed on to the bmc. Plus some IPMI systems have multiple
>>> interfaces that point to the same bmc. It might be best to have the
>>> user create a bmc device then tie an interface device to it.
>>>
>>> If I do this, what is the acceptable way to look up another object
>>> this way? I hunted a bit and didn't come up with anything clean.
>> Yes, you're right indeed!!! I think you want something like
>>
>> -object ipmi-bmc-extern,id=bmc0,chardev=foo
>> -device isa-ipmi-kcs,bmc=bmc0
>>
>> vs.
>>
>> -object ipmi-bmc,id=bmc0
>> -device isa-ipmi-bt,bmc=bmc0
>>
>> ipmi-bmc would be a subclass of Object like the one that you have, but
>> it needs to implement the UserCreatable interface; see backends/rng.c
>> for an example.
>>
>> Then ipmi-isa-kcs would be your usual ISA device, so a subclass of
>> TYPE_ISA_DEVICE; however it would implement IPMIInterface, which would
>> be an interface rather than an abstract class. For an example of
>> interface boilerplate, see hw/core/hotplug.c. For an example of how to
>> implement the "bmc" property, see hw/mem/pc-dimm.c.
>>
>> Paolo
> I've been trying to piece this together, and the problem is that BT and
> KCS can sit on different kinds of busses, not just ISA. There are PCI
> and memory based implementations. I'd prefer to have one implementation
> for all, so I'm trying to figure out a way to piece all these things
> together.
>
> What I've come up with is the following class structure:
>
> IPMIBmc (abstract subclass of Device)
> Implements the base BMC handling
This is actually a subclass of Object that implements UserCreatable.
But that's a detail.
> IPMIBmcInternal (subclass of IPMIBmc)
> An internal BMC
>
> IPMIBmcExternal (subclass of IPMIBmc)
> A connection to an external BMC
These are good.
> BusDevice (subclass of Interface)
> An interface where a device can connect to a bus and do I/O and
> interrupts.
>
> BusDeviceISA (subclass of ISADevice, implements BusDevice)
> An ISA interface for BusDevice
See below...
> IPMIInterface (subclass of Interface)
> An Interface that connects between a BMC and a physical IPMI interface
> (BT, KCS, SMBus)
This is okay.
> IPMIDevice (abstract subclass of Device, implements IPMIInterface)
> The base class for the various IPMI devices. This code finds the IPMIBmc
> and the BusDevice objects and plugs them in to the subclasses of this
> class.
>
> IPMIDevKCS (subclass of IPMIDevice)
> KCS interface
>
> IPMIDevBT (subclass of IPMIDevice)
> BT interface
For now I would just make IPMIDevKCS and IPMIDevBT two ISADevice
subclasses. Any code reuse between them can be placed in the
implementation of IPMIInterface: interface methods need not be abstract,
they can have a default implementation.
Regarding BusDevice, if a PCI interface is added in the future we can
use C composition (structs :)) to group the common KCS and BT code.
There's no need for an explicit class hierarchy; for an example see the
AHCI and EHCI devices.
The SMBus interface can be added already (through a subclass of I2CSlave
that implements IPMIInterface.
> So on the command line, you would say:
>
> -device isadev,irq=5,id=ipmiisadev,addr=0xca2 -device
> ipmi-bmc-internal,id=bmc1
> -device ipmi-kcs,bmc=bmc1,busdev=ipmiisadev
In my proposal this would be
-object ipmi-bmc-internal,id=bmc1
-device isa-ipmi-kcs,bmc=bmc1,irq=5,iobase=0xca2
(the irq and iobase can be given suitable defaults of course; iobase is
a more standard name for ISA I/O ports).
> This seems rather complicated, but it seem like the only way to break
> this up.
If you want a pure QOM solution it is. But we can use plain struct
composition too, in order to keep the implementation simple. The same
is done in the kernel, which uses structs or kobjects depending on the
use case.
> And I don't know if object_property_add_link() works on interfaces
Yes, it does.
> Does this sound plausible?
It did---does what I wrote also sound plausible? :)
Paolo
^ permalink raw reply [flat|nested] 38+ messages in thread
end of thread, other threads:[~2015-05-16 13:47 UTC | newest]
Thread overview: 38+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-04-23 22:57 [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 01/17] Add a base IPMI interface minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 02/17] ipmi: Add a PC ISA type structure minyard
2015-04-26 8:58 ` Michael S. Tsirkin
2015-04-26 9:07 ` Michael S. Tsirkin
2015-05-08 21:16 ` Corey Minyard
2015-05-11 14:21 ` Paolo Bonzini
2015-05-11 17:26 ` Andreas Färber
2015-05-11 19:42 ` Paolo Bonzini
2015-05-11 19:58 ` Corey Minyard
2015-05-13 14:52 ` Paolo Bonzini
2015-05-16 1:48 ` Corey Minyard
2015-05-16 13:47 ` Paolo Bonzini
2015-04-26 9:05 ` Michael S. Tsirkin
2015-04-26 17:03 ` Paolo Bonzini
2015-05-08 20:59 ` Corey Minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 03/17] ipmi: Add a KCS low-level interface minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 04/17] ipmi: Add a BT " minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 05/17] ipmi: Add a local BMC simulation minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 06/17] ipmi: Add an external connection simulation interface minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 07/17] ipmi: Add tests minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 08/17] ipmi: Add documentation minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 09/17] ipmi: Add migration capability to the IPMI device minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 10/17] ipmi: Add a firmware configuration repository minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 12/17] smbios: Add a function to directly add an entry minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 13/17] pc: Postpone SMBIOS table installation to post machine init minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 14/17] ipmi: Add SMBIOS table entry minyard
2015-04-26 8:36 ` Michael S. Tsirkin
2015-04-23 22:57 ` [Qemu-devel] [PATCH 15/17] acpi: Add a way for devices to add ACPI tables minyard
2015-04-23 22:57 ` [Qemu-devel] [PATCH 16/17] ipmi: Add ACPI table entries minyard
2015-04-26 8:36 ` Michael S. Tsirkin
2015-04-23 22:57 ` [Qemu-devel] [PATCH 17/17] bios: Add tests for the IPMI ACPI and SMBIOS entries minyard
2015-04-23 23:11 ` [Qemu-devel] [PATCH 00/17] Update to adding an IPMI device to qemu Eric Blake
2015-04-26 11:39 ` Andreas Färber
2015-04-26 16:52 ` Paolo Bonzini
2015-04-27 13:19 ` Corey Minyard
2015-04-24 9:38 ` Paolo Bonzini
2015-04-24 13:07 ` Corey Minyard
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