[PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[Leonid Yegoshin]

SEGBITS default is 40 bits or less, depending from CPU type.
This patch introduces 48bits of application virtual address (SEGBITS) support.
It is defined only for 16K and 64K pages and is optional (configurable).

Penalty - a small number of additional pages for generic (small) applications.
But for 64K pages it adds 3rd level of PTE structure, which has a little
impact during software TLB refill.

This patch is needed because MIPS I6XXX and P6XXX cores have 48 bit of
virtual address in each segment (SEGBITS).

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
---
V2: Added correction for defintion of TASK_SIZE64
---
 arch/mips/Kconfig                  |   11 +++++++++++
 arch/mips/include/asm/pgtable-64.h |   18 +++++++++++-------
 arch/mips/include/asm/processor.h  |    6 +++++-
 3 files changed, 27 insertions(+), 8 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 76efb02ae99f..3acff2f065e9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2032,6 +2032,17 @@ config PAGE_SIZE_64KB
 
 endchoice
 
+config 48VMBITS
+	bool "48 bits virtual memory"
+	depends on PAGE_SIZE_16KB || PAGE_SIZE_64KB
+	depends on 64BIT
+	help
+	  Define a maximum at least 48 bits of application virtual memory.
+	  Default is 40 bits or less, depending from CPU.
+	  In generic (small) application it is a small set of pages increase
+	  in page tables.
+	  If unsure, say N.
+
 config FORCE_MAX_ZONEORDER
 	int "Maximum zone order"
 	range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index cf661a2fb141..c6b5473440e6 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -17,7 +17,7 @@
 #include <asm/cachectl.h>
 #include <asm/fixmap.h>
 
-#ifdef CONFIG_PAGE_SIZE_64KB
+#if defined(CONFIG_PAGE_SIZE_64KB) && !defined(CONFIG_48VMBITS)
 #include <asm-generic/pgtable-nopmd.h>
 #else
 #include <asm-generic/pgtable-nopud.h>
@@ -90,7 +90,11 @@
 #define PTE_ORDER		0
 #endif
 #ifdef CONFIG_PAGE_SIZE_16KB
-#define PGD_ORDER		0
+#ifdef CONFIG_48VMBITS
+#define PGD_ORDER               1
+#else
+#define PGD_ORDER               0
+#endif
 #define PUD_ORDER		aieeee_attempt_to_allocate_pud
 #define PMD_ORDER		0
 #define PTE_ORDER		0
@@ -104,7 +108,11 @@
 #ifdef CONFIG_PAGE_SIZE_64KB
 #define PGD_ORDER		0
 #define PUD_ORDER		aieeee_attempt_to_allocate_pud
+#ifdef CONFIG_48VMBITS
+#define PMD_ORDER		0
+#else
 #define PMD_ORDER		aieeee_attempt_to_allocate_pmd
+#endif
 #define PTE_ORDER		0
 #endif
 
@@ -114,11 +122,7 @@
 #endif
 #define PTRS_PER_PTE	((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
 
-#if PGDIR_SIZE >= TASK_SIZE64
-#define USER_PTRS_PER_PGD	(1)
-#else
-#define USER_PTRS_PER_PGD	(TASK_SIZE64 / PGDIR_SIZE)
-#endif
+#define USER_PTRS_PER_PGD       ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1)
 #define FIRST_USER_ADDRESS	0UL
 
 /*
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 9b3b48e21c22..bd2030f32ea4 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -69,7 +69,11 @@ extern unsigned int vced_count, vcei_count;
  * 8192EB ...
  */
 #define TASK_SIZE32	0x7fff8000UL
-#define TASK_SIZE64	0x10000000000UL
+#ifdef CONFIG_48VMBITS
+#define TASK_SIZE64     (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
+#else
+#define TASK_SIZE64     (0x10000000000UL)
+#endif
 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
 #define STACK_TOP_MAX	TASK_SIZE64
 

[PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[Leonid Yegoshin]

SEGBITS default is 40 bits or less, depending from CPU type.
This patch introduces 48bits of application virtual address (SEGBITS) support.
It is defined only for 16K and 64K pages and is optional (configurable).

Penalty - a small number of additional pages for generic (small) applications.
But for 64K pages it adds 3rd level of PTE structure, which has a little
impact during software TLB refill.

This patch is needed because MIPS I6XXX and P6XXX cores have 48 bit of
virtual address in each segment (SEGBITS).

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
---
V2: Added correction for defintion of TASK_SIZE64
---
 arch/mips/Kconfig                  |   11 +++++++++++
 arch/mips/include/asm/pgtable-64.h |   18 +++++++++++-------
 arch/mips/include/asm/processor.h  |    6 +++++-
 3 files changed, 27 insertions(+), 8 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 76efb02ae99f..3acff2f065e9 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2032,6 +2032,17 @@ config PAGE_SIZE_64KB
 
 endchoice
 
+config 48VMBITS
+	bool "48 bits virtual memory"
+	depends on PAGE_SIZE_16KB || PAGE_SIZE_64KB
+	depends on 64BIT
+	help
+	  Define a maximum at least 48 bits of application virtual memory.
+	  Default is 40 bits or less, depending from CPU.
+	  In generic (small) application it is a small set of pages increase
+	  in page tables.
+	  If unsure, say N.
+
 config FORCE_MAX_ZONEORDER
 	int "Maximum zone order"
 	range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
index cf661a2fb141..c6b5473440e6 100644
--- a/arch/mips/include/asm/pgtable-64.h
+++ b/arch/mips/include/asm/pgtable-64.h
@@ -17,7 +17,7 @@
 #include <asm/cachectl.h>
 #include <asm/fixmap.h>
 
-#ifdef CONFIG_PAGE_SIZE_64KB
+#if defined(CONFIG_PAGE_SIZE_64KB) && !defined(CONFIG_48VMBITS)
 #include <asm-generic/pgtable-nopmd.h>
 #else
 #include <asm-generic/pgtable-nopud.h>
@@ -90,7 +90,11 @@
 #define PTE_ORDER		0
 #endif
 #ifdef CONFIG_PAGE_SIZE_16KB
-#define PGD_ORDER		0
+#ifdef CONFIG_48VMBITS
+#define PGD_ORDER               1
+#else
+#define PGD_ORDER               0
+#endif
 #define PUD_ORDER		aieeee_attempt_to_allocate_pud
 #define PMD_ORDER		0
 #define PTE_ORDER		0
@@ -104,7 +108,11 @@
 #ifdef CONFIG_PAGE_SIZE_64KB
 #define PGD_ORDER		0
 #define PUD_ORDER		aieeee_attempt_to_allocate_pud
+#ifdef CONFIG_48VMBITS
+#define PMD_ORDER		0
+#else
 #define PMD_ORDER		aieeee_attempt_to_allocate_pmd
+#endif
 #define PTE_ORDER		0
 #endif
 
@@ -114,11 +122,7 @@
 #endif
 #define PTRS_PER_PTE	((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
 
-#if PGDIR_SIZE >= TASK_SIZE64
-#define USER_PTRS_PER_PGD	(1)
-#else
-#define USER_PTRS_PER_PGD	(TASK_SIZE64 / PGDIR_SIZE)
-#endif
+#define USER_PTRS_PER_PGD       ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1)
 #define FIRST_USER_ADDRESS	0UL
 
 /*
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 9b3b48e21c22..bd2030f32ea4 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -69,7 +69,11 @@ extern unsigned int vced_count, vcei_count;
  * 8192EB ...
  */
 #define TASK_SIZE32	0x7fff8000UL
-#define TASK_SIZE64	0x10000000000UL
+#ifdef CONFIG_48VMBITS
+#define TASK_SIZE64     (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
+#else
+#define TASK_SIZE64     (0x10000000000UL)
+#endif
 #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
 #define STACK_TOP_MAX	TASK_SIZE64
 

Re: [PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[Sergei Shtylyov]

Hello.

On 5/15/2015 4:34 AM, Leonid Yegoshin wrote:

> SEGBITS default is 40 bits or less, depending from CPU type.
> This patch introduces 48bits of application virtual address (SEGBITS) support.
> It is defined only for 16K and 64K pages and is optional (configurable).

> Penalty - a small number of additional pages for generic (small) applications.
> But for 64K pages it adds 3rd level of PTE structure, which has a little
> impact during software TLB refill.

> This patch is needed because MIPS I6XXX and P6XXX cores have 48 bit of
> virtual address in each segment (SEGBITS).

> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> ---
> V2: Added correction for defintion of TASK_SIZE64
> ---
>   arch/mips/Kconfig                  |   11 +++++++++++
>   arch/mips/include/asm/pgtable-64.h |   18 +++++++++++-------
>   arch/mips/include/asm/processor.h  |    6 +++++-
>   3 files changed, 27 insertions(+), 8 deletions(-)

> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 76efb02ae99f..3acff2f065e9 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -2032,6 +2032,17 @@ config PAGE_SIZE_64KB
>
>   endchoice
>
> +config 48VMBITS
> +	bool "48 bits virtual memory"
> +	depends on PAGE_SIZE_16KB || PAGE_SIZE_64KB
> +	depends on 64BIT
> +	help
> +	  Define a maximum at least 48 bits of application virtual memory.
> +	  Default is 40 bits or less, depending from CPU.

    s/from/on/.

> +	  In generic (small) application it is a small set of pages increase
> +	  in page tables.

    Can't parse that...

[...]
> diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
> index cf661a2fb141..c6b5473440e6 100644
> --- a/arch/mips/include/asm/pgtable-64.h
> +++ b/arch/mips/include/asm/pgtable-64.h
[...]
> @@ -114,11 +122,7 @@
>   #endif
>   #define PTRS_PER_PTE	((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
>
> -#if PGDIR_SIZE >= TASK_SIZE64
> -#define USER_PTRS_PER_PGD	(1)
> -#else
> -#define USER_PTRS_PER_PGD	(TASK_SIZE64 / PGDIR_SIZE)
> -#endif
> +#define USER_PTRS_PER_PGD       ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1)

    Could write this as '(TASK_SIZE64 / PGDIR_SIZE ?: 1)'.

[...]
> diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
> index 9b3b48e21c22..bd2030f32ea4 100644
> --- a/arch/mips/include/asm/processor.h
> +++ b/arch/mips/include/asm/processor.h
> @@ -69,7 +69,11 @@ extern unsigned int vced_count, vcei_count;
>    * 8192EB ...
>    */
>   #define TASK_SIZE32	0x7fff8000UL
> -#define TASK_SIZE64	0x10000000000UL
> +#ifdef CONFIG_48VMBITS
> +#define TASK_SIZE64     (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))

    Perhaps '(0x1UL << (min(cpu_data[0].vmbits, 48))'?

> +#else
> +#define TASK_SIZE64     (0x10000000000UL)

    Parens not needed.

[...]

WBR, Sergei

Re: [PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[David Daney]

On 05/14/2015 06:34 PM, Leonid Yegoshin wrote:
> SEGBITS default is 40 bits or less, depending from CPU type.
> This patch introduces 48bits of application virtual address (SEGBITS) support.
> It is defined only for 16K and 64K pages and is optional (configurable).
>
> Penalty - a small number of additional pages for generic (small) applications.
> But for 64K pages it adds 3rd level of PTE structure, which has a little
> impact during software TLB refill.
>
> This patch is needed because MIPS I6XXX and P6XXX cores have 48 bit of
> virtual address in each segment (SEGBITS).
>

I'm concerned that the change log doesn't convey the true reason for the 
patch.

Many processors support larger VA space than is utilized by the kernel. 
  A choice was made to reduce the size of the VA space in order to 
reduce TLB handling overhead.

If the true reason for the patch is to enable larger VA space, say that. 
  But is it really required by those processors you mention?  I doubt it.

David Daney


> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> ---
> V2: Added correction for defintion of TASK_SIZE64
> ---
>   arch/mips/Kconfig                  |   11 +++++++++++
>   arch/mips/include/asm/pgtable-64.h |   18 +++++++++++-------
>   arch/mips/include/asm/processor.h  |    6 +++++-
>   3 files changed, 27 insertions(+), 8 deletions(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 76efb02ae99f..3acff2f065e9 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -2032,6 +2032,17 @@ config PAGE_SIZE_64KB
>
>   endchoice
>
> +config 48VMBITS
> +	bool "48 bits virtual memory"
> +	depends on PAGE_SIZE_16KB || PAGE_SIZE_64KB
> +	depends on 64BIT
> +	help
> +	  Define a maximum at least 48 bits of application virtual memory.
> +	  Default is 40 bits or less, depending from CPU.
> +	  In generic (small) application it is a small set of pages increase
> +	  in page tables.
> +	  If unsure, say N.
> +
>   config FORCE_MAX_ZONEORDER
>   	int "Maximum zone order"
>   	range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
> diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
> index cf661a2fb141..c6b5473440e6 100644
> --- a/arch/mips/include/asm/pgtable-64.h
> +++ b/arch/mips/include/asm/pgtable-64.h
> @@ -17,7 +17,7 @@
>   #include <asm/cachectl.h>
>   #include <asm/fixmap.h>
>
> -#ifdef CONFIG_PAGE_SIZE_64KB
> +#if defined(CONFIG_PAGE_SIZE_64KB) && !defined(CONFIG_48VMBITS)
>   #include <asm-generic/pgtable-nopmd.h>
>   #else
>   #include <asm-generic/pgtable-nopud.h>
> @@ -90,7 +90,11 @@
>   #define PTE_ORDER		0
>   #endif
>   #ifdef CONFIG_PAGE_SIZE_16KB
> -#define PGD_ORDER		0
> +#ifdef CONFIG_48VMBITS
> +#define PGD_ORDER               1
> +#else
> +#define PGD_ORDER               0
> +#endif
>   #define PUD_ORDER		aieeee_attempt_to_allocate_pud
>   #define PMD_ORDER		0
>   #define PTE_ORDER		0
> @@ -104,7 +108,11 @@
>   #ifdef CONFIG_PAGE_SIZE_64KB
>   #define PGD_ORDER		0
>   #define PUD_ORDER		aieeee_attempt_to_allocate_pud
> +#ifdef CONFIG_48VMBITS
> +#define PMD_ORDER		0
> +#else
>   #define PMD_ORDER		aieeee_attempt_to_allocate_pmd
> +#endif
>   #define PTE_ORDER		0
>   #endif
>
> @@ -114,11 +122,7 @@
>   #endif
>   #define PTRS_PER_PTE	((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
>
> -#if PGDIR_SIZE >= TASK_SIZE64
> -#define USER_PTRS_PER_PGD	(1)
> -#else
> -#define USER_PTRS_PER_PGD	(TASK_SIZE64 / PGDIR_SIZE)
> -#endif
> +#define USER_PTRS_PER_PGD       ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1)
>   #define FIRST_USER_ADDRESS	0UL
>
>   /*
> diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
> index 9b3b48e21c22..bd2030f32ea4 100644
> --- a/arch/mips/include/asm/processor.h
> +++ b/arch/mips/include/asm/processor.h
> @@ -69,7 +69,11 @@ extern unsigned int vced_count, vcei_count;
>    * 8192EB ...
>    */
>   #define TASK_SIZE32	0x7fff8000UL
> -#define TASK_SIZE64	0x10000000000UL
> +#ifdef CONFIG_48VMBITS
> +#define TASK_SIZE64     (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
> +#else
> +#define TASK_SIZE64     (0x10000000000UL)
> +#endif
>   #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
>   #define STACK_TOP_MAX	TASK_SIZE64
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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> Please read the FAQ at  http://www.tux.org/lkml/
>
>

Re: [PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[Leonid Yegoshin]

On 05/15/2015 09:28 AM, David Daney wrote:
> On 05/14/2015 06:34 PM, Leonid Yegoshin wrote:
>> SEGBITS default is 40 bits or less, depending from CPU type.
>> This patch introduces 48bits of application virtual address (SEGBITS) support.
>> It is defined only for 16K and 64K pages and is optional (configurable).
>>
>> Penalty - a small number of additional pages for generic (small) applications.
>> But for 64K pages it adds 3rd level of PTE structure, which has a little
>> impact during software TLB refill.
>>
>> This patch is needed because MIPS I6XXX and P6XXX cores have 48 bit of
>> virtual address in each segment (SEGBITS).
>>
> I'm concerned that the change log doesn't convey the true reason for the
> patch.
>
> Many processors support larger VA space than is utilized by the kernel.
>    A choice was made to reduce the size of the VA space in order to
> reduce TLB handling overhead.
>
> If the true reason for the patch is to enable larger VA space, say that.
>    But is it really required by those processors you mention?  I doubt it.
>
> David Daney
>
>

Well, I was not aware about many processors capability, I can't find 
this kind of note anywhere.

And I assumed that statement "If unsure, say N" and the fact that it is 
configurable leads to conclusion that it is completely optional. I have 
a request from management to support 48bit VA but I understand that 
somebody may not like even small penalty.

In other side, this patch was required to test HW capability, GLIBC and 
application compatibility (I tested on buildroot FS).

So, if you still have concern, please propose a description statement.

- Leonid.

Re: [PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[David Daney]

On 05/14/2015 06:34 PM, Leonid Yegoshin wrote:
> SEGBITS default is 40 bits or less, depending from CPU type.
> This patch introduces 48bits of application virtual address (SEGBITS) support.
> It is defined only for 16K and 64K pages and is optional (configurable).
>
> Penalty - a small number of additional pages for generic (small) applications.
> But for 64K pages it adds 3rd level of PTE structure, which has a little
> impact during software TLB refill.
>
> This patch is needed because MIPS I6XXX and P6XXX cores have 48 bit of
> virtual address in each segment (SEGBITS).
>

Those processors don't require the patch.  You wrote the patch to give a 
larger VA space at the request of kernel users.  So perhaps say:

   The patch (optionally) increases the VA space available to userspace 
processes from N-bits to 48-bits


> Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> ---
> V2: Added correction for defintion of TASK_SIZE64
> ---
>   arch/mips/Kconfig                  |   11 +++++++++++
>   arch/mips/include/asm/pgtable-64.h |   18 +++++++++++-------
>   arch/mips/include/asm/processor.h  |    6 +++++-
>   3 files changed, 27 insertions(+), 8 deletions(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 76efb02ae99f..3acff2f065e9 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -2032,6 +2032,17 @@ config PAGE_SIZE_64KB
>
>   endchoice
>
> +config 48VMBITS

Should probabaly be called VABITS instead of VMBITS to match the terms 
used in the architecture reference manuals, as well as other ports (ARM64).

Perhaps MIPS_VA_BITS_48


> +	bool "48 bits virtual memory"
> +	depends on PAGE_SIZE_16KB || PAGE_SIZE_64KB
> +	depends on 64BIT
> +	help
> +	  Define a maximum at least 48 bits of application virtual memory.
> +	  Default is 40 bits or less, depending from CPU.
> +	  In generic (small) application it is a small set of pages increase
> +	  in page tables.
> +	  If unsure, say N.
> +
>   config FORCE_MAX_ZONEORDER
>   	int "Maximum zone order"
>   	range 14 64 if MIPS_HUGE_TLB_SUPPORT && PAGE_SIZE_64KB
> diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h
> index cf661a2fb141..c6b5473440e6 100644
> --- a/arch/mips/include/asm/pgtable-64.h
> +++ b/arch/mips/include/asm/pgtable-64.h
> @@ -17,7 +17,7 @@
>   #include <asm/cachectl.h>
>   #include <asm/fixmap.h>
>
> -#ifdef CONFIG_PAGE_SIZE_64KB
> +#if defined(CONFIG_PAGE_SIZE_64KB) && !defined(CONFIG_48VMBITS)
>   #include <asm-generic/pgtable-nopmd.h>
>   #else
>   #include <asm-generic/pgtable-nopud.h>
> @@ -90,7 +90,11 @@
>   #define PTE_ORDER		0
>   #endif
>   #ifdef CONFIG_PAGE_SIZE_16KB
> -#define PGD_ORDER		0
> +#ifdef CONFIG_48VMBITS
> +#define PGD_ORDER               1
> +#else
> +#define PGD_ORDER               0
> +#endif
>   #define PUD_ORDER		aieeee_attempt_to_allocate_pud
>   #define PMD_ORDER		0
>   #define PTE_ORDER		0
> @@ -104,7 +108,11 @@
>   #ifdef CONFIG_PAGE_SIZE_64KB
>   #define PGD_ORDER		0
>   #define PUD_ORDER		aieeee_attempt_to_allocate_pud
> +#ifdef CONFIG_48VMBITS
> +#define PMD_ORDER		0
> +#else
>   #define PMD_ORDER		aieeee_attempt_to_allocate_pmd
> +#endif
>   #define PTE_ORDER		0
>   #endif
>
> @@ -114,11 +122,7 @@
>   #endif
>   #define PTRS_PER_PTE	((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
>
> -#if PGDIR_SIZE >= TASK_SIZE64
> -#define USER_PTRS_PER_PGD	(1)
> -#else
> -#define USER_PTRS_PER_PGD	(TASK_SIZE64 / PGDIR_SIZE)
> -#endif
> +#define USER_PTRS_PER_PGD       ((TASK_SIZE64 / PGDIR_SIZE)?(TASK_SIZE64 / PGDIR_SIZE):1)
>   #define FIRST_USER_ADDRESS	0UL
>
>   /*
> diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
> index 9b3b48e21c22..bd2030f32ea4 100644
> --- a/arch/mips/include/asm/processor.h
> +++ b/arch/mips/include/asm/processor.h
> @@ -69,7 +69,11 @@ extern unsigned int vced_count, vcei_count;
>    * 8192EB ...
>    */
>   #define TASK_SIZE32	0x7fff8000UL
> -#define TASK_SIZE64	0x10000000000UL
> +#ifdef CONFIG_48VMBITS
> +#define TASK_SIZE64     (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
> +#else
> +#define TASK_SIZE64     (0x10000000000UL)
> +#endif
>   #define TASK_SIZE (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE64)
>   #define STACK_TOP_MAX	TASK_SIZE64
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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> Please read the FAQ at  http://www.tux.org/lkml/
>
>

Re: [PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[Leonid Yegoshin]

On 05/15/2015 01:49 PM, David Daney wrote:
> On 05/14/2015 06:34 PM, Leonid Yegoshin wrote:
>> SEGBITS default is 40 bits or less, depending from CPU type.
>> This patch introduces 48bits of application virtual address (SEGBITS) 
>> support.
>> It is defined only for 16K and 64K pages and is optional (configurable).
>>
>> Penalty - a small number of additional pages for generic (small) 
>> applications.
>> But for 64K pages it adds 3rd level of PTE structure, which has a little
>> impact during software TLB refill.
>>
>> This patch is needed because MIPS I6XXX and P6XXX cores have 48 bit of
>> virtual address in each segment (SEGBITS).
>>
>
> Those processors don't require the patch.  You wrote the patch to give 
> a larger VA space at the request of kernel users.  So perhaps say:
>
>   The patch (optionally) increases the VA space available to userspace 
> processes from N-bits to 48-bits
>

... if CPU model supports that

>
>>
>> +config 48VMBITS
>
> Should probabaly be called VABITS instead of VMBITS to match the terms 
> used in the architecture reference manuals, as well as other ports 
> (ARM64).
>
> Perhaps MIPS_VA_BITS_48

I don't mind here. It can be even called 48SEGBITS or so, to match arch 
manual more. MIPS Arch manual never says about VA bits but speaks about 
PABITS and SEGBITS.

- Leonid.

Re: [PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[Leonid Yegoshin]

On 05/15/2015 01:49 PM, David Daney wrote:
> On 05/14/2015 06:34 PM, Leonid Yegoshin wrote:
>> SEGBITS default is 40 bits or less, depending from CPU type.
>> This patch introduces 48bits of application virtual address (SEGBITS) 
>> support.
>> It is defined only for 16K and 64K pages and is optional (configurable).
>>
>> Penalty - a small number of additional pages for generic (small) 
>> applications.
>> But for 64K pages it adds 3rd level of PTE structure, which has a little
>> impact during software TLB refill.
>>
>> This patch is needed because MIPS I6XXX and P6XXX cores have 48 bit of
>> virtual address in each segment (SEGBITS).
>>
>
> Those processors don't require the patch.  You wrote the patch to give 
> a larger VA space at the request of kernel users.  So perhaps say:
>
>   The patch (optionally) increases the VA space available to userspace 
> processes from N-bits to 48-bits
>

... if CPU model supports that

>
>>
>> +config 48VMBITS
>
> Should probabaly be called VABITS instead of VMBITS to match the terms 
> used in the architecture reference manuals, as well as other ports 
> (ARM64).
>
> Perhaps MIPS_VA_BITS_48

I don't mind here. It can be even called 48SEGBITS or so, to match arch 
manual more. MIPS Arch manual never says about VA bits but speaks about 
PABITS and SEGBITS.

- Leonid.

Re: [PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[Ralf Baechle]

On Thu, May 14, 2015 at 06:34:43PM -0700, Leonid Yegoshin wrote:

The order 1 allocation for the PGD are concerning me a little.  On a
system under even moderate memory pressure that might become a bit of
a reliability or performance issue.

With 4kB pages we already need order 1 or even 2 allocations for the
allocation of the stack and some folks have reported that to be an issue
so we may have to start using the PUD for very large VA spaces.

  Ralf

Re: [PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[Leonid Yegoshin]

On 05/15/2015 02:53 PM, Ralf Baechle wrote:
> On Thu, May 14, 2015 at 06:34:43PM -0700, Leonid Yegoshin wrote:
>
> The order 1 allocation for the PGD are concerning me a little.  On a
> system under even moderate memory pressure that might become a bit of
> a reliability or performance issue.
>
> With 4kB pages we already need order 1 or even 2 allocations for the
> allocation of the stack and some folks have reported that to be an issue
> so we may have to start using the PUD for very large VA spaces.
>
>    Ralf

I don't think it is an issue here - people, who wants to exercise 256 
TERABAIT of memory PER PROCESS may even doesn't note that they have PGD 
= 2 pages. It is definitely not for systems with 4GB physmemory.

I also recommend for low memory to look into CONFIG_COMPACTION, it may 
be a great help for them here, look into mm/vmscan.c, 
in_reclaim_compaction().

Besides that, I defined this feature for 16KB and 64KB pages only, not 
for 4KB.

Re: [PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[Leonid Yegoshin]

On 05/15/2015 02:53 PM, Ralf Baechle wrote:
> On Thu, May 14, 2015 at 06:34:43PM -0700, Leonid Yegoshin wrote:
>
> The order 1 allocation for the PGD are concerning me a little.  On a
> system under even moderate memory pressure that might become a bit of
> a reliability or performance issue.
>
> With 4kB pages we already need order 1 or even 2 allocations for the
> allocation of the stack and some folks have reported that to be an issue
> so we may have to start using the PUD for very large VA spaces.
>
>    Ralf

I don't think it is an issue here - people, who wants to exercise 256 
TERABAIT of memory PER PROCESS may even doesn't note that they have PGD 
= 2 pages. It is definitely not for systems with 4GB physmemory.

I also recommend for low memory to look into CONFIG_COMPACTION, it may 
be a great help for them here, look into mm/vmscan.c, 
in_reclaim_compaction().

Besides that, I defined this feature for 16KB and 64KB pages only, not 
for 4KB.

Re: [PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[Maciej W. Rozycki]

On Fri, 15 May 2015, Leonid Yegoshin wrote:

> > Many processors support larger VA space than is utilized by the kernel.
> >    A choice was made to reduce the size of the VA space in order to
> > reduce TLB handling overhead.
> >
> > If the true reason for the patch is to enable larger VA space, say that.
> >    But is it really required by those processors you mention?  I doubt it.
> 
> Well, I was not aware about many processors capability, I can't find this kind
> of note anywhere.

 The R10000 and friends all have a 44-bit virtual address space, so this 
is no news to Linux.  This is noted in <asm/processor.h> right above the 
change you made there.

  Maciej

Re: [PATCH v2] MIPS64: Support of at least 48 bits of SEGBITS

[Joshua Kinard]

On 05/15/2015 18:39, Leonid Yegoshin wrote:
> On 05/15/2015 02:53 PM, Ralf Baechle wrote:
>> On Thu, May 14, 2015 at 06:34:43PM -0700, Leonid Yegoshin wrote:
>>
>> The order 1 allocation for the PGD are concerning me a little.  On a
>> system under even moderate memory pressure that might become a bit of
>> a reliability or performance issue.
>>
>> With 4kB pages we already need order 1 or even 2 allocations for the
>> allocation of the stack and some folks have reported that to be an issue
>> so we may have to start using the PUD for very large VA spaces.
>>
>>    Ralf
> 
> I don't think it is an issue here - people, who wants to exercise 256 TERABAIT
> of memory PER PROCESS may even doesn't note that they have PGD = 2 pages. It is
> definitely not for systems with 4GB physmemory.
> 
> I also recommend for low memory to look into CONFIG_COMPACTION, it may be a
> great help for them here, look into mm/vmscan.c, in_reclaim_compaction().
> 
> Besides that, I defined this feature for 16KB and 64KB pages only, not for 4KB.

There's something screwy with R14000 CPUs and 16kb/64kb pages.  I haven't
figured it out yet, but you get random SIGSEGV and SIGBUS errors running that
PAGE_SIZE.  I figure it's some unknown/undocumented bit that SGI added and
never disclosed anywhere.

--J