* [Qemu-devel] [PATCH 1/8] Introduce AUX bus.
2015-05-13 19:11 [Qemu-devel] [PATCH 0/8] Xilinx DisplayPort fred.konrad
@ 2015-05-13 19:11 ` fred.konrad
2015-05-13 19:12 ` [Qemu-devel] [PATCH 2/8] i2c: implement broadcast write fred.konrad
` (6 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: fred.konrad @ 2015-05-13 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.crosthwaite, mark.burton, hyunk, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This introduces a new bus: aux-bus.
It contains an address space for aux slaves devices and a bridge to an I2C bus
for I2C through AUX transactions.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/misc/Makefile.objs | 1 +
hw/misc/aux.c | 421 ++++++++++++++++++++++++++++++++++++++++++++++++++
include/hw/aux.h | 127 +++++++++++++++
3 files changed, 549 insertions(+)
create mode 100644 hw/misc/aux.c
create mode 100644 include/hw/aux.h
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 4aa76ff..61eb59b 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -40,3 +40,4 @@ obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o
obj-$(CONFIG_PVPANIC) += pvpanic.o
obj-$(CONFIG_EDU) += edu.o
+obj-y += aux.o
diff --git a/hw/misc/aux.c b/hw/misc/aux.c
new file mode 100644
index 0000000..ad64acd
--- /dev/null
+++ b/hw/misc/aux.c
@@ -0,0 +1,421 @@
+/*
+ * aux.c
+ *
+ * Copyright 2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/*
+ * This is an implementation of the AUX bus for VESA Display Port v1.1a.
+ */
+
+#include "hw/aux.h"
+#include "hw/i2c/i2c.h"
+#include "monitor/monitor.h"
+
+/* #define DEBUG_AUX */
+
+#ifdef DEBUG_AUX
+#define DPRINTF(fmt, ...)\
+do { printf("aux: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...)do {} while (0)
+#endif
+
+#define TYPE_AUXTOI2C "aux-to-i2c-bridge"
+#define AUXTOI2C(obj) OBJECT_CHECK(AUXTOI2CState, (obj), TYPE_AUXTOI2C)
+
+typedef struct AUXTOI2CState AUXTOI2CState;
+
+struct AUXBus {
+ BusState qbus;
+ AUXSlave *current_dev;
+ AUXSlave *dev;
+ uint32_t last_i2c_address;
+ aux_command last_transaction;
+
+ AUXTOI2CState *bridge;
+
+ MemoryRegion *aux_io;
+ AddressSpace aux_addr_space;
+};
+
+static Property aux_props[] = {
+ DEFINE_PROP_UINT64("address", struct AUXSlave, address, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+#define TYPE_AUX_BUS "aux-bus"
+#define AUX_BUS(obj) OBJECT_CHECK(AUXBus, (obj), TYPE_AUX_BUS)
+
+static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent);
+
+static void aux_bus_class_init(ObjectClass *klass, void *data)
+{
+ /*
+ * AUXSlave has an mmio so we need to change the way we print information
+ * in monitor.
+ */
+ BusClass *k = BUS_CLASS(klass);
+ k->print_dev = aux_slave_dev_print;
+}
+
+static const TypeInfo aux_bus_info = {
+ .name = TYPE_AUX_BUS,
+ .parent = TYPE_BUS,
+ .instance_size = sizeof(AUXBus),
+ .class_init = aux_bus_class_init
+};
+
+AUXBus *aux_init_bus(DeviceState *parent, const char *name)
+{
+ AUXBus *bus;
+
+ bus = AUX_BUS(qbus_create(TYPE_AUX_BUS, parent, name));
+
+ /*
+ * Create the bridge.
+ */
+ bus->bridge = AUXTOI2C(qdev_create(BUS(bus), TYPE_AUXTOI2C));
+
+ /*
+ * Memory related.
+ */
+ bus->aux_io = g_malloc(sizeof(*bus->aux_io));
+ memory_region_init(bus->aux_io, OBJECT(bus), "aux-io", (1 << 20));
+ address_space_init(&bus->aux_addr_space, bus->aux_io, "aux-io");
+ return bus;
+}
+
+static void aux_bus_map_device(AUXBus *bus, AUXSlave *dev)
+{
+ memory_region_add_subregion(bus->aux_io, dev->address, dev->mmio);
+}
+
+void aux_set_slave_address(AUXSlave *dev, uint32_t address)
+{
+ qdev_prop_set_uint64(DEVICE(dev), "address", address);
+}
+
+static bool aux_bus_is_bridge(AUXBus *bus, DeviceState *dev)
+{
+ return (dev == DEVICE(bus->bridge));
+}
+
+/*
+ * Make a native request on the AUX bus.
+ */
+static aux_reply aux_native_request(AUXBus *bus, aux_command cmd,
+ uint32_t address, uint8_t len,
+ uint8_t *data)
+{
+ /*
+ * Transactions on aux address map are 1bytes len time.
+ */
+ aux_reply ret = AUX_NACK;
+ size_t i;
+
+ switch (cmd) {
+ case READ_AUX:
+ for (i = 0; i < len; i++) {
+ if (!address_space_rw(&bus->aux_addr_space, address++,
+ MEMTXATTRS_UNSPECIFIED, data++, 1, false)) {
+ ret = AUX_I2C_ACK;
+ } else {
+ ret = AUX_NACK;
+ break;
+ }
+ }
+ break;
+ case WRITE_AUX:
+ for (i = 0; i < len; i++) {
+ if (!address_space_rw(&bus->aux_addr_space, address++,
+ MEMTXATTRS_UNSPECIFIED, data++, 1, true)) {
+ ret = AUX_I2C_ACK;
+ } else {
+ ret = AUX_NACK;
+ break;
+ }
+ }
+ break;
+ default:
+ abort();
+ break;
+ }
+
+ return ret;
+}
+
+aux_reply aux_request(AUXBus *bus, aux_command cmd, uint32_t address,
+ uint8_t len, uint8_t *data)
+{
+ DPRINTF("request at address 0x%5.5X, command %u, len %u\n", address, cmd,
+ len);
+
+ int temp;
+ aux_reply ret = AUX_NACK;
+ I2CBus *i2c_bus = aux_get_i2c_bus(bus);
+
+ switch (cmd) {
+ /*
+ * Forward the request on the AUX bus..
+ */
+ case WRITE_AUX:
+ case READ_AUX:
+ ret = aux_native_request(bus, cmd, address, len, data);
+ break;
+ /*
+ * Classic I2C transactions..
+ */
+ case READ_I2C:
+ if (i2c_bus_busy(i2c_bus)) {
+ i2c_end_transfer(i2c_bus);
+ }
+
+ if (i2c_start_transfer(i2c_bus, address, 1)) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+
+ while (len > 0) {
+ temp = i2c_recv(i2c_bus);
+
+ if (temp < 0) {
+ ret = AUX_I2C_NACK;
+ i2c_end_transfer(i2c_bus);
+ break;
+ }
+
+ *data++ = temp;
+ len--;
+ }
+ i2c_end_transfer(i2c_bus);
+ ret = AUX_I2C_ACK;
+ break;
+ case WRITE_I2C:
+ if (i2c_bus_busy(i2c_bus)) {
+ i2c_end_transfer(i2c_bus);
+ }
+
+ if (i2c_start_transfer(i2c_bus, address, 0)) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+
+ while (len > 0) {
+ if (!i2c_send(i2c_bus, *data++)) {
+ ret = AUX_I2C_NACK;
+ i2c_end_transfer(i2c_bus);
+ break;
+ }
+ len--;
+ }
+ i2c_end_transfer(i2c_bus);
+ ret = AUX_I2C_ACK;
+ break;
+ /*
+ * I2C MOT transactions.
+ *
+ * Here we send a start when:
+ * - We didn't start transaction yet.
+ * - We had a READ and we do a WRITE.
+ * - We change the address.
+ */
+ case WRITE_I2C_MOT:
+ if (!i2c_bus_busy(i2c_bus)) {
+ /*
+ * No transactions started..
+ */
+ if (i2c_start_transfer(i2c_bus, address, 0)) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+ } else if ((address != bus->last_i2c_address) ||
+ (bus->last_transaction == READ_I2C_MOT)) {
+ /*
+ * Transaction started but we need to restart..
+ */
+ i2c_end_transfer(i2c_bus);
+ if (i2c_start_transfer(i2c_bus, address, 0)) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+ }
+
+ while (len > 0) {
+ if (!i2c_send(i2c_bus, *data++)) {
+ ret = AUX_I2C_NACK;
+ i2c_end_transfer(i2c_bus);
+ break;
+ }
+ len--;
+ }
+ bus->last_transaction = WRITE_I2C_MOT;
+ bus->last_i2c_address = address;
+ ret = AUX_I2C_ACK;
+ break;
+ case READ_I2C_MOT:
+ if (!i2c_bus_busy(i2c_bus)) {
+ /*
+ * No transactions started..
+ */
+ if (i2c_start_transfer(i2c_bus, address, 0)) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+ } else if (address != bus->last_i2c_address) {
+ /*
+ * Transaction started but we need to restart..
+ */
+ i2c_end_transfer(i2c_bus);
+ if (i2c_start_transfer(i2c_bus, address, 0)) {
+ ret = AUX_I2C_NACK;
+ break;
+ }
+ }
+
+ while (len > 0) {
+ temp = i2c_recv(i2c_bus);
+
+ if (temp < 0) {
+ ret = AUX_I2C_NACK;
+ i2c_end_transfer(i2c_bus);
+ break;
+ }
+
+ *data++ = temp;
+ len--;
+ }
+ bus->last_transaction = READ_I2C_MOT;
+ bus->last_i2c_address = address;
+ ret = AUX_I2C_ACK;
+ break;
+ default:
+ DPRINTF("Not implemented!\n");
+ ret = AUX_NACK;
+ break;
+ }
+
+ DPRINTF("reply: %u\n", ret);
+ return ret;
+}
+
+/*
+ * AUX to I2C bridge.
+ */
+struct AUXTOI2CState {
+ DeviceState parent_obj;
+ I2CBus *i2c_bus;
+};
+
+I2CBus *aux_get_i2c_bus(AUXBus *bus)
+{
+ return bus->bridge->i2c_bus;
+}
+
+static void aux_bridge_init(Object *obj)
+{
+ AUXTOI2CState *s = AUXTOI2C(obj);
+ /*
+ * Create the I2C Bus.
+ */
+ s->i2c_bus = i2c_init_bus(DEVICE(obj), "aux-i2c");
+}
+
+static const TypeInfo aux_to_i2c_type_info = {
+ .name = TYPE_AUXTOI2C,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(AUXTOI2CState),
+ .instance_init = aux_bridge_init
+};
+
+/*
+ * AUX Slave.
+ */
+static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent)
+{
+ AUXBus *bus = AUX_BUS(qdev_get_parent_bus(dev));
+ hwaddr size;
+ AUXSlave *s;
+
+ /*
+ * Don't print anything if the device is I2C "bridge".
+ */
+ if (aux_bus_is_bridge(bus, dev)) {
+ return;
+ }
+
+ s = AUX_SLAVE(dev);
+
+ size = memory_region_size(s->mmio);
+ monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n",
+ indent, "", s->address, size);
+}
+
+static int aux_slave_qdev_init(DeviceState *dev)
+{
+ AUXSlave *s = AUX_SLAVE(dev);
+ AUXSlaveClass *sc = AUX_SLAVE_GET_CLASS(s);
+
+ return sc->init(s);
+}
+
+DeviceState *aux_create_slave(AUXBus *bus, const char *name, uint32_t addr)
+{
+ DeviceState *dev;
+
+ dev = qdev_create(&bus->qbus, name);
+ qdev_prop_set_uint64(dev, "address", addr);
+ qdev_init_nofail(dev);
+ aux_bus_map_device(AUX_BUS(qdev_get_parent_bus(dev)), AUX_SLAVE(dev));
+ return dev;
+}
+
+void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio)
+{
+ aux_slave->mmio = mmio;
+}
+
+static void aux_slave_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *k = DEVICE_CLASS(klass);
+ k->init = aux_slave_qdev_init;
+ set_bit(DEVICE_CATEGORY_MISC, k->categories);
+ k->bus_type = TYPE_AUX_BUS;
+ k->props = aux_props;
+}
+
+static const TypeInfo aux_slave_type_info = {
+ .name = TYPE_AUX_SLAVE,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(AUXSlave),
+ .abstract = true,
+ .class_size = sizeof(AUXSlaveClass),
+ .class_init = aux_slave_class_init,
+};
+
+static void aux_slave_register_types(void)
+{
+ type_register_static(&aux_bus_info);
+ type_register_static(&aux_slave_type_info);
+ type_register_static(&aux_to_i2c_type_info);
+}
+
+type_init(aux_slave_register_types)
diff --git a/include/hw/aux.h b/include/hw/aux.h
new file mode 100644
index 0000000..b9be4a4
--- /dev/null
+++ b/include/hw/aux.h
@@ -0,0 +1,127 @@
+/*
+ * aux.h
+ *
+ * Copyright (C)2014 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef QEMU_AUX_H
+#define QEMU_AUX_H
+
+#include "hw/qdev.h"
+
+enum aux_command {
+ WRITE_I2C = 0,
+ READ_I2C = 1,
+ WRITE_I2C_STATUS = 2,
+ WRITE_I2C_MOT = 4,
+ READ_I2C_MOT = 5,
+ WRITE_AUX = 8,
+ READ_AUX = 9
+};
+
+enum aux_reply {
+ AUX_I2C_ACK = 0,
+ AUX_NACK = 1,
+ AUX_DEFER = 2,
+ AUX_I2C_NACK = 4,
+ AUX_I2C_DEFER = 8
+};
+
+typedef struct AUXBus AUXBus;
+typedef struct AUXSlave AUXSlave;
+typedef enum aux_command aux_command;
+typedef enum aux_reply aux_reply;
+
+#define TYPE_AUX_SLAVE "aux-slave"
+#define AUX_SLAVE(obj) \
+ OBJECT_CHECK(AUXSlave, (obj), TYPE_AUX_SLAVE)
+#define AUX_SLAVE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AUXSlaveClass, (klass), TYPE_AUX_SLAVE)
+#define AUX_SLAVE_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AUXSlaveClass, (obj), TYPE_AUX_SLAVE)
+
+struct AUXSlave {
+ /* < private > */
+ DeviceState parent_obj;
+
+ /* address of the device on the aux bus. */
+ hwaddr address;
+ /* memory region associated. */
+ MemoryRegion *mmio;
+};
+
+typedef struct AUXSlaveClass {
+ DeviceClass parent_class;
+
+ /* Callbacks provided by the device. */
+ int (*init)(AUXSlave *dev);
+} AUXSlaveClass;
+
+/*
+ * \func aux_init_bus
+ * \brief Init an aux bus.
+ * \param parent The device where this bus is located.
+ * \param name The name of the bus.
+ * \return The new aux bus.
+ */
+AUXBus *aux_init_bus(DeviceState *parent, const char *name);
+
+/*
+ * \func aux_slave_set_address
+ * \brief Set the address of the slave on the aux bus.
+ * \param dev The aux slave device.
+ * \param address The address to give to the slave.
+ */
+void aux_set_slave_address(AUXSlave *dev, uint32_t address);
+
+/*
+ * \func aux_request
+ * \brief Make a request on the bus.
+ * \param bus Ths bus where the request happen.
+ * \param cmd The command requested.
+ * \param address The 20bits address of the slave.
+ * \param len The length of the read or write.
+ * \param data The data array which will be filled or read during transfer.
+ * \return Return the reply of the request.
+ */
+aux_reply aux_request(AUXBus *bus, aux_command cmd, uint32_t address,
+ uint8_t len, uint8_t *data);
+
+/*
+ * \func aux_get_i2c_bus
+ * \brief Get the i2c bus for I2C over AUX command.
+ * \param bus The aux bus.
+ * \return Return the i2c bus associated.
+ */
+I2CBus *aux_get_i2c_bus(AUXBus *bus);
+
+/*
+ * \func aux_init_mmio
+ * \brief Init an mmio for an aux slave, must be called after
+ * memory_region_init_io.
+ * \param aux_slave The aux slave.
+ * \param mmio The mmio to be registered.
+ */
+void aux_init_mmio(AUXSlave *aux_slave, MemoryRegion *mmio);
+
+DeviceState *aux_create_slave(AUXBus *bus, const char *name, uint32_t addr);
+
+#endif /* !QEMU_AUX_H */
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 2/8] i2c: implement broadcast write.
2015-05-13 19:11 [Qemu-devel] [PATCH 0/8] Xilinx DisplayPort fred.konrad
2015-05-13 19:11 ` [Qemu-devel] [PATCH 1/8] Introduce AUX bus fred.konrad
@ 2015-05-13 19:12 ` fred.konrad
2015-05-14 3:58 ` Peter Crosthwaite
2015-05-13 19:12 ` [Qemu-devel] [PATCH 3/8] console: add qemu_alloc_display_format fred.konrad
` (5 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: fred.konrad @ 2015-05-13 19:12 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.crosthwaite, mark.burton, hyunk, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This does a write to every slaves when the I2C bus get a write to address 0.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/i2c/core.c | 46 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/hw/i2c/core.c b/hw/i2c/core.c
index 5a64026..db1cbdd 100644
--- a/hw/i2c/core.c
+++ b/hw/i2c/core.c
@@ -15,6 +15,7 @@ struct I2CBus
I2CSlave *current_dev;
I2CSlave *dev;
uint8_t saved_address;
+ bool broadcast;
};
static Property i2c_props[] = {
@@ -67,6 +68,8 @@ I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
vmstate_register(NULL, -1, &vmstate_i2c_bus, bus);
+
+ bus->broadcast = false;
return bus;
}
@@ -89,6 +92,21 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
I2CSlave *slave = NULL;
I2CSlaveClass *sc;
+ if (address == 0x00) {
+ /*
+ * This is a broadcast.
+ */
+ QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
+ I2CSlave *dev = I2C_SLAVE(kid->child);
+ sc = I2C_SLAVE_GET_CLASS(dev);
+ bus->broadcast = true;
+ if (sc->event) {
+ sc->event(dev, recv ? I2C_START_RECV : I2C_START_SEND);
+ }
+ }
+ return 0;
+ }
+
QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
DeviceState *qdev = kid->child;
I2CSlave *candidate = I2C_SLAVE(qdev);
@@ -114,9 +132,21 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
void i2c_end_transfer(I2CBus *bus)
{
+ BusChild *kid;
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
+ if (bus->broadcast) {
+ QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
+ I2CSlave *dev = I2C_SLAVE(kid->child);
+ sc = I2C_SLAVE_GET_CLASS(dev);
+ if (sc->event) {
+ sc->event(dev, I2C_FINISH);
+ }
+ }
+ bus->broadcast = false;
+ }
+
if (!dev) {
return;
}
@@ -131,8 +161,22 @@ void i2c_end_transfer(I2CBus *bus)
int i2c_send(I2CBus *bus, uint8_t data)
{
+ BusChild *kid;
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
+ int ret = 0;
+
+ if (bus->broadcast) {
+ QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
+ I2CSlave *dev = I2C_SLAVE(kid->child);
+ sc = I2C_SLAVE_GET_CLASS(dev);
+ bus->broadcast = true;
+ if (sc->send) {
+ ret |= sc->send(dev, data);
+ }
+ }
+ return ret;
+ }
if (!dev) {
return -1;
@@ -151,7 +195,7 @@ int i2c_recv(I2CBus *bus)
I2CSlave *dev = bus->current_dev;
I2CSlaveClass *sc;
- if (!dev) {
+ if ((!dev) || (bus->broadcast)) {
return -1;
}
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 2/8] i2c: implement broadcast write.
2015-05-13 19:12 ` [Qemu-devel] [PATCH 2/8] i2c: implement broadcast write fred.konrad
@ 2015-05-14 3:58 ` Peter Crosthwaite
0 siblings, 0 replies; 20+ messages in thread
From: Peter Crosthwaite @ 2015-05-14 3:58 UTC (permalink / raw)
To: Fréderic Konrad; +Cc: Mark Burton, qemu-devel@nongnu.org Developers, hyunk
On Wed, May 13, 2015 at 12:12 PM, <fred.konrad@greensocs.com> wrote:
> From: KONRAD Frederic <fred.konrad@greensocs.com>
>
> This does a write to every slaves when the I2C bus get a write to address 0.
>
"slave"
> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
> ---
> hw/i2c/core.c | 46 +++++++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 45 insertions(+), 1 deletion(-)
>
> diff --git a/hw/i2c/core.c b/hw/i2c/core.c
> index 5a64026..db1cbdd 100644
> --- a/hw/i2c/core.c
> +++ b/hw/i2c/core.c
> @@ -15,6 +15,7 @@ struct I2CBus
> I2CSlave *current_dev;
> I2CSlave *dev;
> uint8_t saved_address;
> + bool broadcast;
> };
>
> static Property i2c_props[] = {
> @@ -67,6 +68,8 @@ I2CBus *i2c_init_bus(DeviceState *parent, const char *name)
>
> bus = I2C_BUS(qbus_create(TYPE_I2C_BUS, parent, name));
> vmstate_register(NULL, -1, &vmstate_i2c_bus, bus);
> +
> + bus->broadcast = false;
0 initialiser should not be needed for new QOM objects.
> return bus;
> }
>
> @@ -89,6 +92,21 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
> I2CSlave *slave = NULL;
> I2CSlaveClass *sc;
>
> + if (address == 0x00) {
> + /*
> + * This is a broadcast.
> + */
one line comment.
> + QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
qbus field is private to the QOM parent and cant be dereffed like
this. Use a BUS() cast.
> + I2CSlave *dev = I2C_SLAVE(kid->child);
> + sc = I2C_SLAVE_GET_CLASS(dev);
> + bus->broadcast = true;
Move outside loop.
> + if (sc->event) {
> + sc->event(dev, recv ? I2C_START_RECV : I2C_START_SEND);
> + }
> + }
> + return 0;
> + }
> +
This leads to some duped code. The existing loop should be refactored
to contain the actual I2C transfer as a conditional, then the
broadcast flag can be ||d into that condition.
> QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
> DeviceState *qdev = kid->child;
> I2CSlave *candidate = I2C_SLAVE(qdev);
> @@ -114,9 +132,21 @@ int i2c_start_transfer(I2CBus *bus, uint8_t address, int recv)
>
> void i2c_end_transfer(I2CBus *bus)
> {
> + BusChild *kid;
> I2CSlave *dev = bus->current_dev;
> I2CSlaveClass *sc;
>
> + if (bus->broadcast) {
> + QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
> + I2CSlave *dev = I2C_SLAVE(kid->child);
> + sc = I2C_SLAVE_GET_CLASS(dev);
> + if (sc->event) {
> + sc->event(dev, I2C_FINISH);
> + }
> + }
> + bus->broadcast = false;
> + }
> +
Similar refactor would help here. Coreify
sc = I2C_SLAVE_GET_CLASS(dev);
if (sc->event) {
sc->event(dev, I2C_FINISH);
}
As a static inline, then i2c_end transfer ether calls for current_dev
or does a single-line bodied loop fr bcast.
Here and below.
Regards,
Peter
> if (!dev) {
> return;
> }
> @@ -131,8 +161,22 @@ void i2c_end_transfer(I2CBus *bus)
>
> int i2c_send(I2CBus *bus, uint8_t data)
> {
> + BusChild *kid;
> I2CSlave *dev = bus->current_dev;
> I2CSlaveClass *sc;
> + int ret = 0;
> +
> + if (bus->broadcast) {
> + QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
> + I2CSlave *dev = I2C_SLAVE(kid->child);
> + sc = I2C_SLAVE_GET_CLASS(dev);
> + bus->broadcast = true;
> + if (sc->send) {
> + ret |= sc->send(dev, data);
> + }
> + }
> + return ret;
> + }
>
> if (!dev) {
> return -1;
> @@ -151,7 +195,7 @@ int i2c_recv(I2CBus *bus)
> I2CSlave *dev = bus->current_dev;
> I2CSlaveClass *sc;
>
> - if (!dev) {
> + if ((!dev) || (bus->broadcast)) {
> return -1;
> }
>
> --
> 1.9.0
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 3/8] console: add qemu_alloc_display_format.
2015-05-13 19:11 [Qemu-devel] [PATCH 0/8] Xilinx DisplayPort fred.konrad
2015-05-13 19:11 ` [Qemu-devel] [PATCH 1/8] Introduce AUX bus fred.konrad
2015-05-13 19:12 ` [Qemu-devel] [PATCH 2/8] i2c: implement broadcast write fred.konrad
@ 2015-05-13 19:12 ` fred.konrad
2015-05-18 7:34 ` Gerd Hoffmann
2015-05-13 19:12 ` [Qemu-devel] [PATCH 4/8] introduce dpcd module fred.konrad
` (4 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: fred.konrad @ 2015-05-13 19:12 UTC (permalink / raw)
To: qemu-devel
Cc: peter.crosthwaite, mark.burton, Gerd Hoffmann, hyunk, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This allows to create a surface with a different format than xrgb8888.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
---
include/ui/console.h | 2 ++
ui/console.c | 25 ++++++++++++++++++++++---
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/include/ui/console.h b/include/ui/console.h
index e8b3a9e..e816182 100644
--- a/include/ui/console.h
+++ b/include/ui/console.h
@@ -206,6 +206,8 @@ DisplaySurface *qemu_create_displaysurface_guestmem(int width, int height,
PixelFormat qemu_default_pixelformat(int bpp);
DisplaySurface *qemu_create_displaysurface(int width, int height);
+DisplaySurface *qemu_create_displaysurface_format(pixman_format_code_t format,
+ int width, int height);
void qemu_free_displaysurface(DisplaySurface *surface);
static inline int is_surface_bgr(DisplaySurface *surface)
diff --git a/ui/console.c b/ui/console.c
index 406c36b..5fc8473 100644
--- a/ui/console.c
+++ b/ui/console.c
@@ -1226,20 +1226,29 @@ static QemuConsole *new_console(DisplayState *ds, console_type_t console_type,
return s;
}
-static void qemu_alloc_display(DisplaySurface *surface, int width, int height)
+static void qemu_alloc_display_format(DisplaySurface *surface,
+ pixman_format_code_t format,
+ int width, int height)
{
qemu_pixman_image_unref(surface->image);
surface->image = NULL;
- surface->format = PIXMAN_x8r8g8b8;
+ surface->format = format;
surface->image = pixman_image_create_bits(surface->format,
width, height,
- NULL, width * 4);
+ NULL,
+ width * PIXMAN_FORMAT_BPP(format)
+ / 8);
assert(surface->image != NULL);
surface->flags = QEMU_ALLOCATED_FLAG;
}
+static void qemu_alloc_display(DisplaySurface *surface, int width, int height)
+{
+ qemu_alloc_display_format(surface, PIXMAN_x8r8g8b8, width, height);
+}
+
DisplaySurface *qemu_create_displaysurface(int width, int height)
{
DisplaySurface *surface = g_new0(DisplaySurface, 1);
@@ -1249,6 +1258,16 @@ DisplaySurface *qemu_create_displaysurface(int width, int height)
return surface;
}
+DisplaySurface *qemu_create_displaysurface_format(pixman_format_code_t format,
+ int width, int height)
+{
+ DisplaySurface *surface = g_new0(DisplaySurface, 1);
+
+ trace_displaysurface_create(surface, width, height);
+ qemu_alloc_display_format(surface, format, width, height);
+ return surface;
+}
+
DisplaySurface *qemu_create_displaysurface_from(int width, int height,
pixman_format_code_t format,
int linesize, uint8_t *data)
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 3/8] console: add qemu_alloc_display_format.
2015-05-13 19:12 ` [Qemu-devel] [PATCH 3/8] console: add qemu_alloc_display_format fred.konrad
@ 2015-05-18 7:34 ` Gerd Hoffmann
2015-05-18 7:51 ` Frederic Konrad
0 siblings, 1 reply; 20+ messages in thread
From: Gerd Hoffmann @ 2015-05-18 7:34 UTC (permalink / raw)
To: fred.konrad; +Cc: peter.crosthwaite, mark.burton, qemu-devel, hyunk
On Mi, 2015-05-13 at 21:12 +0200, fred.konrad@greensocs.com wrote:
> From: KONRAD Frederic <fred.konrad@greensocs.com>
>
> This allows to create a surface with a different format than xrgb8888.
What is the use case for this?
cheers,
Gerd
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH 3/8] console: add qemu_alloc_display_format.
2015-05-18 7:34 ` Gerd Hoffmann
@ 2015-05-18 7:51 ` Frederic Konrad
2015-05-18 11:17 ` Gerd Hoffmann
0 siblings, 1 reply; 20+ messages in thread
From: Frederic Konrad @ 2015-05-18 7:51 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: peter.crosthwaite, mark.burton, qemu-devel, hyunk
On 18/05/2015 09:34, Gerd Hoffmann wrote:
> On Mi, 2015-05-13 at 21:12 +0200, fred.konrad@greensocs.com wrote:
>> From: KONRAD Frederic <fred.konrad@greensocs.com>
>>
>> This allows to create a surface with a different format than xrgb8888.
> What is the use case for this?
>
> cheers,
> Gerd
>
>
>
Hi,
The Display Port introduced in patch 7 and the driver use differents
pixel format.
eg: rgb565, RGB888, etc. see xilinx_dp_change_graphic_fmt in patch 7:
+static void xilinx_dp_change_graphic_fmt(XilinxDPState *s)
+{
+ switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) {
+ case DP_GRAPHIC_RGBA8888:
+ s->planes[0].format = PIXMAN_r8g8b8a8;
+ break;
+ case DP_GRAPHIC_ABGR8888:
+ s->planes[0].format = PIXMAN_a8b8g8r8;
+ break;
+ case DP_GRAPHIC_RGB565:
+ s->planes[0].format = PIXMAN_r5g6b5;
+ break;
+ case DP_GRAPHIC_RGB888:
+ s->planes[0].format = PIXMAN_r8g8b8;
+ break;
+ case DP_GRAPHIC_BGR888:
+ s->planes[0].format = PIXMAN_b8g8r8;
+ break;
+ default:
+ DPRINTF("error: unsupported graphic format %u.\n",
+ s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
+ abort();
+ break;
+ }
+
+ switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) {
+ case 0:
+ s->planes[1].format = PIXMAN_r8g8b8a8;
+ break;
+ case DP_NL_VID_RGBA8880:
+ s->planes[1].format = PIXMAN_r8g8b8a8;
+ break;
+ default:
+ DPRINTF("error: unsupported video format %u.\n",
+ s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
+ abort();
+ break;
+ }
+
+ xilinx_dp_recreate_surface(s);
+}
It needs alpha blending of two planes as well. I do this work with pixman.
Thanks,
Fred
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 3/8] console: add qemu_alloc_display_format.
2015-05-18 7:51 ` Frederic Konrad
@ 2015-05-18 11:17 ` Gerd Hoffmann
2015-05-18 11:56 ` Frederic Konrad
0 siblings, 1 reply; 20+ messages in thread
From: Gerd Hoffmann @ 2015-05-18 11:17 UTC (permalink / raw)
To: Frederic Konrad; +Cc: peter.crosthwaite, mark.burton, qemu-devel, hyunk
On Mo, 2015-05-18 at 09:51 +0200, Frederic Konrad wrote:
> On 18/05/2015 09:34, Gerd Hoffmann wrote:
> > On Mi, 2015-05-13 at 21:12 +0200, fred.konrad@greensocs.com wrote:
> >> From: KONRAD Frederic <fred.konrad@greensocs.com>
> >>
> >> This allows to create a surface with a different format than xrgb8888.
> > What is the use case for this?
> >
> > cheers,
> > Gerd
> >
> >
> >
> Hi,
>
> The Display Port introduced in patch 7 and the driver use differents
> pixel format.
> eg: rgb565, RGB888, etc. see xilinx_dp_change_graphic_fmt in patch 7:
Ah, and dpdma scatterlists (patch 6) suggest the guest framebuffer is
not contiguous in guest phyiscal memory, correct? So using guest memory
as surface storage using qemu_create_displaysurface_from() doesn't work.
But I think you can simply call qemu_create_displaysurface_from() with
linesize=0 and data=NULL to make pixman allocate storage for you.
cheers,
Gerd
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Qemu-devel] [PATCH 3/8] console: add qemu_alloc_display_format.
2015-05-18 11:17 ` Gerd Hoffmann
@ 2015-05-18 11:56 ` Frederic Konrad
0 siblings, 0 replies; 20+ messages in thread
From: Frederic Konrad @ 2015-05-18 11:56 UTC (permalink / raw)
To: Gerd Hoffmann; +Cc: peter.crosthwaite, mark.burton, qemu-devel, hyunk
On 18/05/2015 13:17, Gerd Hoffmann wrote:
> On Mo, 2015-05-18 at 09:51 +0200, Frederic Konrad wrote:
>> On 18/05/2015 09:34, Gerd Hoffmann wrote:
>>> On Mi, 2015-05-13 at 21:12 +0200, fred.konrad@greensocs.com wrote:
>>>> From: KONRAD Frederic <fred.konrad@greensocs.com>
>>>>
>>>> This allows to create a surface with a different format than xrgb8888.
>>> What is the use case for this?
>>>
>>> cheers,
>>> Gerd
>>>
>>>
>>>
>> Hi,
>>
>> The Display Port introduced in patch 7 and the driver use differents
>> pixel format.
>> eg: rgb565, RGB888, etc. see xilinx_dp_change_graphic_fmt in patch 7:
> Ah, and dpdma scatterlists (patch 6) suggest the guest framebuffer is
> not contiguous in guest phyiscal memory, correct? So using guest memory
> as surface storage using qemu_create_displaysurface_from() doesn't work.
Exactly, the framebuffer is not necessarilly contiguous, so I need to
put the
fragment into the pixman storage.
> But I think you can simply call qemu_create_displaysurface_from() with
> linesize=0 and data=NULL to make pixman allocate storage for you.
Ah, maybe! I'll check that.
Thanks,
Fred
> cheers,
> Gerd
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 4/8] introduce dpcd module.
2015-05-13 19:11 [Qemu-devel] [PATCH 0/8] Xilinx DisplayPort fred.konrad
` (2 preceding siblings ...)
2015-05-13 19:12 ` [Qemu-devel] [PATCH 3/8] console: add qemu_alloc_display_format fred.konrad
@ 2015-05-13 19:12 ` fred.konrad
2015-05-14 4:10 ` Peter Crosthwaite
2015-05-13 19:12 ` [Qemu-devel] [PATCH 5/8] hw/i2c-ddc.c: Implement DDC I2C slave fred.konrad
` (3 subsequent siblings)
7 siblings, 1 reply; 20+ messages in thread
From: fred.konrad @ 2015-05-13 19:12 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.crosthwaite, mark.burton, hyunk, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This introduces a DPCD modules. It wires on a aux-bus and can be accessed by
driver to get lane-speed, etc.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/display/Makefile.objs | 1 +
hw/display/dpcd.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++
hw/display/dpcd.h | 72 ++++++++++++++++++++++++
3 files changed, 212 insertions(+)
create mode 100644 hw/display/dpcd.c
create mode 100644 hw/display/dpcd.h
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index 3ea106d..f746cec 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -34,3 +34,4 @@ obj-$(CONFIG_CG3) += cg3.o
obj-$(CONFIG_VGA) += vga.o
common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o
+common-obj-y += dpcd.o
diff --git a/hw/display/dpcd.c b/hw/display/dpcd.c
new file mode 100644
index 0000000..757b65e
--- /dev/null
+++ b/hw/display/dpcd.c
@@ -0,0 +1,139 @@
+/*
+ * dpcd.c
+ *
+ * Copyright (C)2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/*
+ * This is a simple AUX slave which emulate a screen connected.
+ */
+
+#include "hw/aux.h"
+#include "dpcd.h"
+
+/* #define DEBUG_DPCD */
+#ifdef DEBUG_DPCD
+#define DPRINTF(fmt, ...) do { printf("dpcd: "fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
+struct DPCDState {
+ AUXSlave parent_obj;
+
+ size_t current_reg;
+ /*
+ * The DCPD is 0x7FFFF length but read as 0 after offset 0x600.
+ */
+ uint8_t dpcd_info[0x600];
+
+ MemoryRegion iomem;
+};
+
+static void dpcd_realize(DeviceState *dev, Error **errp)
+{
+
+}
+
+static uint64_t aux_read(void *opaque, hwaddr offset, unsigned size)
+{
+ uint64_t ret;
+ DPCDState *e = DPCD(opaque);
+ assert(size == 1);
+
+ if (offset <= 0x600) {
+ ret = e->dpcd_info[offset];
+ } else {
+ ret = 0;
+ }
+
+ DPRINTF("read %u @0x%8.8lX\n", (uint8_t)ret, offset);
+ return ret;
+}
+
+static void aux_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ DPCDState *e = DPCD(opaque);
+ assert(size == 1);
+
+ DPRINTF("write %u @0x%8.8lX\n", (uint8_t)value, offset);
+
+ if (offset <= 0x600) {
+ e->dpcd_info[offset] = value;
+ }
+}
+
+static const MemoryRegionOps aux_ops = {
+ .read = aux_read,
+ .write = aux_write
+};
+
+static void aux_edid_init(Object *obj)
+{
+ /*
+ * Create a default DPCD..
+ */
+ DPCDState *s = DPCD(obj);
+
+ memset(&(s->dpcd_info), 0, sizeof(s->dpcd_info));
+
+ s->current_reg = 0;
+
+ s->dpcd_info[0x00] = DPCD_REV_1_0;
+ s->dpcd_info[0x01] = DPCD_5_4GBPS;
+ s->dpcd_info[0x02] = 0x1;
+ s->dpcd_info[0x08] = DPCD_EDID_PRESENT;
+ s->dpcd_info[0x09] = 0xFF;
+
+ /* CR DONE, CE DONE, SYMBOL LOCKED.. */
+ s->dpcd_info[0x202] = 0x07;
+ /* INTERLANE_ALIGN_DONE.. */
+ s->dpcd_info[0x204] = 0x01;
+ s->dpcd_info[0x205] = 0x01;
+
+ /*
+ * Create the address-map.
+ */
+ memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x7FFFF);
+ aux_init_mmio(AUX_SLAVE(obj), &s->iomem);
+}
+
+static void aux_edid_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ dc->realize = dpcd_realize;
+}
+
+static const TypeInfo aux_edid_info = {
+ .name = TYPE_DPCD,
+ .parent = TYPE_AUX_SLAVE,
+ .instance_size = sizeof(DPCDState),
+ .instance_init = aux_edid_init,
+ .class_init = aux_edid_class_init,
+};
+
+static void aux_edid_register_types(void)
+{
+ type_register_static(&aux_edid_info);
+}
+
+type_init(aux_edid_register_types)
diff --git a/hw/display/dpcd.h b/hw/display/dpcd.h
new file mode 100644
index 0000000..cd22258
--- /dev/null
+++ b/hw/display/dpcd.h
@@ -0,0 +1,72 @@
+/*
+ * dpcd.h
+ *
+ * Copyright (C)2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef DPCD_H
+#define DPCD_H
+
+typedef struct DPCDState DPCDState;
+
+#define TYPE_DPCD "dpcd"
+#define DPCD(obj) OBJECT_CHECK(DPCDState, (obj), TYPE_DPCD)
+
+/* DCPD Revision. */
+#define DPCD_REV_1_0 0x10
+#define DPCD_REV_1_1 0x11
+
+/* DCPD Max Link Rate. */
+#define DPCD_1_62GBPS 0x06
+#define DPCD_2_7GBPS 0x0A
+#define DPCD_5_4GBPS 0x14
+
+/* DCPD Max down spread. */
+#define DPCD_UP_TO_0_5 0x01
+#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAINING 0x40
+
+/* DCPD Downstream port type. */
+#define DPCD_DISPLAY_PORT 0x00
+#define DPCD_ANALOG 0x02
+#define DPCD_DVI_HDMI 0x04
+#define DPCD_OTHER 0x06
+
+/* DPCD Format conversion. */
+#define DPCD_FORMAT_CONVERSION 0x08
+
+/* Main link channel coding. */
+#define DPCD_ANSI_8B_10B 0x01
+
+/* Down stream port count. */
+#define DPCD_OUI_SUPPORTED 0x80
+
+/* Receiver port capability. */
+#define DPCD_EDID_PRESENT 0x02
+#define DPCD_ASSOCIATED_TO_PRECEDING_PORT 0x04
+
+/* Down stream port capability. */
+#define DPCD_CAP_DISPLAY_PORT 0x000
+#define DPCD_CAP_ANALOG_VGA 0x001
+#define DPCD_CAP_DVI 0x002
+#define DPCD_CAP_HDMI 0x003
+#define DPCD_CAP_OTHER 0x100
+
+#endif /* !DPCD_H */
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 4/8] introduce dpcd module.
2015-05-13 19:12 ` [Qemu-devel] [PATCH 4/8] introduce dpcd module fred.konrad
@ 2015-05-14 4:10 ` Peter Crosthwaite
2015-05-18 13:57 ` Frederic Konrad
0 siblings, 1 reply; 20+ messages in thread
From: Peter Crosthwaite @ 2015-05-14 4:10 UTC (permalink / raw)
To: Fréderic Konrad; +Cc: Mark Burton, qemu-devel@nongnu.org Developers, hyunk
On Wed, May 13, 2015 at 12:12 PM, <fred.konrad@greensocs.com> wrote:
> From: KONRAD Frederic <fred.konrad@greensocs.com>
>
> This introduces a DPCD modules. It wires on a aux-bus and can be accessed by
> driver to get lane-speed, etc.
>
> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
> ---
> hw/display/Makefile.objs | 1 +
> hw/display/dpcd.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++
> hw/display/dpcd.h | 72 ++++++++++++++++++++++++
> 3 files changed, 212 insertions(+)
> create mode 100644 hw/display/dpcd.c
> create mode 100644 hw/display/dpcd.h
>
> diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
> index 3ea106d..f746cec 100644
> --- a/hw/display/Makefile.objs
> +++ b/hw/display/Makefile.objs
> @@ -34,3 +34,4 @@ obj-$(CONFIG_CG3) += cg3.o
> obj-$(CONFIG_VGA) += vga.o
>
> common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o
> +common-obj-y += dpcd.o
> diff --git a/hw/display/dpcd.c b/hw/display/dpcd.c
> new file mode 100644
> index 0000000..757b65e
> --- /dev/null
> +++ b/hw/display/dpcd.c
> @@ -0,0 +1,139 @@
> +/*
> + * dpcd.c
> + *
> + * Copyright (C)2015 : GreenSocs Ltd
> + * http://www.greensocs.com/ , email: info@greensocs.com
> + *
> + * Developed by :
> + * Frederic Konrad <fred.konrad@greensocs.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option)any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +/*
> + * This is a simple AUX slave which emulate a screen connected.
> + */
emulates a connected screen.
> +
> +#include "hw/aux.h"
> +#include "dpcd.h"
> +
> +/* #define DEBUG_DPCD */
> +#ifdef DEBUG_DPCD
> +#define DPRINTF(fmt, ...) do { printf("dpcd: "fmt , ## __VA_ARGS__); } while (0)
> +#else
> +#define DPRINTF(fmt, ...) do {} while (0)
> +#endif
> +
Same comment as before about debug stuffs.
> +struct DPCDState {
> + AUXSlave parent_obj;
> +
> + size_t current_reg;
What the actual size of the bus? This should be a fixed width type to match.
> + /*
> + * The DCPD is 0x7FFFF length but read as 0 after offset 0x600.
> + */
> + uint8_t dpcd_info[0x600];
> +
> + MemoryRegion iomem;
> +};
> +
> +static void dpcd_realize(DeviceState *dev, Error **errp)
> +{
> +
> +}
Blank realize not needed. Just leave the hook unset.
> +
> +static uint64_t aux_read(void *opaque, hwaddr offset, unsigned size)
The fn name should match the name of the bus and not the attached dev.
> +{
> + uint64_t ret;
> + DPCDState *e = DPCD(opaque);
> + assert(size == 1);
Is this a limitation of aux or the device? In the former, I would just
delete assertion. For the later it should be a GUEST_ERROR or UNIMP.
> +
> + if (offset <= 0x600) {
> + ret = e->dpcd_info[offset];
> + } else {
> + ret = 0;
GUEST_ERROR?
> + }
> +
> + DPRINTF("read %u @0x%8.8lX\n", (uint8_t)ret, offset);
> + return ret;
> +}
> +
> +static void aux_write(void *opaque, hwaddr offset, uint64_t value,
> + unsigned size)
> +{
> + DPCDState *e = DPCD(opaque);
> + assert(size == 1);
> +
> + DPRINTF("write %u @0x%8.8lX\n", (uint8_t)value, offset);
> +
> + if (offset <= 0x600) {
> + e->dpcd_info[offset] = value;
> + }
> +}
> +
> +static const MemoryRegionOps aux_ops = {
> + .read = aux_read,
> + .write = aux_write
Chould you set your access width restrictions here instead of the assert?
> +};
> +
> +static void aux_edid_init(Object *obj)
> +{
> + /*
> + * Create a default DPCD..
> + */
> + DPCDState *s = DPCD(obj);
> +
> + memset(&(s->dpcd_info), 0, sizeof(s->dpcd_info));
> +
> + s->current_reg = 0;
> +
> + s->dpcd_info[0x00] = DPCD_REV_1_0;
> + s->dpcd_info[0x01] = DPCD_5_4GBPS;
> + s->dpcd_info[0x02] = 0x1;
> + s->dpcd_info[0x08] = DPCD_EDID_PRESENT;
> + s->dpcd_info[0x09] = 0xFF;
> +
> + /* CR DONE, CE DONE, SYMBOL LOCKED.. */
> + s->dpcd_info[0x202] = 0x07;
> + /* INTERLANE_ALIGN_DONE.. */
> + s->dpcd_info[0x204] = 0x01;
> + s->dpcd_info[0x205] = 0x01;
> +
State setup should be handled by a reset callback.
> + /*
> + * Create the address-map.
> + */
> + memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x7FFFF);
> + aux_init_mmio(AUX_SLAVE(obj), &s->iomem);
> +}
> +
> +static void aux_edid_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> + dc->realize = dpcd_realize;
reset and vmsd hooks needed.
> +}
> +
> +static const TypeInfo aux_edid_info = {
> + .name = TYPE_DPCD,
> + .parent = TYPE_AUX_SLAVE,
> + .instance_size = sizeof(DPCDState),
> + .instance_init = aux_edid_init,
> + .class_init = aux_edid_class_init,
> +};
> +
> +static void aux_edid_register_types(void)
> +{
> + type_register_static(&aux_edid_info);
> +}
> +
> +type_init(aux_edid_register_types)
> diff --git a/hw/display/dpcd.h b/hw/display/dpcd.h
> new file mode 100644
> index 0000000..cd22258
> --- /dev/null
> +++ b/hw/display/dpcd.h
> @@ -0,0 +1,72 @@
> +/*
> + * dpcd.h
> + *
> + * Copyright (C)2015 : GreenSocs Ltd
> + * http://www.greensocs.com/ , email: info@greensocs.com
> + *
> + * Developed by :
> + * Frederic Konrad <fred.konrad@greensocs.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option)any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#ifndef DPCD_H
> +#define DPCD_H
> +
> +typedef struct DPCDState DPCDState;
> +
> +#define TYPE_DPCD "dpcd"
> +#define DPCD(obj) OBJECT_CHECK(DPCDState, (obj), TYPE_DPCD)
> +
> +/* DCPD Revision. */
> +#define DPCD_REV_1_0 0x10
> +#define DPCD_REV_1_1 0x11
> +
> +/* DCPD Max Link Rate. */
> +#define DPCD_1_62GBPS 0x06
> +#define DPCD_2_7GBPS 0x0A
> +#define DPCD_5_4GBPS 0x14
> +
> +/* DCPD Max down spread. */
> +#define DPCD_UP_TO_0_5 0x01
> +#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAINING 0x40
> +
> +/* DCPD Downstream port type. */
> +#define DPCD_DISPLAY_PORT 0x00
> +#define DPCD_ANALOG 0x02
> +#define DPCD_DVI_HDMI 0x04
> +#define DPCD_OTHER 0x06
> +
Tab constants out to consistent tab stop for readability.
Regards,
Peter
> +/* DPCD Format conversion. */
> +#define DPCD_FORMAT_CONVERSION 0x08
> +
> +/* Main link channel coding. */
> +#define DPCD_ANSI_8B_10B 0x01
> +
> +/* Down stream port count. */
> +#define DPCD_OUI_SUPPORTED 0x80
> +
> +/* Receiver port capability. */
> +#define DPCD_EDID_PRESENT 0x02
> +#define DPCD_ASSOCIATED_TO_PRECEDING_PORT 0x04
> +
> +/* Down stream port capability. */
> +#define DPCD_CAP_DISPLAY_PORT 0x000
> +#define DPCD_CAP_ANALOG_VGA 0x001
> +#define DPCD_CAP_DVI 0x002
> +#define DPCD_CAP_HDMI 0x003
> +#define DPCD_CAP_OTHER 0x100
> +
> +#endif /* !DPCD_H */
> --
> 1.9.0
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 4/8] introduce dpcd module.
2015-05-14 4:10 ` Peter Crosthwaite
@ 2015-05-18 13:57 ` Frederic Konrad
0 siblings, 0 replies; 20+ messages in thread
From: Frederic Konrad @ 2015-05-18 13:57 UTC (permalink / raw)
To: Peter Crosthwaite; +Cc: Mark Burton, qemu-devel@nongnu.org Developers, hyunk
On 14/05/2015 06:10, Peter Crosthwaite wrote:
> On Wed, May 13, 2015 at 12:12 PM, <fred.konrad@greensocs.com> wrote:
>> From: KONRAD Frederic <fred.konrad@greensocs.com>
>>
>> This introduces a DPCD modules. It wires on a aux-bus and can be accessed by
>> driver to get lane-speed, etc.
>>
>> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
>> ---
>> hw/display/Makefile.objs | 1 +
>> hw/display/dpcd.c | 139 +++++++++++++++++++++++++++++++++++++++++++++++
>> hw/display/dpcd.h | 72 ++++++++++++++++++++++++
>> 3 files changed, 212 insertions(+)
>> create mode 100644 hw/display/dpcd.c
>> create mode 100644 hw/display/dpcd.h
>>
>> diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
>> index 3ea106d..f746cec 100644
>> --- a/hw/display/Makefile.objs
>> +++ b/hw/display/Makefile.objs
>> @@ -34,3 +34,4 @@ obj-$(CONFIG_CG3) += cg3.o
>> obj-$(CONFIG_VGA) += vga.o
>>
>> common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o
>> +common-obj-y += dpcd.o
>> diff --git a/hw/display/dpcd.c b/hw/display/dpcd.c
>> new file mode 100644
>> index 0000000..757b65e
>> --- /dev/null
>> +++ b/hw/display/dpcd.c
>> @@ -0,0 +1,139 @@
>> +/*
>> + * dpcd.c
>> + *
>> + * Copyright (C)2015 : GreenSocs Ltd
>> + * http://www.greensocs.com/ , email: info@greensocs.com
>> + *
>> + * Developed by :
>> + * Frederic Konrad <fred.konrad@greensocs.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation, either version 2 of the License, or
>> + * (at your option)any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +/*
>> + * This is a simple AUX slave which emulate a screen connected.
>> + */
> emulates a connected screen.
>
>> +
>> +#include "hw/aux.h"
>> +#include "dpcd.h"
>> +
>> +/* #define DEBUG_DPCD */
>> +#ifdef DEBUG_DPCD
>> +#define DPRINTF(fmt, ...) do { printf("dpcd: "fmt , ## __VA_ARGS__); } while (0)
>> +#else
>> +#define DPRINTF(fmt, ...) do {} while (0)
>> +#endif
>> +
> Same comment as before about debug stuffs.
>
>> +struct DPCDState {
>> + AUXSlave parent_obj;
>> +
>> + size_t current_reg;
> What the actual size of the bus? This should be a fixed width type to match.
Actually this is a mistake and is unused, so I just drop it.
>
>> + /*
>> + * The DCPD is 0x7FFFF length but read as 0 after offset 0x600.
>> + */
>> + uint8_t dpcd_info[0x600];
>> +
>> + MemoryRegion iomem;
>> +};
>> +
>> +static void dpcd_realize(DeviceState *dev, Error **errp)
>> +{
>> +
>> +}
> Blank realize not needed. Just leave the hook unset.
Ok makes sense.
>
>> +
>> +static uint64_t aux_read(void *opaque, hwaddr offset, unsigned size)
> The fn name should match the name of the bus and not the attached dev.
I guess you mean the opposite :).
>> +{
>> + uint64_t ret;
>> + DPCDState *e = DPCD(opaque);
>> + assert(size == 1);
> Is this a limitation of aux or the device? In the former, I would just
> delete assertion. For the later it should be a GUEST_ERROR or UNIMP.
>
>> +
>> + if (offset <= 0x600) {
>> + ret = e->dpcd_info[offset];
>> + } else {
>> + ret = 0;
> GUEST_ERROR?
Actually I think it's fine like that. The region size is 0x80000 the
first 0x600 are
used, the rest is read as zero.
>
>> + }
>> +
>> + DPRINTF("read %u @0x%8.8lX\n", (uint8_t)ret, offset);
>> + return ret;
>> +}
>> +
>> +static void aux_write(void *opaque, hwaddr offset, uint64_t value,
>> + unsigned size)
>> +{
>> + DPCDState *e = DPCD(opaque);
>> + assert(size == 1);
>> +
>> + DPRINTF("write %u @0x%8.8lX\n", (uint8_t)value, offset);
>> +
>> + if (offset <= 0x600) {
>> + e->dpcd_info[offset] = value;
>> + }
>> +}
>> +
>> +static const MemoryRegionOps aux_ops = {
>> + .read = aux_read,
>> + .write = aux_write
> Chould you set your access width restrictions here instead of the assert?
Yes, I do that.
>
>> +};
>> +
>> +static void aux_edid_init(Object *obj)
>> +{
>> + /*
>> + * Create a default DPCD..
>> + */
>> + DPCDState *s = DPCD(obj);
>> +
>> + memset(&(s->dpcd_info), 0, sizeof(s->dpcd_info));
>> +
>> + s->current_reg = 0;
>> +
>> + s->dpcd_info[0x00] = DPCD_REV_1_0;
>> + s->dpcd_info[0x01] = DPCD_5_4GBPS;
>> + s->dpcd_info[0x02] = 0x1;
>> + s->dpcd_info[0x08] = DPCD_EDID_PRESENT;
>> + s->dpcd_info[0x09] = 0xFF;
>> +
>> + /* CR DONE, CE DONE, SYMBOL LOCKED.. */
>> + s->dpcd_info[0x202] = 0x07;
>> + /* INTERLANE_ALIGN_DONE.. */
>> + s->dpcd_info[0x204] = 0x01;
>> + s->dpcd_info[0x205] = 0x01;
>> +
> State setup should be handled by a reset callback.
>
>> + /*
>> + * Create the address-map.
>> + */
>> + memory_region_init_io(&s->iomem, obj, &aux_ops, s, TYPE_DPCD, 0x7FFFF);
>> + aux_init_mmio(AUX_SLAVE(obj), &s->iomem);
>> +}
>> +
>> +static void aux_edid_class_init(ObjectClass *oc, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(oc);
>> + dc->realize = dpcd_realize;
> reset and vmsd hooks needed.
>
>> +}
>> +
>> +static const TypeInfo aux_edid_info = {
>> + .name = TYPE_DPCD,
>> + .parent = TYPE_AUX_SLAVE,
>> + .instance_size = sizeof(DPCDState),
>> + .instance_init = aux_edid_init,
>> + .class_init = aux_edid_class_init,
>> +};
>> +
>> +static void aux_edid_register_types(void)
>> +{
>> + type_register_static(&aux_edid_info);
>> +}
>> +
>> +type_init(aux_edid_register_types)
>> diff --git a/hw/display/dpcd.h b/hw/display/dpcd.h
>> new file mode 100644
>> index 0000000..cd22258
>> --- /dev/null
>> +++ b/hw/display/dpcd.h
>> @@ -0,0 +1,72 @@
>> +/*
>> + * dpcd.h
>> + *
>> + * Copyright (C)2015 : GreenSocs Ltd
>> + * http://www.greensocs.com/ , email: info@greensocs.com
>> + *
>> + * Developed by :
>> + * Frederic Konrad <fred.konrad@greensocs.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation, either version 2 of the License, or
>> + * (at your option)any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +#ifndef DPCD_H
>> +#define DPCD_H
>> +
>> +typedef struct DPCDState DPCDState;
>> +
>> +#define TYPE_DPCD "dpcd"
>> +#define DPCD(obj) OBJECT_CHECK(DPCDState, (obj), TYPE_DPCD)
>> +
>> +/* DCPD Revision. */
>> +#define DPCD_REV_1_0 0x10
>> +#define DPCD_REV_1_1 0x11
>> +
>> +/* DCPD Max Link Rate. */
>> +#define DPCD_1_62GBPS 0x06
>> +#define DPCD_2_7GBPS 0x0A
>> +#define DPCD_5_4GBPS 0x14
>> +
>> +/* DCPD Max down spread. */
>> +#define DPCD_UP_TO_0_5 0x01
>> +#define DPCD_NO_AUX_HANDSHAKE_LINK_TRAINING 0x40
>> +
>> +/* DCPD Downstream port type. */
>> +#define DPCD_DISPLAY_PORT 0x00
>> +#define DPCD_ANALOG 0x02
>> +#define DPCD_DVI_HDMI 0x04
>> +#define DPCD_OTHER 0x06
>> +
> Tab constants out to consistent tab stop for readability.
>
> Regards,
> Peter
>
>> +/* DPCD Format conversion. */
>> +#define DPCD_FORMAT_CONVERSION 0x08
>> +
>> +/* Main link channel coding. */
>> +#define DPCD_ANSI_8B_10B 0x01
>> +
>> +/* Down stream port count. */
>> +#define DPCD_OUI_SUPPORTED 0x80
>> +
>> +/* Receiver port capability. */
>> +#define DPCD_EDID_PRESENT 0x02
>> +#define DPCD_ASSOCIATED_TO_PRECEDING_PORT 0x04
>> +
>> +/* Down stream port capability. */
>> +#define DPCD_CAP_DISPLAY_PORT 0x000
>> +#define DPCD_CAP_ANALOG_VGA 0x001
>> +#define DPCD_CAP_DVI 0x002
>> +#define DPCD_CAP_HDMI 0x003
>> +#define DPCD_CAP_OTHER 0x100
>> +
>> +#endif /* !DPCD_H */
>> --
>> 1.9.0
>>
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 5/8] hw/i2c-ddc.c: Implement DDC I2C slave
2015-05-13 19:11 [Qemu-devel] [PATCH 0/8] Xilinx DisplayPort fred.konrad
` (3 preceding siblings ...)
2015-05-13 19:12 ` [Qemu-devel] [PATCH 4/8] introduce dpcd module fred.konrad
@ 2015-05-13 19:12 ` fred.konrad
2015-05-13 19:12 ` [Qemu-devel] [PATCH 6/8] Introduce xilinx dpdma fred.konrad
` (2 subsequent siblings)
7 siblings, 0 replies; 20+ messages in thread
From: fred.konrad @ 2015-05-13 19:12 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, peter.crosthwaite, mark.burton, hyunk, fred.konrad
From: Peter Maydell <peter.maydell@linaro.org>
Implement an I2C slave which implements DDC and returns the
EDID data for an attached monitor.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
- Rebased on the current master.
- Modified for QOM.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/i2c/Makefile.objs | 2 +-
hw/i2c/i2c-ddc.c | 288 +++++++++++++++++++++++++++++++++++++++++++++++++++
hw/i2c/i2c-ddc.h | 34 ++++++
3 files changed, 323 insertions(+), 1 deletion(-)
create mode 100644 hw/i2c/i2c-ddc.c
create mode 100644 hw/i2c/i2c-ddc.h
diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs
index 648278e..7399b00 100644
--- a/hw/i2c/Makefile.objs
+++ b/hw/i2c/Makefile.objs
@@ -1,4 +1,4 @@
-common-obj-y += core.o smbus.o smbus_eeprom.o
+common-obj-y += core.o smbus.o smbus_eeprom.o i2c-ddc.o
common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
common-obj-$(CONFIG_ACPI) += smbus_ich9.o
common-obj-$(CONFIG_APM) += pm_smbus.o
diff --git a/hw/i2c/i2c-ddc.c b/hw/i2c/i2c-ddc.c
new file mode 100644
index 0000000..71b303c
--- /dev/null
+++ b/hw/i2c/i2c-ddc.c
@@ -0,0 +1,288 @@
+/* A simple I2C slave for returning monitor EDID data via DDC.
+ *
+ * Copyright (c) 2011 Linaro Limited
+ * Written by Peter Maydell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "hw/i2c/i2c.h"
+#include "i2c-ddc.h"
+
+/* #define DEBUG_I2CDDC */
+#ifdef DEBUG_I2CDDC
+#define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
+#else
+#define DPRINTF(fmt, ...) do {} while (0)
+#endif
+
+/* Structure defining a monitor's characteristics in a
+ * readable format: this should be passed to build_edid_blob()
+ * to convert it into the 128 byte binary EDID blob.
+ * Not all bits of the EDID are customisable here.
+ */
+typedef struct {
+ char manuf_id[3]; /* three upper case letters */
+ uint16_t product_id;
+ uint32_t serial_no;
+ uint8_t manuf_week;
+ int manuf_year;
+ uint8_t h_cm;
+ uint8_t v_cm;
+ uint8_t gamma;
+ char monitor_name[14];
+ char serial_no_string[14];
+ /* Range limits */
+ uint8_t vmin; /* Hz */
+ uint8_t vmax; /* Hz */
+ uint8_t hmin; /* kHz */
+ uint8_t hmax; /* kHz */
+ uint8_t pixclock; /* MHz / 10 */
+ uint8_t timing_data[18];
+} edid_data;
+
+/* EDID data for a simple LCD monitor */
+static const edid_data lcd_edid = {
+ /* The manuf_id ought really to be an assigned EISA ID */
+ .manuf_id = "QMU",
+ .product_id = 0,
+ .serial_no = 1,
+ .manuf_week = 1,
+ .manuf_year = 2011,
+ .h_cm = 40,
+ .v_cm = 30,
+ .gamma = 0x78,
+ .monitor_name = "QEMU monitor",
+ .serial_no_string = "1",
+ .vmin = 40,
+ .vmax = 120,
+ .hmin = 30,
+ .hmax = 100,
+ .pixclock = 18,
+ .timing_data = {
+ /* Borrowed from a 21" LCD */
+ 0x48, 0x3f, 0x40, 0x30, 0x62, 0xb0, 0x32, 0x40, 0x40,
+ 0xc0, 0x13, 0x00, 0x98, 0x32, 0x11, 0x00, 0x00, 0x1e
+ }
+};
+
+static uint8_t manuf_char_to_int(char c)
+{
+ return (c - 'A') & 0x1f;
+}
+
+static void write_ascii_descriptor_block(uint8_t *descblob, uint8_t blocktype,
+ const char *string)
+{
+ /* Write an EDID Descriptor Block of the "ascii string" type */
+ int i;
+ descblob[0] = descblob[1] = descblob[2] = descblob[4] = 0;
+ descblob[3] = blocktype;
+ /* The rest is 13 bytes of ASCII; if less then the rest must
+ * be filled with newline then spaces
+ */
+ for (i = 5; i < 19; i++) {
+ descblob[i] = string[i - 5];
+ if (!descblob[i]) {
+ break;
+ }
+ }
+ if (i < 19) {
+ descblob[i++] = '\n';
+ }
+ for ( ; i < 19; i++) {
+ descblob[i] = ' ';
+ }
+}
+
+static void write_range_limits_descriptor(const edid_data *edid,
+ uint8_t *descblob)
+{
+ int i;
+ descblob[0] = descblob[1] = descblob[2] = descblob[4] = 0;
+ descblob[3] = 0xfd;
+ descblob[5] = edid->vmin;
+ descblob[6] = edid->vmax;
+ descblob[7] = edid->hmin;
+ descblob[8] = edid->hmax;
+ descblob[9] = edid->pixclock;
+ descblob[10] = 0;
+ descblob[11] = 0xa;
+ for (i = 12; i < 19; i++) {
+ descblob[i] = 0x20;
+ }
+}
+
+static void build_edid_blob(const edid_data *edid, uint8_t *blob)
+{
+ /* Write an EDID 1.3 format blob (128 bytes) based
+ * on the edid_data structure.
+ */
+ int i;
+ uint8_t cksum;
+
+ /* 00-07 : header */
+ blob[0] = blob[7] = 0;
+ for (i = 1 ; i < 7; i++) {
+ blob[i] = 0xff;
+ }
+ /* 08-09 : manufacturer ID */
+ blob[8] = (manuf_char_to_int(edid->manuf_id[0]) << 2)
+ | (manuf_char_to_int(edid->manuf_id[1]) >> 3);
+ blob[9] = (manuf_char_to_int(edid->manuf_id[1]) << 5)
+ | manuf_char_to_int(edid->manuf_id[2]);
+ /* 10-11 : product ID code */
+ blob[10] = edid->product_id;
+ blob[11] = edid->product_id >> 8;
+ blob[12] = edid->serial_no;
+ blob[13] = edid->serial_no >> 8;
+ blob[14] = edid->serial_no >> 16;
+ blob[15] = edid->serial_no >> 24;
+ /* 16 : week of manufacture */
+ blob[16] = edid->manuf_week;
+ /* 17 : year of manufacture - 1990 */
+ blob[17] = edid->manuf_year - 1990;
+ /* 18, 19 : EDID version and revision */
+ blob[18] = 1;
+ blob[19] = 3;
+ /* 20 - 24 : basic display parameters */
+ /* We are always a digital display */
+ blob[20] = 0x80;
+ /* 21, 22 : max h/v size in cm */
+ blob[21] = edid->h_cm;
+ blob[22] = edid->v_cm;
+ /* 23 : gamma (divide by 100 then add 1 for actual value) */
+ blob[23] = edid->gamma;
+ /* 24 feature support: no power management, RGB, preferred timing mode,
+ * standard colour space
+ */
+ blob[24] = 0x0e;
+ /* 25 - 34 : chromaticity coordinates. These are the
+ * standard sRGB chromaticity values
+ */
+ blob[25] = 0xee;
+ blob[26] = 0x91;
+ blob[27] = 0xa3;
+ blob[28] = 0x54;
+ blob[29] = 0x4c;
+ blob[30] = 0x99;
+ blob[31] = 0x26;
+ blob[32] = 0x0f;
+ blob[33] = 0x50;
+ blob[34] = 0x54;
+ /* 35, 36 : Established timings: claim to support everything */
+ blob[35] = blob[36] = 0xff;
+ /* 37 : manufacturer's reserved timing: none */
+ blob[37] = 0;
+ /* 38 - 53 : standard timing identification
+ * don't claim anything beyond what the 'established timings'
+ * already provide. Unused slots must be (0x1, 0x1)
+ */
+ for (i = 38; i < 54; i++) {
+ blob[i] = 0x1;
+ }
+ /* 54 - 71 : descriptor block 1 : must be preferred timing data */
+ memcpy(blob + 54, edid->timing_data, 18);
+ /* 72 - 89, 90 - 107, 108 - 125 : descriptor block 2, 3, 4
+ * Order not important, but we must have a monitor name and a
+ * range limits descriptor.
+ */
+ write_range_limits_descriptor(edid, blob + 72);
+ write_ascii_descriptor_block(blob + 90, 0xfc, edid->monitor_name);
+ write_ascii_descriptor_block(blob + 108, 0xff, edid->serial_no_string);
+
+ /* 126 : extension flag */
+ blob[126] = 0;
+
+ cksum = 0;
+ DPRINTF("EDID blob:");
+ for (i = 0; i < 127; i++) {
+ cksum += blob[i];
+ DPRINTF("%c0x%02x,", i % 8 ? ' ' : '\n', blob[i]);
+ }
+ /* 127 : checksum */
+ blob[127] = -cksum;
+ DPRINTF(" 0x%02x\n", blob[127]);
+}
+
+static void i2c_ddc_reset(DeviceState *ds)
+{
+ I2CDDCState *s = I2CDDC(ds);
+ s->firstbyte = 0;
+ s->reg = 0;
+}
+
+static void i2c_ddc_event(I2CSlave *i2c, enum i2c_event event)
+{
+ I2CDDCState *s = I2CDDC(i2c);
+ if (event == I2C_START_SEND) {
+ s->firstbyte = 1;
+ }
+}
+
+static int i2c_ddc_rx(I2CSlave *i2c)
+{
+ I2CDDCState *s = I2CDDC(i2c);
+
+ int value;
+ value = s->edid_blob[s->reg];
+
+ s->reg++;
+ return value;
+}
+
+static int i2c_ddc_tx(I2CSlave *i2c, uint8_t data)
+{
+ I2CDDCState *s = I2CDDC(i2c);
+ if (s->firstbyte) {
+ s->reg = data;
+ s->firstbyte = 0;
+ DPRINTF("[EDID] Written new pointer: %u\n", data);
+ return 1;
+ }
+
+ /* Ignore all writes */
+ s->reg++;
+ return 1;
+}
+
+static void i2c_ddc_init(Object *obj)
+{
+ I2CDDCState *s = I2CDDC(obj);
+ build_edid_blob(&lcd_edid, s->edid_blob);
+}
+
+static void i2c_ddc_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ I2CSlaveClass *klass = I2C_SLAVE_CLASS(oc);
+
+ dc->reset = i2c_ddc_reset;
+ klass->event = i2c_ddc_event;
+ klass->recv = i2c_ddc_rx;
+ klass->send = i2c_ddc_tx;
+}
+
+static TypeInfo i2c_ddc_info = {
+ .name = TYPE_I2CDDC,
+ .parent = TYPE_I2C_SLAVE,
+ .instance_size = sizeof(I2CDDCState),
+ .instance_init = i2c_ddc_init,
+ .class_init = i2c_ddc_class_init
+};
+
+static void ddc_register_devices(void)
+{
+ type_register_static(&i2c_ddc_info);
+}
+
+type_init(ddc_register_devices);
diff --git a/hw/i2c/i2c-ddc.h b/hw/i2c/i2c-ddc.h
new file mode 100644
index 0000000..fdf802e
--- /dev/null
+++ b/hw/i2c/i2c-ddc.h
@@ -0,0 +1,34 @@
+/* A simple I2C slave for returning monitor EDID data via DDC.
+ *
+ * Copyright (c) 2011 Linaro Limited
+ * Written by Peter Maydell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef I2C_DDC
+#define I2C_DDC
+
+/* A simple I2C slave which just returns the contents of its EDID blob. */
+
+typedef struct I2CDDCState {
+ I2CSlave i2c;
+ int firstbyte;
+ uint8_t reg;
+ uint8_t edid_blob[128];
+} I2CDDCState;
+
+#define TYPE_I2CDDC "i2c-ddc"
+#define I2CDDC(obj) OBJECT_CHECK(I2CDDCState, (obj), TYPE_I2CDDC)
+
+#endif /* !I2C_DDC */
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 6/8] Introduce xilinx dpdma.
2015-05-13 19:11 [Qemu-devel] [PATCH 0/8] Xilinx DisplayPort fred.konrad
` (4 preceding siblings ...)
2015-05-13 19:12 ` [Qemu-devel] [PATCH 5/8] hw/i2c-ddc.c: Implement DDC I2C slave fred.konrad
@ 2015-05-13 19:12 ` fred.konrad
2015-05-18 8:17 ` Peter Crosthwaite
2015-05-13 19:12 ` [Qemu-devel] [PATCH 7/8] Introduce xilinx dp fred.konrad
2015-05-13 19:12 ` [Qemu-devel] [PATCH 8/8] arm: xlnx-zynqmp: Add DisplayPort and DPDMA fred.konrad
7 siblings, 1 reply; 20+ messages in thread
From: fred.konrad @ 2015-05-13 19:12 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.crosthwaite, mark.burton, hyunk, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This is the implementation of the DPDMA.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/dma/Makefile.objs | 1 +
hw/dma/xilinx_dpdma.c | 1149 +++++++++++++++++++++++++++++++++++++++++++++++++
hw/dma/xilinx_dpdma.h | 71 +++
3 files changed, 1221 insertions(+)
create mode 100644 hw/dma/xilinx_dpdma.c
create mode 100644 hw/dma/xilinx_dpdma.h
diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
index 0e65ed0..7198e5a 100644
--- a/hw/dma/Makefile.objs
+++ b/hw/dma/Makefile.objs
@@ -8,6 +8,7 @@ common-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
common-obj-$(CONFIG_STP2000) += sparc32_dma.o
common-obj-$(CONFIG_SUN4M) += sun4m_iommu.o
+common-obj-y += xilinx_dpdma.o
obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o
obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o
diff --git a/hw/dma/xilinx_dpdma.c b/hw/dma/xilinx_dpdma.c
new file mode 100644
index 0000000..6479148
--- /dev/null
+++ b/hw/dma/xilinx_dpdma.c
@@ -0,0 +1,1149 @@
+/*
+ * xilinx_dpdma.c
+ *
+ * Copyright (C) 2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "xilinx_dpdma.h"
+
+#ifndef DEBUG_DPDMA
+#define DEBUG_DPDMA 0
+#endif
+
+#define DPRINTF(fmt, ...) do { \
+ if (DEBUG_DPDMA) { \
+ qemu_log("xilinx_dpdma: " fmt , ## __VA_ARGS__); \
+ } \
+} while (0);
+
+/*
+ * Registers offset for DPDMA.
+ */
+#define DPDMA_ERR_CTRL (0x00000000)
+#define DPDMA_ISR (0x00000004 >> 2)
+#define DPDMA_IMR (0x00000008 >> 2)
+#define DPDMA_IEN (0x0000000C >> 2)
+#define DPDMA_IDS (0x00000010 >> 2)
+#define DPDMA_EISR (0x00000014 >> 2)
+#define DPDMA_EIMR (0x00000018 >> 2)
+#define DPDMA_EIEN (0x0000001C >> 2)
+#define DPDMA_EIDS (0x00000020 >> 2)
+#define DPDMA_CNTL (0x00000100 >> 2)
+#define DPDMA_GBL (0x00000104 >> 2)
+#define DPDMA_ALC0_CNTL (0x00000108 >> 2)
+#define DPDMA_ALC0_STATUS (0x0000010C >> 2)
+#define DPDMA_ALC0_MAX (0x00000110 >> 2)
+#define DPDMA_ALC0_MIN (0x00000114 >> 2)
+#define DPDMA_ALC0_ACC (0x00000118 >> 2)
+#define DPDMA_ALC0_ACC_TRAN (0x0000011C >> 2)
+#define DPDMA_ALC1_CNTL (0x00000120 >> 2)
+#define DPDMA_ALC1_STATUS (0x00000124 >> 2)
+#define DPDMA_ALC1_MAX (0x00000128 >> 2)
+#define DPDMA_ALC1_MIN (0x0000012C >> 2)
+#define DPDMA_ALC1_ACC (0x00000130 >> 2)
+#define DPDMA_ALC1_ACC_TRAN (0x00000134 >> 2)
+#define DPDMA_CH0_DSCR_STRT_ADDRE (0x00000200 >> 2)
+#define DPDMA_CH0_DSCR_STRT_ADDR (0x00000204 >> 2)
+#define DPDMA_CH0_DSCR_NEXT_ADDRE (0x00000208 >> 2)
+#define DPDMA_CH0_DSCR_NEXT_ADDR (0x0000020C >> 2)
+#define DPDMA_CH0_PYLD_CUR_ADDRE (0x00000210 >> 2)
+#define DPDMA_CH0_PYLD_CUR_ADDR (0x00000214 >> 2)
+#define DPDMA_CH0_CNTL (0x00000218 >> 2)
+#define DPDMA_CH0_STATUS (0x0000021C >> 2)
+#define DPDMA_CH0_VDO (0x00000220 >> 2)
+#define DPDMA_CH0_PYLD_SZ (0x00000224 >> 2)
+#define DPDMA_CH0_DSCR_ID (0x00000228 >> 2)
+#define DPDMA_CH1_DSCR_STRT_ADDRE (0x00000300 >> 2)
+#define DPDMA_CH1_DSCR_STRT_ADDR (0x00000304 >> 2)
+#define DPDMA_CH1_DSCR_NEXT_ADDRE (0x00000308 >> 2)
+#define DPDMA_CH1_DSCR_NEXT_ADDR (0x0000030C >> 2)
+#define DPDMA_CH1_PYLD_CUR_ADDRE (0x00000310 >> 2)
+#define DPDMA_CH1_PYLD_CUR_ADDR (0x00000314 >> 2)
+#define DPDMA_CH1_CNTL (0x00000318 >> 2)
+#define DPDMA_CH1_STATUS (0x0000031C >> 2)
+#define DPDMA_CH1_VDO (0x00000320 >> 2)
+#define DPDMA_CH1_PYLD_SZ (0x00000324 >> 2)
+#define DPDMA_CH1_DSCR_ID (0x00000328 >> 2)
+#define DPDMA_CH2_DSCR_STRT_ADDRE (0x00000400 >> 2)
+#define DPDMA_CH2_DSCR_STRT_ADDR (0x00000404 >> 2)
+#define DPDMA_CH2_DSCR_NEXT_ADDRE (0x00000408 >> 2)
+#define DPDMA_CH2_DSCR_NEXT_ADDR (0x0000040C >> 2)
+#define DPDMA_CH2_PYLD_CUR_ADDRE (0x00000410 >> 2)
+#define DPDMA_CH2_PYLD_CUR_ADDR (0x00000414 >> 2)
+#define DPDMA_CH2_CNTL (0x00000418 >> 2)
+#define DPDMA_CH2_STATUS (0x0000041C >> 2)
+#define DPDMA_CH2_VDO (0x00000420 >> 2)
+#define DPDMA_CH2_PYLD_SZ (0x00000424 >> 2)
+#define DPDMA_CH2_DSCR_ID (0x00000428 >> 2)
+#define DPDMA_CH3_DSCR_STRT_ADDRE (0x00000500 >> 2)
+#define DPDMA_CH3_DSCR_STRT_ADDR (0x00000504 >> 2)
+#define DPDMA_CH3_DSCR_NEXT_ADDRE (0x00000508 >> 2)
+#define DPDMA_CH3_DSCR_NEXT_ADDR (0x0000050C >> 2)
+#define DPDMA_CH3_PYLD_CUR_ADDRE (0x00000510 >> 2)
+#define DPDMA_CH3_PYLD_CUR_ADDR (0x00000514 >> 2)
+#define DPDMA_CH3_CNTL (0x00000518 >> 2)
+#define DPDMA_CH3_STATUS (0x0000051C >> 2)
+#define DPDMA_CH3_VDO (0x00000520 >> 2)
+#define DPDMA_CH3_PYLD_SZ (0x00000524 >> 2)
+#define DPDMA_CH3_DSCR_ID (0x00000528 >> 2)
+#define DPDMA_CH4_DSCR_STRT_ADDRE (0x00000600 >> 2)
+#define DPDMA_CH4_DSCR_STRT_ADDR (0x00000604 >> 2)
+#define DPDMA_CH4_DSCR_NEXT_ADDRE (0x00000608 >> 2)
+#define DPDMA_CH4_DSCR_NEXT_ADDR (0x0000060C >> 2)
+#define DPDMA_CH4_PYLD_CUR_ADDRE (0x00000610 >> 2)
+#define DPDMA_CH4_PYLD_CUR_ADDR (0x00000614 >> 2)
+#define DPDMA_CH4_CNTL (0x00000618 >> 2)
+#define DPDMA_CH4_STATUS (0x0000061C >> 2)
+#define DPDMA_CH4_VDO (0x00000620 >> 2)
+#define DPDMA_CH4_PYLD_SZ (0x00000624 >> 2)
+#define DPDMA_CH4_DSCR_ID (0x00000628 >> 2)
+#define DPDMA_CH5_DSCR_STRT_ADDRE (0x00000700 >> 2)
+#define DPDMA_CH5_DSCR_STRT_ADDR (0x00000704 >> 2)
+#define DPDMA_CH5_DSCR_NEXT_ADDRE (0x00000708 >> 2)
+#define DPDMA_CH5_DSCR_NEXT_ADDR (0x0000070C >> 2)
+#define DPDMA_CH5_PYLD_CUR_ADDRE (0x00000710 >> 2)
+#define DPDMA_CH5_PYLD_CUR_ADDR (0x00000714 >> 2)
+#define DPDMA_CH5_CNTL (0x00000718 >> 2)
+#define DPDMA_CH5_STATUS (0x0000071C >> 2)
+#define DPDMA_CH5_VDO (0x00000720 >> 2)
+#define DPDMA_CH5_PYLD_SZ (0x00000724 >> 2)
+#define DPDMA_CH5_DSCR_ID (0x00000728 >> 2)
+#define DPDMA_ECO (0x00000FFC >> 2)
+
+/*
+ * Descriptor control field.
+ */
+#define CONTROL_PREAMBLE_VALUE 0xA5
+
+#define CONTROL_PREAMBLE 0xFF
+#define EN_DSCR_DONE_INTR (1 << 8)
+#define EN_DSCR_UPDATE (1 << 9)
+#define IGNORE_DONE (1 << 10)
+#define AXI_BURST_TYPE (1 << 11)
+#define AXCACHE (0x0F << 12)
+#define AXPROT (0x2 << 16)
+#define DESCRIPTOR_MODE (1 << 18)
+#define LAST_DESCRIPTOR (1 << 19)
+#define ENABLE_CRC (1 << 20)
+#define LAST_DESCRIPTOR_OF_FRAME (1 << 21)
+
+typedef enum DPDMABurstType {
+ DPDMA_INCR = 0,
+ DPDMA_FIXED = 1
+} DPDMABurstType;
+
+typedef enum DPDMAMode {
+ DPDMA_CONTIGOUS = 0,
+ DPDMA_FRAGMENTED = 1
+} DPDMAMode;
+
+typedef struct DPDMADescriptor {
+ uint32_t control;
+ uint32_t descriptor_id;
+ /* transfer size in byte. */
+ uint32_t xfer_size;
+ uint32_t line_size_stride;
+ uint32_t timestamp_lsb;
+ uint32_t timestamp_msb;
+ /* contains extension for both descriptor and source. */
+ uint32_t address_extension;
+ uint32_t next_descriptor;
+ uint32_t source_address;
+ uint32_t address_extension_23;
+ uint32_t address_extension_45;
+ uint32_t source_address2;
+ uint32_t source_address3;
+ uint32_t source_address4;
+ uint32_t source_address5;
+ uint32_t crc;
+} DPDMADescriptor;
+
+static bool xilinx_dpdma_desc_is_last(DPDMADescriptor *desc)
+{
+ return ((desc->control & 0x00080000) != 0);
+}
+
+static bool xilinx_dpdma_desc_is_last_of_frame(DPDMADescriptor *desc)
+{
+ return ((desc->control & 0x00200000) != 0);
+}
+
+static uint64_t xilinx_dpdma_desc_get_source_address(DPDMADescriptor *desc,
+ uint8_t frag)
+{
+ uint64_t addr = 0;
+ assert(frag < 5);
+
+ switch (frag) {
+ case 0:
+ addr = desc->source_address
+ + (extract32(desc->address_extension, 16, 12) << 20);
+ break;
+ case 1:
+ addr = desc->source_address2
+ + (extract32(desc->address_extension_23, 0, 12) << 8);
+ break;
+ case 2:
+ addr = desc->source_address3
+ + (extract32(desc->address_extension_23, 16, 12) << 20);
+ break;
+ case 3:
+ addr = desc->source_address4
+ + (extract32(desc->address_extension_45, 0, 12) << 8);
+ break;
+ case 4:
+ addr = desc->source_address5
+ + (extract32(desc->address_extension_45, 16, 12) << 20);
+ break;
+ default:
+ addr = 0;
+ break;
+ }
+
+ return addr;
+}
+
+static uint32_t xilinx_dpdma_desc_get_transfer_size(DPDMADescriptor *desc)
+{
+ return desc->xfer_size;
+}
+
+static uint32_t xilinx_dpdma_desc_get_line_size(DPDMADescriptor *desc)
+{
+ return desc->line_size_stride & 0x3FFFF;
+}
+
+static uint32_t xilinx_dpdma_desc_get_line_stride(DPDMADescriptor *desc)
+{
+ return (desc->line_size_stride >> 18) * 16;
+}
+
+static inline bool xilinx_dpdma_desc_crc_enabled(DPDMADescriptor *desc)
+{
+ return ((desc->control & (1 << 20)) != 0);
+}
+
+static inline bool xilinx_dpdma_desc_check_crc(DPDMADescriptor *desc)
+{
+ uint32_t *p = (uint32_t *)(desc);
+ uint32_t crc = 0;
+ uint8_t i;
+
+ for (i = 0; i < 15; i++) {
+ crc += p[i];
+ }
+
+ return (crc == desc->crc);
+}
+
+static inline bool xilinx_dpdma_desc_completion_interrupt(DPDMADescriptor *desc)
+{
+ return ((desc->control & (1 << 8)) != 0);
+}
+
+static inline bool xilinx_dpdma_desc_is_valid(DPDMADescriptor *desc)
+{
+ return ((desc->control & 0xFF) == 0xA5);
+}
+
+static inline bool xilinx_dpdma_desc_is_contiguous(DPDMADescriptor *desc)
+{
+ return ((desc->control & 0x00040000) == 0);
+}
+
+static inline bool xilinx_dpdma_desc_update_enabled(DPDMADescriptor *desc)
+{
+ return ((desc->control & (1 << 9)) != 0);
+}
+
+static inline void xilinx_dpdma_desc_set_done(DPDMADescriptor *desc)
+{
+ desc->timestamp_msb |= (1 << 31);
+}
+
+static inline bool xilinx_dpdma_desc_is_already_done(DPDMADescriptor *desc)
+{
+ return ((desc->timestamp_msb & (1 << 31)) != 0);
+}
+
+static inline bool xilinx_dpdma_desc_ignore_done_bit(DPDMADescriptor *desc)
+{
+ return ((desc->control & (1 << 10)) != 0);
+}
+
+static const VMStateDescription vmstate_xilinx_dpdma = {
+ .name = TYPE_XILINX_DPDMA,
+ .version_id = 1,
+ .fields = (VMStateField[]) {
+
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void xilinx_dpdma_update_irq(XilinxDPDMAState *s)
+{
+ uint32_t flags;
+
+ flags = ((s->registers[DPDMA_ISR] & (~s->registers[DPDMA_IMR]))
+ | (s->registers[DPDMA_EISR] & (~s->registers[DPDMA_EIMR])));
+ qemu_set_irq(s->irq, flags != 0);
+}
+
+static uint64_t xilinx_dpdma_descriptor_start_address(XilinxDPDMAState *s,
+ uint8_t channel)
+{
+ switch (channel) {
+ case 0:
+ return (s->registers[DPDMA_CH0_DSCR_STRT_ADDRE] << 16)
+ + s->registers[DPDMA_CH0_DSCR_STRT_ADDR];
+ break;
+ case 1:
+ return (s->registers[DPDMA_CH1_DSCR_STRT_ADDRE] << 16)
+ + s->registers[DPDMA_CH1_DSCR_STRT_ADDR];
+ break;
+ case 2:
+ return (s->registers[DPDMA_CH2_DSCR_STRT_ADDRE] << 16)
+ + s->registers[DPDMA_CH2_DSCR_STRT_ADDR];
+ break;
+ case 3:
+ return (s->registers[DPDMA_CH3_DSCR_STRT_ADDRE] << 16)
+ + s->registers[DPDMA_CH3_DSCR_STRT_ADDR];
+ break;
+ case 4:
+ return (s->registers[DPDMA_CH4_DSCR_STRT_ADDRE] << 16)
+ + s->registers[DPDMA_CH4_DSCR_STRT_ADDR];
+ break;
+ case 5:
+ return (s->registers[DPDMA_CH5_DSCR_STRT_ADDRE] << 16)
+ + s->registers[DPDMA_CH5_DSCR_STRT_ADDR];
+ break;
+ default:
+ /* Should not happen. */
+ return 0;
+ break;
+ }
+}
+
+static uint64_t xilinx_dpdma_descriptor_next_address(XilinxDPDMAState *s,
+ uint8_t channel)
+{
+ switch (channel) {
+ case 0:
+ return ((uint64_t)s->registers[DPDMA_CH0_DSCR_NEXT_ADDRE] << 32)
+ + s->registers[DPDMA_CH0_DSCR_NEXT_ADDR];
+ break;
+ case 1:
+ return ((uint64_t)s->registers[DPDMA_CH1_DSCR_NEXT_ADDRE] << 32)
+ + s->registers[DPDMA_CH1_DSCR_NEXT_ADDR];
+ break;
+ case 2:
+ return ((uint64_t)s->registers[DPDMA_CH2_DSCR_NEXT_ADDRE] << 32)
+ + s->registers[DPDMA_CH2_DSCR_NEXT_ADDR];
+ break;
+ case 3:
+ return ((uint64_t)s->registers[DPDMA_CH3_DSCR_NEXT_ADDRE] << 32)
+ + s->registers[DPDMA_CH3_DSCR_NEXT_ADDR];
+ break;
+ case 4:
+ return ((uint64_t)s->registers[DPDMA_CH4_DSCR_NEXT_ADDRE] << 32)
+ + s->registers[DPDMA_CH4_DSCR_NEXT_ADDR];
+ break;
+ case 5:
+ return ((uint64_t)s->registers[DPDMA_CH5_DSCR_NEXT_ADDRE] << 32)
+ + s->registers[DPDMA_CH5_DSCR_NEXT_ADDR];
+ break;
+ default:
+ /* Should not happen. */
+ return 0;
+ break;
+ }
+}
+
+static inline void xilinx_dpdma_set_desc_next_address(XilinxDPDMAState *s,
+ uint8_t channel,
+ uint64_t addr)
+{
+ switch (channel) {
+ case 0:
+ s->registers[DPDMA_CH0_DSCR_NEXT_ADDRE] = addr >> 32;
+ s->registers[DPDMA_CH0_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
+ break;
+ case 1:
+ s->registers[DPDMA_CH1_DSCR_NEXT_ADDRE] = addr >> 32;
+ s->registers[DPDMA_CH1_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
+ break;
+ case 2:
+ s->registers[DPDMA_CH2_DSCR_NEXT_ADDRE] = addr >> 32;
+ s->registers[DPDMA_CH2_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
+ break;
+ case 3:
+ s->registers[DPDMA_CH3_DSCR_NEXT_ADDRE] = addr >> 32;
+ s->registers[DPDMA_CH3_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
+ break;
+ case 4:
+ s->registers[DPDMA_CH4_DSCR_NEXT_ADDRE] = addr >> 32;
+ s->registers[DPDMA_CH4_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
+ break;
+ case 5:
+ s->registers[DPDMA_CH5_DSCR_NEXT_ADDRE] = addr >> 32;
+ s->registers[DPDMA_CH5_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
+ break;
+ default:
+ /* Should not happen. */
+ break;
+ }
+}
+
+static bool xilinx_dpdma_is_channel_enabled(XilinxDPDMAState *s,
+ uint8_t channel)
+{
+ switch (channel) {
+ case 0:
+ return ((s->registers[DPDMA_CH0_CNTL] & 0x01) != 0);
+ break;
+ case 1:
+ return ((s->registers[DPDMA_CH1_CNTL] & 0x01) != 0);
+ break;
+ case 2:
+ return ((s->registers[DPDMA_CH2_CNTL] & 0x01) != 0);
+ break;
+ case 3:
+ return ((s->registers[DPDMA_CH3_CNTL] & 0x01) != 0);
+ break;
+ case 4:
+ return ((s->registers[DPDMA_CH4_CNTL] & 0x01) != 0);
+ break;
+ case 5:
+ return ((s->registers[DPDMA_CH5_CNTL] & 0x01) != 0);
+ break;
+ default:
+ /* Should not happen. */
+ return 0;
+ break;
+ }
+}
+
+static bool xilinx_dpdma_is_channel_paused(XilinxDPDMAState *s,
+ uint8_t channel)
+{
+ switch (channel) {
+ case 0:
+ return ((s->registers[DPDMA_CH0_CNTL] & 0x02) != 0);
+ break;
+ case 1:
+ return ((s->registers[DPDMA_CH1_CNTL] & 0x02) != 0);
+ break;
+ case 2:
+ return ((s->registers[DPDMA_CH2_CNTL] & 0x02) != 0);
+ break;
+ case 3:
+ return ((s->registers[DPDMA_CH3_CNTL] & 0x02) != 0);
+ break;
+ case 4:
+ return ((s->registers[DPDMA_CH4_CNTL] & 0x02) != 0);
+ break;
+ case 5:
+ return ((s->registers[DPDMA_CH5_CNTL] & 0x02) != 0);
+ break;
+ default:
+ /* Should not happen. */
+ return 0;
+ break;
+ }
+}
+
+static inline bool xilinx_dpdma_is_channel_retriggered(XilinxDPDMAState *s,
+ uint8_t channel)
+{
+ return s->registers[DPDMA_GBL] & ((1 << 6) << channel);
+}
+
+static inline bool xilinx_dpdma_is_channel_triggered(XilinxDPDMAState *s,
+ uint8_t channel)
+{
+ return s->registers[DPDMA_GBL] & (1 << channel);
+}
+
+static void xilinx_dpdma_update_desc_info(XilinxDPDMAState *s, uint8_t channel,
+ DPDMADescriptor *desc)
+{
+ switch (channel) {
+ case 0:
+ s->registers[DPDMA_CH0_DSCR_NEXT_ADDRE] = desc->address_extension
+ & 0x0000FFFF;
+ s->registers[DPDMA_CH0_DSCR_NEXT_ADDR] = desc->next_descriptor;
+ s->registers[DPDMA_CH0_PYLD_CUR_ADDRE] =
+ extract32(desc->address_extension, 16, 16);
+ s->registers[DPDMA_CH0_PYLD_CUR_ADDR] = desc->source_address;
+ s->registers[DPDMA_CH0_VDO] = extract32(desc->line_size_stride, 18, 14)
+ + (extract32(desc->line_size_stride, 0, 18)
+ << 14);
+ s->registers[DPDMA_CH0_PYLD_SZ] = desc->xfer_size;
+ s->registers[DPDMA_CH0_DSCR_ID] = desc->descriptor_id;
+
+ /* Compute the status register with the descriptor information. */
+ s->registers[DPDMA_CH0_STATUS] = (desc->control & 0xFF) << 13;
+ if ((desc->control & (1 << 8)) != 0) {
+ s->registers[DPDMA_CH0_STATUS] |= (1 << 12);
+ }
+ if ((desc->control & (1 << 9)) != 0) {
+ s->registers[DPDMA_CH0_STATUS] |= (1 << 11);
+ }
+ if ((desc->timestamp_msb & (1 << 31)) != 0) {
+ s->registers[DPDMA_CH0_STATUS] |= (1 << 10);
+ }
+ if ((desc->control & (1 << 10)) != 0) {
+ s->registers[DPDMA_CH0_STATUS] |= (1 << 9);
+ }
+ if ((desc->control & (1 << 21)) != 0) {
+ s->registers[DPDMA_CH0_STATUS] |= (1 << 8);
+ }
+ if ((desc->control & (1 << 19)) != 0) {
+ s->registers[DPDMA_CH0_STATUS] |= (1 << 7);
+ }
+ if ((desc->control & (1 << 20)) != 0) {
+ s->registers[DPDMA_CH0_STATUS] |= (1 << 6);
+ }
+ if ((desc->control & (1 << 18)) != 0) {
+ s->registers[DPDMA_CH0_STATUS] |= (1 << 5);
+ }
+ if ((desc->control & (1 << 11)) != 0) {
+ s->registers[DPDMA_CH0_STATUS] |= (1 << 4);
+ }
+ /* XXX: BURST_LEN? */
+ break;
+ case 1:
+ s->registers[DPDMA_CH1_DSCR_NEXT_ADDRE] = desc->address_extension
+ & 0x0000FFFF;
+ s->registers[DPDMA_CH1_DSCR_NEXT_ADDR] = desc->next_descriptor;
+ s->registers[DPDMA_CH1_PYLD_CUR_ADDRE] =
+ extract32(desc->address_extension, 16, 16);
+ s->registers[DPDMA_CH1_PYLD_CUR_ADDR] = desc->source_address;
+ s->registers[DPDMA_CH1_VDO] = extract32(desc->line_size_stride, 18, 14)
+ + (extract32(desc->line_size_stride, 0, 18)
+ << 14);
+ s->registers[DPDMA_CH1_PYLD_SZ] = desc->xfer_size;
+ s->registers[DPDMA_CH1_DSCR_ID] = desc->descriptor_id;
+
+ /* Compute the status register with the descriptor information. */
+ s->registers[DPDMA_CH1_STATUS] = (desc->control & 0xFF) << 13;
+ if ((desc->control & (1 << 8)) != 0) {
+ s->registers[DPDMA_CH1_STATUS] |= (1 << 12);
+ }
+ if ((desc->control & (1 << 9)) != 0) {
+ s->registers[DPDMA_CH1_STATUS] |= (1 << 11);
+ }
+ if ((desc->timestamp_msb & (1 << 31)) != 0) {
+ s->registers[DPDMA_CH1_STATUS] |= (1 << 10);
+ }
+ if ((desc->control & (1 << 10)) != 0) {
+ s->registers[DPDMA_CH1_STATUS] |= (1 << 9);
+ }
+ if ((desc->control & (1 << 21)) != 0) {
+ s->registers[DPDMA_CH1_STATUS] |= (1 << 8);
+ }
+ if ((desc->control & (1 << 19)) != 0) {
+ s->registers[DPDMA_CH1_STATUS] |= (1 << 7);
+ }
+ if ((desc->control & (1 << 20)) != 0) {
+ s->registers[DPDMA_CH1_STATUS] |= (1 << 6);
+ }
+ if ((desc->control & (1 << 18)) != 0) {
+ s->registers[DPDMA_CH1_STATUS] |= (1 << 5);
+ }
+ if ((desc->control & (1 << 11)) != 0) {
+ s->registers[DPDMA_CH1_STATUS] |= (1 << 4);
+ }
+ /* XXX: BURST_LEN? */
+ break;
+ case 2:
+ s->registers[DPDMA_CH2_DSCR_NEXT_ADDRE] = desc->address_extension
+ & 0x0000FFFF;
+ s->registers[DPDMA_CH2_DSCR_NEXT_ADDR] = desc->next_descriptor;
+ s->registers[DPDMA_CH2_PYLD_CUR_ADDRE] =
+ extract32(desc->address_extension, 16, 16);
+ s->registers[DPDMA_CH2_PYLD_CUR_ADDR] = desc->source_address;
+ s->registers[DPDMA_CH2_VDO] = extract32(desc->line_size_stride, 18, 14)
+ + (extract32(desc->line_size_stride, 0, 18)
+ << 14);
+ s->registers[DPDMA_CH2_PYLD_SZ] = desc->xfer_size;
+ s->registers[DPDMA_CH2_DSCR_ID] = desc->descriptor_id;
+
+ /* Compute the status register with the descriptor information. */
+ s->registers[DPDMA_CH2_STATUS] = (desc->control & 0xFF) << 13;
+ if ((desc->control & (1 << 8)) != 0) {
+ s->registers[DPDMA_CH2_STATUS] |= (1 << 12);
+ }
+ if ((desc->control & (1 << 9)) != 0) {
+ s->registers[DPDMA_CH2_STATUS] |= (1 << 11);
+ }
+ if ((desc->timestamp_msb & (1 << 31)) != 0) {
+ s->registers[DPDMA_CH2_STATUS] |= (1 << 10);
+ }
+ if ((desc->control & (1 << 10)) != 0) {
+ s->registers[DPDMA_CH2_STATUS] |= (1 << 9);
+ }
+ if ((desc->control & (1 << 21)) != 0) {
+ s->registers[DPDMA_CH2_STATUS] |= (1 << 8);
+ }
+ if ((desc->control & (1 << 19)) != 0) {
+ s->registers[DPDMA_CH2_STATUS] |= (1 << 7);
+ }
+ if ((desc->control & (1 << 20)) != 0) {
+ s->registers[DPDMA_CH2_STATUS] |= (1 << 6);
+ }
+ if ((desc->control & (1 << 18)) != 0) {
+ s->registers[DPDMA_CH2_STATUS] |= (1 << 5);
+ }
+ if ((desc->control & (1 << 11)) != 0) {
+ s->registers[DPDMA_CH2_STATUS] |= (1 << 4);
+ }
+ /* XXX: BURST_LEN? */
+ break;
+ case 3:
+ s->registers[DPDMA_CH3_DSCR_NEXT_ADDRE] = desc->address_extension
+ & 0x0000FFFF;
+ s->registers[DPDMA_CH3_DSCR_NEXT_ADDR] = desc->next_descriptor;
+ s->registers[DPDMA_CH3_PYLD_CUR_ADDRE] =
+ extract32(desc->address_extension, 16, 16);
+ s->registers[DPDMA_CH3_PYLD_CUR_ADDR] = desc->source_address;
+ s->registers[DPDMA_CH3_VDO] = extract32(desc->line_size_stride, 18, 14)
+ + (extract32(desc->line_size_stride, 0, 18)
+ << 14);
+ s->registers[DPDMA_CH3_PYLD_SZ] = desc->xfer_size;
+ s->registers[DPDMA_CH3_DSCR_ID] = desc->descriptor_id;
+
+ /* Compute the status register with the descriptor information. */
+ s->registers[DPDMA_CH3_STATUS] = (desc->control & 0xFF) << 13;
+ if ((desc->control & (1 << 8)) != 0) {
+ s->registers[DPDMA_CH3_STATUS] |= (1 << 12);
+ }
+ if ((desc->control & (1 << 9)) != 0) {
+ s->registers[DPDMA_CH3_STATUS] |= (1 << 11);
+ }
+ if ((desc->timestamp_msb & (1 << 31)) != 0) {
+ s->registers[DPDMA_CH3_STATUS] |= (1 << 10);
+ }
+ if ((desc->control & (1 << 10)) != 0) {
+ s->registers[DPDMA_CH3_STATUS] |= (1 << 9);
+ }
+ if ((desc->control & (1 << 21)) != 0) {
+ s->registers[DPDMA_CH3_STATUS] |= (1 << 8);
+ }
+ if ((desc->control & (1 << 19)) != 0) {
+ s->registers[DPDMA_CH3_STATUS] |= (1 << 7);
+ }
+ if ((desc->control & (1 << 20)) != 0) {
+ s->registers[DPDMA_CH3_STATUS] |= (1 << 6);
+ }
+ if ((desc->control & (1 << 18)) != 0) {
+ s->registers[DPDMA_CH3_STATUS] |= (1 << 5);
+ }
+ if ((desc->control & (1 << 11)) != 0) {
+ s->registers[DPDMA_CH3_STATUS] |= (1 << 4);
+ }
+ /* XXX: BURST_LEN? */
+ break;
+ case 4:
+ s->registers[DPDMA_CH4_DSCR_NEXT_ADDRE] = desc->address_extension
+ & 0x0000FFFF;
+ s->registers[DPDMA_CH4_DSCR_NEXT_ADDR] = desc->next_descriptor;
+ s->registers[DPDMA_CH4_PYLD_CUR_ADDRE] =
+ extract32(desc->address_extension, 16, 16);
+ s->registers[DPDMA_CH4_PYLD_CUR_ADDR] = desc->source_address;
+ s->registers[DPDMA_CH4_VDO] = extract32(desc->line_size_stride, 18, 14)
+ + (extract32(desc->line_size_stride, 0, 18)
+ << 14);
+ s->registers[DPDMA_CH4_PYLD_SZ] = desc->xfer_size;
+ s->registers[DPDMA_CH4_DSCR_ID] = desc->descriptor_id;
+
+ /* Compute the status register with the descriptor information. */
+ s->registers[DPDMA_CH4_STATUS] = (desc->control & 0xFF) << 13;
+ if ((desc->control & (1 << 8)) != 0) {
+ s->registers[DPDMA_CH4_STATUS] |= (1 << 12);
+ }
+ if ((desc->control & (1 << 9)) != 0) {
+ s->registers[DPDMA_CH4_STATUS] |= (1 << 11);
+ }
+ if ((desc->timestamp_msb & (1 << 31)) != 0) {
+ s->registers[DPDMA_CH4_STATUS] |= (1 << 10);
+ }
+ if ((desc->control & (1 << 10)) != 0) {
+ s->registers[DPDMA_CH4_STATUS] |= (1 << 9);
+ }
+ if ((desc->control & (1 << 21)) != 0) {
+ s->registers[DPDMA_CH4_STATUS] |= (1 << 8);
+ }
+ if ((desc->control & (1 << 19)) != 0) {
+ s->registers[DPDMA_CH4_STATUS] |= (1 << 7);
+ }
+ if ((desc->control & (1 << 20)) != 0) {
+ s->registers[DPDMA_CH4_STATUS] |= (1 << 6);
+ }
+ if ((desc->control & (1 << 18)) != 0) {
+ s->registers[DPDMA_CH4_STATUS] |= (1 << 5);
+ }
+ if ((desc->control & (1 << 11)) != 0) {
+ s->registers[DPDMA_CH4_STATUS] |= (1 << 4);
+ }
+ /* XXX: BURST_LEN? */
+ break;
+ case 5:
+ s->registers[DPDMA_CH5_DSCR_NEXT_ADDRE] = desc->address_extension
+ & 0x0000FFFF;
+ s->registers[DPDMA_CH5_DSCR_NEXT_ADDR] = desc->next_descriptor;
+ s->registers[DPDMA_CH5_PYLD_CUR_ADDRE] =
+ extract32(desc->address_extension, 16, 16);
+ s->registers[DPDMA_CH5_PYLD_CUR_ADDR] = desc->source_address;
+ s->registers[DPDMA_CH5_VDO] = extract32(desc->line_size_stride, 18, 14)
+ + (extract32(desc->line_size_stride, 0, 18)
+ << 14);
+ s->registers[DPDMA_CH5_PYLD_SZ] = desc->xfer_size;
+ s->registers[DPDMA_CH5_DSCR_ID] = desc->descriptor_id;
+
+ /* Compute the status register with the descriptor information. */
+ s->registers[DPDMA_CH5_STATUS] = (desc->control & 0xFF) << 13;
+ if ((desc->control & (1 << 8)) != 0) {
+ s->registers[DPDMA_CH5_STATUS] |= (1 << 12);
+ }
+ if ((desc->control & (1 << 9)) != 0) {
+ s->registers[DPDMA_CH5_STATUS] |= (1 << 11);
+ }
+ if ((desc->timestamp_msb & (1 << 31)) != 0) {
+ s->registers[DPDMA_CH5_STATUS] |= (1 << 10);
+ }
+ if ((desc->control & (1 << 10)) != 0) {
+ s->registers[DPDMA_CH5_STATUS] |= (1 << 9);
+ }
+ if ((desc->control & (1 << 21)) != 0) {
+ s->registers[DPDMA_CH5_STATUS] |= (1 << 8);
+ }
+ if ((desc->control & (1 << 19)) != 0) {
+ s->registers[DPDMA_CH5_STATUS] |= (1 << 7);
+ }
+ if ((desc->control & (1 << 20)) != 0) {
+ s->registers[DPDMA_CH5_STATUS] |= (1 << 6);
+ }
+ if ((desc->control & (1 << 18)) != 0) {
+ s->registers[DPDMA_CH5_STATUS] |= (1 << 5);
+ }
+ if ((desc->control & (1 << 11)) != 0) {
+ s->registers[DPDMA_CH5_STATUS] |= (1 << 4);
+ }
+ /* XXX: BURST_LEN? */
+ break;
+ default:
+ break;
+ }
+}
+
+#ifdef DEBUG_DPDMA
+static void xilinx_dpdma_dump_descriptor(DPDMADescriptor *desc)
+{
+ uint8_t *p = ((uint8_t *)(desc));
+ size_t i;
+
+ qemu_log("DUMP DESCRIPTOR:\n");
+ for (i = 0; i < 64; i++) {
+ qemu_log(" 0x%2.2X", *p++);
+ if (((i + 1) % 4) == 0) {
+ qemu_log("\n");
+ }
+ }
+}
+#endif
+
+static uint64_t xilinx_dpdma_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ XilinxDPDMAState *s = XILINX_DPDMA(opaque);
+ assert(size == 4);
+ assert((offset % 4) == 0);
+ offset = offset >> 2;
+ DPRINTF("read @%" PRIx64 "\n", offset << 2);
+
+ switch (offset) {
+ /*
+ * Trying to read a write only register.
+ */
+ case DPDMA_GBL:
+ return 0;
+ break;
+ default:
+ assert(offset <= (0xFFC >> 2));
+ return s->registers[offset];
+ break;
+ }
+ return 0;
+}
+
+static void xilinx_dpdma_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ XilinxDPDMAState *s = XILINX_DPDMA(opaque);
+ assert(size == 4);
+ assert((offset % 4) == 0);
+ offset = offset >> 2;
+ DPRINTF("write @%" PRIx64 " = 0x%8.8lX\n", offset << 2, value);
+
+ switch (offset) {
+ case DPDMA_ISR:
+ value = ~value;
+ s->registers[DPDMA_ISR] &= value;
+ xilinx_dpdma_update_irq(s);
+ break;
+ case DPDMA_IEN:
+ value = ~value;
+ s->registers[DPDMA_IMR] &= value;
+ break;
+ case DPDMA_IDS:
+ s->registers[DPDMA_IMR] |= value;
+ break;
+ case DPDMA_EISR:
+ value = ~value;
+ s->registers[DPDMA_EISR] &= value;
+ xilinx_dpdma_update_irq(s);
+ break;
+ case DPDMA_EIEN:
+ value = ~value;
+ s->registers[DPDMA_EIMR] &= value;
+ break;
+ case DPDMA_EIDS:
+ s->registers[DPDMA_EIMR] |= value;
+ break;
+ case DPDMA_IMR:
+ case DPDMA_EIMR:
+ case DPDMA_CH0_DSCR_NEXT_ADDRE:
+ case DPDMA_CH0_DSCR_NEXT_ADDR:
+ case DPDMA_CH1_DSCR_NEXT_ADDRE:
+ case DPDMA_CH1_DSCR_NEXT_ADDR:
+ case DPDMA_CH2_DSCR_NEXT_ADDRE:
+ case DPDMA_CH2_DSCR_NEXT_ADDR:
+ case DPDMA_CH3_DSCR_NEXT_ADDRE:
+ case DPDMA_CH3_DSCR_NEXT_ADDR:
+ case DPDMA_CH4_DSCR_NEXT_ADDRE:
+ case DPDMA_CH4_DSCR_NEXT_ADDR:
+ case DPDMA_CH5_DSCR_NEXT_ADDRE:
+ case DPDMA_CH5_DSCR_NEXT_ADDR:
+ case DPDMA_CH0_PYLD_CUR_ADDRE:
+ case DPDMA_CH0_PYLD_CUR_ADDR:
+ case DPDMA_CH1_PYLD_CUR_ADDRE:
+ case DPDMA_CH1_PYLD_CUR_ADDR:
+ case DPDMA_CH2_PYLD_CUR_ADDRE:
+ case DPDMA_CH2_PYLD_CUR_ADDR:
+ case DPDMA_CH3_PYLD_CUR_ADDRE:
+ case DPDMA_CH3_PYLD_CUR_ADDR:
+ case DPDMA_CH4_PYLD_CUR_ADDRE:
+ case DPDMA_CH4_PYLD_CUR_ADDR:
+ case DPDMA_CH5_PYLD_CUR_ADDRE:
+ case DPDMA_CH5_PYLD_CUR_ADDR:
+ case DPDMA_CH0_STATUS:
+ case DPDMA_CH1_STATUS:
+ case DPDMA_CH2_STATUS:
+ case DPDMA_CH3_STATUS:
+ case DPDMA_CH4_STATUS:
+ case DPDMA_CH5_STATUS:
+ case DPDMA_CH0_VDO:
+ case DPDMA_CH1_VDO:
+ case DPDMA_CH2_VDO:
+ case DPDMA_CH3_VDO:
+ case DPDMA_CH4_VDO:
+ case DPDMA_CH5_VDO:
+ case DPDMA_CH0_PYLD_SZ:
+ case DPDMA_CH1_PYLD_SZ:
+ case DPDMA_CH2_PYLD_SZ:
+ case DPDMA_CH3_PYLD_SZ:
+ case DPDMA_CH4_PYLD_SZ:
+ case DPDMA_CH5_PYLD_SZ:
+ case DPDMA_CH0_DSCR_ID:
+ case DPDMA_CH1_DSCR_ID:
+ case DPDMA_CH2_DSCR_ID:
+ case DPDMA_CH3_DSCR_ID:
+ case DPDMA_CH4_DSCR_ID:
+ case DPDMA_CH5_DSCR_ID:
+ /*
+ * Trying to write to a read only register..
+ */
+ break;
+ case DPDMA_GBL:
+ /*
+ * This is a write only register so it's read as zero in the read
+ * callback.
+ * We store the value anyway so we can know if the channel is
+ * enabled.
+ */
+ s->registers[offset] = value & 0x00000FFF;
+ break;
+ case DPDMA_CH0_DSCR_STRT_ADDRE:
+ case DPDMA_CH1_DSCR_STRT_ADDRE:
+ case DPDMA_CH2_DSCR_STRT_ADDRE:
+ case DPDMA_CH3_DSCR_STRT_ADDRE:
+ case DPDMA_CH4_DSCR_STRT_ADDRE:
+ case DPDMA_CH5_DSCR_STRT_ADDRE:
+ value &= 0x0000FFFF;
+ s->registers[offset] = value;
+ break;
+ case DPDMA_CH0_CNTL:
+ case DPDMA_CH1_CNTL:
+ case DPDMA_CH2_CNTL:
+ case DPDMA_CH3_CNTL:
+ case DPDMA_CH4_CNTL:
+ case DPDMA_CH5_CNTL:
+ value &= 0x3FFFFFFF;
+ s->registers[offset] = value;
+ break;
+ default:
+ assert(offset <= (0xFFC >> 2));
+ s->registers[offset] = value;
+ break;
+ }
+}
+
+static const MemoryRegionOps dma_ops = {
+ .read = xilinx_dpdma_read,
+ .write = xilinx_dpdma_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void xilinx_dpdma_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ XilinxDPDMAState *s = XILINX_DPDMA(obj);
+
+ memory_region_init_io(&s->iomem, obj, &dma_ops, s,
+ TYPE_XILINX_DPDMA, 0x1000);
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq);
+}
+
+static void xilinx_dpdma_reset(DeviceState *dev)
+{
+ XilinxDPDMAState *s = XILINX_DPDMA(dev);
+ memset(s->registers, 0, sizeof(s->registers));
+ s->registers[DPDMA_IMR] = 0x07FFFFFF;
+ s->registers[DPDMA_EIMR] = 0xFFFFFFFF;
+ s->registers[DPDMA_ALC0_MIN] = 0x0000FFFF;
+ s->registers[DPDMA_ALC1_MIN] = 0x0000FFFF;
+}
+
+static void xilinx_dpdma_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->vmsd = &vmstate_xilinx_dpdma;
+ dc->reset = xilinx_dpdma_reset;
+}
+
+static const TypeInfo xilinx_dpdma_info = {
+ .name = TYPE_XILINX_DPDMA,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XilinxDPDMAState),
+ .instance_init = xilinx_dpdma_init,
+ .class_init = xilinx_dpdma_class_init,
+};
+
+static void xilinx_dpdma_register_types(void)
+{
+ type_register_static(&xilinx_dpdma_info);
+}
+
+size_t xilinx_dpdma_start_operation(XilinxDPDMAState *s, uint8_t channel,
+ bool one_desc)
+{
+ uint64_t desc_addr;
+ uint64_t source_addr[6];
+ DPDMADescriptor desc;
+ bool done = false;
+ size_t ptr = 0;
+
+ assert(channel <= 5);
+
+ if (channel == 3) {
+ s->registers[DPDMA_ISR] |= (1 << 27);
+ xilinx_dpdma_update_irq(s);
+ }
+
+ DPRINTF("dpdma_start_channel() on channel %u\n", channel);
+
+ if (!xilinx_dpdma_is_channel_triggered(s, channel)) {
+ DPRINTF("Channel isn't triggered..\n");
+ return 0;
+ }
+
+ if (!xilinx_dpdma_is_channel_enabled(s, channel)) {
+ DPRINTF("Channel isn't enabled..\n");
+ return 0;
+ }
+
+ if (xilinx_dpdma_is_channel_paused(s, channel)) {
+ DPRINTF("Channel is paused..\n");
+ return 0;
+ }
+
+ do {
+ if ((s->operation_finished[channel])
+ || xilinx_dpdma_is_channel_retriggered(s, channel)) {
+ desc_addr = xilinx_dpdma_descriptor_start_address(s, channel);
+ s->operation_finished[channel] = false;
+ } else {
+ desc_addr = xilinx_dpdma_descriptor_next_address(s, channel);
+ }
+
+ if (dma_memory_read(&address_space_memory, desc_addr, &desc,
+ sizeof(DPDMADescriptor))) {
+ s->registers[DPDMA_EISR] |= ((1 << 1) << channel);
+ xilinx_dpdma_update_irq(s);
+ s->operation_finished[channel] = true;
+ DPRINTF("Can't get the descriptor.\n");
+ break;
+ }
+
+ xilinx_dpdma_update_desc_info(s, channel, &desc);
+
+ #ifdef DEBUG_DPDMA
+ xilinx_dpdma_dump_descriptor(&desc);
+ #endif
+
+ DPRINTF("location of the descriptor: 0x%8.8lx\n", desc_addr);
+ if (!xilinx_dpdma_desc_is_valid(&desc)) {
+ s->registers[DPDMA_EISR] |= ((1 << 7) << channel);
+ xilinx_dpdma_update_irq(s);
+ s->operation_finished[channel] = true;
+ DPRINTF("Invalid descriptor..\n");
+ break;
+ }
+
+ if (xilinx_dpdma_desc_crc_enabled(&desc)
+ & !xilinx_dpdma_desc_check_crc(&desc)) {
+ s->registers[DPDMA_EISR] |= ((1 << 13) << channel);
+ xilinx_dpdma_update_irq(s);
+ s->operation_finished[channel] = true;
+ DPRINTF("Bad CRC for descriptor..\n");
+ break;
+ }
+
+ if (xilinx_dpdma_desc_is_already_done(&desc)
+ && !xilinx_dpdma_desc_ignore_done_bit(&desc)) {
+ /* We are trying to process an already processed descriptor. */
+ s->registers[DPDMA_EISR] |= ((1 << 25) << channel);
+ xilinx_dpdma_update_irq(s);
+ s->operation_finished[channel] = true;
+ DPRINTF("Already processed descriptor..\n");
+ break;
+ }
+
+ done = xilinx_dpdma_desc_is_last(&desc)
+ | xilinx_dpdma_desc_is_last_of_frame(&desc);
+
+ s->operation_finished[channel] = done;
+ if (s->data[channel]) {
+ int64_t transfer_len =
+ xilinx_dpdma_desc_get_transfer_size(&desc);
+ uint32_t line_size = xilinx_dpdma_desc_get_line_size(&desc);
+ uint32_t line_stride = xilinx_dpdma_desc_get_line_stride(&desc);
+ if (xilinx_dpdma_desc_is_contiguous(&desc)) {
+ source_addr[0] =
+ xilinx_dpdma_desc_get_source_address(&desc, 0);
+ while (transfer_len != 0) {
+ if (dma_memory_read(&address_space_memory,
+ source_addr[0],
+ &(s->data[channel][ptr]),
+ line_size)) {
+ s->registers[DPDMA_ISR] |= ((1 << 12) << channel);
+ xilinx_dpdma_update_irq(s);
+ DPRINTF("Can't get data.\n");
+ break;
+ }
+ ptr += line_size;
+ transfer_len -= line_size;
+ source_addr[0] += line_stride;
+ }
+ } else {
+ DPRINTF("Source address:\n");
+ int frag;
+ for (frag = 0; frag < 5; frag++) {
+ source_addr[frag] =
+ xilinx_dpdma_desc_get_source_address(&desc, frag);
+ DPRINTF("Fragment %u: 0x%8.8lX\n", frag + 1,
+ source_addr[frag]);
+ }
+
+ frag = 0;
+ while (transfer_len < 0) {
+ if (frag >= 5) {
+ break;
+ }
+ size_t fragment_len = 4096 - (source_addr[frag] % 4096);
+
+ if (dma_memory_read(&address_space_memory,
+ source_addr[frag],
+ &(s->data[channel][ptr]),
+ fragment_len)) {
+ s->registers[DPDMA_ISR] |= ((1 << 12) << channel);
+ xilinx_dpdma_update_irq(s);
+ DPRINTF("Can't get data.\n");
+ break;
+ }
+ ptr += fragment_len;
+ transfer_len -= fragment_len;
+ frag += 1;
+ }
+ }
+ }
+
+ if (xilinx_dpdma_desc_update_enabled(&desc)) {
+ /* The descriptor need to be updated when it's completed. */
+ DPRINTF("update the descriptor with the done flag set.\n");
+ xilinx_dpdma_desc_set_done(&desc);
+ if (dma_memory_write(&address_space_memory, desc_addr, &desc,
+ sizeof(DPDMADescriptor))) {
+ abort();
+ }
+ }
+
+ if (xilinx_dpdma_desc_completion_interrupt(&desc)) {
+ DPRINTF("completion interrupt enabled!\n");
+ s->registers[DPDMA_ISR] |= (1 << channel);
+ xilinx_dpdma_update_irq(s);
+ }
+
+ } while (!done && !one_desc);
+
+ return ptr;
+}
+
+/*
+ * Set the host location to be filled with the data.
+ */
+void xilinx_dpdma_set_host_data_location(XilinxDPDMAState *s, uint8_t channel,
+ void *p)
+{
+ if (!s) {
+ qemu_log_mask(LOG_UNIMP, "DPDMA client not attached to valid DPDMA"
+ " instance\n");
+ return;
+ }
+
+ assert(channel <= 5);
+ s->data[channel] = p;
+}
+
+type_init(xilinx_dpdma_register_types)
diff --git a/hw/dma/xilinx_dpdma.h b/hw/dma/xilinx_dpdma.h
new file mode 100644
index 0000000..f92167d
--- /dev/null
+++ b/hw/dma/xilinx_dpdma.h
@@ -0,0 +1,71 @@
+/*
+ * xilinx_dpdma.h
+ *
+ * Copyright (C) 2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef XILINX_DPDMA_H
+#define XILINX_DPDMA_H
+
+#include "hw/sysbus.h"
+#include "ui/console.h"
+#include "sysemu/dma.h"
+
+struct XilinxDPDMAState {
+ SysBusDevice parent_obj;
+ MemoryRegion iomem;
+ uint32_t registers[0x1000 >> 2];
+ uint8_t *data[6];
+ bool operation_finished[6];
+ qemu_irq irq;
+};
+
+typedef struct XilinxDPDMAState XilinxDPDMAState;
+
+#define TYPE_XILINX_DPDMA "xlnx.dpdma"
+#define XILINX_DPDMA(obj) OBJECT_CHECK(XilinxDPDMAState, (obj), \
+ TYPE_XILINX_DPDMA)
+
+/*
+ * \func xilinx_dpdma_start_operation.
+ * \brief Start the operation on the specified channel. The DPDMA get the
+ * current descriptor and retrieve data to the buffer specified by
+ * dpdma_set_host_data_location.
+ * \arg s The DPDMA instance.
+ * \arg channel The channel to start.
+ * \return the number of byte transfered by the DPDMA or 0 if an error occured.
+ */
+size_t xilinx_dpdma_start_operation(XilinxDPDMAState *s, uint8_t channel,
+ bool one_desc);
+
+/*
+ * \func xilinx_dpdma_set_host_data_location.
+ * \brief Set the location in the host memory where to store the data out from
+ * the dma channel.
+ * \arg s The DPDMA instance.
+ * \arg channel The channel associated to the pointer.
+ * \arg p The buffer where to store the data.
+ */
+/* XXX: add a maximum size arg and send an interrupt in case of overflow. */
+void xilinx_dpdma_set_host_data_location(XilinxDPDMAState *s, uint8_t channel,
+ void *p);
+
+#endif /* !XILINX_DPDMA_H */
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 6/8] Introduce xilinx dpdma.
2015-05-13 19:12 ` [Qemu-devel] [PATCH 6/8] Introduce xilinx dpdma fred.konrad
@ 2015-05-18 8:17 ` Peter Crosthwaite
2015-05-18 8:43 ` Frederic Konrad
0 siblings, 1 reply; 20+ messages in thread
From: Peter Crosthwaite @ 2015-05-18 8:17 UTC (permalink / raw)
To: Fréderic Konrad; +Cc: Mark Burton, qemu-devel@nongnu.org Developers, hyunk
On Wed, May 13, 2015 at 12:12 PM, <fred.konrad@greensocs.com> wrote:
> From: KONRAD Frederic <fred.konrad@greensocs.com>
>
> This is the implementation of the DPDMA.
>
> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
> ---
> hw/dma/Makefile.objs | 1 +
> hw/dma/xilinx_dpdma.c | 1149 +++++++++++++++++++++++++++++++++++++++++++++++++
> hw/dma/xilinx_dpdma.h | 71 +++
> 3 files changed, 1221 insertions(+)
> create mode 100644 hw/dma/xilinx_dpdma.c
> create mode 100644 hw/dma/xilinx_dpdma.h
>
> diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
> index 0e65ed0..7198e5a 100644
> --- a/hw/dma/Makefile.objs
> +++ b/hw/dma/Makefile.objs
> @@ -8,6 +8,7 @@ common-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
> common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
> common-obj-$(CONFIG_STP2000) += sparc32_dma.o
> common-obj-$(CONFIG_SUN4M) += sun4m_iommu.o
> +common-obj-y += xilinx_dpdma.o
Conditional.
>
> obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o
> obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o
> diff --git a/hw/dma/xilinx_dpdma.c b/hw/dma/xilinx_dpdma.c
> new file mode 100644
> index 0000000..6479148
> --- /dev/null
> +++ b/hw/dma/xilinx_dpdma.c
> @@ -0,0 +1,1149 @@
> +/*
> + * xilinx_dpdma.c
> + *
> + * Copyright (C) 2015 : GreenSocs Ltd
> + * http://www.greensocs.com/ , email: info@greensocs.com
> + *
> + * Developed by :
> + * Frederic Konrad <fred.konrad@greensocs.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#include "xilinx_dpdma.h"
> +
> +#ifndef DEBUG_DPDMA
> +#define DEBUG_DPDMA 0
> +#endif
> +
> +#define DPRINTF(fmt, ...) do { \
> + if (DEBUG_DPDMA) { \
> + qemu_log("xilinx_dpdma: " fmt , ## __VA_ARGS__); \
> + } \
> +} while (0);
> +
> +/*
> + * Registers offset for DPDMA.
> + */
> +#define DPDMA_ERR_CTRL (0x00000000)
With only a 0x1000 register address range shouldnt need the 8 hex
digits for offests.
> +#define DPDMA_ISR (0x00000004 >> 2)
> +#define DPDMA_IMR (0x00000008 >> 2)
> +#define DPDMA_IEN (0x0000000C >> 2)
> +#define DPDMA_IDS (0x00000010 >> 2)
> +#define DPDMA_EISR (0x00000014 >> 2)
> +#define DPDMA_EIMR (0x00000018 >> 2)
> +#define DPDMA_EIEN (0x0000001C >> 2)
> +#define DPDMA_EIDS (0x00000020 >> 2)
> +#define DPDMA_CNTL (0x00000100 >> 2)
> +#define DPDMA_GBL (0x00000104 >> 2)
> +#define DPDMA_ALC0_CNTL (0x00000108 >> 2)
> +#define DPDMA_ALC0_STATUS (0x0000010C >> 2)
> +#define DPDMA_ALC0_MAX (0x00000110 >> 2)
> +#define DPDMA_ALC0_MIN (0x00000114 >> 2)
> +#define DPDMA_ALC0_ACC (0x00000118 >> 2)
> +#define DPDMA_ALC0_ACC_TRAN (0x0000011C >> 2)
> +#define DPDMA_ALC1_CNTL (0x00000120 >> 2)
> +#define DPDMA_ALC1_STATUS (0x00000124 >> 2)
> +#define DPDMA_ALC1_MAX (0x00000128 >> 2)
> +#define DPDMA_ALC1_MIN (0x0000012C >> 2)
> +#define DPDMA_ALC1_ACC (0x00000130 >> 2)
> +#define DPDMA_ALC1_ACC_TRAN (0x00000134 >> 2)
> +#define DPDMA_CH0_DSCR_STRT_ADDRE (0x00000200 >> 2)
> +#define DPDMA_CH0_DSCR_STRT_ADDR (0x00000204 >> 2)
> +#define DPDMA_CH0_DSCR_NEXT_ADDRE (0x00000208 >> 2)
> +#define DPDMA_CH0_DSCR_NEXT_ADDR (0x0000020C >> 2)
> +#define DPDMA_CH0_PYLD_CUR_ADDRE (0x00000210 >> 2)
> +#define DPDMA_CH0_PYLD_CUR_ADDR (0x00000214 >> 2)
> +#define DPDMA_CH0_CNTL (0x00000218 >> 2)
> +#define DPDMA_CH0_STATUS (0x0000021C >> 2)
> +#define DPDMA_CH0_VDO (0x00000220 >> 2)
> +#define DPDMA_CH0_PYLD_SZ (0x00000224 >> 2)
> +#define DPDMA_CH0_DSCR_ID (0x00000228 >> 2)
These per-channel addresses should be collapsable using a macro:
#define DPDMA_DSCR_ID_CH(n) ((0x00000228 + n * 100) >> 2)
> +#define DPDMA_CH1_DSCR_STRT_ADDRE (0x00000300 >> 2)
> +#define DPDMA_CH1_DSCR_STRT_ADDR (0x00000304 >> 2)
> +#define DPDMA_CH1_DSCR_NEXT_ADDRE (0x00000308 >> 2)
> +#define DPDMA_CH1_DSCR_NEXT_ADDR (0x0000030C >> 2)
> +#define DPDMA_CH1_PYLD_CUR_ADDRE (0x00000310 >> 2)
> +#define DPDMA_CH1_PYLD_CUR_ADDR (0x00000314 >> 2)
> +#define DPDMA_CH1_CNTL (0x00000318 >> 2)
> +#define DPDMA_CH1_STATUS (0x0000031C >> 2)
> +#define DPDMA_CH1_VDO (0x00000320 >> 2)
> +#define DPDMA_CH1_PYLD_SZ (0x00000324 >> 2)
> +#define DPDMA_CH1_DSCR_ID (0x00000328 >> 2)
> +#define DPDMA_CH2_DSCR_STRT_ADDRE (0x00000400 >> 2)
> +#define DPDMA_CH2_DSCR_STRT_ADDR (0x00000404 >> 2)
> +#define DPDMA_CH2_DSCR_NEXT_ADDRE (0x00000408 >> 2)
> +#define DPDMA_CH2_DSCR_NEXT_ADDR (0x0000040C >> 2)
> +#define DPDMA_CH2_PYLD_CUR_ADDRE (0x00000410 >> 2)
> +#define DPDMA_CH2_PYLD_CUR_ADDR (0x00000414 >> 2)
> +#define DPDMA_CH2_CNTL (0x00000418 >> 2)
> +#define DPDMA_CH2_STATUS (0x0000041C >> 2)
> +#define DPDMA_CH2_VDO (0x00000420 >> 2)
> +#define DPDMA_CH2_PYLD_SZ (0x00000424 >> 2)
> +#define DPDMA_CH2_DSCR_ID (0x00000428 >> 2)
> +#define DPDMA_CH3_DSCR_STRT_ADDRE (0x00000500 >> 2)
> +#define DPDMA_CH3_DSCR_STRT_ADDR (0x00000504 >> 2)
> +#define DPDMA_CH3_DSCR_NEXT_ADDRE (0x00000508 >> 2)
> +#define DPDMA_CH3_DSCR_NEXT_ADDR (0x0000050C >> 2)
> +#define DPDMA_CH3_PYLD_CUR_ADDRE (0x00000510 >> 2)
> +#define DPDMA_CH3_PYLD_CUR_ADDR (0x00000514 >> 2)
> +#define DPDMA_CH3_CNTL (0x00000518 >> 2)
> +#define DPDMA_CH3_STATUS (0x0000051C >> 2)
> +#define DPDMA_CH3_VDO (0x00000520 >> 2)
> +#define DPDMA_CH3_PYLD_SZ (0x00000524 >> 2)
> +#define DPDMA_CH3_DSCR_ID (0x00000528 >> 2)
> +#define DPDMA_CH4_DSCR_STRT_ADDRE (0x00000600 >> 2)
> +#define DPDMA_CH4_DSCR_STRT_ADDR (0x00000604 >> 2)
> +#define DPDMA_CH4_DSCR_NEXT_ADDRE (0x00000608 >> 2)
> +#define DPDMA_CH4_DSCR_NEXT_ADDR (0x0000060C >> 2)
> +#define DPDMA_CH4_PYLD_CUR_ADDRE (0x00000610 >> 2)
> +#define DPDMA_CH4_PYLD_CUR_ADDR (0x00000614 >> 2)
> +#define DPDMA_CH4_CNTL (0x00000618 >> 2)
> +#define DPDMA_CH4_STATUS (0x0000061C >> 2)
> +#define DPDMA_CH4_VDO (0x00000620 >> 2)
> +#define DPDMA_CH4_PYLD_SZ (0x00000624 >> 2)
> +#define DPDMA_CH4_DSCR_ID (0x00000628 >> 2)
> +#define DPDMA_CH5_DSCR_STRT_ADDRE (0x00000700 >> 2)
> +#define DPDMA_CH5_DSCR_STRT_ADDR (0x00000704 >> 2)
> +#define DPDMA_CH5_DSCR_NEXT_ADDRE (0x00000708 >> 2)
> +#define DPDMA_CH5_DSCR_NEXT_ADDR (0x0000070C >> 2)
> +#define DPDMA_CH5_PYLD_CUR_ADDRE (0x00000710 >> 2)
> +#define DPDMA_CH5_PYLD_CUR_ADDR (0x00000714 >> 2)
> +#define DPDMA_CH5_CNTL (0x00000718 >> 2)
> +#define DPDMA_CH5_STATUS (0x0000071C >> 2)
> +#define DPDMA_CH5_VDO (0x00000720 >> 2)
> +#define DPDMA_CH5_PYLD_SZ (0x00000724 >> 2)
> +#define DPDMA_CH5_DSCR_ID (0x00000728 >> 2)
> +#define DPDMA_ECO (0x00000FFC >> 2)
> +
Drop ECO field.
> +/*
> + * Descriptor control field.
> + */
> +#define CONTROL_PREAMBLE_VALUE 0xA5
> +
> +#define CONTROL_PREAMBLE 0xFF
> +#define EN_DSCR_DONE_INTR (1 << 8)
> +#define EN_DSCR_UPDATE (1 << 9)
> +#define IGNORE_DONE (1 << 10)
> +#define AXI_BURST_TYPE (1 << 11)
> +#define AXCACHE (0x0F << 12)
> +#define AXPROT (0x2 << 16)
> +#define DESCRIPTOR_MODE (1 << 18)
> +#define LAST_DESCRIPTOR (1 << 19)
> +#define ENABLE_CRC (1 << 20)
> +#define LAST_DESCRIPTOR_OF_FRAME (1 << 21)
> +
> +typedef enum DPDMABurstType {
> + DPDMA_INCR = 0,
> + DPDMA_FIXED = 1
> +} DPDMABurstType;
> +
> +typedef enum DPDMAMode {
> + DPDMA_CONTIGOUS = 0,
> + DPDMA_FRAGMENTED = 1
> +} DPDMAMode;
> +
> +typedef struct DPDMADescriptor {
> + uint32_t control;
> + uint32_t descriptor_id;
> + /* transfer size in byte. */
> + uint32_t xfer_size;
> + uint32_t line_size_stride;
> + uint32_t timestamp_lsb;
> + uint32_t timestamp_msb;
> + /* contains extension for both descriptor and source. */
> + uint32_t address_extension;
> + uint32_t next_descriptor;
> + uint32_t source_address;
> + uint32_t address_extension_23;
> + uint32_t address_extension_45;
> + uint32_t source_address2;
> + uint32_t source_address3;
> + uint32_t source_address4;
> + uint32_t source_address5;
> + uint32_t crc;
> +} DPDMADescriptor;
> +
> +static bool xilinx_dpdma_desc_is_last(DPDMADescriptor *desc)
> +{
> + return ((desc->control & 0x00080000) != 0);
Single bit extract32s are cleaner IMO (check the AArch64 translate
code where they started using them).
> +}
> +
> +static bool xilinx_dpdma_desc_is_last_of_frame(DPDMADescriptor *desc)
> +{
> + return ((desc->control & 0x00200000) != 0);
> +}
> +
> +static uint64_t xilinx_dpdma_desc_get_source_address(DPDMADescriptor *desc,
> + uint8_t frag)
> +{
> + uint64_t addr = 0;
> + assert(frag < 5);
> +
> + switch (frag) {
> + case 0:
> + addr = desc->source_address
> + + (extract32(desc->address_extension, 16, 12) << 20);
> + break;
> + case 1:
> + addr = desc->source_address2
> + + (extract32(desc->address_extension_23, 0, 12) << 8);
> + break;
> + case 2:
> + addr = desc->source_address3
> + + (extract32(desc->address_extension_23, 16, 12) << 20);
> + break;
> + case 3:
> + addr = desc->source_address4
> + + (extract32(desc->address_extension_45, 0, 12) << 8);
> + break;
> + case 4:
> + addr = desc->source_address5
> + + (extract32(desc->address_extension_45, 16, 12) << 20);
> + break;
> + default:
> + addr = 0;
> + break;
> + }
> +
> + return addr;
> +}
> +
> +static uint32_t xilinx_dpdma_desc_get_transfer_size(DPDMADescriptor *desc)
> +{
> + return desc->xfer_size;
> +}
> +
> +static uint32_t xilinx_dpdma_desc_get_line_size(DPDMADescriptor *desc)
> +{
> + return desc->line_size_stride & 0x3FFFF;
extract.
> +}
> +
> +static uint32_t xilinx_dpdma_desc_get_line_stride(DPDMADescriptor *desc)
> +{
> + return (desc->line_size_stride >> 18) * 16;
extract.
> +}
> +
> +static inline bool xilinx_dpdma_desc_crc_enabled(DPDMADescriptor *desc)
> +{
> + return ((desc->control & (1 << 20)) != 0);
> +}
> +
> +static inline bool xilinx_dpdma_desc_check_crc(DPDMADescriptor *desc)
> +{
> + uint32_t *p = (uint32_t *)(desc);
parenthesis not needed.
> + uint32_t crc = 0;
> + uint8_t i;
> +
> + for (i = 0; i < 15; i++) {
Does 15 need a macro? Is it the descriptor length?
> + crc += p[i];
> + }
> +
> + return (crc == desc->crc);
> +}
> +
> +static inline bool xilinx_dpdma_desc_completion_interrupt(DPDMADescriptor *desc)
> +{
> + return ((desc->control & (1 << 8)) != 0);
> +}
> +
> +static inline bool xilinx_dpdma_desc_is_valid(DPDMADescriptor *desc)
> +{
> + return ((desc->control & 0xFF) == 0xA5);
> +}
> +
> +static inline bool xilinx_dpdma_desc_is_contiguous(DPDMADescriptor *desc)
> +{
> + return ((desc->control & 0x00040000) == 0);
> +}
> +
> +static inline bool xilinx_dpdma_desc_update_enabled(DPDMADescriptor *desc)
> +{
> + return ((desc->control & (1 << 9)) != 0);
> +}
> +
> +static inline void xilinx_dpdma_desc_set_done(DPDMADescriptor *desc)
> +{
> + desc->timestamp_msb |= (1 << 31);
> +}
> +
> +static inline bool xilinx_dpdma_desc_is_already_done(DPDMADescriptor *desc)
> +{
> + return ((desc->timestamp_msb & (1 << 31)) != 0);
> +}
> +
> +static inline bool xilinx_dpdma_desc_ignore_done_bit(DPDMADescriptor *desc)
> +{
> + return ((desc->control & (1 << 10)) != 0);
> +}
> +
> +static const VMStateDescription vmstate_xilinx_dpdma = {
> + .name = TYPE_XILINX_DPDMA,
> + .version_id = 1,
> + .fields = (VMStateField[]) {
> +
I think this needs population?
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static void xilinx_dpdma_update_irq(XilinxDPDMAState *s)
> +{
> + uint32_t flags;
> +
> + flags = ((s->registers[DPDMA_ISR] & (~s->registers[DPDMA_IMR]))
> + | (s->registers[DPDMA_EISR] & (~s->registers[DPDMA_EIMR])));
> + qemu_set_irq(s->irq, flags != 0);
> +}
> +
> +static uint64_t xilinx_dpdma_descriptor_start_address(XilinxDPDMAState *s,
> + uint8_t channel)
> +{
> + switch (channel) {
> + case 0:
> + return (s->registers[DPDMA_CH0_DSCR_STRT_ADDRE] << 16)
> + + s->registers[DPDMA_CH0_DSCR_STRT_ADDR];
> + break;
> + case 1:
> + return (s->registers[DPDMA_CH1_DSCR_STRT_ADDRE] << 16)
> + + s->registers[DPDMA_CH1_DSCR_STRT_ADDR];
> + break;
> + case 2:
> + return (s->registers[DPDMA_CH2_DSCR_STRT_ADDRE] << 16)
> + + s->registers[DPDMA_CH2_DSCR_STRT_ADDR];
> + break;
> + case 3:
> + return (s->registers[DPDMA_CH3_DSCR_STRT_ADDRE] << 16)
> + + s->registers[DPDMA_CH3_DSCR_STRT_ADDR];
> + break;
> + case 4:
> + return (s->registers[DPDMA_CH4_DSCR_STRT_ADDRE] << 16)
> + + s->registers[DPDMA_CH4_DSCR_STRT_ADDR];
> + break;
> + case 5:
> + return (s->registers[DPDMA_CH5_DSCR_STRT_ADDRE] << 16)
> + + s->registers[DPDMA_CH5_DSCR_STRT_ADDR];
> + break;
Can the 6X repetition be collapsed using some indexing math?
> + default:
> + /* Should not happen. */
> + return 0;
> + break;
> + }
> +}
> +
> +static uint64_t xilinx_dpdma_descriptor_next_address(XilinxDPDMAState *s,
> + uint8_t channel)
> +{
> + switch (channel) {
> + case 0:
> + return ((uint64_t)s->registers[DPDMA_CH0_DSCR_NEXT_ADDRE] << 32)
> + + s->registers[DPDMA_CH0_DSCR_NEXT_ADDR];
> + break;
> + case 1:
> + return ((uint64_t)s->registers[DPDMA_CH1_DSCR_NEXT_ADDRE] << 32)
> + + s->registers[DPDMA_CH1_DSCR_NEXT_ADDR];
> + break;
> + case 2:
> + return ((uint64_t)s->registers[DPDMA_CH2_DSCR_NEXT_ADDRE] << 32)
> + + s->registers[DPDMA_CH2_DSCR_NEXT_ADDR];
> + break;
> + case 3:
> + return ((uint64_t)s->registers[DPDMA_CH3_DSCR_NEXT_ADDRE] << 32)
> + + s->registers[DPDMA_CH3_DSCR_NEXT_ADDR];
> + break;
> + case 4:
> + return ((uint64_t)s->registers[DPDMA_CH4_DSCR_NEXT_ADDRE] << 32)
> + + s->registers[DPDMA_CH4_DSCR_NEXT_ADDR];
> + break;
> + case 5:
> + return ((uint64_t)s->registers[DPDMA_CH5_DSCR_NEXT_ADDRE] << 32)
> + + s->registers[DPDMA_CH5_DSCR_NEXT_ADDR];
> + break;
same.
> + default:
> + /* Should not happen. */
> + return 0;
> + break;
> + }
> +}
> +
> +static inline void xilinx_dpdma_set_desc_next_address(XilinxDPDMAState *s,
> + uint8_t channel,
> + uint64_t addr)
> +{
> + switch (channel) {
> + case 0:
> + s->registers[DPDMA_CH0_DSCR_NEXT_ADDRE] = addr >> 32;
> + s->registers[DPDMA_CH0_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
extract64
> + break;
> + case 1:
> + s->registers[DPDMA_CH1_DSCR_NEXT_ADDRE] = addr >> 32;
> + s->registers[DPDMA_CH1_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
> + break;
> + case 2:
> + s->registers[DPDMA_CH2_DSCR_NEXT_ADDRE] = addr >> 32;
> + s->registers[DPDMA_CH2_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
> + break;
> + case 3:
> + s->registers[DPDMA_CH3_DSCR_NEXT_ADDRE] = addr >> 32;
> + s->registers[DPDMA_CH3_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
> + break;
> + case 4:
> + s->registers[DPDMA_CH4_DSCR_NEXT_ADDRE] = addr >> 32;
> + s->registers[DPDMA_CH4_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
> + break;
> + case 5:
> + s->registers[DPDMA_CH5_DSCR_NEXT_ADDRE] = addr >> 32;
> + s->registers[DPDMA_CH5_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
> + break;
repetition.
> + default:
> + /* Should not happen. */
> + break;
> + }
> +}
> +
> +static bool xilinx_dpdma_is_channel_enabled(XilinxDPDMAState *s,
> + uint8_t channel)
> +{
> + switch (channel) {
> + case 0:
> + return ((s->registers[DPDMA_CH0_CNTL] & 0x01) != 0);
0x1 needs macro definition.
> + break;
unreachable break statements.
> + case 1:
> + return ((s->registers[DPDMA_CH1_CNTL] & 0x01) != 0);
> + break;
> + case 2:
> + return ((s->registers[DPDMA_CH2_CNTL] & 0x01) != 0);
> + break;
> + case 3:
> + return ((s->registers[DPDMA_CH3_CNTL] & 0x01) != 0);
> + break;
> + case 4:
> + return ((s->registers[DPDMA_CH4_CNTL] & 0x01) != 0);
> + break;
> + case 5:
> + return ((s->registers[DPDMA_CH5_CNTL] & 0x01) != 0);
> + break;
> + default:
> + /* Should not happen. */
> + return 0;
> + break;
> + }
> +}
> +
> +static bool xilinx_dpdma_is_channel_paused(XilinxDPDMAState *s,
> + uint8_t channel)
> +{
> + switch (channel) {
> + case 0:
> + return ((s->registers[DPDMA_CH0_CNTL] & 0x02) != 0);
> + break;
> + case 1:
> + return ((s->registers[DPDMA_CH1_CNTL] & 0x02) != 0);
> + break;
> + case 2:
> + return ((s->registers[DPDMA_CH2_CNTL] & 0x02) != 0);
> + break;
> + case 3:
> + return ((s->registers[DPDMA_CH3_CNTL] & 0x02) != 0);
> + break;
> + case 4:
> + return ((s->registers[DPDMA_CH4_CNTL] & 0x02) != 0);
> + break;
> + case 5:
> + return ((s->registers[DPDMA_CH5_CNTL] & 0x02) != 0);
> + break;
Same comments as above.
> + default:
> + /* Should not happen. */
> + return 0;
> + break;
> + }
> +}
> +
> +static inline bool xilinx_dpdma_is_channel_retriggered(XilinxDPDMAState *s,
> + uint8_t channel)
> +{
> + return s->registers[DPDMA_GBL] & ((1 << 6) << channel);
> +}
> +
> +static inline bool xilinx_dpdma_is_channel_triggered(XilinxDPDMAState *s,
> + uint8_t channel)
> +{
> + return s->registers[DPDMA_GBL] & (1 << channel);
> +}
> +
> +static void xilinx_dpdma_update_desc_info(XilinxDPDMAState *s, uint8_t channel,
> + DPDMADescriptor *desc)
> +{
> + switch (channel) {
> + case 0:
> + s->registers[DPDMA_CH0_DSCR_NEXT_ADDRE] = desc->address_extension
> + & 0x0000FFFF;
extract for consistency with code below.
> + s->registers[DPDMA_CH0_DSCR_NEXT_ADDR] = desc->next_descriptor;
> + s->registers[DPDMA_CH0_PYLD_CUR_ADDRE] =
> + extract32(desc->address_extension, 16, 16);
> + s->registers[DPDMA_CH0_PYLD_CUR_ADDR] = desc->source_address;
> + s->registers[DPDMA_CH0_VDO] = extract32(desc->line_size_stride, 18, 14)
> + + (extract32(desc->line_size_stride, 0, 18)
> + << 14);
> + s->registers[DPDMA_CH0_PYLD_SZ] = desc->xfer_size;
> + s->registers[DPDMA_CH0_DSCR_ID] = desc->descriptor_id;
> +
> + /* Compute the status register with the descriptor information. */
> + s->registers[DPDMA_CH0_STATUS] = (desc->control & 0xFF) << 13;
> + if ((desc->control & (1 << 8)) != 0) {
> + s->registers[DPDMA_CH0_STATUS] |= (1 << 12);
> + }
> + if ((desc->control & (1 << 9)) != 0) {
> + s->registers[DPDMA_CH0_STATUS] |= (1 << 11);
> + }
> + if ((desc->timestamp_msb & (1 << 31)) != 0) {
> + s->registers[DPDMA_CH0_STATUS] |= (1 << 10);
> + }
> + if ((desc->control & (1 << 10)) != 0) {
> + s->registers[DPDMA_CH0_STATUS] |= (1 << 9);
> + }
> + if ((desc->control & (1 << 21)) != 0) {
> + s->registers[DPDMA_CH0_STATUS] |= (1 << 8);
> + }
> + if ((desc->control & (1 << 19)) != 0) {
> + s->registers[DPDMA_CH0_STATUS] |= (1 << 7);
> + }
> + if ((desc->control & (1 << 20)) != 0) {
> + s->registers[DPDMA_CH0_STATUS] |= (1 << 6);
> + }
> + if ((desc->control & (1 << 18)) != 0) {
> + s->registers[DPDMA_CH0_STATUS] |= (1 << 5);
> + }
> + if ((desc->control & (1 << 11)) != 0) {
> + s->registers[DPDMA_CH0_STATUS] |= (1 << 4);
> + }
> + /* XXX: BURST_LEN? */
What does this mean?
> + break;
> + case 1:
> + s->registers[DPDMA_CH1_DSCR_NEXT_ADDRE] = desc->address_extension
> + & 0x0000FFFF;
> + s->registers[DPDMA_CH1_DSCR_NEXT_ADDR] = desc->next_descriptor;
> + s->registers[DPDMA_CH1_PYLD_CUR_ADDRE] =
> + extract32(desc->address_extension, 16, 16);
> + s->registers[DPDMA_CH1_PYLD_CUR_ADDR] = desc->source_address;
> + s->registers[DPDMA_CH1_VDO] = extract32(desc->line_size_stride, 18, 14)
> + + (extract32(desc->line_size_stride, 0, 18)
> + << 14);
> + s->registers[DPDMA_CH1_PYLD_SZ] = desc->xfer_size;
> + s->registers[DPDMA_CH1_DSCR_ID] = desc->descriptor_id;
> +
> + /* Compute the status register with the descriptor information. */
> + s->registers[DPDMA_CH1_STATUS] = (desc->control & 0xFF) << 13;
> + if ((desc->control & (1 << 8)) != 0) {
> + s->registers[DPDMA_CH1_STATUS] |= (1 << 12);
> + }
> + if ((desc->control & (1 << 9)) != 0) {
> + s->registers[DPDMA_CH1_STATUS] |= (1 << 11);
> + }
> + if ((desc->timestamp_msb & (1 << 31)) != 0) {
> + s->registers[DPDMA_CH1_STATUS] |= (1 << 10);
> + }
> + if ((desc->control & (1 << 10)) != 0) {
> + s->registers[DPDMA_CH1_STATUS] |= (1 << 9);
> + }
> + if ((desc->control & (1 << 21)) != 0) {
> + s->registers[DPDMA_CH1_STATUS] |= (1 << 8);
> + }
> + if ((desc->control & (1 << 19)) != 0) {
> + s->registers[DPDMA_CH1_STATUS] |= (1 << 7);
> + }
> + if ((desc->control & (1 << 20)) != 0) {
> + s->registers[DPDMA_CH1_STATUS] |= (1 << 6);
> + }
> + if ((desc->control & (1 << 18)) != 0) {
> + s->registers[DPDMA_CH1_STATUS] |= (1 << 5);
> + }
> + if ((desc->control & (1 << 11)) != 0) {
> + s->registers[DPDMA_CH1_STATUS] |= (1 << 4);
> + }
> + /* XXX: BURST_LEN? */
> + break;
> + case 2:
> + s->registers[DPDMA_CH2_DSCR_NEXT_ADDRE] = desc->address_extension
> + & 0x0000FFFF;
> + s->registers[DPDMA_CH2_DSCR_NEXT_ADDR] = desc->next_descriptor;
> + s->registers[DPDMA_CH2_PYLD_CUR_ADDRE] =
> + extract32(desc->address_extension, 16, 16);
> + s->registers[DPDMA_CH2_PYLD_CUR_ADDR] = desc->source_address;
> + s->registers[DPDMA_CH2_VDO] = extract32(desc->line_size_stride, 18, 14)
> + + (extract32(desc->line_size_stride, 0, 18)
> + << 14);
> + s->registers[DPDMA_CH2_PYLD_SZ] = desc->xfer_size;
> + s->registers[DPDMA_CH2_DSCR_ID] = desc->descriptor_id;
> +
> + /* Compute the status register with the descriptor information. */
> + s->registers[DPDMA_CH2_STATUS] = (desc->control & 0xFF) << 13;
> + if ((desc->control & (1 << 8)) != 0) {
> + s->registers[DPDMA_CH2_STATUS] |= (1 << 12);
> + }
> + if ((desc->control & (1 << 9)) != 0) {
> + s->registers[DPDMA_CH2_STATUS] |= (1 << 11);
> + }
> + if ((desc->timestamp_msb & (1 << 31)) != 0) {
> + s->registers[DPDMA_CH2_STATUS] |= (1 << 10);
> + }
> + if ((desc->control & (1 << 10)) != 0) {
> + s->registers[DPDMA_CH2_STATUS] |= (1 << 9);
> + }
> + if ((desc->control & (1 << 21)) != 0) {
> + s->registers[DPDMA_CH2_STATUS] |= (1 << 8);
> + }
> + if ((desc->control & (1 << 19)) != 0) {
> + s->registers[DPDMA_CH2_STATUS] |= (1 << 7);
> + }
> + if ((desc->control & (1 << 20)) != 0) {
> + s->registers[DPDMA_CH2_STATUS] |= (1 << 6);
> + }
> + if ((desc->control & (1 << 18)) != 0) {
> + s->registers[DPDMA_CH2_STATUS] |= (1 << 5);
> + }
> + if ((desc->control & (1 << 11)) != 0) {
> + s->registers[DPDMA_CH2_STATUS] |= (1 << 4);
> + }
> + /* XXX: BURST_LEN? */
> + break;
Ok definately want to do something about the repetition on this one.
If the variable numbers are regular use math to calculate them. If
they are irregular make some data table arrays that can be indexed on
the switch variable.
> + case 3:
> + s->registers[DPDMA_CH3_DSCR_NEXT_ADDRE] = desc->address_extension
> + & 0x0000FFFF;
> + s->registers[DPDMA_CH3_DSCR_NEXT_ADDR] = desc->next_descriptor;
> + s->registers[DPDMA_CH3_PYLD_CUR_ADDRE] =
> + extract32(desc->address_extension, 16, 16);
> + s->registers[DPDMA_CH3_PYLD_CUR_ADDR] = desc->source_address;
> + s->registers[DPDMA_CH3_VDO] = extract32(desc->line_size_stride, 18, 14)
> + + (extract32(desc->line_size_stride, 0, 18)
> + << 14);
> + s->registers[DPDMA_CH3_PYLD_SZ] = desc->xfer_size;
> + s->registers[DPDMA_CH3_DSCR_ID] = desc->descriptor_id;
> +
> + /* Compute the status register with the descriptor information. */
> + s->registers[DPDMA_CH3_STATUS] = (desc->control & 0xFF) << 13;
> + if ((desc->control & (1 << 8)) != 0) {
> + s->registers[DPDMA_CH3_STATUS] |= (1 << 12);
> + }
> + if ((desc->control & (1 << 9)) != 0) {
> + s->registers[DPDMA_CH3_STATUS] |= (1 << 11);
> + }
> + if ((desc->timestamp_msb & (1 << 31)) != 0) {
> + s->registers[DPDMA_CH3_STATUS] |= (1 << 10);
> + }
> + if ((desc->control & (1 << 10)) != 0) {
> + s->registers[DPDMA_CH3_STATUS] |= (1 << 9);
> + }
> + if ((desc->control & (1 << 21)) != 0) {
> + s->registers[DPDMA_CH3_STATUS] |= (1 << 8);
> + }
> + if ((desc->control & (1 << 19)) != 0) {
> + s->registers[DPDMA_CH3_STATUS] |= (1 << 7);
> + }
> + if ((desc->control & (1 << 20)) != 0) {
> + s->registers[DPDMA_CH3_STATUS] |= (1 << 6);
> + }
> + if ((desc->control & (1 << 18)) != 0) {
> + s->registers[DPDMA_CH3_STATUS] |= (1 << 5);
> + }
> + if ((desc->control & (1 << 11)) != 0) {
> + s->registers[DPDMA_CH3_STATUS] |= (1 << 4);
> + }
> + /* XXX: BURST_LEN? */
> + break;
> + case 4:
> + s->registers[DPDMA_CH4_DSCR_NEXT_ADDRE] = desc->address_extension
> + & 0x0000FFFF;
> + s->registers[DPDMA_CH4_DSCR_NEXT_ADDR] = desc->next_descriptor;
> + s->registers[DPDMA_CH4_PYLD_CUR_ADDRE] =
> + extract32(desc->address_extension, 16, 16);
> + s->registers[DPDMA_CH4_PYLD_CUR_ADDR] = desc->source_address;
> + s->registers[DPDMA_CH4_VDO] = extract32(desc->line_size_stride, 18, 14)
> + + (extract32(desc->line_size_stride, 0, 18)
> + << 14);
> + s->registers[DPDMA_CH4_PYLD_SZ] = desc->xfer_size;
> + s->registers[DPDMA_CH4_DSCR_ID] = desc->descriptor_id;
> +
> + /* Compute the status register with the descriptor information. */
> + s->registers[DPDMA_CH4_STATUS] = (desc->control & 0xFF) << 13;
> + if ((desc->control & (1 << 8)) != 0) {
> + s->registers[DPDMA_CH4_STATUS] |= (1 << 12);
> + }
> + if ((desc->control & (1 << 9)) != 0) {
> + s->registers[DPDMA_CH4_STATUS] |= (1 << 11);
> + }
> + if ((desc->timestamp_msb & (1 << 31)) != 0) {
> + s->registers[DPDMA_CH4_STATUS] |= (1 << 10);
> + }
> + if ((desc->control & (1 << 10)) != 0) {
> + s->registers[DPDMA_CH4_STATUS] |= (1 << 9);
> + }
> + if ((desc->control & (1 << 21)) != 0) {
> + s->registers[DPDMA_CH4_STATUS] |= (1 << 8);
> + }
> + if ((desc->control & (1 << 19)) != 0) {
> + s->registers[DPDMA_CH4_STATUS] |= (1 << 7);
> + }
> + if ((desc->control & (1 << 20)) != 0) {
> + s->registers[DPDMA_CH4_STATUS] |= (1 << 6);
> + }
> + if ((desc->control & (1 << 18)) != 0) {
> + s->registers[DPDMA_CH4_STATUS] |= (1 << 5);
> + }
> + if ((desc->control & (1 << 11)) != 0) {
> + s->registers[DPDMA_CH4_STATUS] |= (1 << 4);
> + }
> + /* XXX: BURST_LEN? */
> + break;
> + case 5:
> + s->registers[DPDMA_CH5_DSCR_NEXT_ADDRE] = desc->address_extension
> + & 0x0000FFFF;
> + s->registers[DPDMA_CH5_DSCR_NEXT_ADDR] = desc->next_descriptor;
> + s->registers[DPDMA_CH5_PYLD_CUR_ADDRE] =
> + extract32(desc->address_extension, 16, 16);
> + s->registers[DPDMA_CH5_PYLD_CUR_ADDR] = desc->source_address;
> + s->registers[DPDMA_CH5_VDO] = extract32(desc->line_size_stride, 18, 14)
> + + (extract32(desc->line_size_stride, 0, 18)
> + << 14);
> + s->registers[DPDMA_CH5_PYLD_SZ] = desc->xfer_size;
> + s->registers[DPDMA_CH5_DSCR_ID] = desc->descriptor_id;
> +
> + /* Compute the status register with the descriptor information. */
> + s->registers[DPDMA_CH5_STATUS] = (desc->control & 0xFF) << 13;
> + if ((desc->control & (1 << 8)) != 0) {
> + s->registers[DPDMA_CH5_STATUS] |= (1 << 12);
> + }
> + if ((desc->control & (1 << 9)) != 0) {
> + s->registers[DPDMA_CH5_STATUS] |= (1 << 11);
Number 9 and 11 and those below need macroification.
> + }
> + if ((desc->timestamp_msb & (1 << 31)) != 0) {
> + s->registers[DPDMA_CH5_STATUS] |= (1 << 10);
> + }
> + if ((desc->control & (1 << 10)) != 0) {
> + s->registers[DPDMA_CH5_STATUS] |= (1 << 9);
> + }
> + if ((desc->control & (1 << 21)) != 0) {
> + s->registers[DPDMA_CH5_STATUS] |= (1 << 8);
> + }
> + if ((desc->control & (1 << 19)) != 0) {
> + s->registers[DPDMA_CH5_STATUS] |= (1 << 7);
> + }
> + if ((desc->control & (1 << 20)) != 0) {
> + s->registers[DPDMA_CH5_STATUS] |= (1 << 6);
> + }
> + if ((desc->control & (1 << 18)) != 0) {
> + s->registers[DPDMA_CH5_STATUS] |= (1 << 5);
> + }
> + if ((desc->control & (1 << 11)) != 0) {
> + s->registers[DPDMA_CH5_STATUS] |= (1 << 4);
> + }
> + /* XXX: BURST_LEN? */
> + break;
> + default:
> + break;
> + }
> +}
> +
> +#ifdef DEBUG_DPDMA
> +static void xilinx_dpdma_dump_descriptor(DPDMADescriptor *desc)
> +{
> + uint8_t *p = ((uint8_t *)(desc));
Two sets of unneeded parenthesis.
> + size_t i;
> +
> + qemu_log("DUMP DESCRIPTOR:\n");
> + for (i = 0; i < 64; i++) {
> + qemu_log(" 0x%2.2X", *p++);
The 0x infront of each byte is hard to read.
Would you need a PRIx8 here?
> + if (((i + 1) % 4) == 0) {
> + qemu_log("\n");
> + }
> + }
qemu_hexdump can do this though.
> +}
> +#endif
> +
> +static uint64_t xilinx_dpdma_read(void *opaque, hwaddr offset,
> + unsigned size)
> +{
> + XilinxDPDMAState *s = XILINX_DPDMA(opaque);
Blank line.
> + assert(size == 4);
> + assert((offset % 4) == 0);
Memory API can enforce this with the MemoryRegionOps and assertions
can be dropped.
> + offset = offset >> 2;
> + DPRINTF("read @%" PRIx64 "\n", offset << 2);
> +
> + switch (offset) {
> + /*
> + * Trying to read a write only register.
> + */
> + case DPDMA_GBL:
> + return 0;
> + break;
Unreachable break.
> + default:
> + assert(offset <= (0xFFC >> 2));
> + return s->registers[offset];
> + break;
> + }
> + return 0;
> +}
> +
> +static void xilinx_dpdma_write(void *opaque, hwaddr offset,
> + uint64_t value, unsigned size)
> +{
> + XilinxDPDMAState *s = XILINX_DPDMA(opaque);
> + assert(size == 4);
> + assert((offset % 4) == 0);
Same comments.
> + offset = offset >> 2;
> + DPRINTF("write @%" PRIx64 " = 0x%8.8lX\n", offset << 2, value);
Formats dont look right. Should it be a HWADDR_PRIx and then a PRIx64?
Print first then shift.
> +
> + switch (offset) {
> + case DPDMA_ISR:
> + value = ~value;
> + s->registers[DPDMA_ISR] &= value;
&= ~value to save a LOC.
> + xilinx_dpdma_update_irq(s);
> + break;
> + case DPDMA_IEN:
> + value = ~value;
> + s->registers[DPDMA_IMR] &= value;
> + break;
> + case DPDMA_IDS:
> + s->registers[DPDMA_IMR] |= value;
> + break;
> + case DPDMA_EISR:
> + value = ~value;
> + s->registers[DPDMA_EISR] &= value;
> + xilinx_dpdma_update_irq(s);
> + break;
> + case DPDMA_EIEN:
> + value = ~value;
> + s->registers[DPDMA_EIMR] &= value;
> + break;
> + case DPDMA_EIDS:
> + s->registers[DPDMA_EIMR] |= value;
> + break;
> + case DPDMA_IMR:
> + case DPDMA_EIMR:
> + case DPDMA_CH0_DSCR_NEXT_ADDRE:
> + case DPDMA_CH0_DSCR_NEXT_ADDR:
> + case DPDMA_CH1_DSCR_NEXT_ADDRE:
> + case DPDMA_CH1_DSCR_NEXT_ADDR:
> + case DPDMA_CH2_DSCR_NEXT_ADDRE:
> + case DPDMA_CH2_DSCR_NEXT_ADDR:
> + case DPDMA_CH3_DSCR_NEXT_ADDRE:
> + case DPDMA_CH3_DSCR_NEXT_ADDR:
> + case DPDMA_CH4_DSCR_NEXT_ADDRE:
> + case DPDMA_CH4_DSCR_NEXT_ADDR:
> + case DPDMA_CH5_DSCR_NEXT_ADDRE:
> + case DPDMA_CH5_DSCR_NEXT_ADDR:
> + case DPDMA_CH0_PYLD_CUR_ADDRE:
> + case DPDMA_CH0_PYLD_CUR_ADDR:
> + case DPDMA_CH1_PYLD_CUR_ADDRE:
> + case DPDMA_CH1_PYLD_CUR_ADDR:
> + case DPDMA_CH2_PYLD_CUR_ADDRE:
> + case DPDMA_CH2_PYLD_CUR_ADDR:
> + case DPDMA_CH3_PYLD_CUR_ADDRE:
> + case DPDMA_CH3_PYLD_CUR_ADDR:
> + case DPDMA_CH4_PYLD_CUR_ADDRE:
> + case DPDMA_CH4_PYLD_CUR_ADDR:
> + case DPDMA_CH5_PYLD_CUR_ADDRE:
> + case DPDMA_CH5_PYLD_CUR_ADDR:
> + case DPDMA_CH0_STATUS:
> + case DPDMA_CH1_STATUS:
> + case DPDMA_CH2_STATUS:
> + case DPDMA_CH3_STATUS:
> + case DPDMA_CH4_STATUS:
> + case DPDMA_CH5_STATUS:
> + case DPDMA_CH0_VDO:
> + case DPDMA_CH1_VDO:
> + case DPDMA_CH2_VDO:
> + case DPDMA_CH3_VDO:
> + case DPDMA_CH4_VDO:
> + case DPDMA_CH5_VDO:
> + case DPDMA_CH0_PYLD_SZ:
> + case DPDMA_CH1_PYLD_SZ:
> + case DPDMA_CH2_PYLD_SZ:
> + case DPDMA_CH3_PYLD_SZ:
> + case DPDMA_CH4_PYLD_SZ:
> + case DPDMA_CH5_PYLD_SZ:
> + case DPDMA_CH0_DSCR_ID:
> + case DPDMA_CH1_DSCR_ID:
> + case DPDMA_CH2_DSCR_ID:
> + case DPDMA_CH3_DSCR_ID:
> + case DPDMA_CH4_DSCR_ID:
> + case DPDMA_CH5_DSCR_ID:
Any opportunities for case FOO ... BAR in this?
> + /*
> + * Trying to write to a read only register..
> + */
> + break;
> + case DPDMA_GBL:
> + /*
> + * This is a write only register so it's read as zero in the read
> + * callback.
> + * We store the value anyway so we can know if the channel is
> + * enabled.
> + */
> + s->registers[offset] = value & 0x00000FFF;
> + break;
> + case DPDMA_CH0_DSCR_STRT_ADDRE:
> + case DPDMA_CH1_DSCR_STRT_ADDRE:
> + case DPDMA_CH2_DSCR_STRT_ADDRE:
> + case DPDMA_CH3_DSCR_STRT_ADDRE:
> + case DPDMA_CH4_DSCR_STRT_ADDRE:
> + case DPDMA_CH5_DSCR_STRT_ADDRE:
> + value &= 0x0000FFFF;
> + s->registers[offset] = value;
> + break;
> + case DPDMA_CH0_CNTL:
> + case DPDMA_CH1_CNTL:
> + case DPDMA_CH2_CNTL:
> + case DPDMA_CH3_CNTL:
> + case DPDMA_CH4_CNTL:
> + case DPDMA_CH5_CNTL:
> + value &= 0x3FFFFFFF;
> + s->registers[offset] = value;
> + break;
> + default:
> + assert(offset <= (0xFFC >> 2));
> + s->registers[offset] = value;
> + break;
> + }
> +}
> +
> +static const MemoryRegionOps dma_ops = {
> + .read = xilinx_dpdma_read,
> + .write = xilinx_dpdma_write,
The MMIO size and alignment restrictions go here.
> + .endianness = DEVICE_NATIVE_ENDIAN,
> +};
> +
> +static void xilinx_dpdma_init(Object *obj)
> +{
> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
> + XilinxDPDMAState *s = XILINX_DPDMA(obj);
> +
> + memory_region_init_io(&s->iomem, obj, &dma_ops, s,
> + TYPE_XILINX_DPDMA, 0x1000);
> + sysbus_init_mmio(sbd, &s->iomem);
> + sysbus_init_irq(sbd, &s->irq);
> +}
> +
> +static void xilinx_dpdma_reset(DeviceState *dev)
> +{
> + XilinxDPDMAState *s = XILINX_DPDMA(dev);
blank line.
> + memset(s->registers, 0, sizeof(s->registers));
> + s->registers[DPDMA_IMR] = 0x07FFFFFF;
> + s->registers[DPDMA_EIMR] = 0xFFFFFFFF;
> + s->registers[DPDMA_ALC0_MIN] = 0x0000FFFF;
> + s->registers[DPDMA_ALC1_MIN] = 0x0000FFFF;
> +}
> +
> +static void xilinx_dpdma_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> +
> + dc->vmsd = &vmstate_xilinx_dpdma;
> + dc->reset = xilinx_dpdma_reset;
> +}
> +
> +static const TypeInfo xilinx_dpdma_info = {
> + .name = TYPE_XILINX_DPDMA,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(XilinxDPDMAState),
> + .instance_init = xilinx_dpdma_init,
> + .class_init = xilinx_dpdma_class_init,
> +};
> +
> +static void xilinx_dpdma_register_types(void)
> +{
> + type_register_static(&xilinx_dpdma_info);
> +}
> +
> +size_t xilinx_dpdma_start_operation(XilinxDPDMAState *s, uint8_t channel,
> + bool one_desc)
> +{
> + uint64_t desc_addr;
> + uint64_t source_addr[6];
> + DPDMADescriptor desc;
> + bool done = false;
> + size_t ptr = 0;
> +
> + assert(channel <= 5);
> +
> + if (channel == 3) {
> + s->registers[DPDMA_ISR] |= (1 << 27);
> + xilinx_dpdma_update_irq(s);
> + }
Interesting special case for #3. does it need a comment?
> +
> + DPRINTF("dpdma_start_channel() on channel %u\n", channel);
> +
> + if (!xilinx_dpdma_is_channel_triggered(s, channel)) {
> + DPRINTF("Channel isn't triggered..\n");
> + return 0;
> + }
> +
> + if (!xilinx_dpdma_is_channel_enabled(s, channel)) {
> + DPRINTF("Channel isn't enabled..\n");
> + return 0;
> + }
> +
> + if (xilinx_dpdma_is_channel_paused(s, channel)) {
> + DPRINTF("Channel is paused..\n");
> + return 0;
> + }
> +
> + do {
> + if ((s->operation_finished[channel])
> + || xilinx_dpdma_is_channel_retriggered(s, channel)) {
> + desc_addr = xilinx_dpdma_descriptor_start_address(s, channel);
> + s->operation_finished[channel] = false;
> + } else {
> + desc_addr = xilinx_dpdma_descriptor_next_address(s, channel);
> + }
> +
> + if (dma_memory_read(&address_space_memory, desc_addr, &desc,
> + sizeof(DPDMADescriptor))) {
> + s->registers[DPDMA_EISR] |= ((1 << 1) << channel);
> + xilinx_dpdma_update_irq(s);
> + s->operation_finished[channel] = true;
> + DPRINTF("Can't get the descriptor.\n");
> + break;
> + }
> +
> + xilinx_dpdma_update_desc_info(s, channel, &desc);
> +
> + #ifdef DEBUG_DPDMA
No leading whitespace before #if
> + xilinx_dpdma_dump_descriptor(&desc);
> + #endif
> +
> + DPRINTF("location of the descriptor: 0x%8.8lx\n", desc_addr);
Should this be PRIx64? (there's more of these below).
> + if (!xilinx_dpdma_desc_is_valid(&desc)) {
> + s->registers[DPDMA_EISR] |= ((1 << 7) << channel);
> + xilinx_dpdma_update_irq(s);
> + s->operation_finished[channel] = true;
> + DPRINTF("Invalid descriptor..\n");
> + break;
> + }
> +
> + if (xilinx_dpdma_desc_crc_enabled(&desc)
> + & !xilinx_dpdma_desc_check_crc(&desc)) {
&&
> + s->registers[DPDMA_EISR] |= ((1 << 13) << channel);
> + xilinx_dpdma_update_irq(s);
> + s->operation_finished[channel] = true;
> + DPRINTF("Bad CRC for descriptor..\n");
> + break;
> + }
> +
> + if (xilinx_dpdma_desc_is_already_done(&desc)
> + && !xilinx_dpdma_desc_ignore_done_bit(&desc)) {
> + /* We are trying to process an already processed descriptor. */
> + s->registers[DPDMA_EISR] |= ((1 << 25) << channel);
> + xilinx_dpdma_update_irq(s);
> + s->operation_finished[channel] = true;
> + DPRINTF("Already processed descriptor..\n");
> + break;
> + }
> +
> + done = xilinx_dpdma_desc_is_last(&desc)
> + | xilinx_dpdma_desc_is_last_of_frame(&desc);
||. these "is" function results should be treated as logicals.
> +
> + s->operation_finished[channel] = done;
> + if (s->data[channel]) {
> + int64_t transfer_len =
> + xilinx_dpdma_desc_get_transfer_size(&desc);
> + uint32_t line_size = xilinx_dpdma_desc_get_line_size(&desc);
> + uint32_t line_stride = xilinx_dpdma_desc_get_line_stride(&desc);
> + if (xilinx_dpdma_desc_is_contiguous(&desc)) {
> + source_addr[0] =
> + xilinx_dpdma_desc_get_source_address(&desc, 0);
> + while (transfer_len != 0) {
> + if (dma_memory_read(&address_space_memory,
> + source_addr[0],
> + &(s->data[channel][ptr]),
parenthesis not needed.
> + line_size)) {
> + s->registers[DPDMA_ISR] |= ((1 << 12) << channel);
> + xilinx_dpdma_update_irq(s);
> + DPRINTF("Can't get data.\n");
> + break;
> + }
> + ptr += line_size;
> + transfer_len -= line_size;
> + source_addr[0] += line_stride;
> + }
> + } else {
> + DPRINTF("Source address:\n");
> + int frag;
> + for (frag = 0; frag < 5; frag++) {
> + source_addr[frag] =
> + xilinx_dpdma_desc_get_source_address(&desc, frag);
> + DPRINTF("Fragment %u: 0x%8.8lX\n", frag + 1,
> + source_addr[frag]);
> + }
> +
> + frag = 0;
> + while (transfer_len < 0) {
&& frag < 5 ?
> + if (frag >= 5) {
> + break;
> + }
To drop this.
> + size_t fragment_len = 4096 - (source_addr[frag] % 4096);
Magic number 4096.
> +
> + if (dma_memory_read(&address_space_memory,
> + source_addr[frag],
> + &(s->data[channel][ptr]),
> + fragment_len)) {
> + s->registers[DPDMA_ISR] |= ((1 << 12) << channel);
> + xilinx_dpdma_update_irq(s);
> + DPRINTF("Can't get data.\n");
> + break;
> + }
> + ptr += fragment_len;
> + transfer_len -= fragment_len;
> + frag += 1;
> + }
> + }
> + }
> +
> + if (xilinx_dpdma_desc_update_enabled(&desc)) {
> + /* The descriptor need to be updated when it's completed. */
> + DPRINTF("update the descriptor with the done flag set.\n");
> + xilinx_dpdma_desc_set_done(&desc);
> + if (dma_memory_write(&address_space_memory, desc_addr, &desc,
> + sizeof(DPDMADescriptor))) {
> + abort();
It should be left the the memory API to determine if its a memory
write is fatal. There are system level changed beyond this modules
control that could cause memory API to say no to this op. A quick grep
suggest its normal to just post the write and not assert success. The
one user of the return value I can see (ohci) does a graceful failure
on it.
> + }
> + }
> +
> + if (xilinx_dpdma_desc_completion_interrupt(&desc)) {
> + DPRINTF("completion interrupt enabled!\n");
> + s->registers[DPDMA_ISR] |= (1 << channel);
> + xilinx_dpdma_update_irq(s);
> + }
> +
> + } while (!done && !one_desc);
> +
> + return ptr;
> +}
> +
> +/*
> + * Set the host location to be filled with the data.
> + */
Non-static function can just rely on comment in heade.
> +void xilinx_dpdma_set_host_data_location(XilinxDPDMAState *s, uint8_t channel,
> + void *p)
> +{
> + if (!s) {
> + qemu_log_mask(LOG_UNIMP, "DPDMA client not attached to valid DPDMA"
> + " instance\n");
> + return;
> + }
> +
> + assert(channel <= 5);
> + s->data[channel] = p;
> +}
> +
> +type_init(xilinx_dpdma_register_types)
> diff --git a/hw/dma/xilinx_dpdma.h b/hw/dma/xilinx_dpdma.h
> new file mode 100644
> index 0000000..f92167d
> --- /dev/null
> +++ b/hw/dma/xilinx_dpdma.h
> @@ -0,0 +1,71 @@
> +/*
> + * xilinx_dpdma.h
> + *
> + * Copyright (C) 2015 : GreenSocs Ltd
> + * http://www.greensocs.com/ , email: info@greensocs.com
> + *
> + * Developed by :
> + * Frederic Konrad <fred.konrad@greensocs.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + *
> + */
> +
> +#ifndef XILINX_DPDMA_H
> +#define XILINX_DPDMA_H
> +
> +#include "hw/sysbus.h"
> +#include "ui/console.h"
> +#include "sysemu/dma.h"
> +
> +struct XilinxDPDMAState {
/*< private >*/
> + SysBusDevice parent_obj;
/*< public >*/
> + MemoryRegion iomem;
> + uint32_t registers[0x1000 >> 2];
> + uint8_t *data[6];
> + bool operation_finished[6];
> + qemu_irq irq;
> +};
> +
> +typedef struct XilinxDPDMAState XilinxDPDMAState;
Can you just define and typedef together? Thats quite common. unless
you have a circular ref between module or need to define the type
opaquely.
> +
> +#define TYPE_XILINX_DPDMA "xlnx.dpdma"
> +#define XILINX_DPDMA(obj) OBJECT_CHECK(XilinxDPDMAState, (obj), \
> + TYPE_XILINX_DPDMA)
> +
> +/*
> + * \func xilinx_dpdma_start_operation.
> + * \brief Start the operation on the specified channel. The DPDMA get the
> + * current descriptor and retrieve data to the buffer specified by
> + * dpdma_set_host_data_location.
> + * \arg s The DPDMA instance.
> + * \arg channel The channel to start.
> + * \return the number of byte transfered by the DPDMA or 0 if an error occured.
> + */
> +size_t xilinx_dpdma_start_operation(XilinxDPDMAState *s, uint8_t channel,
> + bool one_desc);
> +
> +/*
> + * \func xilinx_dpdma_set_host_data_location.
> + * \brief Set the location in the host memory where to store the data out from
> + * the dma channel.
> + * \arg s The DPDMA instance.
> + * \arg channel The channel associated to the pointer.
> + * \arg p The buffer where to store the data.
> + */
What is this documentation style? I can only see it in one other file
in the tree (target-xtensa/helper.c). The doxygen * @ style is more
common. Check bitops.h for a fuller example.
> +/* XXX: add a maximum size arg and send an interrupt in case of overflow. */
Does an interrupt have physical meaning? A host buffer overrun is some
sort of fatal error isnt it?
Regards,
Peter
> +void xilinx_dpdma_set_host_data_location(XilinxDPDMAState *s, uint8_t channel,
> + void *p);
> +
> +#endif /* !XILINX_DPDMA_H */
> --
> 1.9.0
>
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 6/8] Introduce xilinx dpdma.
2015-05-18 8:17 ` Peter Crosthwaite
@ 2015-05-18 8:43 ` Frederic Konrad
0 siblings, 0 replies; 20+ messages in thread
From: Frederic Konrad @ 2015-05-18 8:43 UTC (permalink / raw)
To: Peter Crosthwaite; +Cc: Mark Burton, qemu-devel@nongnu.org Developers, hyunk
On 18/05/2015 10:17, Peter Crosthwaite wrote:
> On Wed, May 13, 2015 at 12:12 PM, <fred.konrad@greensocs.com> wrote:
>> From: KONRAD Frederic <fred.konrad@greensocs.com>
>>
>> This is the implementation of the DPDMA.
>>
>> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
>> ---
>> hw/dma/Makefile.objs | 1 +
>> hw/dma/xilinx_dpdma.c | 1149 +++++++++++++++++++++++++++++++++++++++++++++++++
>> hw/dma/xilinx_dpdma.h | 71 +++
>> 3 files changed, 1221 insertions(+)
>> create mode 100644 hw/dma/xilinx_dpdma.c
>> create mode 100644 hw/dma/xilinx_dpdma.h
>>
>> diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs
>> index 0e65ed0..7198e5a 100644
>> --- a/hw/dma/Makefile.objs
>> +++ b/hw/dma/Makefile.objs
>> @@ -8,6 +8,7 @@ common-obj-$(CONFIG_XILINX_AXI) += xilinx_axidma.o
>> common-obj-$(CONFIG_ETRAXFS) += etraxfs_dma.o
>> common-obj-$(CONFIG_STP2000) += sparc32_dma.o
>> common-obj-$(CONFIG_SUN4M) += sun4m_iommu.o
>> +common-obj-y += xilinx_dpdma.o
> Conditional.
Do you want me to use this condition: obj-$(CONFIG_XLNX_ZYNQMP) ?
Seems making sense as it will be the only platform using it.?
>
>> obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o
>> obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o
>> diff --git a/hw/dma/xilinx_dpdma.c b/hw/dma/xilinx_dpdma.c
>> new file mode 100644
>> index 0000000..6479148
>> --- /dev/null
>> +++ b/hw/dma/xilinx_dpdma.c
>> @@ -0,0 +1,1149 @@
>> +/*
>> + * xilinx_dpdma.c
>> + *
>> + * Copyright (C) 2015 : GreenSocs Ltd
>> + * http://www.greensocs.com/ , email: info@greensocs.com
>> + *
>> + * Developed by :
>> + * Frederic Konrad <fred.konrad@greensocs.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation, either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +#include "xilinx_dpdma.h"
>> +
>> +#ifndef DEBUG_DPDMA
>> +#define DEBUG_DPDMA 0
>> +#endif
>> +
>> +#define DPRINTF(fmt, ...) do { \
>> + if (DEBUG_DPDMA) { \
>> + qemu_log("xilinx_dpdma: " fmt , ## __VA_ARGS__); \
>> + } \
>> +} while (0);
>> +
>> +/*
>> + * Registers offset for DPDMA.
>> + */
>> +#define DPDMA_ERR_CTRL (0x00000000)
> With only a 0x1000 register address range shouldnt need the 8 hex
> digits for offests.
Ok.
>
>> +#define DPDMA_ISR (0x00000004 >> 2)
>> +#define DPDMA_IMR (0x00000008 >> 2)
>> +#define DPDMA_IEN (0x0000000C >> 2)
>> +#define DPDMA_IDS (0x00000010 >> 2)
>> +#define DPDMA_EISR (0x00000014 >> 2)
>> +#define DPDMA_EIMR (0x00000018 >> 2)
>> +#define DPDMA_EIEN (0x0000001C >> 2)
>> +#define DPDMA_EIDS (0x00000020 >> 2)
>> +#define DPDMA_CNTL (0x00000100 >> 2)
>> +#define DPDMA_GBL (0x00000104 >> 2)
>> +#define DPDMA_ALC0_CNTL (0x00000108 >> 2)
>> +#define DPDMA_ALC0_STATUS (0x0000010C >> 2)
>> +#define DPDMA_ALC0_MAX (0x00000110 >> 2)
>> +#define DPDMA_ALC0_MIN (0x00000114 >> 2)
>> +#define DPDMA_ALC0_ACC (0x00000118 >> 2)
>> +#define DPDMA_ALC0_ACC_TRAN (0x0000011C >> 2)
>> +#define DPDMA_ALC1_CNTL (0x00000120 >> 2)
>> +#define DPDMA_ALC1_STATUS (0x00000124 >> 2)
>> +#define DPDMA_ALC1_MAX (0x00000128 >> 2)
>> +#define DPDMA_ALC1_MIN (0x0000012C >> 2)
>> +#define DPDMA_ALC1_ACC (0x00000130 >> 2)
>> +#define DPDMA_ALC1_ACC_TRAN (0x00000134 >> 2)
>> +#define DPDMA_CH0_DSCR_STRT_ADDRE (0x00000200 >> 2)
>> +#define DPDMA_CH0_DSCR_STRT_ADDR (0x00000204 >> 2)
>> +#define DPDMA_CH0_DSCR_NEXT_ADDRE (0x00000208 >> 2)
>> +#define DPDMA_CH0_DSCR_NEXT_ADDR (0x0000020C >> 2)
>> +#define DPDMA_CH0_PYLD_CUR_ADDRE (0x00000210 >> 2)
>> +#define DPDMA_CH0_PYLD_CUR_ADDR (0x00000214 >> 2)
>> +#define DPDMA_CH0_CNTL (0x00000218 >> 2)
>> +#define DPDMA_CH0_STATUS (0x0000021C >> 2)
>> +#define DPDMA_CH0_VDO (0x00000220 >> 2)
>> +#define DPDMA_CH0_PYLD_SZ (0x00000224 >> 2)
>> +#define DPDMA_CH0_DSCR_ID (0x00000228 >> 2)
> These per-channel addresses should be collapsable using a macro:
>
> #define DPDMA_DSCR_ID_CH(n) ((0x00000228 + n * 100) >> 2)
true and it will probably help for the repetitions below.
>
>> +#define DPDMA_CH1_DSCR_STRT_ADDRE (0x00000300 >> 2)
>> +#define DPDMA_CH1_DSCR_STRT_ADDR (0x00000304 >> 2)
>> +#define DPDMA_CH1_DSCR_NEXT_ADDRE (0x00000308 >> 2)
>> +#define DPDMA_CH1_DSCR_NEXT_ADDR (0x0000030C >> 2)
>> +#define DPDMA_CH1_PYLD_CUR_ADDRE (0x00000310 >> 2)
>> +#define DPDMA_CH1_PYLD_CUR_ADDR (0x00000314 >> 2)
>> +#define DPDMA_CH1_CNTL (0x00000318 >> 2)
>> +#define DPDMA_CH1_STATUS (0x0000031C >> 2)
>> +#define DPDMA_CH1_VDO (0x00000320 >> 2)
>> +#define DPDMA_CH1_PYLD_SZ (0x00000324 >> 2)
>> +#define DPDMA_CH1_DSCR_ID (0x00000328 >> 2)
>> +#define DPDMA_CH2_DSCR_STRT_ADDRE (0x00000400 >> 2)
>> +#define DPDMA_CH2_DSCR_STRT_ADDR (0x00000404 >> 2)
>> +#define DPDMA_CH2_DSCR_NEXT_ADDRE (0x00000408 >> 2)
>> +#define DPDMA_CH2_DSCR_NEXT_ADDR (0x0000040C >> 2)
>> +#define DPDMA_CH2_PYLD_CUR_ADDRE (0x00000410 >> 2)
>> +#define DPDMA_CH2_PYLD_CUR_ADDR (0x00000414 >> 2)
>> +#define DPDMA_CH2_CNTL (0x00000418 >> 2)
>> +#define DPDMA_CH2_STATUS (0x0000041C >> 2)
>> +#define DPDMA_CH2_VDO (0x00000420 >> 2)
>> +#define DPDMA_CH2_PYLD_SZ (0x00000424 >> 2)
>> +#define DPDMA_CH2_DSCR_ID (0x00000428 >> 2)
>> +#define DPDMA_CH3_DSCR_STRT_ADDRE (0x00000500 >> 2)
>> +#define DPDMA_CH3_DSCR_STRT_ADDR (0x00000504 >> 2)
>> +#define DPDMA_CH3_DSCR_NEXT_ADDRE (0x00000508 >> 2)
>> +#define DPDMA_CH3_DSCR_NEXT_ADDR (0x0000050C >> 2)
>> +#define DPDMA_CH3_PYLD_CUR_ADDRE (0x00000510 >> 2)
>> +#define DPDMA_CH3_PYLD_CUR_ADDR (0x00000514 >> 2)
>> +#define DPDMA_CH3_CNTL (0x00000518 >> 2)
>> +#define DPDMA_CH3_STATUS (0x0000051C >> 2)
>> +#define DPDMA_CH3_VDO (0x00000520 >> 2)
>> +#define DPDMA_CH3_PYLD_SZ (0x00000524 >> 2)
>> +#define DPDMA_CH3_DSCR_ID (0x00000528 >> 2)
>> +#define DPDMA_CH4_DSCR_STRT_ADDRE (0x00000600 >> 2)
>> +#define DPDMA_CH4_DSCR_STRT_ADDR (0x00000604 >> 2)
>> +#define DPDMA_CH4_DSCR_NEXT_ADDRE (0x00000608 >> 2)
>> +#define DPDMA_CH4_DSCR_NEXT_ADDR (0x0000060C >> 2)
>> +#define DPDMA_CH4_PYLD_CUR_ADDRE (0x00000610 >> 2)
>> +#define DPDMA_CH4_PYLD_CUR_ADDR (0x00000614 >> 2)
>> +#define DPDMA_CH4_CNTL (0x00000618 >> 2)
>> +#define DPDMA_CH4_STATUS (0x0000061C >> 2)
>> +#define DPDMA_CH4_VDO (0x00000620 >> 2)
>> +#define DPDMA_CH4_PYLD_SZ (0x00000624 >> 2)
>> +#define DPDMA_CH4_DSCR_ID (0x00000628 >> 2)
>> +#define DPDMA_CH5_DSCR_STRT_ADDRE (0x00000700 >> 2)
>> +#define DPDMA_CH5_DSCR_STRT_ADDR (0x00000704 >> 2)
>> +#define DPDMA_CH5_DSCR_NEXT_ADDRE (0x00000708 >> 2)
>> +#define DPDMA_CH5_DSCR_NEXT_ADDR (0x0000070C >> 2)
>> +#define DPDMA_CH5_PYLD_CUR_ADDRE (0x00000710 >> 2)
>> +#define DPDMA_CH5_PYLD_CUR_ADDR (0x00000714 >> 2)
>> +#define DPDMA_CH5_CNTL (0x00000718 >> 2)
>> +#define DPDMA_CH5_STATUS (0x0000071C >> 2)
>> +#define DPDMA_CH5_VDO (0x00000720 >> 2)
>> +#define DPDMA_CH5_PYLD_SZ (0x00000724 >> 2)
>> +#define DPDMA_CH5_DSCR_ID (0x00000728 >> 2)
>> +#define DPDMA_ECO (0x00000FFC >> 2)
>> +
> Drop ECO field.
>
>> +/*
>> + * Descriptor control field.
>> + */
>> +#define CONTROL_PREAMBLE_VALUE 0xA5
>> +
>> +#define CONTROL_PREAMBLE 0xFF
>> +#define EN_DSCR_DONE_INTR (1 << 8)
>> +#define EN_DSCR_UPDATE (1 << 9)
>> +#define IGNORE_DONE (1 << 10)
>> +#define AXI_BURST_TYPE (1 << 11)
>> +#define AXCACHE (0x0F << 12)
>> +#define AXPROT (0x2 << 16)
>> +#define DESCRIPTOR_MODE (1 << 18)
>> +#define LAST_DESCRIPTOR (1 << 19)
>> +#define ENABLE_CRC (1 << 20)
>> +#define LAST_DESCRIPTOR_OF_FRAME (1 << 21)
>> +
>> +typedef enum DPDMABurstType {
>> + DPDMA_INCR = 0,
>> + DPDMA_FIXED = 1
>> +} DPDMABurstType;
>> +
>> +typedef enum DPDMAMode {
>> + DPDMA_CONTIGOUS = 0,
>> + DPDMA_FRAGMENTED = 1
>> +} DPDMAMode;
>> +
>> +typedef struct DPDMADescriptor {
>> + uint32_t control;
>> + uint32_t descriptor_id;
>> + /* transfer size in byte. */
>> + uint32_t xfer_size;
>> + uint32_t line_size_stride;
>> + uint32_t timestamp_lsb;
>> + uint32_t timestamp_msb;
>> + /* contains extension for both descriptor and source. */
>> + uint32_t address_extension;
>> + uint32_t next_descriptor;
>> + uint32_t source_address;
>> + uint32_t address_extension_23;
>> + uint32_t address_extension_45;
>> + uint32_t source_address2;
>> + uint32_t source_address3;
>> + uint32_t source_address4;
>> + uint32_t source_address5;
>> + uint32_t crc;
>> +} DPDMADescriptor;
>> +
>> +static bool xilinx_dpdma_desc_is_last(DPDMADescriptor *desc)
>> +{
>> + return ((desc->control & 0x00080000) != 0);
> Single bit extract32s are cleaner IMO (check the AArch64 translate
> code where they started using them).
>
>> +}
>> +
>> +static bool xilinx_dpdma_desc_is_last_of_frame(DPDMADescriptor *desc)
>> +{
>> + return ((desc->control & 0x00200000) != 0);
>> +}
>> +
>> +static uint64_t xilinx_dpdma_desc_get_source_address(DPDMADescriptor *desc,
>> + uint8_t frag)
>> +{
>> + uint64_t addr = 0;
>> + assert(frag < 5);
>> +
>> + switch (frag) {
>> + case 0:
>> + addr = desc->source_address
>> + + (extract32(desc->address_extension, 16, 12) << 20);
>> + break;
>> + case 1:
>> + addr = desc->source_address2
>> + + (extract32(desc->address_extension_23, 0, 12) << 8);
>> + break;
>> + case 2:
>> + addr = desc->source_address3
>> + + (extract32(desc->address_extension_23, 16, 12) << 20);
>> + break;
>> + case 3:
>> + addr = desc->source_address4
>> + + (extract32(desc->address_extension_45, 0, 12) << 8);
>> + break;
>> + case 4:
>> + addr = desc->source_address5
>> + + (extract32(desc->address_extension_45, 16, 12) << 20);
>> + break;
>> + default:
>> + addr = 0;
>> + break;
>> + }
>> +
>> + return addr;
>> +}
>> +
>> +static uint32_t xilinx_dpdma_desc_get_transfer_size(DPDMADescriptor *desc)
>> +{
>> + return desc->xfer_size;
>> +}
>> +
>> +static uint32_t xilinx_dpdma_desc_get_line_size(DPDMADescriptor *desc)
>> +{
>> + return desc->line_size_stride & 0x3FFFF;
> extract.
>
>> +}
>> +
>> +static uint32_t xilinx_dpdma_desc_get_line_stride(DPDMADescriptor *desc)
>> +{
>> + return (desc->line_size_stride >> 18) * 16;
> extract.
>
>> +}
>> +
>> +static inline bool xilinx_dpdma_desc_crc_enabled(DPDMADescriptor *desc)
>> +{
>> + return ((desc->control & (1 << 20)) != 0);
>> +}
>> +
>> +static inline bool xilinx_dpdma_desc_check_crc(DPDMADescriptor *desc)
>> +{
>> + uint32_t *p = (uint32_t *)(desc);
> parenthesis not needed.
>
>> + uint32_t crc = 0;
>> + uint8_t i;
>> +
>> + for (i = 0; i < 15; i++) {
> Does 15 need a macro? Is it the descriptor length?
>
>> + crc += p[i];
>> + }
>> +
>> + return (crc == desc->crc);
>> +}
>> +
>> +static inline bool xilinx_dpdma_desc_completion_interrupt(DPDMADescriptor *desc)
>> +{
>> + return ((desc->control & (1 << 8)) != 0);
>> +}
>> +
>> +static inline bool xilinx_dpdma_desc_is_valid(DPDMADescriptor *desc)
>> +{
>> + return ((desc->control & 0xFF) == 0xA5);
>> +}
>> +
>> +static inline bool xilinx_dpdma_desc_is_contiguous(DPDMADescriptor *desc)
>> +{
>> + return ((desc->control & 0x00040000) == 0);
>> +}
>> +
>> +static inline bool xilinx_dpdma_desc_update_enabled(DPDMADescriptor *desc)
>> +{
>> + return ((desc->control & (1 << 9)) != 0);
>> +}
>> +
>> +static inline void xilinx_dpdma_desc_set_done(DPDMADescriptor *desc)
>> +{
>> + desc->timestamp_msb |= (1 << 31);
>> +}
>> +
>> +static inline bool xilinx_dpdma_desc_is_already_done(DPDMADescriptor *desc)
>> +{
>> + return ((desc->timestamp_msb & (1 << 31)) != 0);
>> +}
>> +
>> +static inline bool xilinx_dpdma_desc_ignore_done_bit(DPDMADescriptor *desc)
>> +{
>> + return ((desc->control & (1 << 10)) != 0);
>> +}
>> +
>> +static const VMStateDescription vmstate_xilinx_dpdma = {
>> + .name = TYPE_XILINX_DPDMA,
>> + .version_id = 1,
>> + .fields = (VMStateField[]) {
>> +
> I think this needs population?
>
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>> +
>> +static void xilinx_dpdma_update_irq(XilinxDPDMAState *s)
>> +{
>> + uint32_t flags;
>> +
>> + flags = ((s->registers[DPDMA_ISR] & (~s->registers[DPDMA_IMR]))
>> + | (s->registers[DPDMA_EISR] & (~s->registers[DPDMA_EIMR])));
>> + qemu_set_irq(s->irq, flags != 0);
>> +}
>> +
>> +static uint64_t xilinx_dpdma_descriptor_start_address(XilinxDPDMAState *s,
>> + uint8_t channel)
>> +{
>> + switch (channel) {
>> + case 0:
>> + return (s->registers[DPDMA_CH0_DSCR_STRT_ADDRE] << 16)
>> + + s->registers[DPDMA_CH0_DSCR_STRT_ADDR];
>> + break;
>> + case 1:
>> + return (s->registers[DPDMA_CH1_DSCR_STRT_ADDRE] << 16)
>> + + s->registers[DPDMA_CH1_DSCR_STRT_ADDR];
>> + break;
>> + case 2:
>> + return (s->registers[DPDMA_CH2_DSCR_STRT_ADDRE] << 16)
>> + + s->registers[DPDMA_CH2_DSCR_STRT_ADDR];
>> + break;
>> + case 3:
>> + return (s->registers[DPDMA_CH3_DSCR_STRT_ADDRE] << 16)
>> + + s->registers[DPDMA_CH3_DSCR_STRT_ADDR];
>> + break;
>> + case 4:
>> + return (s->registers[DPDMA_CH4_DSCR_STRT_ADDRE] << 16)
>> + + s->registers[DPDMA_CH4_DSCR_STRT_ADDR];
>> + break;
>> + case 5:
>> + return (s->registers[DPDMA_CH5_DSCR_STRT_ADDRE] << 16)
>> + + s->registers[DPDMA_CH5_DSCR_STRT_ADDR];
>> + break;
> Can the 6X repetition be collapsed using some indexing math?
Yes.
>
>> + default:
>> + /* Should not happen. */
>> + return 0;
>> + break;
>> + }
>> +}
>> +
>> +static uint64_t xilinx_dpdma_descriptor_next_address(XilinxDPDMAState *s,
>> + uint8_t channel)
>> +{
>> + switch (channel) {
>> + case 0:
>> + return ((uint64_t)s->registers[DPDMA_CH0_DSCR_NEXT_ADDRE] << 32)
>> + + s->registers[DPDMA_CH0_DSCR_NEXT_ADDR];
>> + break;
>> + case 1:
>> + return ((uint64_t)s->registers[DPDMA_CH1_DSCR_NEXT_ADDRE] << 32)
>> + + s->registers[DPDMA_CH1_DSCR_NEXT_ADDR];
>> + break;
>> + case 2:
>> + return ((uint64_t)s->registers[DPDMA_CH2_DSCR_NEXT_ADDRE] << 32)
>> + + s->registers[DPDMA_CH2_DSCR_NEXT_ADDR];
>> + break;
>> + case 3:
>> + return ((uint64_t)s->registers[DPDMA_CH3_DSCR_NEXT_ADDRE] << 32)
>> + + s->registers[DPDMA_CH3_DSCR_NEXT_ADDR];
>> + break;
>> + case 4:
>> + return ((uint64_t)s->registers[DPDMA_CH4_DSCR_NEXT_ADDRE] << 32)
>> + + s->registers[DPDMA_CH4_DSCR_NEXT_ADDR];
>> + break;
>> + case 5:
>> + return ((uint64_t)s->registers[DPDMA_CH5_DSCR_NEXT_ADDRE] << 32)
>> + + s->registers[DPDMA_CH5_DSCR_NEXT_ADDR];
>> + break;
> same.
>
>> + default:
>> + /* Should not happen. */
>> + return 0;
>> + break;
>> + }
>> +}
>> +
>> +static inline void xilinx_dpdma_set_desc_next_address(XilinxDPDMAState *s,
>> + uint8_t channel,
>> + uint64_t addr)
>> +{
>> + switch (channel) {
>> + case 0:
>> + s->registers[DPDMA_CH0_DSCR_NEXT_ADDRE] = addr >> 32;
>> + s->registers[DPDMA_CH0_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
> extract64
>
>> + break;
>> + case 1:
>> + s->registers[DPDMA_CH1_DSCR_NEXT_ADDRE] = addr >> 32;
>> + s->registers[DPDMA_CH1_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
>> + break;
>> + case 2:
>> + s->registers[DPDMA_CH2_DSCR_NEXT_ADDRE] = addr >> 32;
>> + s->registers[DPDMA_CH2_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
>> + break;
>> + case 3:
>> + s->registers[DPDMA_CH3_DSCR_NEXT_ADDRE] = addr >> 32;
>> + s->registers[DPDMA_CH3_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
>> + break;
>> + case 4:
>> + s->registers[DPDMA_CH4_DSCR_NEXT_ADDRE] = addr >> 32;
>> + s->registers[DPDMA_CH4_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
>> + break;
>> + case 5:
>> + s->registers[DPDMA_CH5_DSCR_NEXT_ADDRE] = addr >> 32;
>> + s->registers[DPDMA_CH5_DSCR_NEXT_ADDR] = addr & 0xFFFFFFFF;
>> + break;
> repetition.
>
>> + default:
>> + /* Should not happen. */
>> + break;
>> + }
>> +}
>> +
>> +static bool xilinx_dpdma_is_channel_enabled(XilinxDPDMAState *s,
>> + uint8_t channel)
>> +{
>> + switch (channel) {
>> + case 0:
>> + return ((s->registers[DPDMA_CH0_CNTL] & 0x01) != 0);
> 0x1 needs macro definition.
>
>> + break;
> unreachable break statements.
>
>> + case 1:
>> + return ((s->registers[DPDMA_CH1_CNTL] & 0x01) != 0);
>> + break;
>> + case 2:
>> + return ((s->registers[DPDMA_CH2_CNTL] & 0x01) != 0);
>> + break;
>> + case 3:
>> + return ((s->registers[DPDMA_CH3_CNTL] & 0x01) != 0);
>> + break;
>> + case 4:
>> + return ((s->registers[DPDMA_CH4_CNTL] & 0x01) != 0);
>> + break;
>> + case 5:
>> + return ((s->registers[DPDMA_CH5_CNTL] & 0x01) != 0);
>> + break;
>> + default:
>> + /* Should not happen. */
>> + return 0;
>> + break;
>> + }
>> +}
>> +
>> +static bool xilinx_dpdma_is_channel_paused(XilinxDPDMAState *s,
>> + uint8_t channel)
>> +{
>> + switch (channel) {
>> + case 0:
>> + return ((s->registers[DPDMA_CH0_CNTL] & 0x02) != 0);
>> + break;
>> + case 1:
>> + return ((s->registers[DPDMA_CH1_CNTL] & 0x02) != 0);
>> + break;
>> + case 2:
>> + return ((s->registers[DPDMA_CH2_CNTL] & 0x02) != 0);
>> + break;
>> + case 3:
>> + return ((s->registers[DPDMA_CH3_CNTL] & 0x02) != 0);
>> + break;
>> + case 4:
>> + return ((s->registers[DPDMA_CH4_CNTL] & 0x02) != 0);
>> + break;
>> + case 5:
>> + return ((s->registers[DPDMA_CH5_CNTL] & 0x02) != 0);
>> + break;
> Same comments as above.
>
>> + default:
>> + /* Should not happen. */
>> + return 0;
>> + break;
>> + }
>> +}
>> +
>> +static inline bool xilinx_dpdma_is_channel_retriggered(XilinxDPDMAState *s,
>> + uint8_t channel)
>> +{
>> + return s->registers[DPDMA_GBL] & ((1 << 6) << channel);
>> +}
>> +
>> +static inline bool xilinx_dpdma_is_channel_triggered(XilinxDPDMAState *s,
>> + uint8_t channel)
>> +{
>> + return s->registers[DPDMA_GBL] & (1 << channel);
>> +}
>> +
>> +static void xilinx_dpdma_update_desc_info(XilinxDPDMAState *s, uint8_t channel,
>> + DPDMADescriptor *desc)
>> +{
>> + switch (channel) {
>> + case 0:
>> + s->registers[DPDMA_CH0_DSCR_NEXT_ADDRE] = desc->address_extension
>> + & 0x0000FFFF;
> extract for consistency with code below.
>
>> + s->registers[DPDMA_CH0_DSCR_NEXT_ADDR] = desc->next_descriptor;
>> + s->registers[DPDMA_CH0_PYLD_CUR_ADDRE] =
>> + extract32(desc->address_extension, 16, 16);
>> + s->registers[DPDMA_CH0_PYLD_CUR_ADDR] = desc->source_address;
>> + s->registers[DPDMA_CH0_VDO] = extract32(desc->line_size_stride, 18, 14)
>> + + (extract32(desc->line_size_stride, 0, 18)
>> + << 14);
>> + s->registers[DPDMA_CH0_PYLD_SZ] = desc->xfer_size;
>> + s->registers[DPDMA_CH0_DSCR_ID] = desc->descriptor_id;
>> +
>> + /* Compute the status register with the descriptor information. */
>> + s->registers[DPDMA_CH0_STATUS] = (desc->control & 0xFF) << 13;
>> + if ((desc->control & (1 << 8)) != 0) {
>> + s->registers[DPDMA_CH0_STATUS] |= (1 << 12);
>> + }
>> + if ((desc->control & (1 << 9)) != 0) {
>> + s->registers[DPDMA_CH0_STATUS] |= (1 << 11);
>> + }
>> + if ((desc->timestamp_msb & (1 << 31)) != 0) {
>> + s->registers[DPDMA_CH0_STATUS] |= (1 << 10);
>> + }
>> + if ((desc->control & (1 << 10)) != 0) {
>> + s->registers[DPDMA_CH0_STATUS] |= (1 << 9);
>> + }
>> + if ((desc->control & (1 << 21)) != 0) {
>> + s->registers[DPDMA_CH0_STATUS] |= (1 << 8);
>> + }
>> + if ((desc->control & (1 << 19)) != 0) {
>> + s->registers[DPDMA_CH0_STATUS] |= (1 << 7);
>> + }
>> + if ((desc->control & (1 << 20)) != 0) {
>> + s->registers[DPDMA_CH0_STATUS] |= (1 << 6);
>> + }
>> + if ((desc->control & (1 << 18)) != 0) {
>> + s->registers[DPDMA_CH0_STATUS] |= (1 << 5);
>> + }
>> + if ((desc->control & (1 << 11)) != 0) {
>> + s->registers[DPDMA_CH0_STATUS] |= (1 << 4);
>> + }
>> + /* XXX: BURST_LEN? */
> What does this mean?
It means burst lenght is missing from the status register. Seems
impossible to get
and information for that. Probably the best option is to hardcode something?
>
>> + break;
>> + case 1:
>> + s->registers[DPDMA_CH1_DSCR_NEXT_ADDRE] = desc->address_extension
>> + & 0x0000FFFF;
>> + s->registers[DPDMA_CH1_DSCR_NEXT_ADDR] = desc->next_descriptor;
>> + s->registers[DPDMA_CH1_PYLD_CUR_ADDRE] =
>> + extract32(desc->address_extension, 16, 16);
>> + s->registers[DPDMA_CH1_PYLD_CUR_ADDR] = desc->source_address;
>> + s->registers[DPDMA_CH1_VDO] = extract32(desc->line_size_stride, 18, 14)
>> + + (extract32(desc->line_size_stride, 0, 18)
>> + << 14);
>> + s->registers[DPDMA_CH1_PYLD_SZ] = desc->xfer_size;
>> + s->registers[DPDMA_CH1_DSCR_ID] = desc->descriptor_id;
>> +
>> + /* Compute the status register with the descriptor information. */
>> + s->registers[DPDMA_CH1_STATUS] = (desc->control & 0xFF) << 13;
>> + if ((desc->control & (1 << 8)) != 0) {
>> + s->registers[DPDMA_CH1_STATUS] |= (1 << 12);
>> + }
>> + if ((desc->control & (1 << 9)) != 0) {
>> + s->registers[DPDMA_CH1_STATUS] |= (1 << 11);
>> + }
>> + if ((desc->timestamp_msb & (1 << 31)) != 0) {
>> + s->registers[DPDMA_CH1_STATUS] |= (1 << 10);
>> + }
>> + if ((desc->control & (1 << 10)) != 0) {
>> + s->registers[DPDMA_CH1_STATUS] |= (1 << 9);
>> + }
>> + if ((desc->control & (1 << 21)) != 0) {
>> + s->registers[DPDMA_CH1_STATUS] |= (1 << 8);
>> + }
>> + if ((desc->control & (1 << 19)) != 0) {
>> + s->registers[DPDMA_CH1_STATUS] |= (1 << 7);
>> + }
>> + if ((desc->control & (1 << 20)) != 0) {
>> + s->registers[DPDMA_CH1_STATUS] |= (1 << 6);
>> + }
>> + if ((desc->control & (1 << 18)) != 0) {
>> + s->registers[DPDMA_CH1_STATUS] |= (1 << 5);
>> + }
>> + if ((desc->control & (1 << 11)) != 0) {
>> + s->registers[DPDMA_CH1_STATUS] |= (1 << 4);
>> + }
>> + /* XXX: BURST_LEN? */
>> + break;
>> + case 2:
>> + s->registers[DPDMA_CH2_DSCR_NEXT_ADDRE] = desc->address_extension
>> + & 0x0000FFFF;
>> + s->registers[DPDMA_CH2_DSCR_NEXT_ADDR] = desc->next_descriptor;
>> + s->registers[DPDMA_CH2_PYLD_CUR_ADDRE] =
>> + extract32(desc->address_extension, 16, 16);
>> + s->registers[DPDMA_CH2_PYLD_CUR_ADDR] = desc->source_address;
>> + s->registers[DPDMA_CH2_VDO] = extract32(desc->line_size_stride, 18, 14)
>> + + (extract32(desc->line_size_stride, 0, 18)
>> + << 14);
>> + s->registers[DPDMA_CH2_PYLD_SZ] = desc->xfer_size;
>> + s->registers[DPDMA_CH2_DSCR_ID] = desc->descriptor_id;
>> +
>> + /* Compute the status register with the descriptor information. */
>> + s->registers[DPDMA_CH2_STATUS] = (desc->control & 0xFF) << 13;
>> + if ((desc->control & (1 << 8)) != 0) {
>> + s->registers[DPDMA_CH2_STATUS] |= (1 << 12);
>> + }
>> + if ((desc->control & (1 << 9)) != 0) {
>> + s->registers[DPDMA_CH2_STATUS] |= (1 << 11);
>> + }
>> + if ((desc->timestamp_msb & (1 << 31)) != 0) {
>> + s->registers[DPDMA_CH2_STATUS] |= (1 << 10);
>> + }
>> + if ((desc->control & (1 << 10)) != 0) {
>> + s->registers[DPDMA_CH2_STATUS] |= (1 << 9);
>> + }
>> + if ((desc->control & (1 << 21)) != 0) {
>> + s->registers[DPDMA_CH2_STATUS] |= (1 << 8);
>> + }
>> + if ((desc->control & (1 << 19)) != 0) {
>> + s->registers[DPDMA_CH2_STATUS] |= (1 << 7);
>> + }
>> + if ((desc->control & (1 << 20)) != 0) {
>> + s->registers[DPDMA_CH2_STATUS] |= (1 << 6);
>> + }
>> + if ((desc->control & (1 << 18)) != 0) {
>> + s->registers[DPDMA_CH2_STATUS] |= (1 << 5);
>> + }
>> + if ((desc->control & (1 << 11)) != 0) {
>> + s->registers[DPDMA_CH2_STATUS] |= (1 << 4);
>> + }
>> + /* XXX: BURST_LEN? */
>> + break;
> Ok definately want to do something about the repetition on this one.
> If the variable numbers are regular use math to calculate them. If
> they are irregular make some data table arrays that can be indexed on
> the switch variable.
>
>> + case 3:
>> + s->registers[DPDMA_CH3_DSCR_NEXT_ADDRE] = desc->address_extension
>> + & 0x0000FFFF;
>> + s->registers[DPDMA_CH3_DSCR_NEXT_ADDR] = desc->next_descriptor;
>> + s->registers[DPDMA_CH3_PYLD_CUR_ADDRE] =
>> + extract32(desc->address_extension, 16, 16);
>> + s->registers[DPDMA_CH3_PYLD_CUR_ADDR] = desc->source_address;
>> + s->registers[DPDMA_CH3_VDO] = extract32(desc->line_size_stride, 18, 14)
>> + + (extract32(desc->line_size_stride, 0, 18)
>> + << 14);
>> + s->registers[DPDMA_CH3_PYLD_SZ] = desc->xfer_size;
>> + s->registers[DPDMA_CH3_DSCR_ID] = desc->descriptor_id;
>> +
>> + /* Compute the status register with the descriptor information. */
>> + s->registers[DPDMA_CH3_STATUS] = (desc->control & 0xFF) << 13;
>> + if ((desc->control & (1 << 8)) != 0) {
>> + s->registers[DPDMA_CH3_STATUS] |= (1 << 12);
>> + }
>> + if ((desc->control & (1 << 9)) != 0) {
>> + s->registers[DPDMA_CH3_STATUS] |= (1 << 11);
>> + }
>> + if ((desc->timestamp_msb & (1 << 31)) != 0) {
>> + s->registers[DPDMA_CH3_STATUS] |= (1 << 10);
>> + }
>> + if ((desc->control & (1 << 10)) != 0) {
>> + s->registers[DPDMA_CH3_STATUS] |= (1 << 9);
>> + }
>> + if ((desc->control & (1 << 21)) != 0) {
>> + s->registers[DPDMA_CH3_STATUS] |= (1 << 8);
>> + }
>> + if ((desc->control & (1 << 19)) != 0) {
>> + s->registers[DPDMA_CH3_STATUS] |= (1 << 7);
>> + }
>> + if ((desc->control & (1 << 20)) != 0) {
>> + s->registers[DPDMA_CH3_STATUS] |= (1 << 6);
>> + }
>> + if ((desc->control & (1 << 18)) != 0) {
>> + s->registers[DPDMA_CH3_STATUS] |= (1 << 5);
>> + }
>> + if ((desc->control & (1 << 11)) != 0) {
>> + s->registers[DPDMA_CH3_STATUS] |= (1 << 4);
>> + }
>> + /* XXX: BURST_LEN? */
>> + break;
>> + case 4:
>> + s->registers[DPDMA_CH4_DSCR_NEXT_ADDRE] = desc->address_extension
>> + & 0x0000FFFF;
>> + s->registers[DPDMA_CH4_DSCR_NEXT_ADDR] = desc->next_descriptor;
>> + s->registers[DPDMA_CH4_PYLD_CUR_ADDRE] =
>> + extract32(desc->address_extension, 16, 16);
>> + s->registers[DPDMA_CH4_PYLD_CUR_ADDR] = desc->source_address;
>> + s->registers[DPDMA_CH4_VDO] = extract32(desc->line_size_stride, 18, 14)
>> + + (extract32(desc->line_size_stride, 0, 18)
>> + << 14);
>> + s->registers[DPDMA_CH4_PYLD_SZ] = desc->xfer_size;
>> + s->registers[DPDMA_CH4_DSCR_ID] = desc->descriptor_id;
>> +
>> + /* Compute the status register with the descriptor information. */
>> + s->registers[DPDMA_CH4_STATUS] = (desc->control & 0xFF) << 13;
>> + if ((desc->control & (1 << 8)) != 0) {
>> + s->registers[DPDMA_CH4_STATUS] |= (1 << 12);
>> + }
>> + if ((desc->control & (1 << 9)) != 0) {
>> + s->registers[DPDMA_CH4_STATUS] |= (1 << 11);
>> + }
>> + if ((desc->timestamp_msb & (1 << 31)) != 0) {
>> + s->registers[DPDMA_CH4_STATUS] |= (1 << 10);
>> + }
>> + if ((desc->control & (1 << 10)) != 0) {
>> + s->registers[DPDMA_CH4_STATUS] |= (1 << 9);
>> + }
>> + if ((desc->control & (1 << 21)) != 0) {
>> + s->registers[DPDMA_CH4_STATUS] |= (1 << 8);
>> + }
>> + if ((desc->control & (1 << 19)) != 0) {
>> + s->registers[DPDMA_CH4_STATUS] |= (1 << 7);
>> + }
>> + if ((desc->control & (1 << 20)) != 0) {
>> + s->registers[DPDMA_CH4_STATUS] |= (1 << 6);
>> + }
>> + if ((desc->control & (1 << 18)) != 0) {
>> + s->registers[DPDMA_CH4_STATUS] |= (1 << 5);
>> + }
>> + if ((desc->control & (1 << 11)) != 0) {
>> + s->registers[DPDMA_CH4_STATUS] |= (1 << 4);
>> + }
>> + /* XXX: BURST_LEN? */
>> + break;
>> + case 5:
>> + s->registers[DPDMA_CH5_DSCR_NEXT_ADDRE] = desc->address_extension
>> + & 0x0000FFFF;
>> + s->registers[DPDMA_CH5_DSCR_NEXT_ADDR] = desc->next_descriptor;
>> + s->registers[DPDMA_CH5_PYLD_CUR_ADDRE] =
>> + extract32(desc->address_extension, 16, 16);
>> + s->registers[DPDMA_CH5_PYLD_CUR_ADDR] = desc->source_address;
>> + s->registers[DPDMA_CH5_VDO] = extract32(desc->line_size_stride, 18, 14)
>> + + (extract32(desc->line_size_stride, 0, 18)
>> + << 14);
>> + s->registers[DPDMA_CH5_PYLD_SZ] = desc->xfer_size;
>> + s->registers[DPDMA_CH5_DSCR_ID] = desc->descriptor_id;
>> +
>> + /* Compute the status register with the descriptor information. */
>> + s->registers[DPDMA_CH5_STATUS] = (desc->control & 0xFF) << 13;
>> + if ((desc->control & (1 << 8)) != 0) {
>> + s->registers[DPDMA_CH5_STATUS] |= (1 << 12);
>> + }
>> + if ((desc->control & (1 << 9)) != 0) {
>> + s->registers[DPDMA_CH5_STATUS] |= (1 << 11);
> Number 9 and 11 and those below need macroification.
>
>> + }
>> + if ((desc->timestamp_msb & (1 << 31)) != 0) {
>> + s->registers[DPDMA_CH5_STATUS] |= (1 << 10);
>> + }
>> + if ((desc->control & (1 << 10)) != 0) {
>> + s->registers[DPDMA_CH5_STATUS] |= (1 << 9);
>> + }
>> + if ((desc->control & (1 << 21)) != 0) {
>> + s->registers[DPDMA_CH5_STATUS] |= (1 << 8);
>> + }
>> + if ((desc->control & (1 << 19)) != 0) {
>> + s->registers[DPDMA_CH5_STATUS] |= (1 << 7);
>> + }
>> + if ((desc->control & (1 << 20)) != 0) {
>> + s->registers[DPDMA_CH5_STATUS] |= (1 << 6);
>> + }
>> + if ((desc->control & (1 << 18)) != 0) {
>> + s->registers[DPDMA_CH5_STATUS] |= (1 << 5);
>> + }
>> + if ((desc->control & (1 << 11)) != 0) {
>> + s->registers[DPDMA_CH5_STATUS] |= (1 << 4);
>> + }
>> + /* XXX: BURST_LEN? */
>> + break;
>> + default:
>> + break;
>> + }
>> +}
>> +
>> +#ifdef DEBUG_DPDMA
>> +static void xilinx_dpdma_dump_descriptor(DPDMADescriptor *desc)
>> +{
>> + uint8_t *p = ((uint8_t *)(desc));
> Two sets of unneeded parenthesis.
>
>> + size_t i;
>> +
>> + qemu_log("DUMP DESCRIPTOR:\n");
>> + for (i = 0; i < 64; i++) {
>> + qemu_log(" 0x%2.2X", *p++);
> The 0x infront of each byte is hard to read.
>
> Would you need a PRIx8 here?
>
>> + if (((i + 1) % 4) == 0) {
>> + qemu_log("\n");
>> + }
>> + }
> qemu_hexdump can do this though.
>
>> +}
>> +#endif
>> +
>> +static uint64_t xilinx_dpdma_read(void *opaque, hwaddr offset,
>> + unsigned size)
>> +{
>> + XilinxDPDMAState *s = XILINX_DPDMA(opaque);
> Blank line.
>
>> + assert(size == 4);
>> + assert((offset % 4) == 0);
> Memory API can enforce this with the MemoryRegionOps and assertions
> can be dropped.
>
>> + offset = offset >> 2;
>> + DPRINTF("read @%" PRIx64 "\n", offset << 2);
>> +
>> + switch (offset) {
>> + /*
>> + * Trying to read a write only register.
>> + */
>> + case DPDMA_GBL:
>> + return 0;
>> + break;
> Unreachable break.
>
>> + default:
>> + assert(offset <= (0xFFC >> 2));
>> + return s->registers[offset];
>> + break;
>> + }
>> + return 0;
>> +}
>> +
>> +static void xilinx_dpdma_write(void *opaque, hwaddr offset,
>> + uint64_t value, unsigned size)
>> +{
>> + XilinxDPDMAState *s = XILINX_DPDMA(opaque);
>> + assert(size == 4);
>> + assert((offset % 4) == 0);
> Same comments.
>
>> + offset = offset >> 2;
>> + DPRINTF("write @%" PRIx64 " = 0x%8.8lX\n", offset << 2, value);
> Formats dont look right. Should it be a HWADDR_PRIx and then a PRIx64?
Yes good point. Strangely it compiled on both 32 and 64bits guest.
> Print first then shift.
>
>> +
>> + switch (offset) {
>> + case DPDMA_ISR:
>> + value = ~value;
>> + s->registers[DPDMA_ISR] &= value;
> &= ~value to save a LOC.
>
>> + xilinx_dpdma_update_irq(s);
>> + break;
>> + case DPDMA_IEN:
>> + value = ~value;
>> + s->registers[DPDMA_IMR] &= value;
>> + break;
>> + case DPDMA_IDS:
>> + s->registers[DPDMA_IMR] |= value;
>> + break;
>> + case DPDMA_EISR:
>> + value = ~value;
>> + s->registers[DPDMA_EISR] &= value;
>> + xilinx_dpdma_update_irq(s);
>> + break;
>> + case DPDMA_EIEN:
>> + value = ~value;
>> + s->registers[DPDMA_EIMR] &= value;
>> + break;
>> + case DPDMA_EIDS:
>> + s->registers[DPDMA_EIMR] |= value;
>> + break;
>> + case DPDMA_IMR:
>> + case DPDMA_EIMR:
>> + case DPDMA_CH0_DSCR_NEXT_ADDRE:
>> + case DPDMA_CH0_DSCR_NEXT_ADDR:
>> + case DPDMA_CH1_DSCR_NEXT_ADDRE:
>> + case DPDMA_CH1_DSCR_NEXT_ADDR:
>> + case DPDMA_CH2_DSCR_NEXT_ADDRE:
>> + case DPDMA_CH2_DSCR_NEXT_ADDR:
>> + case DPDMA_CH3_DSCR_NEXT_ADDRE:
>> + case DPDMA_CH3_DSCR_NEXT_ADDR:
>> + case DPDMA_CH4_DSCR_NEXT_ADDRE:
>> + case DPDMA_CH4_DSCR_NEXT_ADDR:
>> + case DPDMA_CH5_DSCR_NEXT_ADDRE:
>> + case DPDMA_CH5_DSCR_NEXT_ADDR:
>> + case DPDMA_CH0_PYLD_CUR_ADDRE:
>> + case DPDMA_CH0_PYLD_CUR_ADDR:
>> + case DPDMA_CH1_PYLD_CUR_ADDRE:
>> + case DPDMA_CH1_PYLD_CUR_ADDR:
>> + case DPDMA_CH2_PYLD_CUR_ADDRE:
>> + case DPDMA_CH2_PYLD_CUR_ADDR:
>> + case DPDMA_CH3_PYLD_CUR_ADDRE:
>> + case DPDMA_CH3_PYLD_CUR_ADDR:
>> + case DPDMA_CH4_PYLD_CUR_ADDRE:
>> + case DPDMA_CH4_PYLD_CUR_ADDR:
>> + case DPDMA_CH5_PYLD_CUR_ADDRE:
>> + case DPDMA_CH5_PYLD_CUR_ADDR:
>> + case DPDMA_CH0_STATUS:
>> + case DPDMA_CH1_STATUS:
>> + case DPDMA_CH2_STATUS:
>> + case DPDMA_CH3_STATUS:
>> + case DPDMA_CH4_STATUS:
>> + case DPDMA_CH5_STATUS:
>> + case DPDMA_CH0_VDO:
>> + case DPDMA_CH1_VDO:
>> + case DPDMA_CH2_VDO:
>> + case DPDMA_CH3_VDO:
>> + case DPDMA_CH4_VDO:
>> + case DPDMA_CH5_VDO:
>> + case DPDMA_CH0_PYLD_SZ:
>> + case DPDMA_CH1_PYLD_SZ:
>> + case DPDMA_CH2_PYLD_SZ:
>> + case DPDMA_CH3_PYLD_SZ:
>> + case DPDMA_CH4_PYLD_SZ:
>> + case DPDMA_CH5_PYLD_SZ:
>> + case DPDMA_CH0_DSCR_ID:
>> + case DPDMA_CH1_DSCR_ID:
>> + case DPDMA_CH2_DSCR_ID:
>> + case DPDMA_CH3_DSCR_ID:
>> + case DPDMA_CH4_DSCR_ID:
>> + case DPDMA_CH5_DSCR_ID:
> Any opportunities for case FOO ... BAR in this?
What do you mean?
>
>> + /*
>> + * Trying to write to a read only register..
>> + */
>> + break;
>> + case DPDMA_GBL:
>> + /*
>> + * This is a write only register so it's read as zero in the read
>> + * callback.
>> + * We store the value anyway so we can know if the channel is
>> + * enabled.
>> + */
>> + s->registers[offset] = value & 0x00000FFF;
>> + break;
>> + case DPDMA_CH0_DSCR_STRT_ADDRE:
>> + case DPDMA_CH1_DSCR_STRT_ADDRE:
>> + case DPDMA_CH2_DSCR_STRT_ADDRE:
>> + case DPDMA_CH3_DSCR_STRT_ADDRE:
>> + case DPDMA_CH4_DSCR_STRT_ADDRE:
>> + case DPDMA_CH5_DSCR_STRT_ADDRE:
>> + value &= 0x0000FFFF;
>> + s->registers[offset] = value;
>> + break;
>> + case DPDMA_CH0_CNTL:
>> + case DPDMA_CH1_CNTL:
>> + case DPDMA_CH2_CNTL:
>> + case DPDMA_CH3_CNTL:
>> + case DPDMA_CH4_CNTL:
>> + case DPDMA_CH5_CNTL:
>> + value &= 0x3FFFFFFF;
>> + s->registers[offset] = value;
>> + break;
>> + default:
>> + assert(offset <= (0xFFC >> 2));
>> + s->registers[offset] = value;
>> + break;
>> + }
>> +}
>> +
>> +static const MemoryRegionOps dma_ops = {
>> + .read = xilinx_dpdma_read,
>> + .write = xilinx_dpdma_write,
> The MMIO size and alignment restrictions go here.
>
>> + .endianness = DEVICE_NATIVE_ENDIAN,
>> +};
>> +
>> +static void xilinx_dpdma_init(Object *obj)
>> +{
>> + SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
>> + XilinxDPDMAState *s = XILINX_DPDMA(obj);
>> +
>> + memory_region_init_io(&s->iomem, obj, &dma_ops, s,
>> + TYPE_XILINX_DPDMA, 0x1000);
>> + sysbus_init_mmio(sbd, &s->iomem);
>> + sysbus_init_irq(sbd, &s->irq);
>> +}
>> +
>> +static void xilinx_dpdma_reset(DeviceState *dev)
>> +{
>> + XilinxDPDMAState *s = XILINX_DPDMA(dev);
> blank line.
>
>> + memset(s->registers, 0, sizeof(s->registers));
>> + s->registers[DPDMA_IMR] = 0x07FFFFFF;
>> + s->registers[DPDMA_EIMR] = 0xFFFFFFFF;
>> + s->registers[DPDMA_ALC0_MIN] = 0x0000FFFF;
>> + s->registers[DPDMA_ALC1_MIN] = 0x0000FFFF;
>> +}
>> +
>> +static void xilinx_dpdma_class_init(ObjectClass *oc, void *data)
>> +{
>> + DeviceClass *dc = DEVICE_CLASS(oc);
>> +
>> + dc->vmsd = &vmstate_xilinx_dpdma;
>> + dc->reset = xilinx_dpdma_reset;
>> +}
>> +
>> +static const TypeInfo xilinx_dpdma_info = {
>> + .name = TYPE_XILINX_DPDMA,
>> + .parent = TYPE_SYS_BUS_DEVICE,
>> + .instance_size = sizeof(XilinxDPDMAState),
>> + .instance_init = xilinx_dpdma_init,
>> + .class_init = xilinx_dpdma_class_init,
>> +};
>> +
>> +static void xilinx_dpdma_register_types(void)
>> +{
>> + type_register_static(&xilinx_dpdma_info);
>> +}
>> +
>> +size_t xilinx_dpdma_start_operation(XilinxDPDMAState *s, uint8_t channel,
>> + bool one_desc)
>> +{
>> + uint64_t desc_addr;
>> + uint64_t source_addr[6];
>> + DPDMADescriptor desc;
>> + bool done = false;
>> + size_t ptr = 0;
>> +
>> + assert(channel <= 5);
>> +
>> + if (channel == 3) {
>> + s->registers[DPDMA_ISR] |= (1 << 27);
>> + xilinx_dpdma_update_irq(s);
>> + }
> Interesting special case for #3. does it need a comment?
Yes this is the VSYNC interrupt from DPDMA.
BTW probably 27 needs a macro too, to be clearer.
>
>> +
>> + DPRINTF("dpdma_start_channel() on channel %u\n", channel);
>> +
>> + if (!xilinx_dpdma_is_channel_triggered(s, channel)) {
>> + DPRINTF("Channel isn't triggered..\n");
>> + return 0;
>> + }
>> +
>> + if (!xilinx_dpdma_is_channel_enabled(s, channel)) {
>> + DPRINTF("Channel isn't enabled..\n");
>> + return 0;
>> + }
>> +
>> + if (xilinx_dpdma_is_channel_paused(s, channel)) {
>> + DPRINTF("Channel is paused..\n");
>> + return 0;
>> + }
>> +
>> + do {
>> + if ((s->operation_finished[channel])
>> + || xilinx_dpdma_is_channel_retriggered(s, channel)) {
>> + desc_addr = xilinx_dpdma_descriptor_start_address(s, channel);
>> + s->operation_finished[channel] = false;
>> + } else {
>> + desc_addr = xilinx_dpdma_descriptor_next_address(s, channel);
>> + }
>> +
>> + if (dma_memory_read(&address_space_memory, desc_addr, &desc,
>> + sizeof(DPDMADescriptor))) {
>> + s->registers[DPDMA_EISR] |= ((1 << 1) << channel);
>> + xilinx_dpdma_update_irq(s);
>> + s->operation_finished[channel] = true;
>> + DPRINTF("Can't get the descriptor.\n");
>> + break;
>> + }
>> +
>> + xilinx_dpdma_update_desc_info(s, channel, &desc);
>> +
>> + #ifdef DEBUG_DPDMA
> No leading whitespace before #if
>
>> + xilinx_dpdma_dump_descriptor(&desc);
>> + #endif
>> +
>> + DPRINTF("location of the descriptor: 0x%8.8lx\n", desc_addr);
> Should this be PRIx64? (there's more of these below).
Definitely.
>
>> + if (!xilinx_dpdma_desc_is_valid(&desc)) {
>> + s->registers[DPDMA_EISR] |= ((1 << 7) << channel);
>> + xilinx_dpdma_update_irq(s);
>> + s->operation_finished[channel] = true;
>> + DPRINTF("Invalid descriptor..\n");
>> + break;
>> + }
>> +
>> + if (xilinx_dpdma_desc_crc_enabled(&desc)
>> + & !xilinx_dpdma_desc_check_crc(&desc)) {
> &&
oops didn't see that :).
>
>> + s->registers[DPDMA_EISR] |= ((1 << 13) << channel);
>> + xilinx_dpdma_update_irq(s);
>> + s->operation_finished[channel] = true;
>> + DPRINTF("Bad CRC for descriptor..\n");
>> + break;
>> + }
>> +
>> + if (xilinx_dpdma_desc_is_already_done(&desc)
>> + && !xilinx_dpdma_desc_ignore_done_bit(&desc)) {
>> + /* We are trying to process an already processed descriptor. */
>> + s->registers[DPDMA_EISR] |= ((1 << 25) << channel);
>> + xilinx_dpdma_update_irq(s);
>> + s->operation_finished[channel] = true;
>> + DPRINTF("Already processed descriptor..\n");
>> + break;
>> + }
>> +
>> + done = xilinx_dpdma_desc_is_last(&desc)
>> + | xilinx_dpdma_desc_is_last_of_frame(&desc);
> ||. these "is" function results should be treated as logicals.
>
>> +
>> + s->operation_finished[channel] = done;
>> + if (s->data[channel]) {
>> + int64_t transfer_len =
>> + xilinx_dpdma_desc_get_transfer_size(&desc);
>> + uint32_t line_size = xilinx_dpdma_desc_get_line_size(&desc);
>> + uint32_t line_stride = xilinx_dpdma_desc_get_line_stride(&desc);
>> + if (xilinx_dpdma_desc_is_contiguous(&desc)) {
>> + source_addr[0] =
>> + xilinx_dpdma_desc_get_source_address(&desc, 0);
>> + while (transfer_len != 0) {
>> + if (dma_memory_read(&address_space_memory,
>> + source_addr[0],
>> + &(s->data[channel][ptr]),
> parenthesis not needed.
>
>> + line_size)) {
>> + s->registers[DPDMA_ISR] |= ((1 << 12) << channel);
>> + xilinx_dpdma_update_irq(s);
>> + DPRINTF("Can't get data.\n");
>> + break;
>> + }
>> + ptr += line_size;
>> + transfer_len -= line_size;
>> + source_addr[0] += line_stride;
>> + }
>> + } else {
>> + DPRINTF("Source address:\n");
>> + int frag;
>> + for (frag = 0; frag < 5; frag++) {
>> + source_addr[frag] =
>> + xilinx_dpdma_desc_get_source_address(&desc, frag);
>> + DPRINTF("Fragment %u: 0x%8.8lX\n", frag + 1,
>> + source_addr[frag]);
>> + }
>> +
>> + frag = 0;
>> + while (transfer_len < 0) {
> && frag < 5 ?
yes good point.
>
>> + if (frag >= 5) {
>> + break;
>> + }
> To drop this.
>
>> + size_t fragment_len = 4096 - (source_addr[frag] % 4096);
> Magic number 4096.
>
>> +
>> + if (dma_memory_read(&address_space_memory,
>> + source_addr[frag],
>> + &(s->data[channel][ptr]),
>> + fragment_len)) {
>> + s->registers[DPDMA_ISR] |= ((1 << 12) << channel);
>> + xilinx_dpdma_update_irq(s);
>> + DPRINTF("Can't get data.\n");
>> + break;
>> + }
>> + ptr += fragment_len;
>> + transfer_len -= fragment_len;
>> + frag += 1;
>> + }
>> + }
>> + }
>> +
>> + if (xilinx_dpdma_desc_update_enabled(&desc)) {
>> + /* The descriptor need to be updated when it's completed. */
>> + DPRINTF("update the descriptor with the done flag set.\n");
>> + xilinx_dpdma_desc_set_done(&desc);
>> + if (dma_memory_write(&address_space_memory, desc_addr, &desc,
>> + sizeof(DPDMADescriptor))) {
>> + abort();
> It should be left the the memory API to determine if its a memory
> write is fatal. There are system level changed beyond this modules
> control that could cause memory API to say no to this op. A quick grep
> suggest its normal to just post the write and not assert success. The
> one user of the return value I can see (ohci) does a graceful failure
> on it.
>
>> + }
>> + }
>> +
>> + if (xilinx_dpdma_desc_completion_interrupt(&desc)) {
>> + DPRINTF("completion interrupt enabled!\n");
>> + s->registers[DPDMA_ISR] |= (1 << channel);
>> + xilinx_dpdma_update_irq(s);
>> + }
>> +
>> + } while (!done && !one_desc);
>> +
>> + return ptr;
>> +}
>> +
>> +/*
>> + * Set the host location to be filled with the data.
>> + */
> Non-static function can just rely on comment in heade.
>
>> +void xilinx_dpdma_set_host_data_location(XilinxDPDMAState *s, uint8_t channel,
>> + void *p)
>> +{
>> + if (!s) {
>> + qemu_log_mask(LOG_UNIMP, "DPDMA client not attached to valid DPDMA"
>> + " instance\n");
>> + return;
>> + }
>> +
>> + assert(channel <= 5);
>> + s->data[channel] = p;
>> +}
>> +
>> +type_init(xilinx_dpdma_register_types)
>> diff --git a/hw/dma/xilinx_dpdma.h b/hw/dma/xilinx_dpdma.h
>> new file mode 100644
>> index 0000000..f92167d
>> --- /dev/null
>> +++ b/hw/dma/xilinx_dpdma.h
>> @@ -0,0 +1,71 @@
>> +/*
>> + * xilinx_dpdma.h
>> + *
>> + * Copyright (C) 2015 : GreenSocs Ltd
>> + * http://www.greensocs.com/ , email: info@greensocs.com
>> + *
>> + * Developed by :
>> + * Frederic Konrad <fred.konrad@greensocs.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation, either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along
>> + * with this program; if not, see <http://www.gnu.org/licenses/>.
>> + *
>> + */
>> +
>> +#ifndef XILINX_DPDMA_H
>> +#define XILINX_DPDMA_H
>> +
>> +#include "hw/sysbus.h"
>> +#include "ui/console.h"
>> +#include "sysemu/dma.h"
>> +
>> +struct XilinxDPDMAState {
> /*< private >*/
>
>> + SysBusDevice parent_obj;
> /*< public >*/
>
>> + MemoryRegion iomem;
>> + uint32_t registers[0x1000 >> 2];
>> + uint8_t *data[6];
>> + bool operation_finished[6];
>> + qemu_irq irq;
>> +};
>> +
>> +typedef struct XilinxDPDMAState XilinxDPDMAState;
> Can you just define and typedef together? Thats quite common. unless
> you have a circular ref between module or need to define the type
> opaquely.
>
>> +
>> +#define TYPE_XILINX_DPDMA "xlnx.dpdma"
>> +#define XILINX_DPDMA(obj) OBJECT_CHECK(XilinxDPDMAState, (obj), \
>> + TYPE_XILINX_DPDMA)
>> +
>> +/*
>> + * \func xilinx_dpdma_start_operation.
>> + * \brief Start the operation on the specified channel. The DPDMA get the
>> + * current descriptor and retrieve data to the buffer specified by
>> + * dpdma_set_host_data_location.
>> + * \arg s The DPDMA instance.
>> + * \arg channel The channel to start.
>> + * \return the number of byte transfered by the DPDMA or 0 if an error occured.
>> + */
>> +size_t xilinx_dpdma_start_operation(XilinxDPDMAState *s, uint8_t channel,
>> + bool one_desc);
>> +
>> +/*
>> + * \func xilinx_dpdma_set_host_data_location.
>> + * \brief Set the location in the host memory where to store the data out from
>> + * the dma channel.
>> + * \arg s The DPDMA instance.
>> + * \arg channel The channel associated to the pointer.
>> + * \arg p The buffer where to store the data.
>> + */
> What is this documentation style? I can only see it in one other file
> in the tree (target-xtensa/helper.c). The doxygen * @ style is more
> common. Check bitops.h for a fuller example.
Ok I'll convert.
>
>> +/* XXX: add a maximum size arg and send an interrupt in case of overflow. */
> Does an interrupt have physical meaning? A host buffer overrun is some
> sort of fatal error isnt it?
You mean better aborting when it happens?
>
> Regards,
> Peter
>
>> +void xilinx_dpdma_set_host_data_location(XilinxDPDMAState *s, uint8_t channel,
>> + void *p);
>> +
>> +#endif /* !XILINX_DPDMA_H */
>> --
>> 1.9.0
>>
>>
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* [Qemu-devel] [PATCH 7/8] Introduce xilinx dp.
2015-05-13 19:11 [Qemu-devel] [PATCH 0/8] Xilinx DisplayPort fred.konrad
` (5 preceding siblings ...)
2015-05-13 19:12 ` [Qemu-devel] [PATCH 6/8] Introduce xilinx dpdma fred.konrad
@ 2015-05-13 19:12 ` fred.konrad
2015-05-13 19:12 ` [Qemu-devel] [PATCH 8/8] arm: xlnx-zynqmp: Add DisplayPort and DPDMA fred.konrad
7 siblings, 0 replies; 20+ messages in thread
From: fred.konrad @ 2015-05-13 19:12 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.crosthwaite, mark.burton, hyunk, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This is the implementation of the DisplayPort.
It has an aux-bus to access dpcd and edid needed for the driver to complete.
Graphic plane is connected to the channel 3.
Video plane is connected to the channel 0.
Audio stream are connected to the channels 4 and 5.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/display/Makefile.objs | 2 +-
hw/display/xilinx_dp.c | 1454 ++++++++++++++++++++++++++++++++++++++++++++++
hw/display/xilinx_dp.h | 125 ++++
3 files changed, 1580 insertions(+), 1 deletion(-)
create mode 100644 hw/display/xilinx_dp.c
create mode 100644 hw/display/xilinx_dp.h
diff --git a/hw/display/Makefile.objs b/hw/display/Makefile.objs
index f746cec..908411b 100644
--- a/hw/display/Makefile.objs
+++ b/hw/display/Makefile.objs
@@ -34,4 +34,4 @@ obj-$(CONFIG_CG3) += cg3.o
obj-$(CONFIG_VGA) += vga.o
common-obj-$(CONFIG_QXL) += qxl.o qxl-logger.o qxl-render.o
-common-obj-y += dpcd.o
+common-obj-y += dpcd.o xilinx_dp.o
diff --git a/hw/display/xilinx_dp.c b/hw/display/xilinx_dp.c
new file mode 100644
index 0000000..ca1df1b
--- /dev/null
+++ b/hw/display/xilinx_dp.c
@@ -0,0 +1,1454 @@
+/*
+ * xilinx_dp.c
+ *
+ * Copyright (C) 2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option)any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "xilinx_dp.h"
+
+#ifndef DEBUG_DP
+#define DEBUG_DP 0
+#endif
+
+#define DPRINTF(fmt, ...) do { \
+ if (DEBUG_DP) { \
+ qemu_log("xilinx_dp: " fmt , ## __VA_ARGS__); \
+ } \
+} while (0);
+
+/*
+ * Register offset for DP.
+ */
+#define DP_LINK_BW_SET (0x00000000 >> 2)
+#define DP_LANE_COUNT_SET (0x00000004 >> 2)
+#define DP_ENHANCED_FRAME_EN (0x00000008 >> 2)
+#define DP_TRAINING_PATTERN_SET (0x0000000C >> 2)
+#define DP_LINK_QUAL_PATTERN_SET (0x00000010 >> 2)
+#define DP_SCRAMBLING_DISABLE (0x00000014 >> 2)
+#define DP_DOWNSPREAD_CTRL (0x00000018 >> 2)
+#define DP_SOFTWARE_RESET (0x0000001C >> 2)
+#define DP_TRANSMITTER_ENABLE (0x00000080 >> 2)
+#define DP_MAIN_STREAM_ENABLE (0x00000084 >> 2)
+#define DP_FORCE_SCRAMBLER_RESET (0x000000C0 >> 2)
+#define DP_VERSION_REGISTER (0x000000F8 >> 2)
+#define DP_CORE_ID (0x000000FC >> 2)
+#define DP_AUX_COMMAND_REGISTER (0x00000100 >> 2)
+#define AUX_ADDR_ONLY_MASK (0x00001000)
+#define AUX_COMMAND_MASK (0x00000F00)
+#define AUX_COMMAND_SHIFT (8)
+#define AUX_COMMAND_NBYTES (0x0000000F)
+#define DP_AUX_WRITE_FIFO (0x00000104 >> 2)
+#define DP_AUX_ADDRESS (0x00000108 >> 2)
+#define DP_AUX_CLOCK_DIVIDER (0x0000010C >> 2)
+#define DP_TX_USER_FIFO_OVERFLOW (0x00000110 >> 2)
+#define DP_INTERRUPT_SIGNAL_STATE (0x00000130 >> 2)
+#define DP_AUX_REPLY_DATA (0x00000134 >> 2)
+#define DP_AUX_REPLY_CODE (0x00000138 >> 2)
+#define DP_AUX_REPLY_COUNT (0x0000013C >> 2)
+#define DP_REPLY_DATA_COUNT (0x00000148 >> 2)
+#define DP_REPLY_STATUS (0x0000014C >> 2)
+#define DP_HPD_DURATION (0x00000150 >> 2)
+#define DP_MAIN_STREAM_HTOTAL (0x00000180 >> 2)
+#define DP_MAIN_STREAM_VTOTAL (0x00000184 >> 2)
+#define DP_MAIN_STREAM_POLARITY (0x00000188 >> 2)
+#define DP_MAIN_STREAM_HSWIDTH (0x0000018C >> 2)
+#define DP_MAIN_STREAM_VSWIDTH (0x00000190 >> 2)
+#define DP_MAIN_STREAM_HRES (0x00000194 >> 2)
+#define DP_MAIN_STREAM_VRES (0x00000198 >> 2)
+#define DP_MAIN_STREAM_HSTART (0x0000019C >> 2)
+#define DP_MAIN_STREAM_VSTART (0x000001A0 >> 2)
+#define DP_MAIN_STREAM_MISC0 (0x000001A4 >> 2)
+#define DP_MAIN_STREAM_MISC1 (0x000001A8 >> 2)
+#define DP_MAIN_STREAM_M_VID (0x000001AC >> 2)
+#define DP_MSA_TRANSFER_UNIT_SIZE (0x000001B0 >> 2)
+#define DP_MAIN_STREAM_N_VID (0x000001B4 >> 2)
+#define DP_USER_DATA_COUNT_PER_LANE (0x000001BC >> 2)
+#define DP_MIN_BYTES_PER_TU (0x000001C4 >> 2)
+#define DP_FRAC_BYTES_PER_TU (0x000001C8 >> 2)
+#define DP_INIT_WAIT (0x000001CC >> 2)
+#define DP_PHY_RESET (0x00000200 >> 2)
+#define DP_PHY_VOLTAGE_DIFF_LANE_0 (0x00000220 >> 2)
+#define DP_PHY_VOLTAGE_DIFF_LANE_1 (0x00000224 >> 2)
+#define DP_TRANSMIT_PRBS7 (0x00000230 >> 2)
+#define DP_PHY_CLOCK_SELECT (0x00000234 >> 2)
+#define DP_TX_PHY_POWER_DOWN (0x00000238 >> 2)
+#define DP_PHY_PRECURSOR_LANE_0 (0x0000023C >> 2)
+#define DP_PHY_PRECURSOR_LANE_1 (0x00000240 >> 2)
+#define DP_PHY_POSTCURSOR_LANE_0 (0x0000024C >> 2)
+#define DP_PHY_POSTCURSOR_LANE_1 (0x00000250 >> 2)
+#define DP_PHY_STATUS (0x00000280 >> 2)
+#define DP_TX_AUDIO_CONTROL (0x00000300 >> 2)
+#define DP_TX_AUDIO_CHANNELS (0x00000304 >> 2)
+#define DP_TX_AUDIO_INFO_DATA0 (0x00000308 >> 2)
+#define DP_TX_AUDIO_INFO_DATA1 (0x0000030C >> 2)
+#define DP_TX_AUDIO_INFO_DATA2 (0x00000310 >> 2)
+#define DP_TX_AUDIO_INFO_DATA3 (0x00000314 >> 2)
+#define DP_TX_AUDIO_INFO_DATA4 (0x00000318 >> 2)
+#define DP_TX_AUDIO_INFO_DATA5 (0x0000031C >> 2)
+#define DP_TX_AUDIO_INFO_DATA6 (0x00000320 >> 2)
+#define DP_TX_AUDIO_INFO_DATA7 (0x00000324 >> 2)
+#define DP_TX_M_AUD (0x00000328 >> 2)
+#define DP_TX_N_AUD (0x0000032C >> 2)
+#define DP_TX_AUDIO_EXT_DATA0 (0x00000330 >> 2)
+#define DP_TX_AUDIO_EXT_DATA1 (0x00000334 >> 2)
+#define DP_TX_AUDIO_EXT_DATA2 (0x00000338 >> 2)
+#define DP_TX_AUDIO_EXT_DATA3 (0x0000033C >> 2)
+#define DP_TX_AUDIO_EXT_DATA4 (0x00000340 >> 2)
+#define DP_TX_AUDIO_EXT_DATA5 (0x00000344 >> 2)
+#define DP_TX_AUDIO_EXT_DATA6 (0x00000348 >> 2)
+#define DP_TX_AUDIO_EXT_DATA7 (0x0000034C >> 2)
+#define DP_TX_AUDIO_EXT_DATA8 (0x00000350 >> 2)
+#define DP_INT_STATUS (0x000003A0 >> 2)
+#define DP_INT_MASK (0x000003A4 >> 2)
+#define DP_INT_EN (0x000003A8 >> 2)
+#define DP_INT_DS (0x000003AC >> 2)
+
+/*
+ * Registers offset for Audio Video Buffer configuration.
+ */
+#define V_BLEND_OFFSET (0x0000A000)
+#define V_BLEND_BG_CLR_0 (0x00000000 >> 2)
+#define V_BLEND_BG_CLR_1 (0x00000004 >> 2)
+#define V_BLEND_BG_CLR_2 (0x00000008 >> 2)
+#define V_BLEND_SET_GLOBAL_ALPHA_REG (0x0000000C >> 2)
+#define V_BLEND_OUTPUT_VID_FORMAT (0x00000014 >> 2)
+#define V_BLEND_LAYER0_CONTROL (0x00000018 >> 2)
+#define V_BLEND_LAYER1_CONTROL (0x0000001C >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF0 (0x00000020 >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF1 (0x00000024 >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF2 (0x00000028 >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF3 (0x0000002C >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF4 (0x00000030 >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF5 (0x00000034 >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF6 (0x00000038 >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF7 (0x0000003C >> 2)
+#define V_BLEND_RGB2YCBCR_COEFF8 (0x00000040 >> 2)
+#define V_BLEND_IN1CSC_COEFF0 (0x00000044 >> 2)
+#define V_BLEND_IN1CSC_COEFF1 (0x00000048 >> 2)
+#define V_BLEND_IN1CSC_COEFF2 (0x0000004C >> 2)
+#define V_BLEND_IN1CSC_COEFF3 (0x00000050 >> 2)
+#define V_BLEND_IN1CSC_COEFF4 (0x00000054 >> 2)
+#define V_BLEND_IN1CSC_COEFF5 (0x00000058 >> 2)
+#define V_BLEND_IN1CSC_COEFF6 (0x0000005C >> 2)
+#define V_BLEND_IN1CSC_COEFF7 (0x00000060 >> 2)
+#define V_BLEND_IN1CSC_COEFF8 (0x00000064 >> 2)
+#define V_BLEND_LUMA_IN1CSC_OFFSET (0x00000068 >> 2)
+#define V_BLEND_CR_IN1CSC_OFFSET (0x0000006C >> 2)
+#define V_BLEND_CB_IN1CSC_OFFSET (0x00000070 >> 2)
+#define V_BLEND_LUMA_OUTCSC_OFFSET (0x00000074 >> 2)
+#define V_BLEND_CR_OUTCSC_OFFSET (0x00000078 >> 2)
+#define V_BLEND_CB_OUTCSC_OFFSET (0x0000007C >> 2)
+#define V_BLEND_IN2CSC_COEFF0 (0x00000080 >> 2)
+#define V_BLEND_IN2CSC_COEFF1 (0x00000084 >> 2)
+#define V_BLEND_IN2CSC_COEFF2 (0x00000088 >> 2)
+#define V_BLEND_IN2CSC_COEFF3 (0x0000008C >> 2)
+#define V_BLEND_IN2CSC_COEFF4 (0x00000090 >> 2)
+#define V_BLEND_IN2CSC_COEFF5 (0x00000094 >> 2)
+#define V_BLEND_IN2CSC_COEFF6 (0x00000098 >> 2)
+#define V_BLEND_IN2CSC_COEFF7 (0x0000009C >> 2)
+#define V_BLEND_IN2CSC_COEFF8 (0x000000A0 >> 2)
+#define V_BLEND_LUMA_IN2CSC_OFFSET (0x000000A4 >> 2)
+#define V_BLEND_CR_IN2CSC_OFFSET (0x000000A8 >> 2)
+#define V_BLEND_CB_IN2CSC_OFFSET (0x000000AC >> 2)
+#define V_BLEND_CHROMA_KEY_ENABLE (0x000001D0 >> 2)
+#define V_BLEND_CHROMA_KEY_COMP1 (0x000001D4 >> 2)
+#define V_BLEND_CHROMA_KEY_COMP2 (0x000001D8 >> 2)
+#define V_BLEND_CHROMA_KEY_COMP3 (0x000001DC >> 2)
+
+/*
+ * Registers offset for Audio Video Buffer configuration.
+ */
+#define AV_BUF_MANAGER_OFFSET (0x0000B000)
+#define AV_BUF_FORMAT (0x00000000 >> 2)
+#define AV_BUF_NON_LIVE_LATENCY (0x00000008 >> 2)
+#define AV_CHBUF0 (0x00000010 >> 2)
+#define AV_CHBUF1 (0x00000014 >> 2)
+#define AV_CHBUF2 (0x00000018 >> 2)
+#define AV_CHBUF3 (0x0000001C >> 2)
+#define AV_CHBUF4 (0x00000020 >> 2)
+#define AV_CHBUF5 (0x00000024 >> 2)
+#define AV_BUF_STC_CONTROL (0x0000002C >> 2)
+#define AV_BUF_STC_INIT_VALUE0 (0x00000030 >> 2)
+#define AV_BUF_STC_INIT_VALUE1 (0x00000034 >> 2)
+#define AV_BUF_STC_ADJ (0x00000038 >> 2)
+#define AV_BUF_STC_VIDEO_VSYNC_TS_REG0 (0x0000003C >> 2)
+#define AV_BUF_STC_VIDEO_VSYNC_TS_REG1 (0x00000040 >> 2)
+#define AV_BUF_STC_EXT_VSYNC_TS_REG0 (0x00000044 >> 2)
+#define AV_BUF_STC_EXT_VSYNC_TS_REG1 (0x00000048 >> 2)
+#define AV_BUF_STC_CUSTOM_EVENT_TS_REG0 (0x0000004C >> 2)
+#define AV_BUF_STC_CUSTOM_EVENT_TS_REG1 (0x00000050 >> 2)
+#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG0 (0x00000054 >> 2)
+#define AV_BUF_STC_CUSTOM_EVENT2_TS_REG1 (0x00000058 >> 2)
+#define AV_BUF_STC_SNAPSHOT0 (0x00000060 >> 2)
+#define AV_BUF_STC_SNAPSHOT1 (0x00000064 >> 2)
+#define AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT (0x00000070 >> 2)
+#define AV_BUF_HCOUNT_VCOUNT_INT0 (0x00000074 >> 2)
+#define AV_BUF_HCOUNT_VCOUNT_INT1 (0x00000078 >> 2)
+#define AV_BUF_DITHER_CONFIG (0x0000007C >> 2)
+#define AV_BUF_DITHER_CONFIG_MAX (0x0000008C >> 2)
+#define AV_BUF_DITHER_CONFIG_MIN (0x00000090 >> 2)
+#define AV_BUF_PATTERN_GEN_SELECT (0x00000100 >> 2)
+#define AV_BUF_AUD_VID_CLK_SOURCE (0x00000120 >> 2)
+#define AV_BUF_SRST_REG (0x00000124 >> 2)
+#define AV_BUF_AUDIO_RDY_INTERVAL (0x00000128 >> 2)
+#define AV_BUF_AUDIO_CH_CONFIG (0x0000012C >> 2)
+#define AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR (0x00000200 >> 2)
+#define AV_BUF_GRAPHICS_COMP1_SCALE_FACTOR (0x00000204 >> 2)
+#define AV_BUF_GRAPHICS_COMP2_SCALE_FACTOR (0x00000208 >> 2)
+#define AV_BUF_VIDEO_COMP0_SCALE_FACTOR (0x0000020C >> 2)
+#define AV_BUF_VIDEO_COMP1_SCALE_FACTOR (0x00000210 >> 2)
+#define AV_BUF_VIDEO_COMP2_SCALE_FACTOR (0x00000214 >> 2)
+#define AV_BUF_LIVE_VIDEO_COMP0_SF (0x00000218 >> 2)
+#define AV_BUF_LIVE_VIDEO_COMP1_SF (0x0000021C >> 2)
+#define AV_BUF_LIVE_VIDEO_COMP2_SF (0x00000220 >> 2)
+#define AV_BUF_LIVE_VID_CONFIG (0x00000224 >> 2)
+#define AV_BUF_LIVE_GFX_COMP0_SF (0x00000228 >> 2)
+#define AV_BUF_LIVE_GFX_COMP1_SF (0x0000022C >> 2)
+#define AV_BUF_LIVE_GFX_COMP2_SF (0x00000230 >> 2)
+#define AV_BUF_LIVE_GFX_CONFIG (0x00000234 >> 2)
+
+#define AUDIO_MIXER_REGISTER_OFFSET (0x0000C000)
+#define AUDIO_MIXER_VOLUME_CONTROL (0x00000000 >> 2)
+#define AUDIO_MIXER_META_DATA (0x00000004 >> 2)
+#define AUD_CH_STATUS_REG0 (0x00000008 >> 2)
+#define AUD_CH_STATUS_REG1 (0x0000000C >> 2)
+#define AUD_CH_STATUS_REG2 (0x00000010 >> 2)
+#define AUD_CH_STATUS_REG3 (0x00000014 >> 2)
+#define AUD_CH_STATUS_REG4 (0x00000018 >> 2)
+#define AUD_CH_STATUS_REG5 (0x0000001C >> 2)
+#define AUD_CH_A_DATA_REG0 (0x00000020 >> 2)
+#define AUD_CH_A_DATA_REG1 (0x00000024 >> 2)
+#define AUD_CH_A_DATA_REG2 (0x00000028 >> 2)
+#define AUD_CH_A_DATA_REG3 (0x0000002C >> 2)
+#define AUD_CH_A_DATA_REG4 (0x00000030 >> 2)
+#define AUD_CH_A_DATA_REG5 (0x00000034 >> 2)
+#define AUD_CH_B_DATA_REG0 (0x00000038 >> 2)
+#define AUD_CH_B_DATA_REG1 (0x0000003C >> 2)
+#define AUD_CH_B_DATA_REG2 (0x00000040 >> 2)
+#define AUD_CH_B_DATA_REG3 (0x00000044 >> 2)
+#define AUD_CH_B_DATA_REG4 (0x00000048 >> 2)
+#define AUD_CH_B_DATA_REG5 (0x0000004C >> 2)
+
+typedef enum dp_graphic_fmt {
+ DP_GRAPHIC_RGBA8888 = 0 << 8,
+ DP_GRAPHIC_ABGR8888 = 1 << 8,
+ DP_GRAPHIC_RGB888 = 2 << 8,
+ DP_GRAPHIC_BGR888 = 3 << 8,
+ DP_GRAPHIC_RGBA5551 = 4 << 8,
+ DP_GRAPHIC_RGBA4444 = 5 << 8,
+ DP_GRAPHIC_RGB565 = 6 << 8,
+ DP_GRAPHIC_8BPP = 7 << 8,
+ DP_GRAPHIC_4BPP = 8 << 8,
+ DP_GRAPHIC_2BPP = 9 << 8,
+ DP_GRAPHIC_1BPP = 10 << 8,
+ DP_GRAPHIC_MASK = 0xF << 8
+} dp_graphic_fmt;
+
+typedef enum dp_video_fmt {
+ DP_NL_VID_CB_Y0_CR_Y1 = 0,
+ DP_NL_VID_CR_Y0_CB_Y1 = 1,
+ DP_NL_VID_Y0_CR_Y1_CB = 2,
+ DP_NL_VID_Y0_CB_Y1_CR = 3,
+ DP_NL_VID_YV16 = 4,
+ DP_NL_VID_YV24 = 5,
+ DP_NL_VID_YV16CL = 6,
+ DP_NL_VID_MONO = 7,
+ DP_NL_VID_YV16CL2 = 8,
+ DP_NL_VID_YUV444 = 9,
+ DP_NL_VID_RGB888 = 10,
+ DP_NL_VID_RGBA8880 = 11,
+ DP_NL_VID_RGB888_10BPC = 12,
+ DP_NL_VID_YUV444_10BPC = 13,
+ DP_NL_VID_YV16CL2_10BPC = 14,
+ DP_NL_VID_YV16CL_10BPC = 15,
+ DP_NL_VID_YV16_10BPC = 16,
+ DP_NL_VID_YV24_10BPC = 17,
+ DP_NL_VID_Y_ONLY_10BPC = 18,
+ DP_NL_VID_YV16_420 = 19,
+ DP_NL_VID_YV16CL_420 = 20,
+ DP_NL_VID_YV16CL2_420 = 21,
+ DP_NL_VID_YV16_420_10BPC = 22,
+ DP_NL_VID_YV16CL_420_10BPC = 23,
+ DP_NL_VID_YV16CL2_420_10BPC = 24,
+ DP_NL_VID_FMT_MASK = 0x1F
+} dp_video_fmt;
+
+static const VMStateDescription vmstate_dp = {
+ .name = TYPE_XILINX_DP,
+ .version_id = 1,
+ .fields = (VMStateField[]){
+
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void xilinx_dp_update_irq(XilinxDPState *s);
+
+static uint64_t xilinx_dp_audio_read(void *opaque, hwaddr offset, unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+ assert(size == 4);
+ assert((offset % 4) == 0);
+
+ offset = offset >> 2;
+
+ switch (offset) {
+ default:
+ return s->audio_registers[offset];
+ break;
+ }
+}
+
+static void xilinx_dp_audio_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+ assert(size == 4);
+ assert((offset % 4) == 0);
+
+ offset = offset >> 2;
+
+ switch (offset) {
+ case AUDIO_MIXER_META_DATA:
+ s->audio_registers[offset] = value & 0x00000001;
+ break;
+ default:
+ s->audio_registers[offset] = value;
+ break;
+ }
+}
+
+static const MemoryRegionOps audio_ops = {
+ .read = xilinx_dp_audio_read,
+ .write = xilinx_dp_audio_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static inline uint32_t xilinx_dp_audio_get_volume(XilinxDPState *s,
+ uint8_t channel)
+{
+ switch (channel) {
+ case 0:
+ return s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL] & 0xFFFF;
+ break;
+ case 1:
+ return (s->audio_registers[AUDIO_MIXER_VOLUME_CONTROL] >> 16) & 0xFFFF;
+ break;
+ default:
+ return 0;
+ break;
+ }
+}
+
+static inline uint8_t xilinx_dp_audio_get_channel_count(XilinxDPState *s)
+{
+ return (s->core_registers[DP_TX_AUDIO_CHANNELS] & 0x00000007) + 1;
+}
+
+static inline void xilinx_dp_audio_activate(XilinxDPState *s)
+{
+ bool activated =
+ ((s->core_registers[DP_TX_AUDIO_CONTROL] & 0x00000001) != 0);
+ activated &= (xilinx_dp_audio_get_channel_count(s) > 0);
+ AUD_set_active_out(s->amixer_output_stream, activated);
+ xilinx_dpdma_set_host_data_location(s->dpdma, 4, &s->audio_buffer_0);
+ xilinx_dpdma_set_host_data_location(s->dpdma, 5, &s->audio_buffer_1);
+}
+
+static inline void xilinx_dp_audio_mix_buffer(XilinxDPState *s)
+{
+ /*
+ * Audio packets are signed and have this shape:
+ * | 16 | 16 | 16 | 16 | 16 | 16 | 16 | 16 |
+ * | R3 | L3 | R2 | L2 | R1 | L1 | R0 | L0 |
+ *
+ * Output audio is 16bits saturated.
+ */
+ int i;
+
+ if ((s->audio_data_available[0]) && (xilinx_dp_audio_get_volume(s, 0))) {
+ for (i = 0; i < s->audio_data_available[0] / 2; i++) {
+ s->temp_buffer[i] = (int64_t)(s->audio_buffer_0[i])
+ * xilinx_dp_audio_get_volume(s, 0) / 8192;
+ }
+ s->byte_left = s->audio_data_available[0];
+ } else {
+ memset(s->temp_buffer, 0, s->audio_data_available[1] / 2);
+ }
+
+ if ((s->audio_data_available[1]) && (xilinx_dp_audio_get_volume(s, 1))) {
+ if ((s->audio_data_available[0] == 0)
+ || (s->audio_data_available[1] == s->audio_data_available[0])) {
+ for (i = 0; i < s->audio_data_available[1] / 2; i++) {
+ s->temp_buffer[i] += (int64_t)(s->audio_buffer_1[i])
+ * xilinx_dp_audio_get_volume(s, 1) / 8192;
+ }
+ s->byte_left = s->audio_data_available[1];
+ }
+ }
+
+ for (i = 0; i < s->byte_left / 2; i++) {
+ s->out_buffer[i] = s->temp_buffer[i];
+ if (s->temp_buffer[i] < -32767) {
+ s->out_buffer[i] = -32767;
+ }
+ if (s->temp_buffer[i] > 32767) {
+ s->out_buffer[i] = 32767;
+ }
+ }
+
+ s->data_ptr = 0;
+}
+
+static void xilinx_dp_audio_callback(void *opaque, int avail)
+{
+ /*
+ * Get some data from the DPDMA and compute them. Then wait QEMU's audio
+ * subsystem to call this callback.
+ */
+ XilinxDPState *s = XILINX_DP(opaque);
+ size_t written = 0;
+ static uint8_t buffer;
+
+ /* If there are already some data don't get more data. */
+ if (s->byte_left == 0) {
+ buffer++;
+ s->audio_data_available[0] = xilinx_dpdma_start_operation(s->dpdma, 4,
+ true);
+ if (xilinx_dp_audio_get_channel_count(s) > 1) {
+ s->audio_data_available[1] =
+ xilinx_dpdma_start_operation(s->dpdma, 5, true);
+ }
+ xilinx_dp_audio_mix_buffer(s);
+ }
+
+ /* Send the buffer through the audio. */
+ if (s->byte_left <= MAX_QEMU_BUFFER_SIZE) {
+ if (s->byte_left != 0) {
+ written = AUD_write(s->amixer_output_stream,
+ &s->out_buffer[s->data_ptr], s->byte_left);
+ } else {
+ /*
+ * There is nothing to play.. We don't have any data! Fill the
+ * buffer with zero's and send it.
+ */
+ written = 0;
+ memset(s->out_buffer, 0, 1024);
+ AUD_write(s->amixer_output_stream, s->out_buffer, 1024);
+ }
+ } else {
+ written = AUD_write(s->amixer_output_stream,
+ &s->out_buffer[s->data_ptr], MAX_QEMU_BUFFER_SIZE);
+ }
+ s->byte_left -= written;
+ s->data_ptr += written;
+}
+
+/*
+ * AUX channel related function.
+ */
+static void xilinx_dp_aux_clear_rx_fifo(XilinxDPState *s)
+{
+ fifo8_reset(&s->rx_fifo);
+}
+
+static void xilinx_dp_aux_push_rx_fifo(XilinxDPState *s, uint8_t *buf,
+ size_t len)
+{
+ int i;
+
+ DPRINTF("Push %u data in rx_fifo\n", (unsigned)len);
+ for (i = 0; i < len; i++) {
+ if (fifo8_is_full(&s->rx_fifo)) {
+ DPRINTF("rx_fifo overflow..\n");
+ abort();
+ }
+ fifo8_push(&s->rx_fifo, buf[i]);
+ }
+}
+
+static uint8_t xilinx_dp_aux_pop_rx_fifo(XilinxDPState *s)
+{
+ uint8_t ret;
+
+ if (fifo8_is_empty(&s->rx_fifo)) {
+ DPRINTF("rx_fifo underflow..\n");
+ abort();
+ }
+ ret = fifo8_pop(&s->rx_fifo);
+ DPRINTF("pop 0x%2.2X from rx_fifo.\n", ret);
+ return ret;
+}
+
+static void xilinx_dp_aux_clear_tx_fifo(XilinxDPState *s)
+{
+ fifo8_reset(&s->tx_fifo);
+}
+
+static void xilinx_dp_aux_push_tx_fifo(XilinxDPState *s, uint8_t *buf,
+ size_t len)
+{
+ int i;
+
+ DPRINTF("Push %u data in tx_fifo\n", (unsigned)len);
+ for (i = 0; i < len; i++) {
+ if (fifo8_is_full(&s->tx_fifo)) {
+ DPRINTF("tx_fifo overflow..\n");
+ abort();
+ }
+ fifo8_push(&s->tx_fifo, buf[i]);
+ }
+}
+
+static uint8_t xilinx_dp_aux_pop_tx_fifo(XilinxDPState *s)
+{
+ uint8_t ret;
+
+ if (fifo8_is_empty(&s->tx_fifo)) {
+ DPRINTF("tx_fifo underflow..\n");
+ abort();
+ }
+ ret = fifo8_pop(&s->tx_fifo);
+ DPRINTF("pop 0x%2.2X from tx_fifo.\n", ret);
+ return ret;
+}
+
+static uint32_t xilinx_dp_aux_get_address(XilinxDPState *s)
+{
+ return s->core_registers[DP_AUX_ADDRESS];
+}
+
+static uint8_t xilinx_dp_aux_get_data(XilinxDPState *s)
+{
+ return xilinx_dp_aux_pop_rx_fifo(s);
+}
+
+static void xilinx_dp_aux_set_data(XilinxDPState *s, uint8_t value)
+{
+ xilinx_dp_aux_push_tx_fifo(s, &value, 1);
+}
+
+/*
+ * Get command from the register.
+ */
+static void xilinx_dp_aux_set_command(XilinxDPState *s, uint32_t value)
+{
+ /*
+ * XXX: What happen in the corner case, eg: fifo under/overflow?
+ */
+ bool address_only = (value & AUX_ADDR_ONLY_MASK) != 0;
+ aux_command cmd = (value & AUX_COMMAND_MASK) >> AUX_COMMAND_SHIFT;
+ uint8_t nbytes = (value & AUX_COMMAND_NBYTES) + 1;
+ uint8_t buf[16];
+ int i;
+
+ /*
+ * When an address_only command is executed nothing happen to the fifo, so
+ * just make nbytes = 0.
+ */
+ if (address_only) {
+ nbytes = 0;
+ }
+
+ switch (cmd) {
+ case READ_AUX:
+ case READ_I2C:
+ case READ_I2C_MOT:
+ s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
+ xilinx_dp_aux_get_address(s),
+ nbytes, buf);
+ s->core_registers[DP_REPLY_DATA_COUNT] = nbytes;
+
+ if (s->core_registers[DP_AUX_REPLY_CODE] == AUX_I2C_ACK) {
+ xilinx_dp_aux_push_rx_fifo(s, buf, nbytes);
+ }
+ break;
+ case WRITE_AUX:
+ case WRITE_I2C:
+ case WRITE_I2C_MOT:
+ for (i = 0; i < nbytes; i++) {
+ buf[i] = xilinx_dp_aux_pop_tx_fifo(s);
+ }
+ s->core_registers[DP_AUX_REPLY_CODE] = aux_request(s->aux_bus, cmd,
+ xilinx_dp_aux_get_address(s),
+ nbytes, buf);
+ xilinx_dp_aux_clear_tx_fifo(s);
+ break;
+ case WRITE_I2C_STATUS:
+ default:
+ abort();
+ break;
+ }
+
+ /*
+ * XXX: Trigger an interrupt here?
+ * The reply is received.. so just assert the flag.
+ */
+ s->core_registers[DP_INTERRUPT_SIGNAL_STATE] |= 0x04;
+}
+
+static void xilinx_dp_set_dpdma(Object *obj, const char *name, Object *val,
+ Error **errp)
+{
+ XilinxDPState *s = XILINX_DP(obj);
+ if (s->console) {
+ DisplaySurface *surface = qemu_console_surface(s->console);
+ XilinxDPDMAState *dma = XILINX_DPDMA(val);
+ xilinx_dpdma_set_host_data_location(dma, 3, surface_data(surface));
+ }
+}
+
+/*
+ * Recreate the surfaces for the DP.
+ * This happen after a resolution or format change.
+ */
+static void xilinx_dp_recreate_surface(XilinxDPState *s)
+{
+ uint16_t width = s->core_registers[DP_MAIN_STREAM_HRES];
+ uint16_t height = s->core_registers[DP_MAIN_STREAM_VRES];
+
+ if ((width != 0) && (height != 0)) {
+ s->planes[0].surface
+ = qemu_create_displaysurface_format(s->planes[0].format,
+ width, height);
+ dpy_gfx_replace_surface(s->console, s->planes[0].surface);
+ xilinx_dpdma_set_host_data_location(s->dpdma, 3,
+ surface_data(s->planes[0].surface));
+ /* Do the same for the blending plane. */
+ qemu_free_displaysurface(s->planes[1].surface);
+ s->planes[1].surface
+ = qemu_create_displaysurface_format(s->planes[1].format,
+ width, height);
+ xilinx_dpdma_set_host_data_location(s->dpdma, 0,
+ surface_data(s->planes[1].surface));
+ }
+}
+
+/*
+ * Change the graphic format of the surface.
+ * XXX: To be completed.
+ */
+static void xilinx_dp_change_graphic_fmt(XilinxDPState *s)
+{
+ switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK) {
+ case DP_GRAPHIC_RGBA8888:
+ s->planes[0].format = PIXMAN_r8g8b8a8;
+ break;
+ case DP_GRAPHIC_ABGR8888:
+ s->planes[0].format = PIXMAN_a8b8g8r8;
+ break;
+ case DP_GRAPHIC_RGB565:
+ s->planes[0].format = PIXMAN_r5g6b5;
+ break;
+ case DP_GRAPHIC_RGB888:
+ s->planes[0].format = PIXMAN_r8g8b8;
+ break;
+ case DP_GRAPHIC_BGR888:
+ s->planes[0].format = PIXMAN_b8g8r8;
+ break;
+ default:
+ DPRINTF("error: unsupported graphic format %u.\n",
+ s->avbufm_registers[AV_BUF_FORMAT] & DP_GRAPHIC_MASK);
+ abort();
+ break;
+ }
+
+ switch (s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK) {
+ case 0:
+ s->planes[1].format = PIXMAN_r8g8b8a8;
+ break;
+ case DP_NL_VID_RGBA8880:
+ s->planes[1].format = PIXMAN_r8g8b8a8;
+ break;
+ default:
+ DPRINTF("error: unsupported video format %u.\n",
+ s->avbufm_registers[AV_BUF_FORMAT] & DP_NL_VID_FMT_MASK);
+ abort();
+ break;
+ }
+
+ xilinx_dp_recreate_surface(s);
+}
+
+static void xilinx_dp_update_irq(XilinxDPState *s)
+{
+ uint32_t flags;
+
+ flags = s->core_registers[DP_INT_STATUS] & ~s->core_registers[DP_INT_MASK];
+ DPRINTF("update IRQ value = %" PRIx32 "\n", flags);
+ qemu_set_irq(s->irq, flags != 0);
+}
+
+static uint64_t xilinx_dp_read(void *opaque, hwaddr offset, unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+ uint64_t ret = 0;
+
+ assert(size == 4);
+ assert((offset % 4) == 0);
+ offset = offset >> 2;
+
+ switch (offset) {
+ /*
+ * Trying to read a write only register.
+ */
+ case DP_TX_USER_FIFO_OVERFLOW:
+ ret = s->core_registers[DP_TX_USER_FIFO_OVERFLOW];
+ s->core_registers[DP_TX_USER_FIFO_OVERFLOW] = 0;
+ break;
+ case DP_AUX_WRITE_FIFO:
+ ret = 0;
+ break;
+ case DP_AUX_REPLY_DATA:
+ ret = xilinx_dp_aux_get_data(s);
+ break;
+ case DP_INTERRUPT_SIGNAL_STATE:
+ /*
+ * XXX: Not sure it is the right thing to do actually.
+ * The register is not written by the device driver so it's stuck
+ * to 0x04.
+ */
+ ret = s->core_registers[DP_INTERRUPT_SIGNAL_STATE];
+ s->core_registers[DP_INTERRUPT_SIGNAL_STATE] &= ~0x04;
+ break;
+ case DP_TX_AUDIO_INFO_DATA0:
+ case DP_TX_AUDIO_INFO_DATA1:
+ case DP_TX_AUDIO_INFO_DATA2:
+ case DP_TX_AUDIO_INFO_DATA3:
+ case DP_TX_AUDIO_INFO_DATA4:
+ case DP_TX_AUDIO_INFO_DATA5:
+ case DP_TX_AUDIO_INFO_DATA6:
+ case DP_TX_AUDIO_INFO_DATA7:
+ case DP_TX_AUDIO_EXT_DATA0:
+ case DP_TX_AUDIO_EXT_DATA1:
+ case DP_TX_AUDIO_EXT_DATA2:
+ case DP_TX_AUDIO_EXT_DATA3:
+ case DP_TX_AUDIO_EXT_DATA4:
+ case DP_TX_AUDIO_EXT_DATA5:
+ case DP_TX_AUDIO_EXT_DATA6:
+ case DP_TX_AUDIO_EXT_DATA7:
+ case DP_TX_AUDIO_EXT_DATA8:
+ /* write only registers */
+ ret = 0;
+ break;
+ default:
+ assert(offset <= (0x3AC >> 2));
+ ret = s->core_registers[offset];
+ break;
+ }
+
+ DPRINTF("core read @%" PRIx64 " = 0x%8.8lX\n", offset << 2, ret);
+ return ret;
+}
+
+static void xilinx_dp_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+
+ assert(size == 4);
+ assert((offset % 4) == 0);
+
+ DPRINTF("core write @%" PRIx64 " = 0x%8.8lX\n", offset, value);
+
+ offset = offset >> 2;
+
+ switch (offset) {
+ /*
+ * Only special write case are handled.
+ */
+ case DP_LINK_BW_SET:
+ s->core_registers[offset] = value & 0x000000FF;
+ break;
+ case DP_LANE_COUNT_SET:
+ case DP_MAIN_STREAM_MISC0:
+ s->core_registers[offset] = value & 0x0000000F;
+ break;
+ case DP_TRAINING_PATTERN_SET:
+ case DP_LINK_QUAL_PATTERN_SET:
+ case DP_MAIN_STREAM_POLARITY:
+ case DP_PHY_VOLTAGE_DIFF_LANE_0:
+ case DP_PHY_VOLTAGE_DIFF_LANE_1:
+ s->core_registers[offset] = value & 0x00000003;
+ break;
+ case DP_ENHANCED_FRAME_EN:
+ case DP_SCRAMBLING_DISABLE:
+ case DP_DOWNSPREAD_CTRL:
+ case DP_MAIN_STREAM_ENABLE:
+ case DP_TRANSMIT_PRBS7:
+ s->core_registers[offset] = value & 0x00000001;
+ break;
+ case DP_PHY_CLOCK_SELECT:
+ s->core_registers[offset] = value & 0x00000007;
+ case DP_SOFTWARE_RESET:
+ /*
+ * No need to update this bit as it's read '0'.
+ */
+ /*
+ * TODO: reset IP.
+ */
+ break;
+ case DP_TRANSMITTER_ENABLE:
+ s->core_registers[offset] = value & 0x01;
+ break;
+ case DP_FORCE_SCRAMBLER_RESET:
+ /*
+ * No need to update this bit as it's read '0'.
+ */
+ /*
+ * TODO: force a scrambler reset??
+ */
+ break;
+ case DP_AUX_COMMAND_REGISTER:
+ s->core_registers[offset] = value & 0x00001F0F;
+ xilinx_dp_aux_set_command(s, s->core_registers[offset]);
+ break;
+ case DP_MAIN_STREAM_HTOTAL:
+ case DP_MAIN_STREAM_VTOTAL:
+ case DP_MAIN_STREAM_HSTART:
+ case DP_MAIN_STREAM_VSTART:
+ s->core_registers[offset] = value & 0x0000FFFF;
+ break;
+ case DP_MAIN_STREAM_HRES:
+ case DP_MAIN_STREAM_VRES:
+ s->core_registers[offset] = value & 0x0000FFFF;
+ xilinx_dp_recreate_surface(s);
+ break;
+ case DP_MAIN_STREAM_HSWIDTH:
+ case DP_MAIN_STREAM_VSWIDTH:
+ s->core_registers[offset] = value & 0x00007FFF;
+ break;
+ case DP_MAIN_STREAM_MISC1:
+ s->core_registers[offset] = value & 0x00000086;
+ break;
+ case DP_MAIN_STREAM_M_VID:
+ case DP_MAIN_STREAM_N_VID:
+ s->core_registers[offset] = value & 0x00FFFFFF;
+ break;
+ case DP_MSA_TRANSFER_UNIT_SIZE:
+ case DP_MIN_BYTES_PER_TU:
+ case DP_INIT_WAIT:
+ s->core_registers[offset] = value & 0x00000007;
+ break;
+ case DP_USER_DATA_COUNT_PER_LANE:
+ s->core_registers[offset] = value & 0x0003FFFF;
+ break;
+ case DP_FRAC_BYTES_PER_TU:
+ s->core_registers[offset] = value & 0x000003FF;
+ break;
+ case DP_PHY_RESET:
+ s->core_registers[offset] = value & 0x00010003;
+ /*
+ * TODO: Reset something?
+ */
+ break;
+ case DP_TX_PHY_POWER_DOWN:
+ s->core_registers[offset] = value & 0x0000000F;
+ /*
+ * TODO: Power down things?
+ */
+ break;
+ case DP_AUX_WRITE_FIFO:
+ xilinx_dp_aux_set_data(s, value & 0x0000000F);
+ break;
+ case DP_AUX_CLOCK_DIVIDER:
+ /*
+ * XXX: Do we need to model that?
+ */
+ break;
+ case DP_AUX_REPLY_COUNT:
+ /*
+ * Writing to this register clear the counter.
+ */
+ s->core_registers[offset] = 0x00000000;
+ break;
+ case DP_AUX_ADDRESS:
+ s->core_registers[offset] = value & 0x000FFFFF;
+ break;
+ case DP_VERSION_REGISTER:
+ case DP_CORE_ID:
+ case DP_TX_USER_FIFO_OVERFLOW:
+ case DP_AUX_REPLY_DATA:
+ case DP_AUX_REPLY_CODE:
+ case DP_REPLY_DATA_COUNT:
+ case DP_REPLY_STATUS:
+ case DP_HPD_DURATION:
+ /*
+ * Write to read only location..
+ */
+ break;
+ case DP_TX_AUDIO_CONTROL:
+ s->core_registers[offset] = value & 0x00000001;
+ xilinx_dp_audio_activate(s);
+ break;
+ case DP_TX_AUDIO_CHANNELS:
+ s->core_registers[offset] = value & 0x00000007;
+ xilinx_dp_audio_activate(s);
+ break;
+ case DP_INT_STATUS:
+ s->core_registers[DP_INT_STATUS] &= ~value;
+ xilinx_dp_update_irq(s);
+ break;
+ case DP_INT_EN:
+ s->core_registers[DP_INT_MASK] &= ~value;
+ xilinx_dp_update_irq(s);
+ break;
+ case DP_INT_DS:
+ s->core_registers[DP_INT_MASK] |= ~value;
+ xilinx_dp_update_irq(s);
+ break;
+ default:
+ assert(offset <= (0x504C >> 2));
+ s->core_registers[offset] = value;
+ break;
+ }
+}
+
+static const MemoryRegionOps dp_ops = {
+ .read = xilinx_dp_read,
+ .write = xilinx_dp_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+/*
+ * This is to handle Read/Write to the Video Blender.
+ */
+static void xilinx_dp_vblend_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+ assert(size == 4);
+ assert((offset % 4) == 0);
+
+ DPRINTF("vblend: write @%" PRIx64 " = 0x%8.8lX\n", offset, value);
+
+ offset = offset >> 2;
+
+ switch (offset) {
+ case V_BLEND_BG_CLR_0:
+ case V_BLEND_BG_CLR_1:
+ case V_BLEND_BG_CLR_2:
+ s->vblend_registers[offset] = value & 0x00000FFF;
+ break;
+ case V_BLEND_SET_GLOBAL_ALPHA_REG:
+ s->vblend_registers[offset] = value & 0x000001FF;
+ break;
+ case V_BLEND_OUTPUT_VID_FORMAT:
+ /*
+ * TODO: create an enum for blended video format?
+ * We don't really care of this I guess as we will output it as RGB
+ * in the QEMU console.
+ */
+ s->vblend_registers[offset] = value & 0x00000017;
+ break;
+ case V_BLEND_LAYER0_CONTROL:
+ case V_BLEND_LAYER1_CONTROL:
+ s->vblend_registers[offset] = value & 0x00000103;
+ break;
+ case V_BLEND_RGB2YCBCR_COEFF0:
+ case V_BLEND_RGB2YCBCR_COEFF1:
+ case V_BLEND_RGB2YCBCR_COEFF2:
+ case V_BLEND_RGB2YCBCR_COEFF3:
+ case V_BLEND_RGB2YCBCR_COEFF4:
+ case V_BLEND_RGB2YCBCR_COEFF5:
+ case V_BLEND_RGB2YCBCR_COEFF6:
+ case V_BLEND_RGB2YCBCR_COEFF7:
+ case V_BLEND_RGB2YCBCR_COEFF8:
+ case V_BLEND_IN1CSC_COEFF0:
+ case V_BLEND_IN1CSC_COEFF1:
+ case V_BLEND_IN1CSC_COEFF2:
+ case V_BLEND_IN1CSC_COEFF3:
+ case V_BLEND_IN1CSC_COEFF4:
+ case V_BLEND_IN1CSC_COEFF5:
+ case V_BLEND_IN1CSC_COEFF6:
+ case V_BLEND_IN1CSC_COEFF7:
+ case V_BLEND_IN1CSC_COEFF8:
+ case V_BLEND_IN2CSC_COEFF0:
+ case V_BLEND_IN2CSC_COEFF1:
+ case V_BLEND_IN2CSC_COEFF2:
+ case V_BLEND_IN2CSC_COEFF3:
+ case V_BLEND_IN2CSC_COEFF4:
+ case V_BLEND_IN2CSC_COEFF5:
+ case V_BLEND_IN2CSC_COEFF6:
+ case V_BLEND_IN2CSC_COEFF7:
+ case V_BLEND_IN2CSC_COEFF8:
+ s->vblend_registers[offset] = value & 0x0000FFFF;
+ break;
+ case V_BLEND_LUMA_IN1CSC_OFFSET:
+ case V_BLEND_CR_IN1CSC_OFFSET:
+ case V_BLEND_CB_IN1CSC_OFFSET:
+ case V_BLEND_LUMA_IN2CSC_OFFSET:
+ case V_BLEND_CR_IN2CSC_OFFSET:
+ case V_BLEND_CB_IN2CSC_OFFSET:
+ case V_BLEND_LUMA_OUTCSC_OFFSET:
+ case V_BLEND_CR_OUTCSC_OFFSET:
+ case V_BLEND_CB_OUTCSC_OFFSET:
+ s->vblend_registers[offset] = value & 0x3FFF7FFF;
+ break;
+ case V_BLEND_CHROMA_KEY_ENABLE:
+ s->vblend_registers[offset] = value & 0x00000003;
+ break;
+ case V_BLEND_CHROMA_KEY_COMP1:
+ case V_BLEND_CHROMA_KEY_COMP2:
+ case V_BLEND_CHROMA_KEY_COMP3:
+ s->vblend_registers[offset] = value & 0x0FFF0FFF;
+ break;
+ default:
+ s->vblend_registers[offset] = value;
+ break;
+ }
+}
+
+static uint64_t xilinx_dp_vblend_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+ uint32_t ret;
+
+ assert(size == 4);
+ assert((offset % 4) == 0);
+ offset = offset >> 2;
+
+ ret = s->vblend_registers[offset];
+ DPRINTF("vblend: read @%" PRIx64 " = 0x%8.8X\n", offset << 2, ret);
+ return ret;
+}
+
+static const MemoryRegionOps vblend_ops = {
+ .read = xilinx_dp_vblend_read,
+ .write = xilinx_dp_vblend_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static inline uint8_t xilinx_dp_global_alpha_value(XilinxDPState *s)
+{
+ return (s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x1FE) >> 1;
+}
+
+static inline bool xilinx_dp_global_alpha_enabled(XilinxDPState *s)
+{
+ /*
+ * If the alpha is totally opaque (255) we don't consider the alpha is
+ * disabled to reduce CPU consumption.
+ */
+ return ((xilinx_dp_global_alpha_value(s) != 0xFF) &&
+ ((s->vblend_registers[V_BLEND_SET_GLOBAL_ALPHA_REG] & 0x01) != 0));
+}
+
+/*
+ * This is to handle Read/Write to the Audio Video buffer manager.
+ */
+static void xilinx_dp_avbufm_write(void *opaque, hwaddr offset, uint64_t value,
+ unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+ assert(size == 4);
+ assert((offset % 4) == 0);
+
+ offset = offset >> 2;
+
+ switch (offset) {
+ case AV_BUF_FORMAT:
+ s->avbufm_registers[offset] = value & 0x00000FFF;
+ xilinx_dp_change_graphic_fmt(s);
+ break;
+ case AV_CHBUF0:
+ case AV_CHBUF1:
+ case AV_CHBUF2:
+ case AV_CHBUF3:
+ case AV_CHBUF4:
+ case AV_CHBUF5:
+ /*
+ * TODO: enable the operation?
+ */
+ s->avbufm_registers[offset] = value & 0x0000007F;
+ break;
+ case AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT:
+ /*
+ * TODO:
+ * - Pattern generator for both Audio and Video.
+ * - An enumeration for the source?
+ */
+ s->avbufm_registers[offset] = value & 0x0000007F;
+ break;
+ case AV_BUF_DITHER_CONFIG:
+ s->avbufm_registers[offset] = value & 0x000007FF;
+ break;
+ case AV_BUF_DITHER_CONFIG_MAX:
+ case AV_BUF_DITHER_CONFIG_MIN:
+ s->avbufm_registers[offset] = value & 0x00000FFF;
+ break;
+ case AV_BUF_PATTERN_GEN_SELECT:
+ s->avbufm_registers[offset] = value & 0xFFFFFF03;
+ break;
+ case AV_BUF_AUD_VID_CLK_SOURCE:
+ s->avbufm_registers[offset] = value & 0x00000007;
+ break;
+ case AV_BUF_SRST_REG:
+ /*
+ * TODO: Reset the Audio Video Buffer Manager module?
+ */
+ s->avbufm_registers[offset] = value & 0x00000002;
+ break;
+ case AV_BUF_AUDIO_CH_CONFIG:
+ s->avbufm_registers[offset] = value & 0x00000003;
+ break;
+ case AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR:
+ case AV_BUF_GRAPHICS_COMP1_SCALE_FACTOR:
+ case AV_BUF_GRAPHICS_COMP2_SCALE_FACTOR:
+ case AV_BUF_VIDEO_COMP0_SCALE_FACTOR:
+ case AV_BUF_VIDEO_COMP1_SCALE_FACTOR:
+ case AV_BUF_VIDEO_COMP2_SCALE_FACTOR:
+ s->avbufm_registers[offset] = value & 0x0000FFFF;
+ break;
+
+
+ case AV_BUF_LIVE_VIDEO_COMP0_SF:
+ case AV_BUF_LIVE_VIDEO_COMP1_SF:
+ case AV_BUF_LIVE_VIDEO_COMP2_SF:
+ case AV_BUF_LIVE_VID_CONFIG:
+ case AV_BUF_LIVE_GFX_COMP0_SF:
+ case AV_BUF_LIVE_GFX_COMP1_SF:
+ case AV_BUF_LIVE_GFX_COMP2_SF:
+ case AV_BUF_LIVE_GFX_CONFIG:
+ case AV_BUF_NON_LIVE_LATENCY:
+ case AV_BUF_STC_CONTROL:
+ case AV_BUF_STC_INIT_VALUE0:
+ case AV_BUF_STC_INIT_VALUE1:
+ case AV_BUF_STC_ADJ:
+ case AV_BUF_STC_VIDEO_VSYNC_TS_REG0:
+ case AV_BUF_STC_VIDEO_VSYNC_TS_REG1:
+ case AV_BUF_STC_EXT_VSYNC_TS_REG0:
+ case AV_BUF_STC_EXT_VSYNC_TS_REG1:
+ case AV_BUF_STC_CUSTOM_EVENT_TS_REG0:
+ case AV_BUF_STC_CUSTOM_EVENT_TS_REG1:
+ case AV_BUF_STC_CUSTOM_EVENT2_TS_REG0:
+ case AV_BUF_STC_CUSTOM_EVENT2_TS_REG1:
+ case AV_BUF_STC_SNAPSHOT0:
+ case AV_BUF_STC_SNAPSHOT1:
+ case AV_BUF_HCOUNT_VCOUNT_INT0:
+ case AV_BUF_HCOUNT_VCOUNT_INT1:
+ /*
+ * Non implemented.
+ */
+ break;
+ default:
+ s->avbufm_registers[offset] = value;
+ break;
+ }
+}
+
+static uint64_t xilinx_dp_avbufm_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+ assert(size == 4);
+ assert((offset % 4) == 0);
+
+ offset = offset >> 2;
+
+ return s->avbufm_registers[offset];
+}
+
+static const MemoryRegionOps avbufm_ops = {
+ .read = xilinx_dp_avbufm_read,
+ .write = xilinx_dp_avbufm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+/*
+ * This is a global alpha blending using pixman.
+ * Both graphic and video planes are multiplied with the global alpha
+ * coefficient and added.
+ * XXX: The result is stored in the graphic surface which is then displayed.
+ * It might be better to have a destination plane which is associated to
+ * the console.
+ */
+static inline void xilinx_dp_blend_surface(XilinxDPState *s)
+{
+ pixman_fixed_t alpha1[] = { pixman_double_to_fixed(1),
+ pixman_double_to_fixed(1),
+ pixman_double_to_fixed(1.0) };
+ pixman_fixed_t alpha2[] = { pixman_double_to_fixed(1),
+ pixman_double_to_fixed(1),
+ pixman_double_to_fixed(1.0) };
+
+ if ((surface_width(s->planes[0].surface)
+ != surface_width(s->planes[1].surface)) ||
+ (surface_height(s->planes[0].surface)
+ != surface_height(s->planes[1].surface))) {
+ return;
+ }
+
+ alpha1[2] = pixman_double_to_fixed(xilinx_dp_global_alpha_value(s) / 256.0);
+ alpha2[2] = pixman_double_to_fixed((255.0 - xilinx_dp_global_alpha_value(s))
+ / 256.0);
+
+ pixman_image_set_filter(s->planes[0].surface->image,
+ PIXMAN_FILTER_CONVOLUTION, alpha1, 3);
+ pixman_image_set_filter(s->planes[1].surface->image,
+ PIXMAN_FILTER_CONVOLUTION, alpha2, 3);
+ pixman_image_composite(PIXMAN_OP_SRC, s->planes[0].surface->image, 0,
+ s->planes[0].surface->image, 0, 0, 0, 0, 0, 0,
+ surface_width(s->planes[0].surface),
+ surface_height(s->planes[0].surface));
+ pixman_image_composite(PIXMAN_OP_ADD, s->planes[1].surface->image, 0,
+ s->planes[0].surface->image, 0, 0, 0, 0, 0, 0,
+ surface_width(s->planes[0].surface),
+ surface_height(s->planes[0].surface));
+}
+
+static void xilinx_dp_update_display(void *opaque)
+{
+ XilinxDPState *s = XILINX_DP(opaque);
+
+ if (DEBUG_DP) {
+ int64_t last_time = 0;
+ int64_t frame = 0;
+ int64_t time = get_clock();
+ int64_t fps;
+
+ if (last_time == 0) {
+ last_time = get_clock();
+ }
+ frame++;
+ if (last_time + 1000000000 < time) {
+ fps = (1000000000.0 * frame) / (time - last_time);
+ last_time = time;
+ frame = 0;
+ DPRINTF("xilinx_dp: %ldfps\n", fps);
+ }
+ }
+
+
+ if ((s->core_registers[DP_TRANSMITTER_ENABLE] & 0x01) == 0) {
+ return;
+ }
+
+ s->core_registers[DP_INT_STATUS] |= (1 << 13);
+ xilinx_dp_update_irq(s);
+
+ /*
+ * Trigger the DMA channel.
+ */
+ if (!xilinx_dpdma_start_operation(s->dpdma, 3, false)) {
+ /*
+ * An error occured don't do anything with the data..
+ * Trigger an underflow interrupt.
+ */
+ s->core_registers[DP_INT_STATUS] |= (1 << 21);
+ xilinx_dp_update_irq(s);
+ return;
+ }
+
+ if (xilinx_dp_global_alpha_enabled(s)) {
+ if (!xilinx_dpdma_start_operation(s->dpdma, 0, false)) {
+ s->core_registers[DP_INT_STATUS] |= (1 << 21);
+ xilinx_dp_update_irq(s);
+ return;
+ }
+ xilinx_dp_blend_surface(s);
+ }
+
+ /*
+ * XXX: We might want to update only what changed.
+ */
+ dpy_gfx_update(s->console, 0, 0, surface_width(s->planes[0].surface),
+ surface_height(s->planes[0].surface));
+}
+
+static void xilinx_dp_invalidate_display(void *opaque)
+{
+
+}
+
+static const GraphicHwOps xilinx_dp_gfx_ops = {
+ .invalidate = xilinx_dp_invalidate_display,
+ .gfx_update = xilinx_dp_update_display,
+};
+
+static void xilinx_dp_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ XilinxDPState *s = XILINX_DP(obj);
+
+ memory_region_init(&s->container, obj, TYPE_XILINX_DP, 0xC050);
+
+ memory_region_init_io(&s->core_iomem, obj, &dp_ops, s, TYPE_XILINX_DP
+ ".core", 0x3AF);
+ memory_region_add_subregion(&s->container, 0x0000, &s->core_iomem);
+
+ memory_region_init_io(&s->vblend_iomem, obj, &vblend_ops, s, TYPE_XILINX_DP
+ ".v_blend", 0x1DF);
+ memory_region_add_subregion(&s->container, 0xA000, &s->vblend_iomem);
+
+ memory_region_init_io(&s->avbufm_iomem, obj, &avbufm_ops, s, TYPE_XILINX_DP
+ ".av_buffer_manager", 0x238);
+ memory_region_add_subregion(&s->container, 0xB000, &s->avbufm_iomem);
+ memory_region_init_io(&s->audio_iomem, obj, &audio_ops, s, TYPE_XILINX_DP
+ ".audio", sizeof(s->audio_registers));
+ memory_region_add_subregion(&s->container, 0xC000, &s->audio_iomem);
+ sysbus_init_mmio(sbd, &s->container);
+
+ sysbus_init_irq(sbd, &s->irq);
+
+ object_property_add_link(obj, "dpdma", TYPE_XILINX_DPDMA,
+ (Object **) &s->dpdma,
+ xilinx_dp_set_dpdma,
+ OBJ_PROP_LINK_UNREF_ON_RELEASE,
+ &error_abort);
+
+ s->byte_left = 0;
+
+ /*
+ * Initialize AUX Bus.
+ */
+ s->aux_bus = aux_init_bus(DEVICE(obj), "aux");
+
+ /*
+ * Initialize DPCD and EDID..
+ */
+ s->dpcd = DPCD(aux_create_slave(s->aux_bus, "dpcd", 0x00000));
+ s->edid = I2CDDC(qdev_create(BUS(aux_get_i2c_bus(s->aux_bus)), "i2c-ddc"));
+ i2c_set_slave_address(I2C_SLAVE(s->edid), 0x50);
+}
+
+static void xilinx_dp_realize(DeviceState *dev, Error **errp)
+{
+ XilinxDPState *s = XILINX_DP(dev);
+ DisplaySurface *surface;
+
+ s->console = graphic_console_init(dev, 0, &xilinx_dp_gfx_ops, s);
+ surface = qemu_console_surface(s->console);
+ xilinx_dpdma_set_host_data_location(s->dpdma, 3, surface_data(surface));
+ fifo8_create(&s->rx_fifo, 16);
+ fifo8_create(&s->tx_fifo, 16);
+
+ /* Audio */
+ struct audsettings as;
+ as.freq = 44100;
+ as.nchannels = 2;
+ as.fmt = AUD_FMT_S16;
+ as.endianness = 0;
+
+ AUD_register_card("xilinx_dp.audio", &s->aud_card);
+
+ s->amixer_output_stream = AUD_open_out(&s->aud_card,
+ s->amixer_output_stream,
+ "xilinx_dp.audio.out",
+ s,
+ xilinx_dp_audio_callback,
+ &as);
+ AUD_set_volume_out(s->amixer_output_stream, 0, 255, 255);
+ xilinx_dp_audio_activate(s);
+}
+
+static void xilinx_dp_reset(DeviceState *dev)
+{
+ XilinxDPState *s = XILINX_DP(dev);
+
+ /*
+ * Reset the Display Port registers.
+ */
+ memset(s->core_registers, 0, sizeof(s->core_registers));
+ s->core_registers[DP_VERSION_REGISTER] = 0x04010000;
+ s->core_registers[DP_CORE_ID] = 0x01020000;
+ s->core_registers[DP_REPLY_STATUS] = 0x00000010;
+ s->core_registers[DP_MSA_TRANSFER_UNIT_SIZE] = 0x00000040;
+ s->core_registers[DP_INIT_WAIT] = 0x00000020;
+ s->core_registers[DP_PHY_RESET] = 0x00010003;
+ s->core_registers[DP_INT_MASK] = 0xFFFFF03F;
+
+ /*
+ * XXX: We are ready so simply reset that to 0x43, some bit missing from the
+ * documentation.
+ */
+ s->core_registers[DP_PHY_STATUS] = 0x00000043;
+
+ /*
+ * XXX: Assume we have something connected on the AUX connector.
+ */
+ s->core_registers[DP_INTERRUPT_SIGNAL_STATE] = 0x00000001;
+
+ /*
+ * Video Blender register reset.
+ */
+ s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF0] = 0x00001000;
+ s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF4] = 0x00001000;
+ s->vblend_registers[V_BLEND_RGB2YCBCR_COEFF8] = 0x00001000;
+ s->vblend_registers[V_BLEND_IN1CSC_COEFF0] = 0x00001000;
+ s->vblend_registers[V_BLEND_IN1CSC_COEFF4] = 0x00001000;
+ s->vblend_registers[V_BLEND_IN1CSC_COEFF8] = 0x00001000;
+ s->vblend_registers[V_BLEND_IN2CSC_COEFF0] = 0x00001000;
+ s->vblend_registers[V_BLEND_IN2CSC_COEFF4] = 0x00001000;
+ s->vblend_registers[V_BLEND_IN2CSC_COEFF8] = 0x00001000;
+
+ /*
+ * Audio Video Buffer Manager register reset.
+ */
+ s->avbufm_registers[AV_BUF_NON_LIVE_LATENCY] = 0x00000180;
+ s->avbufm_registers[AV_BUF_OUTPUT_AUDIO_VIDEO_SELECT] = 0x00000008;
+ s->avbufm_registers[AV_BUF_DITHER_CONFIG_MAX] = 0x00000FFF;
+ s->avbufm_registers[AV_BUF_GRAPHICS_COMP0_SCALE_FACTOR] = 0x00010101;
+ s->avbufm_registers[AV_BUF_GRAPHICS_COMP1_SCALE_FACTOR] = 0x00010101;
+ s->avbufm_registers[AV_BUF_GRAPHICS_COMP2_SCALE_FACTOR] = 0x00010101;
+ s->avbufm_registers[AV_BUF_VIDEO_COMP0_SCALE_FACTOR] = 0x00010101;
+ s->avbufm_registers[AV_BUF_VIDEO_COMP1_SCALE_FACTOR] = 0x00010101;
+ s->avbufm_registers[AV_BUF_VIDEO_COMP2_SCALE_FACTOR] = 0x00010101;
+ s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP0_SF] = 0x00010101;
+ s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP1_SF] = 0x00010101;
+ s->avbufm_registers[AV_BUF_LIVE_VIDEO_COMP2_SF] = 0x00010101;
+ s->avbufm_registers[AV_BUF_LIVE_GFX_COMP0_SF] = 0x00010101;
+ s->avbufm_registers[AV_BUF_LIVE_GFX_COMP1_SF] = 0x00010101;
+ s->avbufm_registers[AV_BUF_LIVE_GFX_COMP2_SF] = 0x00010101;
+
+ /*
+ * Audio register reset.
+ */
+ memset(s->audio_registers, 0, sizeof(s->audio_registers));
+
+ xilinx_dp_aux_clear_rx_fifo(s);
+ xilinx_dp_change_graphic_fmt(s);
+}
+
+static void xilinx_dp_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = xilinx_dp_realize;
+ dc->vmsd = &vmstate_dp;
+ dc->reset = xilinx_dp_reset;
+}
+
+static const TypeInfo xilinx_dp_info = {
+ .name = TYPE_XILINX_DP,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(XilinxDPState),
+ .instance_init = xilinx_dp_init,
+ .class_init = xilinx_dp_class_init,
+};
+
+static void xilinx_dp_register_types(void)
+{
+ type_register_static(&xilinx_dp_info);
+}
+
+type_init(xilinx_dp_register_types)
diff --git a/hw/display/xilinx_dp.h b/hw/display/xilinx_dp.h
new file mode 100644
index 0000000..62e16ec
--- /dev/null
+++ b/hw/display/xilinx_dp.h
@@ -0,0 +1,125 @@
+/*
+ * xilinx_dp.h
+ *
+ * Copyright (C) 2015 : GreenSocs Ltd
+ * http://www.greensocs.com/ , email: info@greensocs.com
+ *
+ * Developed by :
+ * Frederic Konrad <fred.konrad@greensocs.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include "hw/sysbus.h"
+#include "ui/console.h"
+#include "hw/aux.h"
+#include "hw/i2c/i2c.h"
+#include "hw/display/dpcd.h"
+#include "hw/i2c/i2c-ddc.h"
+#include "qemu/fifo8.h"
+#include "hw/dma/xilinx_dpdma.h"
+#include "audio/audio.h"
+
+#ifndef XILINX_DP_H
+#define XILINX_DP_H
+
+#define AUD_CHBUF_MAX_DEPTH 32768
+#define MAX_QEMU_BUFFER_SIZE 4096
+
+struct PixmanPlane {
+ pixman_format_code_t format;
+ DisplaySurface *surface;
+};
+
+struct XilinxDPState {
+ SysBusDevice parent_obj;
+ MemoryRegion container;
+
+ /*
+ * Registers for the Core.
+ */
+ uint32_t core_registers[0x3AF >> 2];
+ MemoryRegion core_iomem;
+
+ /*
+ * Registers for Audio Video Buffer Manager.
+ */
+ uint32_t avbufm_registers[0x238 >> 2];
+ MemoryRegion avbufm_iomem;
+
+ /*
+ * Register for Video Blender.
+ */
+ uint32_t vblend_registers[0x1DF >> 2];
+ MemoryRegion vblend_iomem;
+
+ /*
+ * Registers for Audio.
+ */
+ uint32_t audio_registers[0x50 >> 2];
+ MemoryRegion audio_iomem;
+
+ QemuConsole *console;
+ /*
+ * 0: Graphic plane, 1: Video plane.
+ */
+ struct PixmanPlane planes[2];
+
+ /*
+ * Audio related.
+ */
+ QEMUSoundCard aud_card;
+ SWVoiceOut *amixer_output_stream;
+ int16_t audio_buffer_0[AUD_CHBUF_MAX_DEPTH];
+ int16_t audio_buffer_1[AUD_CHBUF_MAX_DEPTH];
+ size_t audio_data_available[2];
+ int64_t temp_buffer[AUD_CHBUF_MAX_DEPTH];
+ int16_t out_buffer[AUD_CHBUF_MAX_DEPTH];
+ size_t byte_left; /* byte available in out_buffer. */
+ size_t data_ptr; /* next byte to be sent to QEMU. */
+
+ /*
+ * Associated DPDMA controller.
+ */
+ XilinxDPDMAState *dpdma;
+
+ /*
+ * IRQ.
+ */
+ qemu_irq irq;
+
+ /*
+ * AUX bus.
+ */
+ AUXBus *aux_bus;
+
+ Fifo8 rx_fifo;
+ Fifo8 tx_fifo;
+
+ uint32_t last_request;
+
+ /*
+ * XXX: This should be in an other module.
+ */
+ DPCDState *dpcd;
+ I2CDDCState *edid;
+};
+
+typedef struct XilinxDPState XilinxDPState;
+
+#define TYPE_XILINX_DP "xlnx.v-dp"
+#define XILINX_DP(obj) OBJECT_CHECK(XilinxDPState, (obj), TYPE_XILINX_DP)
+
+#endif /* !XILINX_DP_H */
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [Qemu-devel] [PATCH 8/8] arm: xlnx-zynqmp: Add DisplayPort and DPDMA.
2015-05-13 19:11 [Qemu-devel] [PATCH 0/8] Xilinx DisplayPort fred.konrad
` (6 preceding siblings ...)
2015-05-13 19:12 ` [Qemu-devel] [PATCH 7/8] Introduce xilinx dp fred.konrad
@ 2015-05-13 19:12 ` fred.konrad
2015-05-14 3:30 ` Peter Crosthwaite
7 siblings, 1 reply; 20+ messages in thread
From: fred.konrad @ 2015-05-13 19:12 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.crosthwaite, mark.burton, hyunk, fred.konrad
From: KONRAD Frederic <fred.konrad@greensocs.com>
This adds the DP and the DPDMA to the Zynq MP.
Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
---
hw/arm/xlnx-zynqmp.c | 23 +++++++++++++++++++++++
include/hw/arm/xlnx-zynqmp.h | 4 ++++
2 files changed, 27 insertions(+)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index dff6c8a..0eb82fa 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -27,6 +27,10 @@
#define GIC_BASE_ADDR 0xf9000000
#define GIC_DIST_ADDR 0xf9010000
#define GIC_CPU_ADDR 0xf9020000
+#define DP_ADDR 0xfd4a0000
+#define DP_IRQ 113
+#define DPDMA_ADDR 0xfd4c0000
+#define DPDMA_IRQ 116
static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
@@ -83,6 +87,16 @@ static void xlnx_zynqmp_init(Object *obj)
object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
}
+
+ object_initialize(&s->dp, sizeof(s->dp), TYPE_XILINX_DP);
+ object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
+ TYPE_XILINX_DP, OBJECT(&s->dp), &error_abort);
+ qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
+ object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XILINX_DPDMA);
+ object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
+ TYPE_XILINX_DPDMA, OBJECT(&s->dpdma),
+ &error_abort);
+ qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
}
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@@ -186,6 +200,15 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
gic_spi[uart_intr[i]]);
}
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
+ object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
+ &error_abort);
+ object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
+ object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
}
static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 79c2b0b..66ec010 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -22,6 +22,8 @@
#include "hw/intc/arm_gic.h"
#include "hw/net/cadence_gem.h"
#include "hw/char/cadence_uart.h"
+#include "hw/dma/xilinx_dpdma.h"
+#include "hw/display/xilinx_dp.h"
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
@@ -52,6 +54,8 @@ typedef struct XlnxZynqMPState {
MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
+ XilinxDPState dp;
+ XilinxDPDMAState dpdma;
} XlnxZynqMPState;
#define XLNX_ZYNQMP_H
--
1.9.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 8/8] arm: xlnx-zynqmp: Add DisplayPort and DPDMA.
2015-05-13 19:12 ` [Qemu-devel] [PATCH 8/8] arm: xlnx-zynqmp: Add DisplayPort and DPDMA fred.konrad
@ 2015-05-14 3:30 ` Peter Crosthwaite
2015-05-18 6:58 ` Frederic Konrad
0 siblings, 1 reply; 20+ messages in thread
From: Peter Crosthwaite @ 2015-05-14 3:30 UTC (permalink / raw)
To: Fréderic Konrad; +Cc: Mark Burton, qemu-devel@nongnu.org Developers, hyunk
On Wed, May 13, 2015 at 12:12 PM, <fred.konrad@greensocs.com> wrote:
> From: KONRAD Frederic <fred.konrad@greensocs.com>
>
> This adds the DP and the DPDMA to the Zynq MP.
>
> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
> ---
> hw/arm/xlnx-zynqmp.c | 23 +++++++++++++++++++++++
> include/hw/arm/xlnx-zynqmp.h | 4 ++++
> 2 files changed, 27 insertions(+)
>
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index dff6c8a..0eb82fa 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -27,6 +27,10 @@
> #define GIC_BASE_ADDR 0xf9000000
> #define GIC_DIST_ADDR 0xf9010000
> #define GIC_CPU_ADDR 0xf9020000
Blank line.
> +#define DP_ADDR 0xfd4a0000
> +#define DP_IRQ 113
Blank line
> +#define DPDMA_ADDR 0xfd4c0000
> +#define DPDMA_IRQ 116
>
> static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
> 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
> @@ -83,6 +87,16 @@ static void xlnx_zynqmp_init(Object *obj)
> object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
> qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
> }
> +
> + object_initialize(&s->dp, sizeof(s->dp), TYPE_XILINX_DP);
> + object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
> + TYPE_XILINX_DP, OBJECT(&s->dp), &error_abort);
> + qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
> + object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XILINX_DPDMA);
> + object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
> + TYPE_XILINX_DPDMA, OBJECT(&s->dpdma),
> + &error_abort);
> + qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
> }
>
> static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> @@ -186,6 +200,15 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
> gic_spi[uart_intr[i]]);
> }
> +
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
> + object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
> + &error_abort);
Does moving the set_link after the realizes remove the need for the
dummy object_property_add_child?
Regards,
Peter
> + object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
> + object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
> }
>
> static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index 79c2b0b..66ec010 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -22,6 +22,8 @@
> #include "hw/intc/arm_gic.h"
> #include "hw/net/cadence_gem.h"
> #include "hw/char/cadence_uart.h"
> +#include "hw/dma/xilinx_dpdma.h"
> +#include "hw/display/xilinx_dp.h"
>
> #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
> #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
> @@ -52,6 +54,8 @@ typedef struct XlnxZynqMPState {
> MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
> CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
> CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
> + XilinxDPState dp;
> + XilinxDPDMAState dpdma;
> } XlnxZynqMPState;
>
> #define XLNX_ZYNQMP_H
> --
> 1.9.0
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [Qemu-devel] [PATCH 8/8] arm: xlnx-zynqmp: Add DisplayPort and DPDMA.
2015-05-14 3:30 ` Peter Crosthwaite
@ 2015-05-18 6:58 ` Frederic Konrad
0 siblings, 0 replies; 20+ messages in thread
From: Frederic Konrad @ 2015-05-18 6:58 UTC (permalink / raw)
To: Peter Crosthwaite; +Cc: Mark Burton, qemu-devel@nongnu.org Developers, hyunk
Hi Peter,
Thanks for your review.
On 14/05/2015 05:30, Peter Crosthwaite wrote:
> On Wed, May 13, 2015 at 12:12 PM, <fred.konrad@greensocs.com> wrote:
>> From: KONRAD Frederic <fred.konrad@greensocs.com>
>>
>> This adds the DP and the DPDMA to the Zynq MP.
>>
>> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com>
>> ---
>> hw/arm/xlnx-zynqmp.c | 23 +++++++++++++++++++++++
>> include/hw/arm/xlnx-zynqmp.h | 4 ++++
>> 2 files changed, 27 insertions(+)
>>
>> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
>> index dff6c8a..0eb82fa 100644
>> --- a/hw/arm/xlnx-zynqmp.c
>> +++ b/hw/arm/xlnx-zynqmp.c
>> @@ -27,6 +27,10 @@
>> #define GIC_BASE_ADDR 0xf9000000
>> #define GIC_DIST_ADDR 0xf9010000
>> #define GIC_CPU_ADDR 0xf9020000
> Blank line.
>
>> +#define DP_ADDR 0xfd4a0000
>> +#define DP_IRQ 113
> Blank line
>
Done, BTW do you agree with the IRQ number?
>> +#define DPDMA_ADDR 0xfd4c0000
>> +#define DPDMA_IRQ 116
>>
>> static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] = {
>> 0xFF0B0000, 0xFF0C0000, 0xFF0D0000, 0xFF0E0000,
>> @@ -83,6 +87,16 @@ static void xlnx_zynqmp_init(Object *obj)
>> object_initialize(&s->uart[i], sizeof(s->uart[i]), TYPE_CADENCE_UART);
>> qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
>> }
>> +
>> + object_initialize(&s->dp, sizeof(s->dp), TYPE_XILINX_DP);
>> + object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
>> + TYPE_XILINX_DP, OBJECT(&s->dp), &error_abort);
>> + qdev_set_parent_bus(DEVICE(&s->dp), sysbus_get_default());
>> + object_initialize(&s->dpdma, sizeof(s->dpdma), TYPE_XILINX_DPDMA);
>> + object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
>> + TYPE_XILINX_DPDMA, OBJECT(&s->dpdma),
>> + &error_abort);
>> + qdev_set_parent_bus(DEVICE(&s->dpdma), sysbus_get_default());
>> }
>>
>> static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>> @@ -186,6 +200,15 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
>> sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
>> gic_spi[uart_intr[i]]);
>> }
>> +
>> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dp), 0, DP_ADDR);
>> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dp), 0, gic_spi[DP_IRQ]);
>> + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dpdma), 0, DPDMA_ADDR);
>> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dpdma), 0, gic_spi[DPDMA_IRQ]);
>> + object_property_set_link(OBJECT(&s->dp), OBJECT(&s->dpdma), "dpdma",
>> + &error_abort);
> Does moving the set_link after the realizes remove the need for the
> dummy object_property_add_child?
>
> Regards,
> Peter
Ahh good point, I didn't see that object_property_add_child was done in
the realize
step. So yes, you're right. I fixed that.
Thanks,
Fred
>
>> + object_property_set_bool(OBJECT(&s->dp), true, "realized", &err);
>> + object_property_set_bool(OBJECT(&s->dpdma), true, "realized", &err);
>> }
>>
>> static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data)
>> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
>> index 79c2b0b..66ec010 100644
>> --- a/include/hw/arm/xlnx-zynqmp.h
>> +++ b/include/hw/arm/xlnx-zynqmp.h
>> @@ -22,6 +22,8 @@
>> #include "hw/intc/arm_gic.h"
>> #include "hw/net/cadence_gem.h"
>> #include "hw/char/cadence_uart.h"
>> +#include "hw/dma/xilinx_dpdma.h"
>> +#include "hw/display/xilinx_dp.h"
>>
>> #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
>> #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
>> @@ -52,6 +54,8 @@ typedef struct XlnxZynqMPState {
>> MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
>> CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
>> CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
>> + XilinxDPState dp;
>> + XilinxDPDMAState dpdma;
>> } XlnxZynqMPState;
>>
>> #define XLNX_ZYNQMP_H
>> --
>> 1.9.0
>>
>>
^ permalink raw reply [flat|nested] 20+ messages in thread