* [PATCH 1/3] x86: support additional Broadwell model
2015-05-18 12:49 [PATCH 0/3] x86: mwait-idle sync with recent Linux Jan Beulich
@ 2015-05-18 12:54 ` Jan Beulich
2015-05-18 12:58 ` Jan Beulich
2015-05-18 12:55 ` [PATCH 2/3] mwait-idle: update support for Silvermont Core in Baytrail SOC Jan Beulich
2015-05-18 12:55 ` [PATCH 3/3] mwait-idle: add support for the Airmont Core in the Cherrytrail and Braswell SOCs Jan Beulich
2 siblings, 1 reply; 5+ messages in thread
From: Jan Beulich @ 2015-05-18 12:54 UTC (permalink / raw)
To: xen-devel; +Cc: Andrew Cooper, Keir Fraser
[-- Attachment #1: Type: text/plain, Size: 412 bytes --]
Signed-off-by: Len Brown <len.brown@intel.com>
[Linux commit bea57077e44ec9c1e6d3a3c142c8a3c0289e290d]
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -683,6 +683,7 @@ static struct intel_idle_id {
ICPU(0x46, hsw),
ICPU(0x4d, avn),
ICPU(0x3d, bdw),
+ ICPU(0x47, bdw),
ICPU(0x4f, bdw),
ICPU(0x56, bdw),
{}
[-- Attachment #2: mwait-idle-Broadwell-47.patch --]
[-- Type: text/plain, Size: 456 bytes --]
mwait-idle: support additional Broadwell model
Signed-off-by: Len Brown <len.brown@intel.com>
[Linux commit bea57077e44ec9c1e6d3a3c142c8a3c0289e290d]
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -683,6 +683,7 @@ static struct intel_idle_id {
ICPU(0x46, hsw),
ICPU(0x4d, avn),
ICPU(0x3d, bdw),
+ ICPU(0x47, bdw),
ICPU(0x4f, bdw),
ICPU(0x56, bdw),
{}
[-- Attachment #3: Type: text/plain, Size: 126 bytes --]
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Xen-devel@lists.xen.org
http://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 2/3] mwait-idle: update support for Silvermont Core in Baytrail SOC
2015-05-18 12:49 [PATCH 0/3] x86: mwait-idle sync with recent Linux Jan Beulich
2015-05-18 12:54 ` [PATCH 1/3] x86: support additional Broadwell model Jan Beulich
@ 2015-05-18 12:55 ` Jan Beulich
2015-05-18 12:55 ` [PATCH 3/3] mwait-idle: add support for the Airmont Core in the Cherrytrail and Braswell SOCs Jan Beulich
2 siblings, 0 replies; 5+ messages in thread
From: Jan Beulich @ 2015-05-18 12:55 UTC (permalink / raw)
To: xen-devel; +Cc: Andrew Cooper, Keir Fraser
[-- Attachment #1: Type: text/plain, Size: 1567 bytes --]
On some Silvermont-Core/Baytrail-SOC systems,
C1E latency is higher than original specifications.
Although C1E is still enumerated in CPUID.MWAIT.EDX,
we delete the state from intel_idle to avoid latency impact.
Under some conditions, the latency of the C6N-BYT and C6S-BYT states
may exceed the specified values of 40 and 140 usec, respectively.
Increase those values to 300 and 500 usec; to assure
that the hardware does not violate constraints that may be set
by the Linux PM_QOS sub-system.
Also increase the C7-BYT target residency to 4.0 ms from 1.5 ms.
Signed-off-by: Len Brown <len.brown@intel.com>
[Linux commit d7ef76717322c8e2df7d4360b33faa9466cb1a0d]
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -196,28 +196,22 @@ static const struct cpuidle_state byt_cs
.target_residency = 1,
},
{
- .name = "C1E-BYT",
- .flags = MWAIT2flg(0x01),
- .exit_latency = 15,
- .target_residency = 30,
- },
- {
.name = "C6N-BYT",
.flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
- .exit_latency = 40,
+ .exit_latency = 300,
.target_residency = 275,
},
{
.name = "C6S-BYT",
.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
- .exit_latency = 140,
+ .exit_latency = 500,
.target_residency = 560,
},
{
.name = "C7-BYT",
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 1200,
- .target_residency = 1500,
+ .target_residency = 4000,
},
{
.name = "C7S-BYT",
[-- Attachment #2: mwait-idle-Baytrail-no-C1E.patch --]
[-- Type: text/plain, Size: 1627 bytes --]
mwait-idle: update support for Silvermont Core in Baytrail SOC
On some Silvermont-Core/Baytrail-SOC systems,
C1E latency is higher than original specifications.
Although C1E is still enumerated in CPUID.MWAIT.EDX,
we delete the state from intel_idle to avoid latency impact.
Under some conditions, the latency of the C6N-BYT and C6S-BYT states
may exceed the specified values of 40 and 140 usec, respectively.
Increase those values to 300 and 500 usec; to assure
that the hardware does not violate constraints that may be set
by the Linux PM_QOS sub-system.
Also increase the C7-BYT target residency to 4.0 ms from 1.5 ms.
Signed-off-by: Len Brown <len.brown@intel.com>
[Linux commit d7ef76717322c8e2df7d4360b33faa9466cb1a0d]
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -196,28 +196,22 @@ static const struct cpuidle_state byt_cs
.target_residency = 1,
},
{
- .name = "C1E-BYT",
- .flags = MWAIT2flg(0x01),
- .exit_latency = 15,
- .target_residency = 30,
- },
- {
.name = "C6N-BYT",
.flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
- .exit_latency = 40,
+ .exit_latency = 300,
.target_residency = 275,
},
{
.name = "C6S-BYT",
.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
- .exit_latency = 140,
+ .exit_latency = 500,
.target_residency = 560,
},
{
.name = "C7-BYT",
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
.exit_latency = 1200,
- .target_residency = 1500,
+ .target_residency = 4000,
},
{
.name = "C7S-BYT",
[-- Attachment #3: Type: text/plain, Size: 126 bytes --]
_______________________________________________
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Xen-devel@lists.xen.org
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^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 3/3] mwait-idle: add support for the Airmont Core in the Cherrytrail and Braswell SOCs
2015-05-18 12:49 [PATCH 0/3] x86: mwait-idle sync with recent Linux Jan Beulich
2015-05-18 12:54 ` [PATCH 1/3] x86: support additional Broadwell model Jan Beulich
2015-05-18 12:55 ` [PATCH 2/3] mwait-idle: update support for Silvermont Core in Baytrail SOC Jan Beulich
@ 2015-05-18 12:55 ` Jan Beulich
2 siblings, 0 replies; 5+ messages in thread
From: Jan Beulich @ 2015-05-18 12:55 UTC (permalink / raw)
To: xen-devel; +Cc: Andrew Cooper, Keir Fraser
[-- Attachment #1: Type: text/plain, Size: 1920 bytes --]
Support C-states for the Airmont core in the Cherrytrail and Braswell SOCs.
The states are similar to those of Silvermont in Baytrail,
except both flavors of C6 states are faster.
Signed-off-by: Len Brown <len.brown@intel.com>
[Linux commit cab07a5652d1d124b505c2b7ed21c6823295c5d7]
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -222,6 +222,40 @@ static const struct cpuidle_state byt_cs
{}
};
+static const struct cpuidle_state cht_cstates[] = {
+ {
+ .name = "C1-CHT",
+ .flags = MWAIT2flg(0x00),
+ .exit_latency = 1,
+ .target_residency = 1,
+ },
+ {
+ .name = "C6N-CHT",
+ .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 80,
+ .target_residency = 275,
+ },
+ {
+ .name = "C6S-CHT",
+ .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 200,
+ .target_residency = 560,
+ },
+ {
+ .name = "C7-CHT",
+ .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 1200,
+ .target_residency = 4000,
+ },
+ {
+ .name = "C7S-CHT",
+ .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 10000,
+ .target_residency = 20000,
+ },
+ {}
+};
+
static const struct cpuidle_state ivb_cstates[] = {
{
.name = "C1-IVB",
@@ -625,6 +659,12 @@ static const struct idle_cpu idle_cpu_by
.byt_auto_demotion_disable_flag = 1,
};
+static const struct idle_cpu idle_cpu_cht = {
+ .state_table = cht_cstates,
+ .disable_promotion_to_c1e = 1,
+ .byt_auto_demotion_disable_flag = 1,
+};
+
static const struct idle_cpu idle_cpu_ivb = {
.state_table = ivb_cstates,
.disable_promotion_to_c1e = 1,
@@ -669,6 +709,7 @@ static struct intel_idle_id {
ICPU(0x2d, snb),
ICPU(0x36, atom),
ICPU(0x37, byt),
+ ICPU(0x4c, cht),
ICPU(0x3a, ivb),
ICPU(0x3e, ivt),
ICPU(0x3c, hsw),
[-- Attachment #2: mwait-idle-Cherrytrail.patch --]
[-- Type: text/plain, Size: 1999 bytes --]
mwait-idle: add support for the Airmont Core in the Cherrytrail and Braswell SOCs
Support C-states for the Airmont core in the Cherrytrail and Braswell SOCs.
The states are similar to those of Silvermont in Baytrail,
except both flavors of C6 states are faster.
Signed-off-by: Len Brown <len.brown@intel.com>
[Linux commit cab07a5652d1d124b505c2b7ed21c6823295c5d7]
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -222,6 +222,40 @@ static const struct cpuidle_state byt_cs
{}
};
+static const struct cpuidle_state cht_cstates[] = {
+ {
+ .name = "C1-CHT",
+ .flags = MWAIT2flg(0x00),
+ .exit_latency = 1,
+ .target_residency = 1,
+ },
+ {
+ .name = "C6N-CHT",
+ .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 80,
+ .target_residency = 275,
+ },
+ {
+ .name = "C6S-CHT",
+ .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 200,
+ .target_residency = 560,
+ },
+ {
+ .name = "C7-CHT",
+ .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 1200,
+ .target_residency = 4000,
+ },
+ {
+ .name = "C7S-CHT",
+ .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
+ .exit_latency = 10000,
+ .target_residency = 20000,
+ },
+ {}
+};
+
static const struct cpuidle_state ivb_cstates[] = {
{
.name = "C1-IVB",
@@ -625,6 +659,12 @@ static const struct idle_cpu idle_cpu_by
.byt_auto_demotion_disable_flag = 1,
};
+static const struct idle_cpu idle_cpu_cht = {
+ .state_table = cht_cstates,
+ .disable_promotion_to_c1e = 1,
+ .byt_auto_demotion_disable_flag = 1,
+};
+
static const struct idle_cpu idle_cpu_ivb = {
.state_table = ivb_cstates,
.disable_promotion_to_c1e = 1,
@@ -669,6 +709,7 @@ static struct intel_idle_id {
ICPU(0x2d, snb),
ICPU(0x36, atom),
ICPU(0x37, byt),
+ ICPU(0x4c, cht),
ICPU(0x3a, ivb),
ICPU(0x3e, ivt),
ICPU(0x3c, hsw),
[-- Attachment #3: Type: text/plain, Size: 126 bytes --]
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http://lists.xen.org/xen-devel
^ permalink raw reply [flat|nested] 5+ messages in thread