* [Qemu-devel] [PATCH v4 0/3] target-mips: Add support for misaligned accesses
@ 2015-05-20 15:12 Yongbok Kim
2015-05-20 15:12 ` [Qemu-devel] [PATCH v4 1/3] target-mips: Misaligned memory accesses for R6 Yongbok Kim
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Yongbok Kim @ 2015-05-20 15:12 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, leon.alrae, afaerber, rth
This patch set adds support for misaligned memory accesses in MIPS architecture
Release 6 and MIPS SIMD Architecture.
The behaviour, semantics, and architecture specifications of misaligned memory
accesses are described in:
MIPS Architecture For Programmers Volume I-A: Introduction to the MIPS64
Architecture, Appendix B Misaligned Memory Accesses.
Available at http://www.imgtec.com/mips/architectures/mips64.asp
Regards,
Yongbok
v4:
* Removed the work-around per the recent TCG change for misaligned accesses
* Added probe_write() (Richard)
* Used helper_ret_*_mmu directly (Richard)
* Removed TLB checking for MSA LD (Richard)
* Removed unnecessary save_cpu_state() calls
v3:
* Rewrote MSA patch
* Work-around is using byte-to-byte accesses and endianness corrections for
R5+MSA. (This replaces the misaligned flag from v2.) (Leon)
* Bug fixes (Leon)
* Separate helper functions for each data formats
v2:
* Removed re-translation in the mips_cpu_do_unaligned_access() (Peter)
* Checks validity only if an access is spanning into two pages in MSA (Leon)
* Introduced misaligned flag to indicate MSA ld/st is ongoing, is used to
allow misaligned accesses in the mips_cpu_do_unaligned_access() callback.
This is crucial to support MSA misaligned accesses in Release 5 cores.
Yongbok Kim (3):
target-mips: Misaligned memory accesses for R6
softmmu: Add probe_write()
target-mips: Misaligned memory accesses for MSA
include/exec/exec-all.h | 2 +
softmmu_template.h | 21 ++++++
target-mips/helper.h | 10 +++-
target-mips/op_helper.c | 144 +++++++++++++++++++++++------------------
target-mips/translate.c | 21 ++++--
target-mips/translate_init.c | 2 +-
6 files changed, 127 insertions(+), 73 deletions(-)
--
1.7.5.4
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v4 1/3] target-mips: Misaligned memory accesses for R6
2015-05-20 15:12 [Qemu-devel] [PATCH v4 0/3] target-mips: Add support for misaligned accesses Yongbok Kim
@ 2015-05-20 15:12 ` Yongbok Kim
2015-05-20 17:09 ` Richard Henderson
2015-05-20 15:12 ` [Qemu-devel] [PATCH v4 2/3] softmmu: Add probe_write() Yongbok Kim
2015-05-20 15:12 ` [Qemu-devel] [PATCH v4 3/3] target-mips: Misaligned memory accesses for MSA Yongbok Kim
2 siblings, 1 reply; 11+ messages in thread
From: Yongbok Kim @ 2015-05-20 15:12 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, leon.alrae, afaerber, rth
Release 6 requires misaligned memory access support for all ordinary memory
access instructions (for example, LW/SW, LWC1/SWC1).
However misaligned support is not provided for certain special memory accesses
such as atomics (for example, LL/SC).
Allows misaligned accesses from mips_cpu_do_unaligned_access() callback,
if it is a R6 core. As the helper functions of LL/SC is checking misalignment,
just allowing all for R6 is good enough.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
---
target-mips/op_helper.c | 7 +++++++
target-mips/translate_init.c | 2 +-
2 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 73a8e45..58f02cf 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -2215,6 +2215,13 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
int error_code = 0;
int excp;
+ if (env->insn_flags & ISA_MIPS32R6) {
+ /* Release 6 provides support for misaligned memory access for
+ * all ordinary memory reference instructions
+ * */
+ return;
+ }
+
env->CP0_BadVAddr = addr;
if (access_type == MMU_DATA_STORE) {
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 85a65e7..ec54fef 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -607,7 +607,7 @@ static const mips_def_t mips_defs[] =
},
{
/* A generic CPU supporting MIPS64 Release 6 ISA.
- FIXME: Support IEEE 754-2008 FP and misaligned memory accesses.
+ FIXME: Support IEEE 754-2008 FP.
Eventually this should be replaced by a real CPU model. */
.name = "MIPS64R6-generic",
.CP0_PRid = 0x00010000,
--
1.7.5.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v4 2/3] softmmu: Add probe_write()
2015-05-20 15:12 [Qemu-devel] [PATCH v4 0/3] target-mips: Add support for misaligned accesses Yongbok Kim
2015-05-20 15:12 ` [Qemu-devel] [PATCH v4 1/3] target-mips: Misaligned memory accesses for R6 Yongbok Kim
@ 2015-05-20 15:12 ` Yongbok Kim
2015-05-20 17:10 ` Richard Henderson
2015-05-20 15:12 ` [Qemu-devel] [PATCH v4 3/3] target-mips: Misaligned memory accesses for MSA Yongbok Kim
2 siblings, 1 reply; 11+ messages in thread
From: Yongbok Kim @ 2015-05-20 15:12 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, leon.alrae, afaerber, rth
Add probe_write() forces a tlb_fill if the specified guest virtual
index isn't in the TCG softmmu TLB.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
---
include/exec/exec-all.h | 2 ++
softmmu_template.h | 21 +++++++++++++++++++++
2 files changed, 23 insertions(+), 0 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index b58cd47..af51203 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -109,6 +109,8 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, MemTxAttrs attrs,
int prot, int mmu_idx, target_ulong size);
void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
+void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
+ uintptr_t retaddr);
#else
static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
{
diff --git a/softmmu_template.h b/softmmu_template.h
index 39f571b..c175d17 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -548,6 +548,27 @@ glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
helper_te_st_name(env, addr, val, oi, GETRA());
}
+#if DATA_SIZE == 1
+/*
+ * Force a tlb_fill if the specified guest virtual index isn't in the TCG
+ * softmmu TLB.
+ */
+void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
+ uintptr_t retaddr)
+{
+ int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
+ target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
+
+ if ((addr & TARGET_PAGE_MASK)
+ != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
+ /* TLB entry is for a different page */
+ if (!VICTIM_TLB_HIT(addr_write)) {
+ tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
+ }
+ }
+ return;
+}
+#endif
#endif /* !defined(SOFTMMU_CODE_ACCESS) */
#undef READ_ACCESS_TYPE
--
1.7.5.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Qemu-devel] [PATCH v4 3/3] target-mips: Misaligned memory accesses for MSA
2015-05-20 15:12 [Qemu-devel] [PATCH v4 0/3] target-mips: Add support for misaligned accesses Yongbok Kim
2015-05-20 15:12 ` [Qemu-devel] [PATCH v4 1/3] target-mips: Misaligned memory accesses for R6 Yongbok Kim
2015-05-20 15:12 ` [Qemu-devel] [PATCH v4 2/3] softmmu: Add probe_write() Yongbok Kim
@ 2015-05-20 15:12 ` Yongbok Kim
2015-05-20 17:25 ` Richard Henderson
2 siblings, 1 reply; 11+ messages in thread
From: Yongbok Kim @ 2015-05-20 15:12 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, leon.alrae, afaerber, rth
MIPS SIMD Architecture vector loads and stores require misalignment support.
MSA Memory access should work as an atomic operation. Therefore, it has to
check validity of all addresses for a vector store access if it is spanning
into two pages.
Separating helper functions for each data format as format is known in
translation.
To use mmu_idx from cpu_mmu_index() instead of calculating it from hflag.
Removing save_cpu_state() call in translation because it is able to use
cpu_restore_state() on fault as GETRA() is passed.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
---
target-mips/helper.h | 10 +++-
target-mips/op_helper.c | 137 +++++++++++++++++++++++++---------------------
target-mips/translate.c | 21 +++++---
3 files changed, 96 insertions(+), 72 deletions(-)
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 3bd0b02..c532276 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -931,5 +931,11 @@ DEF_HELPER_4(msa_ftint_u_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ffint_s_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ffint_u_df, void, env, i32, i32, i32)
-DEF_HELPER_5(msa_ld_df, void, env, i32, i32, i32, s32)
-DEF_HELPER_5(msa_st_df, void, env, i32, i32, i32, s32)
+#define MSALDST_PROTO(type) \
+DEF_HELPER_4(msa_ld_ ## type, void, env, i32, i32, s32) \
+DEF_HELPER_4(msa_st_ ## type, void, env, i32, i32, s32)
+MSALDST_PROTO(b)
+MSALDST_PROTO(h)
+MSALDST_PROTO(w)
+MSALDST_PROTO(d)
+#undef MSALDST_PROTO
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 58f02cf..37667c1 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -3565,72 +3565,83 @@ FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
/* Element-by-element access macros */
#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
-void helper_msa_ld_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t rs,
- int32_t s10)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- target_ulong addr = env->active_tc.gpr[rs] + (s10 << df);
- int i;
-
- switch (df) {
- case DF_BYTE:
- for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
- pwd->b[i] = do_lbu(env, addr + (i << DF_BYTE),
- env->hflags & MIPS_HFLAG_KSU);
- }
- break;
- case DF_HALF:
- for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
- pwd->h[i] = do_lhu(env, addr + (i << DF_HALF),
- env->hflags & MIPS_HFLAG_KSU);
- }
- break;
- case DF_WORD:
- for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
- pwd->w[i] = do_lw(env, addr + (i << DF_WORD),
- env->hflags & MIPS_HFLAG_KSU);
- }
- break;
- case DF_DOUBLE:
- for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
- pwd->d[i] = do_ld(env, addr + (i << DF_DOUBLE),
- env->hflags & MIPS_HFLAG_KSU);
- }
- break;
- }
+#define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
+void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, uint32_t rs,\
+ int32_t s10) \
+{ \
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
+ wr_t wx; \
+ target_ulong addr = env->active_tc.gpr[rs] + (s10 << DF); \
+ int i; \
+ for (i = 0; i < DF_ELEMENTS(DF); i++) { \
+ wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
+ } \
+ memcpy(pwd, &wx, sizeof(wr_t)); \
}
-void helper_msa_st_df(CPUMIPSState *env, uint32_t df, uint32_t wd, uint32_t rs,
- int32_t s10)
+#if !defined(CONFIG_USER_ONLY)
+MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, \
+ make_memop_idx(MO_UNALN, cpu_mmu_index(env)), GETRA())
+MSA_LD_DF(DF_HALF, h, helper_ret_lduw_mmu, \
+ make_memop_idx(MO_UNALN, cpu_mmu_index(env)), GETRA())
+MSA_LD_DF(DF_WORD, w, helper_ret_ldul_mmu, \
+ make_memop_idx(MO_UNALN, cpu_mmu_index(env)), GETRA())
+MSA_LD_DF(DF_DOUBLE, d, helper_ret_ldq_mmu, \
+ make_memop_idx(MO_UNALN, cpu_mmu_index(env)), GETRA())
+#else
+MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
+MSA_LD_DF(DF_HALF, h, cpu_lduw_data)
+MSA_LD_DF(DF_WORD, w, cpu_ldl_data)
+MSA_LD_DF(DF_DOUBLE, d, cpu_ldq_data)
+#endif
+
+static inline void ensure_writable_pages(CPUMIPSState *env,
+ target_ulong addr,
+ int mmu_idx,
+ uintptr_t retaddr)
{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- target_ulong addr = env->active_tc.gpr[rs] + (s10 << df);
- int i;
+#if !defined(CONFIG_USER_ONLY)
+#define MSA_PAGESPAN(x) (unlikely((((x) & ~TARGET_PAGE_MASK) \
+ + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE))
+ target_ulong page_addr;
- switch (df) {
- case DF_BYTE:
- for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) {
- do_sb(env, addr + (i << DF_BYTE), pwd->b[i],
- env->hflags & MIPS_HFLAG_KSU);
- }
- break;
- case DF_HALF:
- for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) {
- do_sh(env, addr + (i << DF_HALF), pwd->h[i],
- env->hflags & MIPS_HFLAG_KSU);
- }
- break;
- case DF_WORD:
- for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) {
- do_sw(env, addr + (i << DF_WORD), pwd->w[i],
- env->hflags & MIPS_HFLAG_KSU);
- }
- break;
- case DF_DOUBLE:
- for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) {
- do_sd(env, addr + (i << DF_DOUBLE), pwd->d[i],
- env->hflags & MIPS_HFLAG_KSU);
- }
- break;
+ if (MSA_PAGESPAN(addr)) {
+ /* first page */
+ probe_write(env, addr, mmu_idx, retaddr);
+ /* second page */
+ page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
+ probe_write(env, page_addr, mmu_idx, retaddr);
}
+#endif
}
+
+#define MSA_ST_DF(DF, TYPE, ST_INSN, ...) \
+void helper_msa_st_ ## TYPE(CPUMIPSState *env, uint32_t wd, uint32_t rs,\
+ int32_t s10) \
+{ \
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
+ target_ulong addr = env->active_tc.gpr[rs] + (s10 << DF); \
+ int mmu_idx = cpu_mmu_index(env); \
+ int i; \
+ ensure_writable_pages(env, addr, mmu_idx, GETRA()); \
+ for (i = 0; i < DF_ELEMENTS(DF); i++) { \
+ ST_INSN(env, addr + (i << DF), pwd->TYPE[i], ##__VA_ARGS__); \
+ } \
+}
+
+#if !defined(CONFIG_USER_ONLY)
+MSA_ST_DF(DF_BYTE, b, helper_ret_stb_mmu, \
+ make_memop_idx(MO_UNALN, mmu_idx), GETRA())
+MSA_ST_DF(DF_HALF, h, helper_ret_stw_mmu, \
+ make_memop_idx(MO_UNALN, mmu_idx), GETRA())
+MSA_ST_DF(DF_WORD, w, helper_ret_stl_mmu, \
+ make_memop_idx(MO_UNALN, mmu_idx), GETRA())
+MSA_ST_DF(DF_DOUBLE, d, helper_ret_stq_mmu, \
+ make_memop_idx(MO_UNALN, mmu_idx), GETRA())
+#else
+MSA_ST_DF(DF_BYTE, b, cpu_stb_data)
+MSA_ST_DF(DF_HALF, h, cpu_stw_data)
+MSA_ST_DF(DF_WORD, w, cpu_stl_data)
+MSA_ST_DF(DF_DOUBLE, d, cpu_stq_data)
+#endif
+
diff --git a/target-mips/translate.c b/target-mips/translate.c
index fd063a2..88b3206 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -18402,32 +18402,39 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx)
int32_t s10 = sextract32(ctx->opcode, 16, 10);
uint8_t rs = (ctx->opcode >> 11) & 0x1f;
uint8_t wd = (ctx->opcode >> 6) & 0x1f;
- uint8_t df = (ctx->opcode >> 0) & 0x3;
- TCGv_i32 tdf = tcg_const_i32(df);
TCGv_i32 twd = tcg_const_i32(wd);
TCGv_i32 trs = tcg_const_i32(rs);
TCGv_i32 ts10 = tcg_const_i32(s10);
switch (MASK_MSA_MINOR(opcode)) {
case OPC_LD_B:
+ gen_helper_msa_ld_b(cpu_env, twd, trs, ts10);
+ break;
case OPC_LD_H:
+ gen_helper_msa_ld_h(cpu_env, twd, trs, ts10);
+ break;
case OPC_LD_W:
+ gen_helper_msa_ld_w(cpu_env, twd, trs, ts10);
+ break;
case OPC_LD_D:
- save_cpu_state(ctx, 1);
- gen_helper_msa_ld_df(cpu_env, tdf, twd, trs, ts10);
+ gen_helper_msa_ld_d(cpu_env, twd, trs, ts10);
break;
case OPC_ST_B:
+ gen_helper_msa_st_b(cpu_env, twd, trs, ts10);
+ break;
case OPC_ST_H:
+ gen_helper_msa_st_h(cpu_env, twd, trs, ts10);
+ break;
case OPC_ST_W:
+ gen_helper_msa_st_w(cpu_env, twd, trs, ts10);
+ break;
case OPC_ST_D:
- save_cpu_state(ctx, 1);
- gen_helper_msa_st_df(cpu_env, tdf, twd, trs, ts10);
+ gen_helper_msa_st_d(cpu_env, twd, trs, ts10);
break;
}
tcg_temp_free_i32(twd);
- tcg_temp_free_i32(tdf);
tcg_temp_free_i32(trs);
tcg_temp_free_i32(ts10);
}
--
1.7.5.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/3] target-mips: Misaligned memory accesses for R6
2015-05-20 15:12 ` [Qemu-devel] [PATCH v4 1/3] target-mips: Misaligned memory accesses for R6 Yongbok Kim
@ 2015-05-20 17:09 ` Richard Henderson
2015-05-21 9:47 ` Yongbok Kim
0 siblings, 1 reply; 11+ messages in thread
From: Richard Henderson @ 2015-05-20 17:09 UTC (permalink / raw)
To: Yongbok Kim, qemu-devel; +Cc: peter.maydell, leon.alrae, afaerber
On 05/20/2015 08:12 AM, Yongbok Kim wrote:
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index 73a8e45..58f02cf 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -2215,6 +2215,13 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> int error_code = 0;
> int excp;
>
> + if (env->insn_flags & ISA_MIPS32R6) {
> + /* Release 6 provides support for misaligned memory access for
> + * all ordinary memory reference instructions
> + * */
> + return;
> + }
This should be done instead with MO_UNALN, at translate time.
See target-ppc, DisasContext, default_tcg_memop_mask.
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v4 2/3] softmmu: Add probe_write()
2015-05-20 15:12 ` [Qemu-devel] [PATCH v4 2/3] softmmu: Add probe_write() Yongbok Kim
@ 2015-05-20 17:10 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2015-05-20 17:10 UTC (permalink / raw)
To: Yongbok Kim, qemu-devel; +Cc: peter.maydell, leon.alrae, afaerber
On 05/20/2015 08:12 AM, Yongbok Kim wrote:
> + }
> + return;
> +}
Drop the useless return.
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v4 3/3] target-mips: Misaligned memory accesses for MSA
2015-05-20 15:12 ` [Qemu-devel] [PATCH v4 3/3] target-mips: Misaligned memory accesses for MSA Yongbok Kim
@ 2015-05-20 17:25 ` Richard Henderson
2015-05-21 9:47 ` Yongbok Kim
0 siblings, 1 reply; 11+ messages in thread
From: Richard Henderson @ 2015-05-20 17:25 UTC (permalink / raw)
To: Yongbok Kim, qemu-devel; +Cc: peter.maydell, leon.alrae, afaerber
On 05/20/2015 08:12 AM, Yongbok Kim wrote:
> +#define MSA_LD_DF(DF, TYPE, LD_INSN, ...) \
> +void helper_msa_ld_ ## TYPE(CPUMIPSState *env, uint32_t wd, uint32_t rs,\
> + int32_t s10) \
> +{ \
> + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
> + wr_t wx; \
> + target_ulong addr = env->active_tc.gpr[rs] + (s10 << DF); \
It would be nice to clean this up a bit more. For instance, don't pass the
register number and offset. Instead, compute the address properly during
translation and pass that down.
> + int i; \
> + for (i = 0; i < DF_ELEMENTS(DF); i++) { \
> + wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
Why the varargs? They're the same all the time.
> +MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, \
> + make_memop_idx(MO_UNALN, cpu_mmu_index(env)), GETRA())
I would prefer it if you'd pass the full and proper TCGMemOp.
I.e. MO_TE | MO_{8,16,32,64} | MO_UNALN.
And you might as well hoist that out of the load/store loops.
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/3] target-mips: Misaligned memory accesses for R6
2015-05-20 17:09 ` Richard Henderson
@ 2015-05-21 9:47 ` Yongbok Kim
2015-05-21 16:15 ` Richard Henderson
0 siblings, 1 reply; 11+ messages in thread
From: Yongbok Kim @ 2015-05-21 9:47 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, leon.alrae, afaerber
On 20/05/2015 18:09, Richard Henderson wrote:
> On 05/20/2015 08:12 AM, Yongbok Kim wrote:
>> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
>> index 73a8e45..58f02cf 100644
>> --- a/target-mips/op_helper.c
>> +++ b/target-mips/op_helper.c
>> @@ -2215,6 +2215,13 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
>> int error_code = 0;
>> int excp;
>>
>> + if (env->insn_flags & ISA_MIPS32R6) {
>> + /* Release 6 provides support for misaligned memory access for
>> + * all ordinary memory reference instructions
>> + * */
>> + return;
>> + }
>
> This should be done instead with MO_UNALN, at translate time.
> See target-ppc, DisasContext, default_tcg_memop_mask.
>
>
> r~
>
Fair enough. Actually I considered to pass the information but didn't
bother as this way is so simple.
Regards,
Yongbok
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v4 3/3] target-mips: Misaligned memory accesses for MSA
2015-05-20 17:25 ` Richard Henderson
@ 2015-05-21 9:47 ` Yongbok Kim
2015-05-21 16:16 ` Richard Henderson
0 siblings, 1 reply; 11+ messages in thread
From: Yongbok Kim @ 2015-05-21 9:47 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: peter.maydell, leon.alrae, afaerber
On 20/05/2015 18:25, Richard Henderson wrote:
>
>> + int i; \
>> + for (i = 0; i < DF_ELEMENTS(DF); i++) { \
>> + wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
>
> Why the varargs? They're the same all the time.
No, they aren't. we still need to support linux user mode which don't have
any extra argument.
MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, \
make_memop_idx(MO_UNALN, cpu_mmu_index(env)), GETRA())
VS.
MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
Regards,
Yongbok
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v4 1/3] target-mips: Misaligned memory accesses for R6
2015-05-21 9:47 ` Yongbok Kim
@ 2015-05-21 16:15 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2015-05-21 16:15 UTC (permalink / raw)
To: Yongbok Kim, qemu-devel; +Cc: peter.maydell, leon.alrae, afaerber
On 05/21/2015 02:47 AM, Yongbok Kim wrote:
> Fair enough. Actually I considered to pass the information but didn't
> bother as this way is so simple.
If you ever quit relying on a separate heck for atomics,
which you probably should, this would be incorrect.
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Qemu-devel] [PATCH v4 3/3] target-mips: Misaligned memory accesses for MSA
2015-05-21 9:47 ` Yongbok Kim
@ 2015-05-21 16:16 ` Richard Henderson
0 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2015-05-21 16:16 UTC (permalink / raw)
To: Yongbok Kim, qemu-devel; +Cc: peter.maydell, leon.alrae, afaerber
On 05/21/2015 02:47 AM, Yongbok Kim wrote:
> On 20/05/2015 18:25, Richard Henderson wrote:
>
>>
>>> + int i; \
>>> + for (i = 0; i < DF_ELEMENTS(DF); i++) { \
>>> + wx.TYPE[i] = LD_INSN(env, addr + (i << DF), ##__VA_ARGS__); \
>>
>> Why the varargs? They're the same all the time.
>
> No, they aren't. we still need to support linux user mode which don't have
> any extra argument.
>
> MSA_LD_DF(DF_BYTE, b, helper_ret_ldub_mmu, \
> make_memop_idx(MO_UNALN, cpu_mmu_index(env)), GETRA())
>
> VS.
>
> MSA_LD_DF(DF_BYTE, b, cpu_ldub_data)
Ah, I'd missed that. Thanks,
r~
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2015-05-21 16:16 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-05-20 15:12 [Qemu-devel] [PATCH v4 0/3] target-mips: Add support for misaligned accesses Yongbok Kim
2015-05-20 15:12 ` [Qemu-devel] [PATCH v4 1/3] target-mips: Misaligned memory accesses for R6 Yongbok Kim
2015-05-20 17:09 ` Richard Henderson
2015-05-21 9:47 ` Yongbok Kim
2015-05-21 16:15 ` Richard Henderson
2015-05-20 15:12 ` [Qemu-devel] [PATCH v4 2/3] softmmu: Add probe_write() Yongbok Kim
2015-05-20 17:10 ` Richard Henderson
2015-05-20 15:12 ` [Qemu-devel] [PATCH v4 3/3] target-mips: Misaligned memory accesses for MSA Yongbok Kim
2015-05-20 17:25 ` Richard Henderson
2015-05-21 9:47 ` Yongbok Kim
2015-05-21 16:16 ` Richard Henderson
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