* [PATCH 1/1] clk: tegra: read correct iddq register in PLL_SS registration
@ 2015-05-18 11:03 Bill Huang
[not found] ` <1431946983-29554-1-git-send-email-bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
0 siblings, 1 reply; 5+ messages in thread
From: Bill Huang @ 2015-05-18 11:03 UTC (permalink / raw)
To: pdeschrijver
Cc: mturquette, swarren, thierry.reding, pwalmsley, rklein,
linux-clk, linux-tegra, linux-kernel, Bill Huang
This fixes bug in tegra_clk_register_pllss() which mistakenly assume the
iddq register is the PLL base address.
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 05c6d08..f225325 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1826,7 +1826,7 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
struct clk *clk, *parent;
struct tegra_clk_pll_freq_table cfg;
unsigned long parent_rate;
- u32 val;
+ u32 val, val_iddq;
int i;
if (!pll_params->div_nmp)
@@ -1874,14 +1874,17 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
val = pll_readl_base(pll);
+ val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
if (val & PLL_BASE_ENABLE) {
- if (val & BIT(pll_params->iddq_bit_idx)) {
+ if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
WARN(1, "%s is on but IDDQ set\n", name);
kfree(pll);
return ERR_PTR(-EINVAL);
}
- } else
- val |= BIT(pll_params->iddq_bit_idx);
+ } else {
+ val_iddq |= BIT(pll_params->iddq_bit_idx);
+ writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
+ }
val &= ~PLLSS_LOCK_OVERRIDE;
pll_writel_base(val, pll);
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] clk: tegra: read correct iddq register in PLL_SS registration
2015-05-18 11:03 [PATCH 1/1] clk: tegra: read correct iddq register in PLL_SS registration Bill Huang
@ 2015-05-18 16:53 ` Benson Leung
0 siblings, 0 replies; 5+ messages in thread
From: Benson Leung @ 2015-05-18 16:53 UTC (permalink / raw)
To: Bill Huang
Cc: Peter De Schrijver, Mike Turquette, Stephen Warren,
Thierry Reding, Paul Walmsley, Rhyland Klein,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On Mon, May 18, 2015 at 4:03 AM, Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:
> This fixes bug in tegra_clk_register_pllss() which mistakenly assume the
> iddq register is the PLL base address.
>
> Signed-off-by: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Thanks for the quick fix.
Reviewed-by: Benson Leung <bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
--
Benson Leung
Software Engineer, Chrom* OS
bleung-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] clk: tegra: read correct iddq register in PLL_SS registration
@ 2015-05-18 16:53 ` Benson Leung
0 siblings, 0 replies; 5+ messages in thread
From: Benson Leung @ 2015-05-18 16:53 UTC (permalink / raw)
To: Bill Huang
Cc: Peter De Schrijver, Mike Turquette, Stephen Warren,
Thierry Reding, Paul Walmsley, Rhyland Klein, linux-clk,
linux-tegra, linux-kernel
On Mon, May 18, 2015 at 4:03 AM, Bill Huang <bilhuang@nvidia.com> wrote:
> This fixes bug in tegra_clk_register_pllss() which mistakenly assume the
> iddq register is the PLL base address.
>
> Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Thanks for the quick fix.
Reviewed-by: Benson Leung <bleung@chromium.org>
--
Benson Leung
Software Engineer, Chrom* OS
bleung@chromium.org
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] clk: tegra: read correct iddq register in PLL_SS registration
2015-05-18 11:03 [PATCH 1/1] clk: tegra: read correct iddq register in PLL_SS registration Bill Huang
@ 2015-05-20 17:15 ` Rhyland Klein
0 siblings, 0 replies; 5+ messages in thread
From: Rhyland Klein @ 2015-05-20 17:15 UTC (permalink / raw)
To: Bill Huang, pdeschrijver-DDmLM1+adcrQT0dZR+AlfA
Cc: mturquette-QSEj5FYQhm4dnm+yROfE0A,
swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
pwalmsley-DDmLM1+adcrQT0dZR+AlfA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 5/18/2015 7:03 AM, Bill Huang wrote:
> This fixes bug in tegra_clk_register_pllss() which mistakenly assume the
> iddq register is the PLL base address.
>
> Signed-off-by: Bill Huang <bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/clk/tegra/clk-pll.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> index 05c6d08..f225325 100644
> --- a/drivers/clk/tegra/clk-pll.c
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -1826,7 +1826,7 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
> struct clk *clk, *parent;
> struct tegra_clk_pll_freq_table cfg;
> unsigned long parent_rate;
> - u32 val;
> + u32 val, val_iddq;
> int i;
>
> if (!pll_params->div_nmp)
> @@ -1874,14 +1874,17 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
> pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
>
> val = pll_readl_base(pll);
> + val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
You could/should likely use pll_readl(pll_params->iddq_reg, pll) here.
> if (val & PLL_BASE_ENABLE) {
> - if (val & BIT(pll_params->iddq_bit_idx)) {
> + if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
> WARN(1, "%s is on but IDDQ set\n", name);
> kfree(pll);
> return ERR_PTR(-EINVAL);
> }
> - } else
> - val |= BIT(pll_params->iddq_bit_idx);
> + } else {
> + val_iddq |= BIT(pll_params->iddq_bit_idx);
> + writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
likewise you can use pll_writel(val_iddq, pll_params->iddq_reg, pll) here.
-rhyland
--
nvpublic
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/1] clk: tegra: read correct iddq register in PLL_SS registration
@ 2015-05-20 17:15 ` Rhyland Klein
0 siblings, 0 replies; 5+ messages in thread
From: Rhyland Klein @ 2015-05-20 17:15 UTC (permalink / raw)
To: Bill Huang, pdeschrijver
Cc: mturquette, swarren, thierry.reding, pwalmsley, linux-clk,
linux-tegra, linux-kernel
On 5/18/2015 7:03 AM, Bill Huang wrote:
> This fixes bug in tegra_clk_register_pllss() which mistakenly assume the
> iddq register is the PLL base address.
>
> Signed-off-by: Bill Huang <bilhuang@nvidia.com>
> ---
> drivers/clk/tegra/clk-pll.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
> index 05c6d08..f225325 100644
> --- a/drivers/clk/tegra/clk-pll.c
> +++ b/drivers/clk/tegra/clk-pll.c
> @@ -1826,7 +1826,7 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
> struct clk *clk, *parent;
> struct tegra_clk_pll_freq_table cfg;
> unsigned long parent_rate;
> - u32 val;
> + u32 val, val_iddq;
> int i;
>
> if (!pll_params->div_nmp)
> @@ -1874,14 +1874,17 @@ struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,
> pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);
>
> val = pll_readl_base(pll);
> + val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg);
You could/should likely use pll_readl(pll_params->iddq_reg, pll) here.
> if (val & PLL_BASE_ENABLE) {
> - if (val & BIT(pll_params->iddq_bit_idx)) {
> + if (val_iddq & BIT(pll_params->iddq_bit_idx)) {
> WARN(1, "%s is on but IDDQ set\n", name);
> kfree(pll);
> return ERR_PTR(-EINVAL);
> }
> - } else
> - val |= BIT(pll_params->iddq_bit_idx);
> + } else {
> + val_iddq |= BIT(pll_params->iddq_bit_idx);
> + writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg);
likewise you can use pll_writel(val_iddq, pll_params->iddq_reg, pll) here.
-rhyland
--
nvpublic
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2015-05-20 17:15 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-05-18 11:03 [PATCH 1/1] clk: tegra: read correct iddq register in PLL_SS registration Bill Huang
[not found] ` <1431946983-29554-1-git-send-email-bilhuang-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2015-05-18 16:53 ` Benson Leung
2015-05-18 16:53 ` Benson Leung
2015-05-20 17:15 ` Rhyland Klein
2015-05-20 17:15 ` Rhyland Klein
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.