[PATCH 00/12] drm/i915: PCH modeset sequence fixes

[PATCH 00/12] drm/i915: PCH modeset sequence fixes

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

While fixing up the 12bpc HDMI code I ran afoul of the IBX transcoder B
workaround. Turns out that's currently busted. So I fixed it, but that
caused the dreaded pipe off timeout to make a reappearance. So to fix that
I had to reorganize the crtc disable sequence to actually match the spec
(ie. we must disable the pipe before the port).

Also I got sick of looking at the mess in the DP code, so I went ahead
and cleaned it up a bit. And that also made me notice the CPT/PPT DP
enhanced framing mess, which I also tried to fix.

So basically I stepped ina another rat's nest again, and had to dig myself
out.

So far my ILK and IVB seem happy with the result, but I've been able to test
all of it (eg. SDVO is untested).

The entire series is available here [1] (sitting on top of my HDMI 12bpc
series).

[1] git://github.com/vsyrjala/linux.git pch_modeset_seq_fixes

Ville Syrjälä (12):
  drm/i915: Remove a bogus 12bpc "toggle" from intel_disable_hdmi()
  drm/i915: Remove the double register write from intel_disable_hdmi()
  drm/i915: Clarfify the DP code platform checks
  drm/i915: Clean up the CPT DP .get_hw_state() port readout
  drm/i915: Fix DP enhanced framing for CPT
  drm/i915: Use POSTING_READ() in intel_sdvo_write_sdvox()
  drm/i915: Write the SDVO reg twice on IBX
  drm/i915: Fix the IBX transcoder B workarounds
  drm/i915: Disable HDMI port after the pipe on PCH platforms
  drm/i915: Disable SDVO port after the pipe on PCH platforms
  drm/i915: Disable CRT port after pipe on PCH platforms
  drm/i915: Disable FDI RX/TX before the ports

 drivers/gpu/drm/i915/i915_reg.h      |   1 +
 drivers/gpu/drm/i915/intel_crt.c     |  15 ++++-
 drivers/gpu/drm/i915/intel_display.c |   8 +--
 drivers/gpu/drm/i915/intel_dp.c      | 118 +++++++++++++++++------------------
 drivers/gpu/drm/i915/intel_hdmi.c    |  95 +++++++++++++++-------------
 drivers/gpu/drm/i915/intel_sdvo.c    |  80 +++++++++++++-----------
 6 files changed, 171 insertions(+), 146 deletions(-)

-- 
2.0.5

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[PATCH 01/12] drm/i915: Remove a bogus 12bpc "toggle" from intel_disable_hdmi()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The IBX 12bpc port enable toggle is only relevant when enabling
the port, not when disabling it. Also this code doesn't actually
toggle anything, and essentially just writes the port register
one extra time. Furthermore CPT/PPT don't need such workarounds
and yet we include them. Just kill it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index f3eec38..72fce34 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1127,14 +1127,6 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
 		}
 	}
 
-	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
-	 * we do this anyway which shows more stable in testing.
-	 */
-	if (HAS_PCH_SPLIT(dev)) {
-		I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
-		POSTING_READ(intel_hdmi->hdmi_reg);
-	}
-
 	temp &= ~enable_bits;
 
 	I915_WRITE(intel_hdmi->hdmi_reg, temp);
-- 
2.0.5

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[PATCH 02/12] drm/i915: Remove the double register write from intel_disable_hdmi()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

IBX can have problems with the first write to the port register getting
masked when enabling the port. We are trying to apply the workaround
also when disabling the port where it's not needed, and we also try
to apply it for CPT/PPT as well which don't need it. Just kill it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 72fce34..308015e 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1132,14 +1132,6 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
 	I915_WRITE(intel_hdmi->hdmi_reg, temp);
 	POSTING_READ(intel_hdmi->hdmi_reg);
 
-	/* HW workaround, need to write this twice for issue that may result
-	 * in first write getting masked.
-	 */
-	if (HAS_PCH_SPLIT(dev)) {
-		I915_WRITE(intel_hdmi->hdmi_reg, temp);
-		POSTING_READ(intel_hdmi->hdmi_reg);
-	}
-
 	if (IS_CHERRYVIEW(dev))
 		chv_powergate_phy_lanes(encoder, 0xf);
 
-- 
2.0.5

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[PATCH 03/12] drm/i915: Clarfify the DP code platform checks

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

intel_dp.c is a mess with all the checks for different
platform/PCH variants and ports. Try to clean it up by recognizing
the following facts:
- IVB port A, and CPT port B/C/D are always the special cases
- VLV/CHV don't have port A
- Using the same kind of logic everywhere makes things much easier to
  parse

So let's move the IVB port A and PCH port B/C/D checks to be done first,
and let the other cases fall through, and always check for these things
using the same logic.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 46 ++++++++++++++++++++---------------------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e9426dd..0971a5d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1561,7 +1561,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
 
 	/* Split out the IBX/CPU vs CPT settings */
 
-	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
+	if (IS_GEN7(dev) && port == PORT_A) {
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 			intel_dp->DP |= DP_SYNC_HS_HIGH;
 		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
@@ -1572,7 +1572,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
 			intel_dp->DP |= DP_ENHANCED_FRAMING;
 
 		intel_dp->DP |= crtc->pipe << 29;
-	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
+	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
+		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
+	} else {
 		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 			intel_dp->DP |= intel_dp->color_range;
 
@@ -1585,14 +1587,10 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
 		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
 			intel_dp->DP |= DP_ENHANCED_FRAMING;
 
-		if (!IS_CHERRYVIEW(dev)) {
-			if (crtc->pipe == 1)
-				intel_dp->DP |= DP_PIPEB_SELECT;
-		} else {
+		if (IS_CHERRYVIEW(dev))
 			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
-		}
-	} else {
-		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
+		else if (crtc->pipe == PIPE_B)
+			intel_dp->DP |= DP_PIPEB_SELECT;
 	}
 }
 
@@ -2176,13 +2174,9 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
 	if (!(tmp & DP_PORT_EN))
 		return false;
 
-	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
+	if (IS_GEN7(dev) && port == PORT_A) {
 		*pipe = PORT_TO_PIPE_CPT(tmp);
-	} else if (IS_CHERRYVIEW(dev)) {
-		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
-	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
-		*pipe = PORT_TO_PIPE(tmp);
-	} else {
+	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
 		u32 trans_sel;
 		u32 trans_dp;
 		int i;
@@ -2211,6 +2205,10 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
 
 		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
 			      intel_dp->output_reg);
+	} else if (IS_CHERRYVIEW(dev)) {
+		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
+	} else {
+		*pipe = PORT_TO_PIPE(tmp);
 	}
 
 	return true;
@@ -2231,24 +2229,24 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
 	if (tmp & DP_AUDIO_OUTPUT_ENABLE)
 		pipe_config->has_audio = true;
 
-	if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
-		if (tmp & DP_SYNC_HS_HIGH)
+	if (HAS_PCH_CPT(dev) && port != PORT_A) {
+		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
+		if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
 			flags |= DRM_MODE_FLAG_PHSYNC;
 		else
 			flags |= DRM_MODE_FLAG_NHSYNC;
 
-		if (tmp & DP_SYNC_VS_HIGH)
+		if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
 			flags |= DRM_MODE_FLAG_PVSYNC;
 		else
 			flags |= DRM_MODE_FLAG_NVSYNC;
 	} else {
-		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
-		if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
+		if (tmp & DP_SYNC_HS_HIGH)
 			flags |= DRM_MODE_FLAG_PHSYNC;
 		else
 			flags |= DRM_MODE_FLAG_NHSYNC;
 
-		if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
+		if (tmp & DP_SYNC_VS_HIGH)
 			flags |= DRM_MODE_FLAG_PVSYNC;
 		else
 			flags |= DRM_MODE_FLAG_NVSYNC;
@@ -2415,7 +2413,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
 		}
 		I915_WRITE(DP_TP_CTL(port), temp);
 
-	} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
+	} else if ((IS_GEN7(dev) && port == PORT_A) ||
+		   (HAS_PCH_CPT(dev) && port != PORT_A)) {
 		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
 
 		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
@@ -3842,7 +3841,8 @@ intel_dp_link_down(struct intel_dp *intel_dp)
 
 	DRM_DEBUG_KMS("\n");
 
-	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
+	if ((IS_GEN7(dev) && port == PORT_A) ||
+	    (HAS_PCH_CPT(dev) && port != PORT_A)) {
 		DP &= ~DP_LINK_TRAIN_MASK_CPT;
 		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
 	} else {
-- 
2.0.5

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[PATCH 04/12] drm/i915: Clean up the CPT DP .get_hw_state() port readout

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Define a TRANS_DP_PIPE_TO_PORT() to make the CPT DP .get_hw_state()
pipe readout neater.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  1 +
 drivers/gpu/drm/i915/intel_dp.c | 26 +++++---------------------
 2 files changed, 6 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dcd93b5..0538b24 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6410,6 +6410,7 @@ enum skl_disp_power_wells {
 #define  TRANS_DP_PORT_SEL_D	(2<<29)
 #define  TRANS_DP_PORT_SEL_NONE	(3<<29)
 #define  TRANS_DP_PORT_SEL_MASK	(3<<29)
+#define  TRANS_DP_PIPE_TO_PORT(val)	((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
 #define  TRANS_DP_AUDIO_ONLY	(1<<26)
 #define  TRANS_DP_ENH_FRAMING	(1<<18)
 #define  TRANS_DP_8BPC		(0<<9)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0971a5d..dc89931 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2177,28 +2177,12 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
 	if (IS_GEN7(dev) && port == PORT_A) {
 		*pipe = PORT_TO_PIPE_CPT(tmp);
 	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
-		u32 trans_sel;
-		u32 trans_dp;
-		int i;
-
-		switch (intel_dp->output_reg) {
-		case PCH_DP_B:
-			trans_sel = TRANS_DP_PORT_SEL_B;
-			break;
-		case PCH_DP_C:
-			trans_sel = TRANS_DP_PORT_SEL_C;
-			break;
-		case PCH_DP_D:
-			trans_sel = TRANS_DP_PORT_SEL_D;
-			break;
-		default:
-			return true;
-		}
+		enum pipe p;
 
-		for_each_pipe(dev_priv, i) {
-			trans_dp = I915_READ(TRANS_DP_CTL(i));
-			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
-				*pipe = i;
+		for_each_pipe(dev_priv, p) {
+			u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
+			if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
+				*pipe = p;
 				return true;
 			}
 		}
-- 
2.0.5

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[PATCH 05/12] drm/i915: Fix DP enhanced framing for CPT

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently we're always enabling enhanced framing on CPT even if the sink
doesn't support it. Fix this up by actaully looking at what the sink
tells us.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 3 +--
 drivers/gpu/drm/i915/intel_dp.c      | 9 +++++++++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a392188..a177f2e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4206,8 +4206,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
 		temp &= ~(TRANS_DP_PORT_SEL_MASK |
 			  TRANS_DP_SYNC_MASK |
 			  TRANS_DP_BPC_MASK);
-		temp |= (TRANS_DP_OUTPUT_ENABLE |
-			 TRANS_DP_ENH_FRAMING);
+		temp |= TRANS_DP_OUTPUT_ENABLE;
 		temp |= bpc << 9; /* same format but at 11:9 */
 
 		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dc89931..17b006c 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1573,7 +1573,16 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
 
 		intel_dp->DP |= crtc->pipe << 29;
 	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
+		u32 trans_dp;
+
 		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
+
+		trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
+		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
+			trans_dp |= TRANS_DP_ENH_FRAMING;
+		else
+			trans_dp &= ~TRANS_DP_ENH_FRAMING;
+		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
 	} else {
 		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
 			intel_dp->DP |= intel_dp->color_range;
-- 
2.0.5

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[PATCH 06/12] drm/i915: Use POSTING_READ() in intel_sdvo_write_sdvox()

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use POSTING_READ() in intel_sdvo_write_sdvox() as appropriate.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 10cd332..0a06257 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -242,7 +242,7 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
 
 	if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
 		I915_WRITE(intel_sdvo->sdvo_reg, val);
-		I915_READ(intel_sdvo->sdvo_reg);
+		POSTING_READ(intel_sdvo->sdvo_reg);
 		return;
 	}
 
@@ -259,9 +259,9 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
 	for (i = 0; i < 2; i++)
 	{
 		I915_WRITE(GEN3_SDVOB, bval);
-		I915_READ(GEN3_SDVOB);
+		POSTING_READ(GEN3_SDVOB);
 		I915_WRITE(GEN3_SDVOC, cval);
-		I915_READ(GEN3_SDVOC);
+		POSTING_READ(GEN3_SDVOC);
 	}
 }
 
-- 
2.0.5

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[PATCH 07/12] drm/i915: Write the SDVO reg twice on IBX

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On IBX the SDVO/HDMI register write may be masked when enabling the
port, so it may need to written twice. The HDMI code does this, but
the SDVO code does not. Add the workaround to the SDVO code as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 0a06257..e3e9c98 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -243,6 +243,14 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
 	if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
 		I915_WRITE(intel_sdvo->sdvo_reg, val);
 		POSTING_READ(intel_sdvo->sdvo_reg);
+		/*
+		 * HW workaround, need to write this twice for issue
+		 * that may result in first write getting masked.
+		 */
+		if (HAS_PCH_IBX(dev)) {
+			I915_WRITE(intel_sdvo->sdvo_reg, val);
+			POSTING_READ(intel_sdvo->sdvo_reg);
+		}
 		return;
 	}
 
-- 
2.0.5

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[PATCH 08/12] drm/i915: Fix the IBX transcoder B workarounds

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently the IBX transcoder B workarounds are not working correctly.
Well, the HDMI one seems to be working somewhat, but the DP one is
definitely busted.

After a bit of experimentation it looks like the best way to make this
work is first disable the port on transcoder B, and then re-enable it
transcoder A, and immediately disable it again.

We can also clean up the code by noting that we can't be called without
a valid crtc. And also note that port A on ILK does not need the
workaround, so let's check for that one too.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c   | 37 ++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_hdmi.c | 50 ++++++++++++++++++---------------------
 drivers/gpu/drm/i915/intel_sdvo.c | 41 +++++++++++++-------------------
 3 files changed, 60 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 17b006c..3401cde 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3821,6 +3821,7 @@ static void
 intel_dp_link_down(struct intel_dp *intel_dp)
 {
 	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
 	enum port port = intel_dig_port->port;
 	struct drm_device *dev = intel_dig_port->base.base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -3837,34 +3838,38 @@ intel_dp_link_down(struct intel_dp *intel_dp)
 	if ((IS_GEN7(dev) && port == PORT_A) ||
 	    (HAS_PCH_CPT(dev) && port != PORT_A)) {
 		DP &= ~DP_LINK_TRAIN_MASK_CPT;
-		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
+		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
 	} else {
 		if (IS_CHERRYVIEW(dev))
 			DP &= ~DP_LINK_TRAIN_MASK_CHV;
 		else
 			DP &= ~DP_LINK_TRAIN_MASK;
-		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
+		DP |= DP_LINK_TRAIN_PAT_IDLE;
 	}
+	I915_WRITE(intel_dp->output_reg, DP);
 	POSTING_READ(intel_dp->output_reg);
 
-	if (HAS_PCH_IBX(dev) &&
-	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
-		/* Hardware workaround: leaving our transcoder select
-		 * set to transcoder B while it's off will prevent the
-		 * corresponding HDMI output on transcoder A.
-		 *
-		 * Combine this with another hardware workaround:
-		 * transcoder select bit can only be cleared while the
-		 * port is enabled.
-		 */
-		DP &= ~DP_PIPEB_SELECT;
+	DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
+	I915_WRITE(intel_dp->output_reg, DP);
+	POSTING_READ(intel_dp->output_reg);
+
+	/*
+	 * HW workaround for IBX, we need to move the port
+	 * to transcoder A after disabling it to allow the
+	 * matching HDMI port to be enabled on transcoder A.
+	 */
+	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
+		/* always enable with pattern 1 (as per spec) */
+		DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
+		DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
+		I915_WRITE(intel_dp->output_reg, DP);
+		POSTING_READ(intel_dp->output_reg);
+
+		DP &= ~DP_PORT_EN;
 		I915_WRITE(intel_dp->output_reg, DP);
 		POSTING_READ(intel_dp->output_reg);
 	}
 
-	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
-	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
-	POSTING_READ(intel_dp->output_reg);
 	msleep(intel_dp->panel_power_down_delay);
 }
 
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 308015e..9b9a69e 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1096,39 +1096,13 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
 	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 	u32 temp;
-	u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
 
 	if (crtc->config->has_audio)
 		intel_audio_codec_disable(encoder);
 
 	temp = I915_READ(intel_hdmi->hdmi_reg);
 
-	/* HW workaround for IBX, we need to move the port to transcoder A
-	 * before disabling it. */
-	if (HAS_PCH_IBX(dev)) {
-		struct drm_crtc *crtc = encoder->base.crtc;
-		int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
-
-		if (temp & SDVO_PIPE_B_SELECT) {
-			temp &= ~SDVO_PIPE_B_SELECT;
-			I915_WRITE(intel_hdmi->hdmi_reg, temp);
-			POSTING_READ(intel_hdmi->hdmi_reg);
-
-			/* Again we need to write this twice. */
-			I915_WRITE(intel_hdmi->hdmi_reg, temp);
-			POSTING_READ(intel_hdmi->hdmi_reg);
-
-			/* Transcoder selection bits only update
-			 * effectively on vblank. */
-			if (crtc)
-				intel_wait_for_vblank(dev, pipe);
-			else
-				msleep(50);
-		}
-	}
-
-	temp &= ~enable_bits;
-
+	temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
 	I915_WRITE(intel_hdmi->hdmi_reg, temp);
 	POSTING_READ(intel_hdmi->hdmi_reg);
 
@@ -1136,6 +1110,28 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
 		chv_powergate_phy_lanes(encoder, 0xf);
 
 	intel_hdmi->set_infoframes(&encoder->base, false, NULL);
+
+	/*
+	 * HW workaround for IBX, we need to move the port
+	 * to transcoder A after disabling it to allow the
+	 * matching DP port to be enabled on transcoder A.
+	 */
+	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
+		temp &= ~SDVO_PIPE_B_SELECT;
+		temp |= SDVO_ENABLE;
+		/*
+		 * HW workaround, need to write this twice for issue
+		 * that may result in first write getting masked.
+		 */
+		I915_WRITE(intel_hdmi->hdmi_reg, temp);
+		POSTING_READ(intel_hdmi->hdmi_reg);
+		I915_WRITE(intel_hdmi->hdmi_reg, temp);
+		POSTING_READ(intel_hdmi->hdmi_reg);
+
+		temp &= ~SDVO_ENABLE;
+		I915_WRITE(intel_hdmi->hdmi_reg, temp);
+		POSTING_READ(intel_hdmi->hdmi_reg);
+	}
 }
 
 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index e3e9c98..4a87691 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1437,6 +1437,7 @@ static void intel_disable_sdvo(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
 	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
+	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 	u32 temp;
 
 	intel_sdvo_set_active_outputs(intel_sdvo, 0);
@@ -1445,32 +1446,22 @@ static void intel_disable_sdvo(struct intel_encoder *encoder)
 						   DRM_MODE_DPMS_OFF);
 
 	temp = I915_READ(intel_sdvo->sdvo_reg);
-	if ((temp & SDVO_ENABLE) != 0) {
-		/* HW workaround for IBX, we need to move the port to
-		 * transcoder A before disabling it. */
-		if (HAS_PCH_IBX(encoder->base.dev)) {
-			struct drm_crtc *crtc = encoder->base.crtc;
-			int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
-
-			if (temp & SDVO_PIPE_B_SELECT) {
-				temp &= ~SDVO_PIPE_B_SELECT;
-				I915_WRITE(intel_sdvo->sdvo_reg, temp);
-				POSTING_READ(intel_sdvo->sdvo_reg);
-
-				/* Again we need to write this twice. */
-				I915_WRITE(intel_sdvo->sdvo_reg, temp);
-				POSTING_READ(intel_sdvo->sdvo_reg);
-
-				/* Transcoder selection bits only update
-				 * effectively on vblank. */
-				if (crtc)
-					intel_wait_for_vblank(encoder->base.dev, pipe);
-				else
-					msleep(50);
-			}
-		}
 
-		intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
+	temp &= ~SDVO_ENABLE;
+	intel_sdvo_write_sdvox(intel_sdvo, temp);
+
+	/*
+	 * HW workaround for IBX, we need to move the port
+	 * to transcoder A after disabling it to allow the
+	 * matching DP port to be enabled on transcoder A.
+	 */
+	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
+		temp &= ~SDVO_PIPE_B_SELECT;
+		temp |= SDVO_ENABLE;
+		intel_sdvo_write_sdvox(intel_sdvo, temp);
+
+		temp &= ~SDVO_ENABLE;
+		intel_sdvo_write_sdvox(intel_sdvo, temp);
 	}
 }
 
-- 
2.0.5

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[PATCH 09/12] drm/i915: Disable HDMI port after the pipe on PCH platforms

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

BSpec says we should disable all ports after the pipe on PCH
platforms. Do so. Fixes a pipe off timeout on ILK now caused by
the transcoder B workaround.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_hdmi.c | 33 +++++++++++++++++++++++++++++----
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 9b9a69e..2ee19ca 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -1097,9 +1097,6 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
 	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 	u32 temp;
 
-	if (crtc->config->has_audio)
-		intel_audio_codec_disable(encoder);
-
 	temp = I915_READ(intel_hdmi->hdmi_reg);
 
 	temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
@@ -1134,6 +1131,29 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
 	}
 }
 
+static void g4x_disable_hdmi(struct intel_encoder *encoder)
+{
+	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+
+	if (crtc->config->has_audio)
+		intel_audio_codec_disable(encoder);
+
+	intel_disable_hdmi(encoder);
+}
+
+static void pch_disable_hdmi(struct intel_encoder *encoder)
+{
+	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
+
+	if (crtc->config->has_audio)
+		intel_audio_codec_disable(encoder);
+}
+
+static void pch_post_disable_hdmi(struct intel_encoder *encoder)
+{
+	intel_disable_hdmi(encoder);
+}
+
 static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
 {
 	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
@@ -2020,7 +2040,12 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
 			 DRM_MODE_ENCODER_TMDS);
 
 	intel_encoder->compute_config = intel_hdmi_compute_config;
-	intel_encoder->disable = intel_disable_hdmi;
+	if (HAS_PCH_SPLIT(dev)) {
+		intel_encoder->disable = pch_disable_hdmi;
+		intel_encoder->post_disable = pch_post_disable_hdmi;
+	} else {
+		intel_encoder->disable = g4x_disable_hdmi;
+	}
 	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
 	intel_encoder->get_config = intel_hdmi_get_config;
 	if (IS_CHERRYVIEW(dev)) {
-- 
2.0.5

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[PATCH 10/12] drm/i915: Disable SDVO port after the pipe on PCH platforms

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 25 +++++++++++++++++--------
 1 file changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 4a87691..d24ef75 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1465,6 +1465,15 @@ static void intel_disable_sdvo(struct intel_encoder *encoder)
 	}
 }
 
+static void pch_disable_sdvo(struct intel_encoder *encoder)
+{
+}
+
+static void pch_post_disable_sdvo(struct intel_encoder *encoder)
+{
+	intel_disable_sdvo(encoder);
+}
+
 static void intel_enable_sdvo(struct intel_encoder *encoder)
 {
 	struct drm_device *dev = encoder->base.dev;
@@ -1477,14 +1486,9 @@ static void intel_enable_sdvo(struct intel_encoder *encoder)
 	bool success;
 
 	temp = I915_READ(intel_sdvo->sdvo_reg);
-	if ((temp & SDVO_ENABLE) == 0) {
-		/* HW workaround for IBX, we need to move the port
-		 * to transcoder A before disabling it, so restore it here. */
-		if (HAS_PCH_IBX(dev))
-			temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
+	temp |= SDVO_ENABLE;
+	intel_sdvo_write_sdvox(intel_sdvo, temp);
 
-		intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
-	}
 	for (i = 0; i < 2; i++)
 		intel_wait_for_vblank(dev, intel_crtc->pipe);
 
@@ -2987,7 +2991,12 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
 	}
 
 	intel_encoder->compute_config = intel_sdvo_compute_config;
-	intel_encoder->disable = intel_disable_sdvo;
+	if (HAS_PCH_SPLIT(dev)) {
+		intel_encoder->disable = pch_disable_sdvo;
+		intel_encoder->post_disable = pch_post_disable_sdvo;
+	} else {
+		intel_encoder->disable = intel_disable_sdvo;
+	}
 	intel_encoder->pre_enable = intel_sdvo_pre_enable;
 	intel_encoder->enable = intel_enable_sdvo;
 	intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
-- 
2.0.5

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[PATCH 11/12] drm/i915: Disable CRT port after pipe on PCH platforms

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Follow the BSpec sequence for the CRT port as well on PCH platforms,
ie. disable the pipe before the port.

Didn't bother looking at DDI in detail yet, so leave that one be even
though the CRT is a PCH port there.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_crt.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index 93bb515..521af2c 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -207,6 +207,14 @@ static void intel_disable_crt(struct intel_encoder *encoder)
 	intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
 }
 
+static void pch_disable_crt(struct intel_encoder *encoder)
+{
+}
+
+static void pch_post_disable_crt(struct intel_encoder *encoder)
+{
+	intel_disable_crt(encoder);
+}
 
 static void hsw_crt_post_disable(struct intel_encoder *encoder)
 {
@@ -888,7 +896,12 @@ void intel_crt_init(struct drm_device *dev)
 		crt->adpa_reg = ADPA;
 
 	crt->base.compute_config = intel_crt_compute_config;
-	crt->base.disable = intel_disable_crt;
+	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) {
+		crt->base.disable = pch_disable_crt;
+		crt->base.post_disable = pch_post_disable_crt;
+	} else {
+		crt->base.disable = intel_disable_crt;
+	}
 	crt->base.enable = intel_enable_crt;
 	if (I915_HAS_HOTPLUG(dev))
 		crt->base.hpd_pin = HPD_CRT;
-- 
2.0.5

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[PATCH 12/12] drm/i915: Disable FDI RX/TX before the ports

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Bspec says we should disable the FDI RX/TX before disabling the PCH
ports. Do so.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a177f2e..fbcf26d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5096,13 +5096,14 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
 
 	ironlake_pfit_disable(intel_crtc);
 
+	if (intel_crtc->config->has_pch_encoder)
+		ironlake_fdi_disable(crtc);
+
 	for_each_encoder_on_crtc(dev, crtc, encoder)
 		if (encoder->post_disable)
 			encoder->post_disable(encoder);
 
 	if (intel_crtc->config->has_pch_encoder) {
-		ironlake_fdi_disable(crtc);
-
 		ironlake_disable_pch_transcoder(dev_priv, pipe);
 
 		if (HAS_PCH_CPT(dev)) {
-- 
2.0.5

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Re: [PATCH 06/12] drm/i915: Use POSTING_READ() in intel_sdvo_write_sdvox()

[Daniel Vetter]

On Tue, May 05, 2015 at 05:17:32PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Use POSTING_READ() in intel_sdvo_write_sdvox() as appropriate.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Queued for -next, thanks for the patch.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_sdvo.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index 10cd332..0a06257 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -242,7 +242,7 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
>  
>  	if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
>  		I915_WRITE(intel_sdvo->sdvo_reg, val);
> -		I915_READ(intel_sdvo->sdvo_reg);
> +		POSTING_READ(intel_sdvo->sdvo_reg);
>  		return;
>  	}
>  
> @@ -259,9 +259,9 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
>  	for (i = 0; i < 2; i++)
>  	{
>  		I915_WRITE(GEN3_SDVOB, bval);
> -		I915_READ(GEN3_SDVOB);
> +		POSTING_READ(GEN3_SDVOB);
>  		I915_WRITE(GEN3_SDVOC, cval);
> -		I915_READ(GEN3_SDVOC);
> +		POSTING_READ(GEN3_SDVOC);
>  	}
>  }
>  
> -- 
> 2.0.5
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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Re: [PATCH 01/12] drm/i915: Remove a bogus 12bpc "toggle" from intel_disable_hdmi()

[Jesse Barnes]

On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The IBX 12bpc port enable toggle is only relevant when enabling
> the port, not when disabling it. Also this code doesn't actually
> toggle anything, and essentially just writes the port register
> one extra time. Furthermore CPT/PPT don't need such workarounds
> and yet we include them. Just kill it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_hdmi.c | 8 --------
>  1 file changed, 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index f3eec38..72fce34 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1127,14 +1127,6 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
>  		}
>  	}
>  
> -	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
> -	 * we do this anyway which shows more stable in testing.
> -	 */
> -	if (HAS_PCH_SPLIT(dev)) {
> -		I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
> -		POSTING_READ(intel_hdmi->hdmi_reg);
> -	}
> -
>  	temp &= ~enable_bits;
>  
>  	I915_WRITE(intel_hdmi->hdmi_reg, temp);
> 

Testing wins.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 02/12] drm/i915: Remove the double register write from intel_disable_hdmi()

[Jesse Barnes]

On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> IBX can have problems with the first write to the port register getting
> masked when enabling the port. We are trying to apply the workaround
> also when disabling the port where it's not needed, and we also try
> to apply it for CPT/PPT as well which don't need it. Just kill it.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_hdmi.c | 8 --------
>  1 file changed, 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 72fce34..308015e 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1132,14 +1132,6 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
>  	I915_WRITE(intel_hdmi->hdmi_reg, temp);
>  	POSTING_READ(intel_hdmi->hdmi_reg);
>  
> -	/* HW workaround, need to write this twice for issue that may result
> -	 * in first write getting masked.
> -	 */
> -	if (HAS_PCH_SPLIT(dev)) {
> -		I915_WRITE(intel_hdmi->hdmi_reg, temp);
> -		POSTING_READ(intel_hdmi->hdmi_reg);
> -	}
> -
>  	if (IS_CHERRYVIEW(dev))
>  		chv_powergate_phy_lanes(encoder, 0xf);
>  
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 03/12] drm/i915: Clarfify the DP code platform checks

[Jesse Barnes]

On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> intel_dp.c is a mess with all the checks for different
> platform/PCH variants and ports. Try to clean it up by recognizing
> the following facts:
> - IVB port A, and CPT port B/C/D are always the special cases
> - VLV/CHV don't have port A
> - Using the same kind of logic everywhere makes things much easier to
>   parse
> 
> So let's move the IVB port A and PCH port B/C/D checks to be done first,
> and let the other cases fall through, and always check for these things
> using the same logic.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 46 ++++++++++++++++++++---------------------
>  1 file changed, 23 insertions(+), 23 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index e9426dd..0971a5d 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1561,7 +1561,7 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
>  
>  	/* Split out the IBX/CPU vs CPT settings */
>  
> -	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
> +	if (IS_GEN7(dev) && port == PORT_A) {
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
>  			intel_dp->DP |= DP_SYNC_HS_HIGH;
>  		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> @@ -1572,7 +1572,9 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
>  			intel_dp->DP |= DP_ENHANCED_FRAMING;
>  
>  		intel_dp->DP |= crtc->pipe << 29;
> -	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
> +	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
> +		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
> +	} else {
>  		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
>  			intel_dp->DP |= intel_dp->color_range;
>  
> @@ -1585,14 +1587,10 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
>  		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
>  			intel_dp->DP |= DP_ENHANCED_FRAMING;
>  
> -		if (!IS_CHERRYVIEW(dev)) {
> -			if (crtc->pipe == 1)
> -				intel_dp->DP |= DP_PIPEB_SELECT;
> -		} else {
> +		if (IS_CHERRYVIEW(dev))
>  			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
> -		}
> -	} else {
> -		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
> +		else if (crtc->pipe == PIPE_B)
> +			intel_dp->DP |= DP_PIPEB_SELECT;
>  	}
>  }
>  
> @@ -2176,13 +2174,9 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
>  	if (!(tmp & DP_PORT_EN))
>  		return false;
>  
> -	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
> +	if (IS_GEN7(dev) && port == PORT_A) {
>  		*pipe = PORT_TO_PIPE_CPT(tmp);
> -	} else if (IS_CHERRYVIEW(dev)) {
> -		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
> -	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
> -		*pipe = PORT_TO_PIPE(tmp);
> -	} else {
> +	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
>  		u32 trans_sel;
>  		u32 trans_dp;
>  		int i;
> @@ -2211,6 +2205,10 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
>  
>  		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
>  			      intel_dp->output_reg);
> +	} else if (IS_CHERRYVIEW(dev)) {
> +		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
> +	} else {
> +		*pipe = PORT_TO_PIPE(tmp);
>  	}
>  
>  	return true;
> @@ -2231,24 +2229,24 @@ static void intel_dp_get_config(struct intel_encoder *encoder,
>  	if (tmp & DP_AUDIO_OUTPUT_ENABLE)
>  		pipe_config->has_audio = true;
>  
> -	if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
> -		if (tmp & DP_SYNC_HS_HIGH)
> +	if (HAS_PCH_CPT(dev) && port != PORT_A) {
> +		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
> +		if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
>  			flags |= DRM_MODE_FLAG_PHSYNC;
>  		else
>  			flags |= DRM_MODE_FLAG_NHSYNC;
>  
> -		if (tmp & DP_SYNC_VS_HIGH)
> +		if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
>  			flags |= DRM_MODE_FLAG_PVSYNC;
>  		else
>  			flags |= DRM_MODE_FLAG_NVSYNC;
>  	} else {
> -		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
> -		if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
> +		if (tmp & DP_SYNC_HS_HIGH)
>  			flags |= DRM_MODE_FLAG_PHSYNC;
>  		else
>  			flags |= DRM_MODE_FLAG_NHSYNC;
>  
> -		if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
> +		if (tmp & DP_SYNC_VS_HIGH)
>  			flags |= DRM_MODE_FLAG_PVSYNC;
>  		else
>  			flags |= DRM_MODE_FLAG_NVSYNC;
> @@ -2415,7 +2413,8 @@ _intel_dp_set_link_train(struct intel_dp *intel_dp,
>  		}
>  		I915_WRITE(DP_TP_CTL(port), temp);
>  
> -	} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
> +	} else if ((IS_GEN7(dev) && port == PORT_A) ||
> +		   (HAS_PCH_CPT(dev) && port != PORT_A)) {
>  		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
>  
>  		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> @@ -3842,7 +3841,8 @@ intel_dp_link_down(struct intel_dp *intel_dp)
>  
>  	DRM_DEBUG_KMS("\n");
>  
> -	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
> +	if ((IS_GEN7(dev) && port == PORT_A) ||
> +	    (HAS_PCH_CPT(dev) && port != PORT_A)) {
>  		DP &= ~DP_LINK_TRAIN_MASK_CPT;
>  		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
>  	} else {
> 

Yeah a bit clearer.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 04/12] drm/i915: Clean up the CPT DP .get_hw_state() port readout

[Jesse Barnes]

On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Define a TRANS_DP_PIPE_TO_PORT() to make the CPT DP .get_hw_state()
> pipe readout neater.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>  drivers/gpu/drm/i915/intel_dp.c | 26 +++++---------------------
>  2 files changed, 6 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index dcd93b5..0538b24 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6410,6 +6410,7 @@ enum skl_disp_power_wells {
>  #define  TRANS_DP_PORT_SEL_D	(2<<29)
>  #define  TRANS_DP_PORT_SEL_NONE	(3<<29)
>  #define  TRANS_DP_PORT_SEL_MASK	(3<<29)
> +#define  TRANS_DP_PIPE_TO_PORT(val)	((((val) & TRANS_DP_PORT_SEL_MASK) >> 29) + PORT_B)
>  #define  TRANS_DP_AUDIO_ONLY	(1<<26)
>  #define  TRANS_DP_ENH_FRAMING	(1<<18)
>  #define  TRANS_DP_8BPC		(0<<9)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 0971a5d..dc89931 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2177,28 +2177,12 @@ static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
>  	if (IS_GEN7(dev) && port == PORT_A) {
>  		*pipe = PORT_TO_PIPE_CPT(tmp);
>  	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
> -		u32 trans_sel;
> -		u32 trans_dp;
> -		int i;
> -
> -		switch (intel_dp->output_reg) {
> -		case PCH_DP_B:
> -			trans_sel = TRANS_DP_PORT_SEL_B;
> -			break;
> -		case PCH_DP_C:
> -			trans_sel = TRANS_DP_PORT_SEL_C;
> -			break;
> -		case PCH_DP_D:
> -			trans_sel = TRANS_DP_PORT_SEL_D;
> -			break;
> -		default:
> -			return true;
> -		}
> +		enum pipe p;
>  
> -		for_each_pipe(dev_priv, i) {
> -			trans_dp = I915_READ(TRANS_DP_CTL(i));
> -			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
> -				*pipe = i;
> +		for_each_pipe(dev_priv, p) {
> +			u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
> +			if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
> +				*pipe = p;
>  				return true;
>  			}
>  		}
> 

Nice.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 05/12] drm/i915: Fix DP enhanced framing for CPT

[Jesse Barnes]

On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently we're always enabling enhanced framing on CPT even if the sink
> doesn't support it. Fix this up by actaully looking at what the sink
> tells us.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 3 +--
>  drivers/gpu/drm/i915/intel_dp.c      | 9 +++++++++
>  2 files changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a392188..a177f2e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4206,8 +4206,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc)
>  		temp &= ~(TRANS_DP_PORT_SEL_MASK |
>  			  TRANS_DP_SYNC_MASK |
>  			  TRANS_DP_BPC_MASK);
> -		temp |= (TRANS_DP_OUTPUT_ENABLE |
> -			 TRANS_DP_ENH_FRAMING);
> +		temp |= TRANS_DP_OUTPUT_ENABLE;
>  		temp |= bpc << 9; /* same format but at 11:9 */
>  
>  		if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dc89931..17b006c 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1573,7 +1573,16 @@ static void intel_dp_prepare(struct intel_encoder *encoder)
>  
>  		intel_dp->DP |= crtc->pipe << 29;
>  	} else if (HAS_PCH_CPT(dev) && port != PORT_A) {
> +		u32 trans_dp;
> +
>  		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
> +
> +		trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
> +		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
> +			trans_dp |= TRANS_DP_ENH_FRAMING;
> +		else
> +			trans_dp &= ~TRANS_DP_ENH_FRAMING;
> +		I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
>  	} else {
>  		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
>  			intel_dp->DP |= intel_dp->color_range;
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 07/12] drm/i915: Write the SDVO reg twice on IBX

[Jesse Barnes]

On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On IBX the SDVO/HDMI register write may be masked when enabling the
> port, so it may need to written twice. The HDMI code does this, but
> the SDVO code does not. Add the workaround to the SDVO code as well.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_sdvo.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index 0a06257..e3e9c98 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -243,6 +243,14 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
>  	if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
>  		I915_WRITE(intel_sdvo->sdvo_reg, val);
>  		POSTING_READ(intel_sdvo->sdvo_reg);
> +		/*
> +		 * HW workaround, need to write this twice for issue
> +		 * that may result in first write getting masked.
> +		 */
> +		if (HAS_PCH_IBX(dev)) {
> +			I915_WRITE(intel_sdvo->sdvo_reg, val);
> +			POSTING_READ(intel_sdvo->sdvo_reg);
> +		}
>  		return;
>  	}
>  
> 

This must be the missing fix to all our SDVO problems.  (One can hope.)

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 08/12] drm/i915: Fix the IBX transcoder B workarounds

[Jesse Barnes]

On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently the IBX transcoder B workarounds are not working correctly.
> Well, the HDMI one seems to be working somewhat, but the DP one is
> definitely busted.
> 
> After a bit of experimentation it looks like the best way to make this
> work is first disable the port on transcoder B, and then re-enable it
> transcoder A, and immediately disable it again.
> 
> We can also clean up the code by noting that we can't be called without
> a valid crtc. And also note that port A on ILK does not need the
> workaround, so let's check for that one too.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c   | 37 ++++++++++++++++-------------
>  drivers/gpu/drm/i915/intel_hdmi.c | 50 ++++++++++++++++++---------------------
>  drivers/gpu/drm/i915/intel_sdvo.c | 41 +++++++++++++-------------------
>  3 files changed, 60 insertions(+), 68 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 17b006c..3401cde 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3821,6 +3821,7 @@ static void
>  intel_dp_link_down(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
>  	enum port port = intel_dig_port->port;
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -3837,34 +3838,38 @@ intel_dp_link_down(struct intel_dp *intel_dp)
>  	if ((IS_GEN7(dev) && port == PORT_A) ||
>  	    (HAS_PCH_CPT(dev) && port != PORT_A)) {
>  		DP &= ~DP_LINK_TRAIN_MASK_CPT;
> -		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
> +		DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
>  	} else {
>  		if (IS_CHERRYVIEW(dev))
>  			DP &= ~DP_LINK_TRAIN_MASK_CHV;
>  		else
>  			DP &= ~DP_LINK_TRAIN_MASK;
> -		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
> +		DP |= DP_LINK_TRAIN_PAT_IDLE;
>  	}
> +	I915_WRITE(intel_dp->output_reg, DP);
>  	POSTING_READ(intel_dp->output_reg);
>  
> -	if (HAS_PCH_IBX(dev) &&
> -	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
> -		/* Hardware workaround: leaving our transcoder select
> -		 * set to transcoder B while it's off will prevent the
> -		 * corresponding HDMI output on transcoder A.
> -		 *
> -		 * Combine this with another hardware workaround:
> -		 * transcoder select bit can only be cleared while the
> -		 * port is enabled.
> -		 */
> -		DP &= ~DP_PIPEB_SELECT;
> +	DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
> +	I915_WRITE(intel_dp->output_reg, DP);
> +	POSTING_READ(intel_dp->output_reg);
> +
> +	/*
> +	 * HW workaround for IBX, we need to move the port
> +	 * to transcoder A after disabling it to allow the
> +	 * matching HDMI port to be enabled on transcoder A.
> +	 */
> +	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
> +		/* always enable with pattern 1 (as per spec) */
> +		DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
> +		DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
> +		I915_WRITE(intel_dp->output_reg, DP);
> +		POSTING_READ(intel_dp->output_reg);
> +
> +		DP &= ~DP_PORT_EN;
>  		I915_WRITE(intel_dp->output_reg, DP);
>  		POSTING_READ(intel_dp->output_reg);
>  	}
>  
> -	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
> -	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
> -	POSTING_READ(intel_dp->output_reg);
>  	msleep(intel_dp->panel_power_down_delay);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 308015e..9b9a69e 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1096,39 +1096,13 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
>  	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
>  	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
>  	u32 temp;
> -	u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
>  
>  	if (crtc->config->has_audio)
>  		intel_audio_codec_disable(encoder);
>  
>  	temp = I915_READ(intel_hdmi->hdmi_reg);
>  
> -	/* HW workaround for IBX, we need to move the port to transcoder A
> -	 * before disabling it. */
> -	if (HAS_PCH_IBX(dev)) {
> -		struct drm_crtc *crtc = encoder->base.crtc;
> -		int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
> -
> -		if (temp & SDVO_PIPE_B_SELECT) {
> -			temp &= ~SDVO_PIPE_B_SELECT;
> -			I915_WRITE(intel_hdmi->hdmi_reg, temp);
> -			POSTING_READ(intel_hdmi->hdmi_reg);
> -
> -			/* Again we need to write this twice. */
> -			I915_WRITE(intel_hdmi->hdmi_reg, temp);
> -			POSTING_READ(intel_hdmi->hdmi_reg);
> -
> -			/* Transcoder selection bits only update
> -			 * effectively on vblank. */
> -			if (crtc)
> -				intel_wait_for_vblank(dev, pipe);
> -			else
> -				msleep(50);
> -		}
> -	}
> -
> -	temp &= ~enable_bits;
> -
> +	temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
>  	I915_WRITE(intel_hdmi->hdmi_reg, temp);
>  	POSTING_READ(intel_hdmi->hdmi_reg);
>  
> @@ -1136,6 +1110,28 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
>  		chv_powergate_phy_lanes(encoder, 0xf);
>  
>  	intel_hdmi->set_infoframes(&encoder->base, false, NULL);
> +
> +	/*
> +	 * HW workaround for IBX, we need to move the port
> +	 * to transcoder A after disabling it to allow the
> +	 * matching DP port to be enabled on transcoder A.
> +	 */
> +	if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B) {
> +		temp &= ~SDVO_PIPE_B_SELECT;
> +		temp |= SDVO_ENABLE;
> +		/*
> +		 * HW workaround, need to write this twice for issue
> +		 * that may result in first write getting masked.
> +		 */
> +		I915_WRITE(intel_hdmi->hdmi_reg, temp);
> +		POSTING_READ(intel_hdmi->hdmi_reg);
> +		I915_WRITE(intel_hdmi->hdmi_reg, temp);
> +		POSTING_READ(intel_hdmi->hdmi_reg);
> +
> +		temp &= ~SDVO_ENABLE;
> +		I915_WRITE(intel_hdmi->hdmi_reg, temp);
> +		POSTING_READ(intel_hdmi->hdmi_reg);
> +	}
>  }
>  
>  static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index e3e9c98..4a87691 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -1437,6 +1437,7 @@ static void intel_disable_sdvo(struct intel_encoder *encoder)
>  {
>  	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
>  	struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
> +	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
>  	u32 temp;
>  
>  	intel_sdvo_set_active_outputs(intel_sdvo, 0);
> @@ -1445,32 +1446,22 @@ static void intel_disable_sdvo(struct intel_encoder *encoder)
>  						   DRM_MODE_DPMS_OFF);
>  
>  	temp = I915_READ(intel_sdvo->sdvo_reg);
> -	if ((temp & SDVO_ENABLE) != 0) {
> -		/* HW workaround for IBX, we need to move the port to
> -		 * transcoder A before disabling it. */
> -		if (HAS_PCH_IBX(encoder->base.dev)) {
> -			struct drm_crtc *crtc = encoder->base.crtc;
> -			int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
> -
> -			if (temp & SDVO_PIPE_B_SELECT) {
> -				temp &= ~SDVO_PIPE_B_SELECT;
> -				I915_WRITE(intel_sdvo->sdvo_reg, temp);
> -				POSTING_READ(intel_sdvo->sdvo_reg);
> -
> -				/* Again we need to write this twice. */
> -				I915_WRITE(intel_sdvo->sdvo_reg, temp);
> -				POSTING_READ(intel_sdvo->sdvo_reg);
> -
> -				/* Transcoder selection bits only update
> -				 * effectively on vblank. */
> -				if (crtc)
> -					intel_wait_for_vblank(encoder->base.dev, pipe);
> -				else
> -					msleep(50);
> -			}
> -		}
>  
> -		intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
> +	temp &= ~SDVO_ENABLE;
> +	intel_sdvo_write_sdvox(intel_sdvo, temp);
> +
> +	/*
> +	 * HW workaround for IBX, we need to move the port
> +	 * to transcoder A after disabling it to allow the
> +	 * matching DP port to be enabled on transcoder A.
> +	 */
> +	if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
> +		temp &= ~SDVO_PIPE_B_SELECT;
> +		temp |= SDVO_ENABLE;
> +		intel_sdvo_write_sdvox(intel_sdvo, temp);
> +
> +		temp &= ~SDVO_ENABLE;
> +		intel_sdvo_write_sdvox(intel_sdvo, temp);
>  	}
>  }
>  
> 

Cool, again, testing wins.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 09/12] drm/i915: Disable HDMI port after the pipe on PCH platforms

[Jesse Barnes]

On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> BSpec says we should disable all ports after the pipe on PCH
> platforms. Do so. Fixes a pipe off timeout on ILK now caused by
> the transcoder B workaround.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_hdmi.c | 33 +++++++++++++++++++++++++++++----
>  1 file changed, 29 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 9b9a69e..2ee19ca 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1097,9 +1097,6 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
>  	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
>  	u32 temp;
>  
> -	if (crtc->config->has_audio)
> -		intel_audio_codec_disable(encoder);
> -
>  	temp = I915_READ(intel_hdmi->hdmi_reg);
>  
>  	temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
> @@ -1134,6 +1131,29 @@ static void intel_disable_hdmi(struct intel_encoder *encoder)
>  	}
>  }
>  
> +static void g4x_disable_hdmi(struct intel_encoder *encoder)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> +
> +	if (crtc->config->has_audio)
> +		intel_audio_codec_disable(encoder);
> +
> +	intel_disable_hdmi(encoder);
> +}
> +
> +static void pch_disable_hdmi(struct intel_encoder *encoder)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
> +
> +	if (crtc->config->has_audio)
> +		intel_audio_codec_disable(encoder);
> +}
> +
> +static void pch_post_disable_hdmi(struct intel_encoder *encoder)
> +{
> +	intel_disable_hdmi(encoder);
> +}
> +
>  static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
>  {
>  	struct drm_device *dev = intel_hdmi_to_dev(hdmi);
> @@ -2020,7 +2040,12 @@ void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
>  			 DRM_MODE_ENCODER_TMDS);
>  
>  	intel_encoder->compute_config = intel_hdmi_compute_config;
> -	intel_encoder->disable = intel_disable_hdmi;
> +	if (HAS_PCH_SPLIT(dev)) {
> +		intel_encoder->disable = pch_disable_hdmi;
> +		intel_encoder->post_disable = pch_post_disable_hdmi;
> +	} else {
> +		intel_encoder->disable = g4x_disable_hdmi;
> +	}
>  	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
>  	intel_encoder->get_config = intel_hdmi_get_config;
>  	if (IS_CHERRYVIEW(dev)) {
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 10/12] drm/i915: Disable SDVO port after the pipe on PCH platforms

[Jesse Barnes]

On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_sdvo.c | 25 +++++++++++++++++--------
>  1 file changed, 17 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index 4a87691..d24ef75 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -1465,6 +1465,15 @@ static void intel_disable_sdvo(struct intel_encoder *encoder)
>  	}
>  }
>  
> +static void pch_disable_sdvo(struct intel_encoder *encoder)
> +{
> +}
> +
> +static void pch_post_disable_sdvo(struct intel_encoder *encoder)
> +{
> +	intel_disable_sdvo(encoder);
> +}
> +
>  static void intel_enable_sdvo(struct intel_encoder *encoder)
>  {
>  	struct drm_device *dev = encoder->base.dev;
> @@ -1477,14 +1486,9 @@ static void intel_enable_sdvo(struct intel_encoder *encoder)
>  	bool success;
>  
>  	temp = I915_READ(intel_sdvo->sdvo_reg);
> -	if ((temp & SDVO_ENABLE) == 0) {
> -		/* HW workaround for IBX, we need to move the port
> -		 * to transcoder A before disabling it, so restore it here. */
> -		if (HAS_PCH_IBX(dev))
> -			temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
> +	temp |= SDVO_ENABLE;
> +	intel_sdvo_write_sdvox(intel_sdvo, temp);
>  
> -		intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
> -	}
>  	for (i = 0; i < 2; i++)
>  		intel_wait_for_vblank(dev, intel_crtc->pipe);
>  
> @@ -2987,7 +2991,12 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
>  	}
>  
>  	intel_encoder->compute_config = intel_sdvo_compute_config;
> -	intel_encoder->disable = intel_disable_sdvo;
> +	if (HAS_PCH_SPLIT(dev)) {
> +		intel_encoder->disable = pch_disable_sdvo;
> +		intel_encoder->post_disable = pch_post_disable_sdvo;
> +	} else {
> +		intel_encoder->disable = intel_disable_sdvo;
> +	}
>  	intel_encoder->pre_enable = intel_sdvo_pre_enable;
>  	intel_encoder->enable = intel_enable_sdvo;
>  	intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
> 

Commit should probably have something about the hw workaround block
being superceded (assuming that block was intentional in this patch),
but either way:

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 11/12] drm/i915: Disable CRT port after pipe on PCH platforms

[Jesse Barnes]

On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Follow the BSpec sequence for the CRT port as well on PCH platforms,
> ie. disable the pipe before the port.
> 
> Didn't bother looking at DDI in detail yet, so leave that one be even
> though the CRT is a PCH port there.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_crt.c | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 93bb515..521af2c 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -207,6 +207,14 @@ static void intel_disable_crt(struct intel_encoder *encoder)
>  	intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF);
>  }
>  
> +static void pch_disable_crt(struct intel_encoder *encoder)
> +{
> +}
> +
> +static void pch_post_disable_crt(struct intel_encoder *encoder)
> +{
> +	intel_disable_crt(encoder);
> +}
>  
>  static void hsw_crt_post_disable(struct intel_encoder *encoder)
>  {
> @@ -888,7 +896,12 @@ void intel_crt_init(struct drm_device *dev)
>  		crt->adpa_reg = ADPA;
>  
>  	crt->base.compute_config = intel_crt_compute_config;
> -	crt->base.disable = intel_disable_crt;
> +	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) {
> +		crt->base.disable = pch_disable_crt;
> +		crt->base.post_disable = pch_post_disable_crt;
> +	} else {
> +		crt->base.disable = intel_disable_crt;
> +	}
>  	crt->base.enable = intel_enable_crt;
>  	if (I915_HAS_HOTPLUG(dev))
>  		crt->base.hpd_pin = HPD_CRT;
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 12/12] drm/i915: Disable FDI RX/TX before the ports

[Jesse Barnes]

On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Bspec says we should disable the FDI RX/TX before disabling the PCH
> ports. Do so.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a177f2e..fbcf26d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5096,13 +5096,14 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
>  
>  	ironlake_pfit_disable(intel_crtc);
>  
> +	if (intel_crtc->config->has_pch_encoder)
> +		ironlake_fdi_disable(crtc);
> +
>  	for_each_encoder_on_crtc(dev, crtc, encoder)
>  		if (encoder->post_disable)
>  			encoder->post_disable(encoder);
>  
>  	if (intel_crtc->config->has_pch_encoder) {
> -		ironlake_fdi_disable(crtc);
> -
>  		ironlake_disable_pch_transcoder(dev_priv, pipe);
>  
>  		if (HAS_PCH_CPT(dev)) {
> 

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
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Re: [PATCH 10/12] drm/i915: Disable SDVO port after the pipe on PCH platforms

[Daniel Vetter]

On Thu, May 21, 2015 at 12:26:21PM -0700, Jesse Barnes wrote:
> On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_sdvo.c | 25 +++++++++++++++++--------
> >  1 file changed, 17 insertions(+), 8 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> > index 4a87691..d24ef75 100644
> > --- a/drivers/gpu/drm/i915/intel_sdvo.c
> > +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> > @@ -1465,6 +1465,15 @@ static void intel_disable_sdvo(struct intel_encoder *encoder)
> >  	}
> >  }
> >  
> > +static void pch_disable_sdvo(struct intel_encoder *encoder)
> > +{
> > +}
> > +
> > +static void pch_post_disable_sdvo(struct intel_encoder *encoder)
> > +{
> > +	intel_disable_sdvo(encoder);
> > +}
> > +
> >  static void intel_enable_sdvo(struct intel_encoder *encoder)
> >  {
> >  	struct drm_device *dev = encoder->base.dev;
> > @@ -1477,14 +1486,9 @@ static void intel_enable_sdvo(struct intel_encoder *encoder)
> >  	bool success;
> >  
> >  	temp = I915_READ(intel_sdvo->sdvo_reg);
> > -	if ((temp & SDVO_ENABLE) == 0) {
> > -		/* HW workaround for IBX, we need to move the port
> > -		 * to transcoder A before disabling it, so restore it here. */
> > -		if (HAS_PCH_IBX(dev))
> > -			temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
> > +	temp |= SDVO_ENABLE;
> > +	intel_sdvo_write_sdvox(intel_sdvo, temp);
> >  
> > -		intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
> > -	}
> >  	for (i = 0; i < 2; i++)
> >  		intel_wait_for_vblank(dev, intel_crtc->pipe);
> >  
> > @@ -2987,7 +2991,12 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
> >  	}
> >  
> >  	intel_encoder->compute_config = intel_sdvo_compute_config;
> > -	intel_encoder->disable = intel_disable_sdvo;
> > +	if (HAS_PCH_SPLIT(dev)) {
> > +		intel_encoder->disable = pch_disable_sdvo;
> > +		intel_encoder->post_disable = pch_post_disable_sdvo;
> > +	} else {
> > +		intel_encoder->disable = intel_disable_sdvo;
> > +	}
> >  	intel_encoder->pre_enable = intel_sdvo_pre_enable;
> >  	intel_encoder->enable = intel_enable_sdvo;
> >  	intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
> > 
> 
> Commit should probably have something about the hw workaround block
> being superceded (assuming that block was intentional in this patch),
> but either way:

I added a small note and merged all the patches. Some minor conflicts
because the 12bpc fixes haven't landed yet since they lack review ...
hint, hint ;-)

> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Thanks for patches&review, Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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