From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> To: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>, Paul Burton <paul.burton@imgtec.com> Cc: <linux-mips@linux-mips.org>, <benh@kernel.crashing.org>, <will.deacon@arm.com>, <linux-kernel@vger.kernel.org>, <ralf@linux-mips.org>, <markos.chandras@imgtec.com>, <macro@linux-mips.org>, <Steven.Hill@imgtec.com>, <alexander.h.duyck@redhat.com>, <davem@davemloft.net> Subject: Re: [PATCH 1/3] MIPS: R6: Use lightweight SYNC instruction in smp_* memory barriers Date: Tue, 2 Jun 2015 11:20:56 -0700 [thread overview] Message-ID: <556DF408.2040003@imgtec.com> (raw) In-Reply-To: <20150602121227.GA1474@macpro.local> On 06/02/2015 05:12 AM, Luc Van Oostenryck wrote: > On Tue, Jun 02, 2015 at 11:08:35AM +0100, Paul Burton wrote: > >> I think this would read better as something like: >> >> If a processor does not implement the lightweight sync operations then >> the architecture requires that they interpret the corresponding sync >> instructions as the typical heavyweight "sync 0". Therefore this >> should be safe to enable on all CPUs implementing release 2 or >> later of the MIPS architecture. >> > Is it really the case for release 2? > > I'm asking because recently I needed to do something similar and I couldn't > find this garantee in the revision 2.00 of the manual. Yes. MD00086/MD00084/MD00087 Rev 2.60 are technically MIPS R2. And this revision explicitly lists optional codes and it has a clear statement: > Implementations that do not use any of the non-zero values of stype to > define different barriers, such as ordering bar- > riers, must make those stype values act the same as stype zero. (don't blame me that Rev 2.60 is 5 years after initial 2.00, it is still MIPS R2). - Leonid.
WARNING: multiple messages have this Message-ID (diff)
From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> To: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>, Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org, benh@kernel.crashing.org, will.deacon@arm.com, linux-kernel@vger.kernel.org, ralf@linux-mips.org, markos.chandras@imgtec.com, macro@linux-mips.org, Steven.Hill@imgtec.com, alexander.h.duyck@redhat.com, davem@davemloft.net Subject: Re: [PATCH 1/3] MIPS: R6: Use lightweight SYNC instruction in smp_* memory barriers Date: Tue, 2 Jun 2015 11:20:56 -0700 [thread overview] Message-ID: <556DF408.2040003@imgtec.com> (raw) Message-ID: <20150602182056.ldvMbsIcszjJEFjKje_GwHv5BOJKEIx13JfrHlyAU8I@z> (raw) In-Reply-To: <20150602121227.GA1474@macpro.local> On 06/02/2015 05:12 AM, Luc Van Oostenryck wrote: > On Tue, Jun 02, 2015 at 11:08:35AM +0100, Paul Burton wrote: > >> I think this would read better as something like: >> >> If a processor does not implement the lightweight sync operations then >> the architecture requires that they interpret the corresponding sync >> instructions as the typical heavyweight "sync 0". Therefore this >> should be safe to enable on all CPUs implementing release 2 or >> later of the MIPS architecture. >> > Is it really the case for release 2? > > I'm asking because recently I needed to do something similar and I couldn't > find this garantee in the revision 2.00 of the manual. Yes. MD00086/MD00084/MD00087 Rev 2.60 are technically MIPS R2. And this revision explicitly lists optional codes and it has a clear statement: > Implementations that do not use any of the non-zero values of stype to > define different barriers, such as ordering bar- > riers, must make those stype values act the same as stype zero. (don't blame me that Rev 2.60 is 5 years after initial 2.00, it is still MIPS R2). - Leonid.
next prev parent reply other threads:[~2015-06-02 18:21 UTC|newest] Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-06-02 0:09 [PATCH 0/3] MIPS: SMP memory barriers: lightweight sync, acquire-release Leonid Yegoshin 2015-06-02 0:09 ` Leonid Yegoshin 2015-06-02 0:09 ` [PATCH 1/3] MIPS: R6: Use lightweight SYNC instruction in smp_* memory barriers Leonid Yegoshin 2015-06-02 0:09 ` Leonid Yegoshin 2015-06-02 10:08 ` Paul Burton 2015-06-02 10:08 ` Paul Burton 2015-06-02 12:12 ` Luc Van Oostenryck 2015-06-02 12:44 ` Ralf Baechle 2015-06-02 18:20 ` Leonid Yegoshin [this message] 2015-06-02 18:20 ` Leonid Yegoshin 2015-06-02 10:48 ` James Hogan 2015-06-02 10:48 ` James Hogan 2015-06-02 16:15 ` Maciej W. Rozycki 2015-06-02 23:56 ` David Daney 2015-06-03 1:56 ` Leonid Yegoshin 2015-06-03 1:56 ` Leonid Yegoshin 2015-06-05 13:10 ` Ralf Baechle 2015-06-05 21:18 ` Maciej W. Rozycki 2016-01-28 2:28 ` Joshua Kinard 2016-01-29 13:32 ` Maciej W. Rozycki 2016-01-29 13:32 ` Maciej W. Rozycki 2016-01-30 16:25 ` Joshua Kinard 2015-06-02 0:09 ` [PATCH 2/3] MIPS: enforce LL-SC loop enclosing with SYNC (ACQUIRE and RELEASE) Leonid Yegoshin 2015-06-02 0:09 ` Leonid Yegoshin 2015-06-02 11:39 ` James Hogan 2015-06-02 11:39 ` James Hogan 2015-06-02 18:43 ` Leonid Yegoshin 2015-06-02 18:43 ` Leonid Yegoshin 2015-06-02 18:53 ` Leonid Yegoshin 2015-06-02 0:09 ` [PATCH 3/3] MIPS: bugfix - replace smp_mb with release barrier function in unlocks Leonid Yegoshin 2015-06-02 0:09 ` Leonid Yegoshin 2015-06-02 11:42 ` James Hogan 2015-06-02 11:42 ` James Hogan 2015-06-02 13:22 ` Ralf Baechle 2015-06-02 8:41 ` [PATCH 0/3] MIPS: SMP memory barriers: lightweight sync, acquire-release Joshua Kinard 2015-06-02 9:59 ` Ralf Baechle 2015-06-02 18:59 ` Joshua Kinard 2015-06-02 19:19 ` Ralf Baechle
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