[RFC 0/6] drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs

[RFC 0/6] drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs

[Gwan-gyeong Mun]

On Gen 11 platform, to enable resolutions like 5K@120 (or higher) we need
to use DSC (DP 1.4) or YCbCr4:2:0 (DP 1.3 or 1.4) on DP.
In order to support YCbCr4:2:0 on DP we need to program YCBCR 4:2:0
to MSA and VSC SDP.

This patches are RFC patches that add a VSC structure for handling
Pixel Encoding/Colorimetry Formats and program YCBCR 4:2:0 to MSA and VSC SDP.

This is currently not tested, but I wanted to get some inputs on this approach.
The idea of a scaling (RGB -> YCbCr4:4:4 -> YCbCr 4:2:0) is to follow the
same approach used in YCbCr 4:2:0 on HDMI.

Gwan-gyeong Mun (6):
  drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11
  drm/i915/dp: Add a config function for YCBCR420 outputs
  drm: Add a VSC structure for handling Pixel Encoding/Colorimetry
    Formats
  drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry
    Format
  drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
  drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs

 drivers/gpu/drm/i915/i915_reg.h  |   1 +
 drivers/gpu/drm/i915/intel_ddi.c |  16 +++-
 drivers/gpu/drm/i915/intel_dp.c  | 147 +++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/intel_drv.h |   2 +
 include/drm/drm_dp_helper.h      |  17 ++++
 5 files changed, 176 insertions(+), 7 deletions(-)

-- 
2.20.1

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[RFC 1/6] drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11

[Gwan-gyeong Mun]

Bspec describes that GEN10 only supports capability of YUV 4:2:0 output to
HDMI port and GEN11 supports capability of YUV 4:2:0 output to both DP and
HDMI ports.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 681e88405ada..ad7382d3be86 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -6923,6 +6923,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
 		connector->interlace_allowed = true;
 	connector->doublescan_allowed = 0;
 
+	 if (INTEL_GEN(dev_priv) >= 11)
+		connector->ycbcr_420_allowed = true;
+
 	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
 
 	intel_dp_aux_init(intel_dp);
-- 
2.20.1

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[RFC 2/6] drm/i915/dp: Add a config function for YCBCR420 outputs

[Gwan-gyeong Mun]

This patch checks a support of YCBCR420 outputs on an encoder level.
If the input mode is YCBCR420-only mode then it prepares DP as an YCBCR420
output, else it continues with RGB output mode.
It set output_format to INTEL_OUTPUT_FORMAT_YCBCR420 in order to using
a pipe scaler as RGB to YCbCr 4:4:4.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index ad7382d3be86..a61aff23c8b2 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2098,6 +2098,31 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	return 0;
 }
 
+static bool
+intel_dp_ycbcr420_config(struct drm_connector *connector,
+			 struct intel_crtc_state *config)
+{
+	struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
+
+	if (!connector->ycbcr_420_allowed) {
+		DRM_ERROR("Platform doesn't support YCBCR420 output\n");
+		return false;
+	}
+
+	config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+
+	/* YCBCR 420 output conversion needs a scaler */
+	if (skl_update_scaler_crtc(config)) {
+		DRM_DEBUG_KMS("Scaler allocation for output failed\n");
+		return false;
+	}
+
+	intel_pch_panel_fitting(intel_crtc, config,
+				DRM_MODE_SCALE_FULLSCREEN);
+
+	return true;
+}
+
 int
 intel_dp_compute_config(struct intel_encoder *encoder,
 			struct intel_crtc_state *pipe_config,
@@ -2115,6 +2140,7 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	bool constant_n = drm_dp_has_quirk(&intel_dp->desc,
 					   DP_DPCD_QUIRK_CONSTANT_N);
 	int ret;
+	struct drm_connector *connector = conn_state->connector;
 
 	if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
 		pipe_config->has_pch_encoder = true;
@@ -2123,6 +2149,13 @@ intel_dp_compute_config(struct intel_encoder *encoder,
 	if (lspcon->active)
 		lspcon_ycbcr420_config(&intel_connector->base, pipe_config);
 
+	if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
+		if (!intel_dp_ycbcr420_config(connector, pipe_config)) {
+			DRM_ERROR("Can't support YCBCR420 output\n");
+			return false;
+		}
+	}
+
 	pipe_config->has_drrs = false;
 	if (IS_G4X(dev_priv) || port == PORT_A)
 		pipe_config->has_audio = false;
-- 
2.20.1

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[RFC 3/6] drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats

[Gwan-gyeong Mun]

SDP VSC Header and Data Block follow DP 1.4a spec, section 2.2.5.7.5,
chapter "VSC SDP Payload for Pixel Encoding/Colorimetry Format".

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 include/drm/drm_dp_helper.h | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 5db7fb8c8b50..6091d29757af 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1076,6 +1076,23 @@ struct edp_vsc_psr {
 	u8 DB8_31[24]; /* Reserved */
 } __packed;
 
+struct dp_vsc_sdp {
+	struct dp_sdp_header sdp_header;
+	u8 DB0; /* Stereo Interface */
+	u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */
+	u8 DB2; /* CRC value bits 7:0 of the R or Cr component */
+	u8 DB3; /* CRC value bits 15:8 of the R or Cr component */
+	u8 DB4; /* CRC value bits 7:0 of the G or Y component */
+	u8 DB5; /* CRC value bits 15:8 of the G or Y component */
+	u8 DB6; /* CRC value bits 7:0 of the B or Cb component */
+	u8 DB7; /* CRC value bits 15:8 of the B or Cb component */
+	u8 DB8_15[8];  /* Reserved */
+	u8 DB16; /* Pixel Encoding and Colorimetry Formats */
+	u8 DB17; /* Dynamic Range and Component Bit Depth */
+	u8 DB18; /* Content Type */
+	u8 DB19_31[13]; /* Reserved */
+} __packed;
+
 #define EDP_VSC_PSR_STATE_ACTIVE	(1<<0)
 #define EDP_VSC_PSR_UPDATE_RFB		(1<<1)
 #define EDP_VSC_PSR_CRC_VALUES_VALID	(1<<2)
-- 
2.20.1

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[RFC 4/6] drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format

[Gwan-gyeong Mun]

Function intel_pixel_encoding_setup_vsc handles vsc header and data block
setup for pixel encoding / colorimetry format.

Setup VSC header and data block in function intel_pixel_encoding_setup_vsc
for pixel encoding / colorimetry format as per dp 1.4a spec,
section 2.2.5.7.1, table 2-119: VSC SDP Header Bytes, section 2.2.5.7.5,
table 2-120:VSC SDP Payload for DB16 through DB18.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |  1 +
 drivers/gpu/drm/i915/intel_dp.c  | 72 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h |  2 +
 3 files changed, 75 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ca705546a0ab..8969f03393b8 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3400,6 +3400,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
 
 	intel_edp_backlight_on(crtc_state, conn_state);
 	intel_psr_enable(intel_dp, crtc_state);
+	intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	if (crtc_state->has_audio)
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a61aff23c8b2..3a9a5a3c33a9 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -4402,6 +4402,78 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 	return 0;
 }
 
+static void
+intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state)
+{
+	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+	struct dp_vsc_sdp vsc_sdp;
+
+	if (!intel_dp->attached_connector->base.ycbcr_420_allowed)  return;
+
+	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
+	memset(&vsc_sdp, 0, sizeof(vsc_sdp));
+	vsc_sdp.sdp_header.HB0 = 0;
+	vsc_sdp.sdp_header.HB1 = 0x7;
+
+	/* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
+	 * Colorimetry Format indication. A DP Source device is allowed
+	 * to indicate the pixel encoding/colorimetry format to the DP Sink
+	 * device with VSC SDP only when the DP Sink device supports it
+	 * (i.e., VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the register
+	 * DPRX_FEATURE_ENUMERATION_LIST (DPCD Address 02210h, bit 3) is set to 1)
+	 */
+	vsc_sdp.sdp_header.HB2 = 0x5;
+
+	/* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
+	 * Colorimetry Format indication (HB2 = 05h).
+	 */
+	vsc_sdp.sdp_header.HB3 = 0x13;
+	/* YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
+	 * DB16[3:0] DP 1.4a spec, Table 2-120
+	 */
+
+	/* https://patchwork.freedesktop.org/patch/166830/ i915 implementations
+	 * uses BT.709 color space
+	 */
+	vsc_sdp.DB16 = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
+	vsc_sdp.DB16 |= 0x1; /* 0x1, ITU-R BT.709 */
+
+	/* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
+	 * the following Component Bit Depth values are defined:
+	 * 001b = 8bpc.
+	 * 010b = 10bpc.
+	 * 011b = 12bpc.
+	 * 100b = 16bpc.
+	 */
+	vsc_sdp.DB17 = 0x1;
+
+	/*
+	 * Content Type (Bits 2:0)
+	 * 000b = Not defined.
+	 * 001b = Graphics.
+	 * 010b = Photo.
+	 * 011b = Video.
+	 * 100b = Game
+	 * All other values are RESERVED.
+	 * Note: See CTA-861-G for the definition and expected
+	 * processing by a stream sink for the above contect types.
+	 */
+	vsc_sdp.DB18 = 0;
+
+	intel_dig_port->write_infoframe(&intel_dig_port->base,
+			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
+}
+
+void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420)
+		return;
+
+	intel_pixel_encoding_setup_vsc(intel_dp, crtc_state);
+}
+
 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
 {
 	int status = 0;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 90ba5436370e..bc01a69e8a2a 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1868,6 +1868,8 @@ u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count,
 				int mode_clock, int mode_hdisplay);
 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock,
 				int mode_hdisplay);
+void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp,
+			       const struct intel_crtc_state *crtc_state);
 
 /* intel_vdsc.c */
 int intel_dp_compute_dsc_params(struct intel_dp *intel_dp,
-- 
2.20.1

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[RFC 5/6] drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA

[Gwan-gyeong Mun]

When YCBCR 4:2:0 outputs is used for DP, we should program YCBCR 4:2:0 to
MSA and VSC SDP.

As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication of Color
Encoding Format and Content Color Gamut] while sending YCBCR 420 signals
we should program MSA MISC1 fields which indicate VSC SDP for the Pixel
Encoding/Colorimetry Format.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 1 +
 drivers/gpu/drm/i915/intel_ddi.c | 8 ++++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a64deeb4e517..1045ca41b188 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9425,6 +9425,7 @@ enum skl_power_gate {
 #define  TRANS_MSA_12_BPC		(3 << 5)
 #define  TRANS_MSA_16_BPC		(4 << 5)
 #define  TRANS_MSA_CEA_RANGE		(1 << 3)
+#define  TRANS_MSA_USE_VSC_SDP		(1 << 13)
 
 /* LCPLL Control */
 #define LCPLL_CTL			_MMIO(0x130040)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 8969f03393b8..c6aed2b06a59 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1732,6 +1732,14 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
 	 */
 	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 		temp |= TRANS_MSA_SAMPLING_444 | TRANS_MSA_CLRSP_YCBCR;
+	/*
+	 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
+	 * of Color Encoding Format and Content Color Gamut] while sending
+	 * YCBCR 420 signals we should program MSA MISC1 fields which
+	 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
+	*/
+	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		temp |= TRANS_MSA_USE_VSC_SDP;
 	I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
 }
 
-- 
2.20.1

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[RFC 6/6] drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs

[Gwan-gyeong Mun]

pipe_bpp value was assumed RGB therefore it was multiplied with 3.
But YCbCr 4:2:0 requires multiplier value to 1.5 therefore it divides
pipe_bpp to 2.
 - RGB bpp = bpc x 3
 - YCbCr 4:2:0 bpp = bpc x 1.5

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |  7 +++++-
 drivers/gpu/drm/i915/intel_dp.c  | 41 ++++++++++++++++++++++++++------
 2 files changed, 40 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index c6aed2b06a59..7f56aa7842c1 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1696,6 +1696,7 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 temp;
+	int bpp;
 
 	if (!intel_crtc_has_dp_encoder(crtc_state))
 		return;
@@ -1707,7 +1708,11 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
 	if (crtc_state->limited_color_range)
 		temp |= TRANS_MSA_CEA_RANGE;
 
-	switch (crtc_state->pipe_bpp) {
+	bpp = crtc_state->pipe_bpp;
+	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
+		bpp *= 2;
+
+	switch (bpp) {
 	case 18:
 		temp |= TRANS_MSA_6_BPC;
 		break;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3a9a5a3c33a9..734c5743e03f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1761,12 +1761,13 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 	struct intel_connector *intel_connector = intel_dp->attached_connector;
 	int bpp, bpc;
+	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
 
 	bpp = pipe_config->pipe_bpp;
 	bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
 
 	if (bpc > 0)
-		bpp = min(bpp, 3*bpc);
+		bpp = min(bpp, 3*bpc/bpp_divider);
 
 	if (intel_dp_is_edp(intel_dp)) {
 		/* Get bpp from vbt only for panels that dont have bpp in edid */
@@ -1787,12 +1788,14 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
 				  struct intel_crtc_state *pipe_config,
 				  struct link_config_limits *limits)
 {
+	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
+
 	/* For DP Compliance we override the computed bpp for the pipe */
 	if (intel_dp->compliance.test_data.bpc != 0) {
-		int bpp = 3 * intel_dp->compliance.test_data.bpc;
+		int bpp = 3 * intel_dp->compliance.test_data.bpc / bpp_divider;
 
 		limits->min_bpp = limits->max_bpp = bpp;
-		pipe_config->dither_force_disable = bpp == 6 * 3;
+		pipe_config->dither_force_disable = bpp == 6 * 3 / bpp_divider;
 
 		DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
 	}
@@ -1826,8 +1829,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	int bpp, clock, lane_count;
 	int mode_rate, link_clock, link_avail;
+	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
 
-	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
+	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3 / bpp_divider) {
 		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 						   bpp);
 
@@ -1862,8 +1866,9 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
 	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 	int bpp, clock, lane_count;
 	int mode_rate, link_clock, link_avail;
+	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
 
-	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
+	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3 / bpp_divider) {
 		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
 						   bpp);
 
@@ -2009,6 +2014,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	struct link_config_limits limits;
 	int common_len;
 	int ret;
+	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
 
 	common_len = intel_dp_common_len_rate_limit(intel_dp,
 						    intel_dp->max_link_rate);
@@ -2022,7 +2028,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
 	limits.min_lane_count = 1;
 	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
 
-	limits.min_bpp = 6 * 3;
+	limits.min_bpp = 6 * 3 / bpp_divider;
 	limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
 
 	if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
@@ -2110,6 +2116,11 @@ intel_dp_ycbcr420_config(struct drm_connector *connector,
 	}
 
 	config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
+	/* pipe_bpp value was assumed RGB therefore it was multiplied
+	 * with 3. But YCbCr 4:2:0 requires multiplier value to 1.5
+	 * therefore it divides pipe_bpp to 2.
+	 */
+	config->pipe_bpp /= 2;
 
 	/* YCBCR 420 output conversion needs a scaler */
 	if (skl_update_scaler_crtc(config)) {
@@ -4446,7 +4457,23 @@ intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
 	 * 011b = 12bpc.
 	 * 100b = 16bpc.
 	 */
-	vsc_sdp.DB17 = 0x1;
+	switch (crtc_state->pipe_bpp) {
+	case 12: /* 8bpc */
+		vsc_sdp.DB17 = 0x1;
+		break;
+	case 15: /* 10bpc */
+		vsc_sdp.DB17 = 0x2;
+		break;
+	case 18: /* 12bpc */
+		vsc_sdp.DB17 = 0x3;
+		break;
+	case 24: /* 16bpc */
+		vsc_sdp.DB17 = 0x4;
+		break;
+	default:
+		DRM_DEBUG_KMS("Invalid bpp value '%d'\n", crtc_state->pipe_bpp);
+		break;
+	}
 
 	/*
 	 * Content Type (Bits 2:0)
-- 
2.20.1

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✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs
URL   : https://patchwork.freedesktop.org/series/56059/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
646f25f459f0 drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11
-:20: WARNING:TABSTOP: Statements should start on a tabstop
#20: FILE: drivers/gpu/drm/i915/intel_dp.c:6926:
+	 if (INTEL_GEN(dev_priv) >= 11)

total: 0 errors, 1 warnings, 0 checks, 9 lines checked
485e788bfeee drm/i915/dp: Add a config function for YCBCR420 outputs
bfebbc7e2acb drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats
2b312268f5ba drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format
-:44: ERROR:TRAILING_STATEMENTS: trailing statements should be on next line
#44: FILE: drivers/gpu/drm/i915/intel_dp.c:4412:
+	if (!intel_dp->attached_connector->base.ycbcr_420_allowed)  return;

total: 1 errors, 0 warnings, 0 checks, 93 lines checked
317c3a0c98c6 drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
-:41: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
#41: FILE: drivers/gpu/drm/i915/intel_ddi.c:1740:
+	 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
+	*/

total: 0 errors, 1 warnings, 0 checks, 21 lines checked
49b8aff26fa2 drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs
-:54: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#54: FILE: drivers/gpu/drm/i915/intel_dp.c:1770:
+		bpp = min(bpp, 3*bpc/bpp_divider);
 		                ^

-:54: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
#54: FILE: drivers/gpu/drm/i915/intel_dp.c:1770:
+		bpp = min(bpp, 3*bpc/bpp_divider);
 		                    ^

total: 0 errors, 0 warnings, 2 checks, 119 lines checked

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✗ Fi.CI.SPARSE: warning for drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs
URL   : https://patchwork.freedesktop.org/series/56059/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11
Okay!

Commit: drm/i915/dp: Add a config function for YCBCR420 outputs
Okay!

Commit: drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats
Okay!

Commit: drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format
Okay!

Commit: drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
Okay!

Commit: drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs
-O:drivers/gpu/drm/i915/intel_dp.c:1769:23: warning: expression using sizeof(void)
-O:drivers/gpu/drm/i915/intel_dp.c:1769:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1770:23: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_dp.c:1770:23: warning: expression using sizeof(void)

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✓ Fi.CI.BAT: success for drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs
URL   : https://patchwork.freedesktop.org/series/56059/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5520 -> Patchwork_12111
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/56059/revisions/1/mbox/

Known issues
------------

  Here are the changes found in Patchwork_12111 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-blb-e6850:       PASS -> INCOMPLETE [fdo#107718]

  * igt@kms_busy@basic-flip-a:
    - fi-gdg-551:         PASS -> FAIL [fdo#103182]

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
    - fi-byt-clapper:     PASS -> FAIL [fdo#103191] / [fdo#107362]

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271


Participating hosts (51 -> 45)
------------------------------

  Additional (1): fi-glk-j4005 
  Missing    (7): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus 


Build changes
-------------

    * Linux: CI_DRM_5520 -> Patchwork_12111

  CI_DRM_5520: 91343140b5792a21430708ad761feaf17b8ae1a7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12111: 49b8aff26fa20cf63e93cb18f5a8d473e6a31cc6 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

49b8aff26fa2 drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs
317c3a0c98c6 drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
2b312268f5ba drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format
bfebbc7e2acb drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats
485e788bfeee drm/i915/dp: Add a config function for YCBCR420 outputs
646f25f459f0 drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12111/
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✓ Fi.CI.IGT: success for drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs

[Patchwork]

== Series Details ==

Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs
URL   : https://patchwork.freedesktop.org/series/56059/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_5520_full -> Patchwork_12111_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_12111_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_busy@basic-modeset-a:
    - shard-glk:          NOTRUN -> FAIL [fdo#109490]

  * igt@kms_busy@extended-pageflip-hang-newfb-render-c:
    - shard-apl:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
    - shard-hsw:          PASS -> DMESG-WARN [fdo#107956]

  * igt@kms_cursor_crc@cursor-256x256-sliding:
    - shard-glk:          PASS -> FAIL [fdo#103232]

  * igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
    - shard-glk:          NOTRUN -> FAIL [fdo#105454] / [fdo#106509]

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-glk:          PASS -> FAIL [fdo#105363]

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-glk:          PASS -> FAIL [fdo#102887] / [fdo#105363]

  * igt@kms_plane@plane-position-covered-pipe-a-planes:
    - shard-glk:          PASS -> FAIL [fdo#103166] +1

  * igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
    - shard-apl:          PASS -> FAIL [fdo#103166]

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@hang:
    - shard-glk:          FAIL [fdo#109469] -> PASS

  * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-a:
    - shard-snb:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_busy@extended-pageflip-hang-newfb-render-a:
    - shard-apl:          DMESG-WARN [fdo#107956] -> PASS

  * igt@kms_cursor_crc@cursor-256x256-onscreen:
    - shard-apl:          FAIL [fdo#103232] -> PASS

  * igt@kms_plane@plane-position-covered-pipe-b-planes:
    - shard-apl:          FAIL [fdo#103166] -> PASS

  * igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
    - shard-glk:          FAIL [fdo#103166] -> PASS

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105454]: https://bugs.freedesktop.org/show_bug.cgi?id=105454
  [fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
  [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109469]: https://bugs.freedesktop.org/show_bug.cgi?id=109469
  [fdo#109490]: https://bugs.freedesktop.org/show_bug.cgi?id=109490


Participating hosts (6 -> 4)
------------------------------

  Missing    (2): shard-skl shard-iclb 


Build changes
-------------

    * Linux: CI_DRM_5520 -> Patchwork_12111

  CI_DRM_5520: 91343140b5792a21430708ad761feaf17b8ae1a7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4802: 4049adf01014af077df2174def4fadf7cecb066e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_12111: 49b8aff26fa20cf63e93cb18f5a8d473e6a31cc6 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12111/
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Re: [RFC 1/6] drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11

[Maarten Lankhorst]

Op 31-01-2019 om 22:10 schreef Gwan-gyeong Mun:
> Bspec describes that GEN10 only supports capability of YUV 4:2:0 output to
> HDMI port and GEN11 supports capability of YUV 4:2:0 output to both DP and
> HDMI ports.
>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 681e88405ada..ad7382d3be86 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -6923,6 +6923,9 @@ intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
>  		connector->interlace_allowed = true;
>  	connector->doublescan_allowed = 0;
>  
> +	 if (INTEL_GEN(dev_priv) >= 11)
> +		connector->ycbcr_420_allowed = true;
> +
>  	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
>  
>  	intel_dp_aux_init(intel_dp);

This should probably be done as last patch (6/6). Otherwise looks good.

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

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Re: [RFC 6/6] drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs

[Maarten Lankhorst]

Op 31-01-2019 om 22:10 schreef Gwan-gyeong Mun:
> pipe_bpp value was assumed RGB therefore it was multiplied with 3.
> But YCbCr 4:2:0 requires multiplier value to 1.5 therefore it divides
> pipe_bpp to 2.
>  - RGB bpp = bpc x 3
>  - YCbCr 4:2:0 bpp = bpc x 1.5
>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c |  7 +++++-
>  drivers/gpu/drm/i915/intel_dp.c  | 41 ++++++++++++++++++++++++++------
>  2 files changed, 40 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index c6aed2b06a59..7f56aa7842c1 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1696,6 +1696,7 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 temp;
> +	int bpp;
>  
>  	if (!intel_crtc_has_dp_encoder(crtc_state))
>  		return;
> @@ -1707,7 +1708,11 @@ void intel_ddi_set_pipe_settings(const struct intel_crtc_state *crtc_state)
>  	if (crtc_state->limited_color_range)
>  		temp |= TRANS_MSA_CEA_RANGE;
>  
> -	switch (crtc_state->pipe_bpp) {
> +	bpp = crtc_state->pipe_bpp;
> +	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
> +		bpp *= 2;
> +
> +	switch (bpp) {
>  	case 18:
>  		temp |= TRANS_MSA_6_BPC;
>  		break;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 3a9a5a3c33a9..734c5743e03f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1761,12 +1761,13 @@ static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
>  	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>  	struct intel_connector *intel_connector = intel_dp->attached_connector;
>  	int bpp, bpc;
> +	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
>  
>  	bpp = pipe_config->pipe_bpp;
>  	bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
>  
>  	if (bpc > 0)
> -		bpp = min(bpp, 3*bpc);
> +		bpp = min(bpp, 3*bpc/bpp_divider);
>  
>  	if (intel_dp_is_edp(intel_dp)) {
>  		/* Get bpp from vbt only for panels that dont have bpp in edid */
> @@ -1787,12 +1788,14 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
>  				  struct intel_crtc_state *pipe_config,
>  				  struct link_config_limits *limits)
>  {
> +	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
> +
>  	/* For DP Compliance we override the computed bpp for the pipe */
>  	if (intel_dp->compliance.test_data.bpc != 0) {
> -		int bpp = 3 * intel_dp->compliance.test_data.bpc;
> +		int bpp = 3 * intel_dp->compliance.test_data.bpc / bpp_divider;
>  
>  		limits->min_bpp = limits->max_bpp = bpp;
> -		pipe_config->dither_force_disable = bpp == 6 * 3;
> +		pipe_config->dither_force_disable = bpp == 6 * 3 / bpp_divider;
>  
>  		DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp);
>  	}
> @@ -1826,8 +1829,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
>  	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
>  	int bpp, clock, lane_count;
>  	int mode_rate, link_clock, link_avail;
> +	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
>  
> -	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
> +	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3 / bpp_divider) {
>  		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
>  						   bpp);
>  
> @@ -1862,8 +1866,9 @@ intel_dp_compute_link_config_fast(struct intel_dp *intel_dp,
>  	struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
>  	int bpp, clock, lane_count;
>  	int mode_rate, link_clock, link_avail;
> +	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
>  
> -	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
> +	for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3 / bpp_divider) {
>  		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
>  						   bpp);
>  
> @@ -2009,6 +2014,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  	struct link_config_limits limits;
>  	int common_len;
>  	int ret;
> +	int bpp_divider = pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;
>  
>  	common_len = intel_dp_common_len_rate_limit(intel_dp,
>  						    intel_dp->max_link_rate);
> @@ -2022,7 +2028,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
>  	limits.min_lane_count = 1;
>  	limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
>  
> -	limits.min_bpp = 6 * 3;
> +	limits.min_bpp = 6 * 3 / bpp_divider;
>  	limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
>  
>  	if (intel_dp_is_edp(intel_dp) && intel_dp->edp_dpcd[0] < DP_EDP_14) {
> @@ -2110,6 +2116,11 @@ intel_dp_ycbcr420_config(struct drm_connector *connector,
>  	}
>  
>  	config->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
> +	/* pipe_bpp value was assumed RGB therefore it was multiplied
> +	 * with 3. But YCbCr 4:2:0 requires multiplier value to 1.5
> +	 * therefore it divides pipe_bpp to 2.
> +	 */
> +	config->pipe_bpp /= 2;
>  
>  	/* YCBCR 420 output conversion needs a scaler */
>  	if (skl_update_scaler_crtc(config)) {
> @@ -4446,7 +4457,23 @@ intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
>  	 * 011b = 12bpc.
>  	 * 100b = 16bpc.
>  	 */
> -	vsc_sdp.DB17 = 0x1;
> +	switch (crtc_state->pipe_bpp) {
> +	case 12: /* 8bpc */
> +		vsc_sdp.DB17 = 0x1;
> +		break;
> +	case 15: /* 10bpc */
> +		vsc_sdp.DB17 = 0x2;
> +		break;
> +	case 18: /* 12bpc */
> +		vsc_sdp.DB17 = 0x3;
> +		break;
> +	case 24: /* 16bpc */
> +		vsc_sdp.DB17 = 0x4;
> +		break;
> +	default:
> +		DRM_DEBUG_KMS("Invalid bpp value '%d'\n", crtc_state->pipe_bpp);
> +		break;
> +	}
>  
>  	/*
>  	 * Content Type (Bits 2:0)

For patch 2, 3, 5, and 6:

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

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Re: [RFC 4/6] drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format

[Maarten Lankhorst]

Op 31-01-2019 om 22:10 schreef Gwan-gyeong Mun:
> Function intel_pixel_encoding_setup_vsc handles vsc header and data block
> setup for pixel encoding / colorimetry format.
>
> Setup VSC header and data block in function intel_pixel_encoding_setup_vsc
> for pixel encoding / colorimetry format as per dp 1.4a spec,
> section 2.2.5.7.1, table 2-119: VSC SDP Header Bytes, section 2.2.5.7.5,
> table 2-120:VSC SDP Payload for DB16 through DB18.
>
> Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c |  1 +
>  drivers/gpu/drm/i915/intel_dp.c  | 72 ++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_drv.h |  2 +
>  3 files changed, 75 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index ca705546a0ab..8969f03393b8 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3400,6 +3400,7 @@ static void intel_enable_ddi_dp(struct intel_encoder *encoder,
>  
>  	intel_edp_backlight_on(crtc_state, conn_state);
>  	intel_psr_enable(intel_dp, crtc_state);
> +	intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
>  	intel_edp_drrs_enable(intel_dp, crtc_state);
>  
>  	if (crtc_state->has_audio)
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a61aff23c8b2..3a9a5a3c33a9 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -4402,6 +4402,78 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
>  	return 0;
>  }
>  
> +static void
> +intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
> +			       const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> +	struct dp_vsc_sdp vsc_sdp;
> +
> +	if (!intel_dp->attached_connector->base.ycbcr_420_allowed)  return;
> +
Newline missing?
> +	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */
> +	memset(&vsc_sdp, 0, sizeof(vsc_sdp));
> +	vsc_sdp.sdp_header.HB0 = 0;
> +	vsc_sdp.sdp_header.HB1 = 0x7;
> +
> +	/* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> +	 * Colorimetry Format indication. A DP Source device is allowed
> +	 * to indicate the pixel encoding/colorimetry format to the DP Sink
> +	 * device with VSC SDP only when the DP Sink device supports it
> +	 * (i.e., VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in the register
> +	 * DPRX_FEATURE_ENUMERATION_LIST (DPCD Address 02210h, bit 3) is set to 1)
> +	 */
> +	vsc_sdp.sdp_header.HB2 = 0x5;
> +
> +	/* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
> +	 * Colorimetry Format indication (HB2 = 05h).
> +	 */
> +	vsc_sdp.sdp_header.HB3 = 0x13;
> +	/* YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h
> +	 * DB16[3:0] DP 1.4a spec, Table 2-120
> +	 */
> +
> +	/* https://patchwork.freedesktop.org/patch/166830/ i915 implementations
> +	 * uses BT.709 color space
> +	 */
I think we should refer to commit ids instead of patchwork. :)
> +	vsc_sdp.DB16 = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
> +	vsc_sdp.DB16 |= 0x1; /* 0x1, ITU-R BT.709 */

But speaking of patchwork, might be nice to setup a VSC for not yuv420 as well.

This could be used for https://patchwork.freedesktop.org/series/47132/

:)

> +	/* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only,
> +	 * the following Component Bit Depth values are defined:
> +	 * 001b = 8bpc.
> +	 * 010b = 10bpc.
> +	 * 011b = 12bpc.
> +	 * 100b = 16bpc.
> +	 */
> +	vsc_sdp.DB17 = 0x1;
> +
> +	/*
> +	 * Content Type (Bits 2:0)
> +	 * 000b = Not defined.
> +	 * 001b = Graphics.
> +	 * 010b = Photo.
> +	 * 011b = Video.
> +	 * 100b = Game
> +	 * All other values are RESERVED.
> +	 * Note: See CTA-861-G for the definition and expected
> +	 * processing by a stream sink for the above contect types.
> +	 */
> +	vsc_sdp.DB18 = 0;
> +
> +	intel_dig_port->write_infoframe(&intel_dig_port->base,
> +			crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp));
> +}
> +

This should probably be less hardcoded in the future, but looks ok for now.

~Maarten

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Re: ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs

[Jani Nikula]

FWIW these are all valid checkpatch complaints.

BR,
Jani.

On Thu, 31 Jan 2019, Patchwork <patchwork@emeril.freedesktop.org> wrote:
> == Series Details ==
>
> Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs
> URL   : https://patchwork.freedesktop.org/series/56059/
> State : warning
>
> == Summary ==
>
> $ dim checkpatch origin/drm-tip
> 646f25f459f0 drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11
> -:20: WARNING:TABSTOP: Statements should start on a tabstop
> #20: FILE: drivers/gpu/drm/i915/intel_dp.c:6926:
> +	 if (INTEL_GEN(dev_priv) >= 11)
>
> total: 0 errors, 1 warnings, 0 checks, 9 lines checked
> 485e788bfeee drm/i915/dp: Add a config function for YCBCR420 outputs
> bfebbc7e2acb drm: Add a VSC structure for handling Pixel Encoding/Colorimetry Formats
> 2b312268f5ba drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format
> -:44: ERROR:TRAILING_STATEMENTS: trailing statements should be on next line
> #44: FILE: drivers/gpu/drm/i915/intel_dp.c:4412:
> +	if (!intel_dp->attached_connector->base.ycbcr_420_allowed)  return;
>
> total: 1 errors, 0 warnings, 0 checks, 93 lines checked
> 317c3a0c98c6 drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
> -:41: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the * on each line
> #41: FILE: drivers/gpu/drm/i915/intel_ddi.c:1740:
> +	 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
> +	*/
>
> total: 0 errors, 1 warnings, 0 checks, 21 lines checked
> 49b8aff26fa2 drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs
> -:54: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
> #54: FILE: drivers/gpu/drm/i915/intel_dp.c:1770:
> +		bpp = min(bpp, 3*bpc/bpp_divider);
>  		                ^
>
> -:54: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
> #54: FILE: drivers/gpu/drm/i915/intel_dp.c:1770:
> +		bpp = min(bpp, 3*bpc/bpp_divider);
>  		                    ^
>
> total: 0 errors, 0 warnings, 2 checks, 119 lines checked
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs

[Mun, Gwan-gyeong]

On Mon, 2019-02-18 at 11:44 +0200, Jani Nikula wrote:
> FWIW these are all valid checkpatch complaints.
> 
> BR,
> Jani.
> 
> On Thu, 31 Jan 2019, Patchwork <patchwork@emeril.freedesktop.org>
> wrote:
> > == Series Details ==
> > 
> > Series: drm/i915/dp: Preliminary support for DP YCbCr4:2:0 outputs
> > URL   : https://patchwork.freedesktop.org/series/56059/
> > State : warning
> > 
> > == Summary ==
> > 
> > $ dim checkpatch origin/drm-tip
> > 646f25f459f0 drm/i915/dp: Support DP ports YUV 4:2:0 output to
> > GEN11
> > -:20: WARNING:TABSTOP: Statements should start on a tabstop
> > #20: FILE: drivers/gpu/drm/i915/intel_dp.c:6926:
> > +	 if (INTEL_GEN(dev_priv) >= 11)
> > 
> > total: 0 errors, 1 warnings, 0 checks, 9 lines checked
> > 485e788bfeee drm/i915/dp: Add a config function for YCBCR420
> > outputs
> > bfebbc7e2acb drm: Add a VSC structure for handling Pixel
> > Encoding/Colorimetry Formats
> > 2b312268f5ba drm/i915/dp: Program VSC Header and DB for Pixel
> > Encoding/Colorimetry Format
> > -:44: ERROR:TRAILING_STATEMENTS: trailing statements should be on
> > next line
> > #44: FILE: drivers/gpu/drm/i915/intel_dp.c:4412:
> > +	if (!intel_dp->attached_connector-
> > >base.ycbcr_420_allowed)  return;
> > 
> > total: 1 errors, 0 warnings, 0 checks, 93 lines checked
> > 317c3a0c98c6 drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSA
> > -:41: WARNING:BLOCK_COMMENT_STYLE: Block comments should align the
> > * on each line
> > #41: FILE: drivers/gpu/drm/i915/intel_ddi.c:1740:
> > +	 * indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
> > +	*/
> > 
> > total: 0 errors, 1 warnings, 0 checks, 21 lines checked
> > 49b8aff26fa2 drm/i915/dp: Update pipe_bpp for DP YCbCr4:2:0 outputs
> > -:54: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
> > #54: FILE: drivers/gpu/drm/i915/intel_dp.c:1770:
> > +		bpp = min(bpp, 3*bpc/bpp_divider);
> >  		                ^
> > 
> > -:54: CHECK:SPACING: spaces preferred around that '/' (ctx:VxV)
> > #54: FILE: drivers/gpu/drm/i915/intel_dp.c:1770:
> > +		bpp = min(bpp, 3*bpc/bpp_divider);
> >  		                    ^
> > 
> > total: 0 errors, 0 warnings, 2 checks, 119 lines checked
> > 

Thank you for guiding me.
I will fix all of warnings from Fi.CI.CHECKPATCH.

Br,
Gwan-gyeong.

> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [RFC 1/6] drm/i915/dp: Support DP ports YUV 4:2:0 output to GEN11

[Mun, Gwan-gyeong]

On Fri, 2019-02-08 at 16:24 +0100, Maarten Lankhorst wrote:
> Op 31-01-2019 om 22:10 schreef Gwan-gyeong Mun:
> > Bspec describes that GEN10 only supports capability of YUV 4:2:0
> > output to
> > HDMI port and GEN11 supports capability of YUV 4:2:0 output to both
> > DP and
> > HDMI ports.
> > 
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index 681e88405ada..ad7382d3be86 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -6923,6 +6923,9 @@ intel_dp_init_connector(struct
> > intel_digital_port *intel_dig_port,
> >  		connector->interlace_allowed = true;
> >  	connector->doublescan_allowed = 0;
> >  
> > +	 if (INTEL_GEN(dev_priv) >= 11)
> > +		connector->ycbcr_420_allowed = true;
> > +
> >  	intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
> >  
> >  	intel_dp_aux_init(intel_dp);
> 
> This should probably be done as last patch (6/6). Otherwise looks
> good.
> 

I will reorder this patch as last patch.

Br,
Gwan-gyeong.

> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
> 
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Re: [RFC 4/6] drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format

[Mun, Gwan-gyeong]

On Fri, 2019-02-08 at 16:31 +0100, Maarten Lankhorst wrote:
> Op 31-01-2019 om 22:10 schreef Gwan-gyeong Mun:
> > Function intel_pixel_encoding_setup_vsc handles vsc header and data
> > block
> > setup for pixel encoding / colorimetry format.
> > 
> > Setup VSC header and data block in function
> > intel_pixel_encoding_setup_vsc
> > for pixel encoding / colorimetry format as per dp 1.4a spec,
> > section 2.2.5.7.1, table 2-119: VSC SDP Header Bytes, section
> > 2.2.5.7.5,
> > table 2-120:VSC SDP Payload for DB16 through DB18.
> > 
> > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c |  1 +
> >  drivers/gpu/drm/i915/intel_dp.c  | 72
> > ++++++++++++++++++++++++++++++++
> >  drivers/gpu/drm/i915/intel_drv.h |  2 +
> >  3 files changed, 75 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index ca705546a0ab..8969f03393b8 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -3400,6 +3400,7 @@ static void intel_enable_ddi_dp(struct
> > intel_encoder *encoder,
> >  
> >  	intel_edp_backlight_on(crtc_state, conn_state);
> >  	intel_psr_enable(intel_dp, crtc_state);
> > +	intel_dp_ycbcr_420_enable(intel_dp, crtc_state);
> >  	intel_edp_drrs_enable(intel_dp, crtc_state);
> >  
> >  	if (crtc_state->has_audio)
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index a61aff23c8b2..3a9a5a3c33a9 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -4402,6 +4402,78 @@ u8 intel_dp_dsc_get_slice_count(struct
> > intel_dp *intel_dp,
> >  	return 0;
> >  }
> >  
> > +static void
> > +intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp,
> > +			       const struct intel_crtc_state
> > *crtc_state)
> > +{
> > +	struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> > +	struct dp_vsc_sdp vsc_sdp;
> > +
> > +	if (!intel_dp->attached_connector-
> > >base.ycbcr_420_allowed)  return;
> > +
> Newline missing?
I'll add a missed Newline.
> > +	/* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
> > */
> > +	memset(&vsc_sdp, 0, sizeof(vsc_sdp));
> > +	vsc_sdp.sdp_header.HB0 = 0;
> > +	vsc_sdp.sdp_header.HB1 = 0x7;
> > +
> > +	/* VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
> > +	 * Colorimetry Format indication. A DP Source device is allowed
> > +	 * to indicate the pixel encoding/colorimetry format to the DP
> > Sink
> > +	 * device with VSC SDP only when the DP Sink device supports it
> > +	 * (i.e., VSC_SDP_EXTENSION_FOR_COLORIMETRY_SUPPORTED bit in
> > the register
> > +	 * DPRX_FEATURE_ENUMERATION_LIST (DPCD Address 02210h, bit 3)
> > is set to 1)
> > +	 */
> > +	vsc_sdp.sdp_header.HB2 = 0x5;
> > +
> > +	/* VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/
> > +	 * Colorimetry Format indication (HB2 = 05h).
> > +	 */
> > +	vsc_sdp.sdp_header.HB3 = 0x13;
> > +	/* YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 =
> > 1h
> > +	 * DB16[3:0] DP 1.4a spec, Table 2-120
> > +	 */
> > +
> > +	/* https://patchwork.freedesktop.org/patch/166830/ i915
> > implementations
> > +	 * uses BT.709 color space
> > +	 */
> I think we should refer to commit ids instead of patchwork. :)
I'll refer to commit ids instead of patchwork. 
> > +	vsc_sdp.DB16 = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/
> > +	vsc_sdp.DB16 |= 0x1; /* 0x1, ITU-R BT.709 */
> 
> But speaking of patchwork, might be nice to setup a VSC for not
> yuv420 as well.
> 
Including this patch, there are two setup of vsc functions.
these are intel_psr_setup_vsc() and intel_pixel_encoding_setup_vsc().
In my opinion we can refactor setting of vsc function after these
series.
If I have to make a common setting of vsc fuction prior to this patch,
please let me know.
> This could be used for 
> https://patchwork.freedesktop.org/series/47132/
> 
> :)
> 
Followed to https://patchwork.freedesktop.org/series/47132/, latest
rev17 dropped a patch ("drm: Add DP colorspace property").
After adding this patch we can have a usecase to DP colorspace
property.
therefore after landing this patch, we can add and use dropped patch
("drm: Add DP colorspace property") for setting VSC.
> > +	/* For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and
> > Y Only,
> > +	 * the following Component Bit Depth values are defined:
> > +	 * 001b = 8bpc.
> > +	 * 010b = 10bpc.
> > +	 * 011b = 12bpc.
> > +	 * 100b = 16bpc.
> > +	 */
> > +	vsc_sdp.DB17 = 0x1;
> > +
> > +	/*
> > +	 * Content Type (Bits 2:0)
> > +	 * 000b = Not defined.
> > +	 * 001b = Graphics.
> > +	 * 010b = Photo.
> > +	 * 011b = Video.
> > +	 * 100b = Game
> > +	 * All other values are RESERVED.
> > +	 * Note: See CTA-861-G for the definition and expected
> > +	 * processing by a stream sink for the above contect types.
> > +	 */
> > +	vsc_sdp.DB18 = 0;
> > +
> > +	intel_dig_port->write_infoframe(&intel_dig_port->base,
> > +			crtc_state, DP_SDP_VSC, &vsc_sdp,
> > sizeof(vsc_sdp));
> > +}
> > +
> 
> This should probably be less hardcoded in the future, but looks ok
> for now.
Certainly, I'll reduce hard coded lines in the future.
> 
> ~Maarten
> 
Br,
Gwan-gyeong.
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