[PATCH v2 0/4] Add Pooled EU support to BXT

[PATCH v2 0/4] Add Pooled EU support to BXT

[Arun Siluvery]

v1: http://lists.freedesktop.org/archives/intel-gfx/2015-July/071951.html

v2: auxiliary batch size must be a multiple of 8, use feature flag while
enabling support and add comments to clarify various things.

Resending all patches as the order is changed.

Arun Siluvery (3):
  drm/i915: Add provision to extend Golden context batch
  drm/i915/bxt: Add get_param to query Pooled EU availability
  drm/i915:bxt: Enable Pooled EU support

Mika Kuoppala (1):
  drm/i915: Do kunmap if renderstate parsing fails

 drivers/gpu/drm/i915/i915_dma.c              |  3 ++
 drivers/gpu/drm/i915/i915_drv.c              |  1 +
 drivers/gpu/drm/i915/i915_drv.h              |  5 +-
 drivers/gpu/drm/i915/i915_gem_render_state.c | 70 +++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_gem_render_state.h |  2 +
 drivers/gpu/drm/i915/i915_reg.h              |  2 +
 drivers/gpu/drm/i915/intel_lrc.c             |  6 +++
 include/uapi/drm/i915_drm.h                  |  1 +
 8 files changed, 87 insertions(+), 3 deletions(-)

-- 
1.9.1

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[PATCH v2 1/4] drm/i915: Do kunmap if renderstate parsing fails

[Arun Siluvery]

From: Mika Kuoppala <mika.kuoppala@linux.intel.com>

Kunmap the renderstate page on error path.

Reviewed-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_render_state.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index a0201fc..b6492fe 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -96,8 +96,10 @@ static int render_state_setup(struct render_state *so)
 			s = lower_32_bits(r);
 			if (so->gen >= 8) {
 				if (i + 1 >= rodata->batch_items ||
-				    rodata->batch[i + 1] != 0)
-					return -EINVAL;
+				    rodata->batch[i + 1] != 0) {
+					ret = -EINVAL;
+					goto err_out;
+				}
 
 				d[i++] = s;
 				s = upper_32_bits(r);
@@ -120,6 +122,10 @@ static int render_state_setup(struct render_state *so)
 	}
 
 	return 0;
+
+err_out:
+	kunmap(page);
+	return ret;
 }
 
 void i915_gem_render_state_fini(struct render_state *so)
-- 
1.9.1

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[PATCH v2 2/4] drm/i915: Add provision to extend Golden context batch

[Arun Siluvery]

The Golden batch carries 3D state at the beginning so that HW starts with
a known state. It is carried as a binary blob which is auto-generated from
source. The idea was it would be easier to maintain and keep the complexity
out of the kernel which makes sense as we don't really touch it. However if
you really need to update it then you need to update generator source and
keep the binary blob in sync with it.

There is a need to patch this in bxt to send one additional command to enable
a feature. A solution was to patch the binary data with some additional
data structures (included as part of auto-generator source) but it was
unnecessarily complicated.

Chris suggested the idea of having a secondary batch and execute two batch
buffers. It has clear advantages as we needn't touch the base golden batch,
can customize secondary/auxiliary batch depending on Gen and can be carried
in the driver with no dependencies.

This patch adds support for this auxiliary batch which is inserted at the
end of golden batch and is completely independent from it. Thanks to Mika
for the preliminary review.

v2: Strictly conform to the batch size requirements to cover Gen2 and
add comments to clarify overflow check in macro (Chris, Mika).

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Armin Reese <armin.c.reese@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_render_state.c | 45 ++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_gem_render_state.h |  2 ++
 drivers/gpu/drm/i915/intel_lrc.c             |  6 ++++
 3 files changed, 53 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index b6492fe..5026a62 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -73,6 +73,24 @@ free_gem:
 	return ret;
 }
 
+/*
+ * Macro to add commands to auxiliary batch.
+ * This macro only checks for page overflow before inserting the commands,
+ * this is sufficient as the null state generator makes the final batch
+ * with two passes to build command and state separately. At this point
+ * the size of both are known and it compacts them by relocating the state
+ * right after the commands taking care of aligment so we should sufficient
+ * space below them for adding new commands.
+ */
+#define OUT_BATCH(batch, i, val)				\
+	do {							\
+		if (WARN_ON((i) >= PAGE_SIZE / sizeof(u32))) {	\
+			ret = -ENOSPC;				\
+			goto err_out;				\
+		}						\
+		(batch)[(i)++] = (val);				\
+	} while(0)
+
 static int render_state_setup(struct render_state *so)
 {
 	const struct intel_renderstate_rodata *rodata = so->rodata;
@@ -110,6 +128,21 @@ static int render_state_setup(struct render_state *so)
 
 		d[i++] = s;
 	}
+
+	while (i % CACHELINE_DWORDS)
+		OUT_BATCH(d, i, MI_NOOP);
+
+	so->aux_batch_offset = i * sizeof(u32);
+
+	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
+	so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;
+
+	/*
+	 * Since we are sending length, we need to strictly conform to
+	 * all requirements. For Gen2 this must be a multiple of 8.
+	 */
+	so->aux_batch_size = ALIGN(so->aux_batch_size, 8);
+
 	kunmap(page);
 
 	ret = i915_gem_object_set_to_gtt_domain(so->obj, false);
@@ -128,6 +161,8 @@ err_out:
 	return ret;
 }
 
+#undef OUT_BATCH
+
 void i915_gem_render_state_fini(struct render_state *so)
 {
 	i915_gem_object_ggtt_unpin(so->obj);
@@ -176,6 +211,16 @@ int i915_gem_render_state_init(struct drm_i915_gem_request *req)
 	if (ret)
 		goto out;
 
+	if (so.aux_batch_size > 8) {
+		ret = req->ring->dispatch_execbuffer(req,
+						     (so.ggtt_offset +
+						      so.aux_batch_offset),
+						     so.aux_batch_size,
+						     I915_DISPATCH_SECURE);
+		if (ret)
+			goto out;
+	}
+
 	i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
 
 out:
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.h b/drivers/gpu/drm/i915/i915_gem_render_state.h
index 7aa7372..79de101 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.h
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.h
@@ -37,6 +37,8 @@ struct render_state {
 	struct drm_i915_gem_object *obj;
 	u64 ggtt_offset;
 	int gen;
+	u32 aux_batch_size;
+	u64 aux_batch_offset;
 };
 
 int i915_gem_render_state_init(struct drm_i915_gem_request *req);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index adb386d..5e4771e 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1661,6 +1661,12 @@ static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req)
 	if (ret)
 		goto out;
 
+	ret = req->ring->emit_bb_start(req,
+				       (so.ggtt_offset + so.aux_batch_offset),
+				       I915_DISPATCH_SECURE);
+	if (ret)
+		goto out;
+
 	i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
 
 out:
-- 
1.9.1

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Re: [PATCH v2 2/4] drm/i915: Add provision to extend Golden context batch

[Chris Wilson]

On Fri, Jul 17, 2015 at 07:13:32PM +0100, Arun Siluvery wrote:
> The Golden batch carries 3D state at the beginning so that HW starts with
> a known state. It is carried as a binary blob which is auto-generated from
> source. The idea was it would be easier to maintain and keep the complexity
> out of the kernel which makes sense as we don't really touch it. However if
> you really need to update it then you need to update generator source and
> keep the binary blob in sync with it.
> 
> There is a need to patch this in bxt to send one additional command to enable
> a feature. A solution was to patch the binary data with some additional
> data structures (included as part of auto-generator source) but it was
> unnecessarily complicated.
> 
> Chris suggested the idea of having a secondary batch and execute two batch
> buffers. It has clear advantages as we needn't touch the base golden batch,
> can customize secondary/auxiliary batch depending on Gen and can be carried
> in the driver with no dependencies.
> 
> This patch adds support for this auxiliary batch which is inserted at the
> end of golden batch and is completely independent from it. Thanks to Mika
> for the preliminary review.
> 
> v2: Strictly conform to the batch size requirements to cover Gen2 and
> add comments to clarify overflow check in macro (Chris, Mika).
> 
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Armin Reese <armin.c.reese@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_render_state.c | 45 ++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/i915_gem_render_state.h |  2 ++
>  drivers/gpu/drm/i915/intel_lrc.c             |  6 ++++
>  3 files changed, 53 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
> index b6492fe..5026a62 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
> @@ -73,6 +73,24 @@ free_gem:
>  	return ret;
>  }
>  
> +/*
> + * Macro to add commands to auxiliary batch.
> + * This macro only checks for page overflow before inserting the commands,
> + * this is sufficient as the null state generator makes the final batch
> + * with two passes to build command and state separately. At this point
> + * the size of both are known and it compacts them by relocating the state
> + * right after the commands taking care of aligment so we should sufficient
> + * space below them for adding new commands.
> + */
> +#define OUT_BATCH(batch, i, val)				\
> +	do {							\
> +		if (WARN_ON((i) >= PAGE_SIZE / sizeof(u32))) {	\
> +			ret = -ENOSPC;				\
> +			goto err_out;				\
> +		}						\
> +		(batch)[(i)++] = (val);				\
> +	} while(0)
> +
>  static int render_state_setup(struct render_state *so)
>  {
>  	const struct intel_renderstate_rodata *rodata = so->rodata;
> @@ -110,6 +128,21 @@ static int render_state_setup(struct render_state *so)
>  
>  		d[i++] = s;
>  	}
> +
> +	while (i % CACHELINE_DWORDS)
> +		OUT_BATCH(d, i, MI_NOOP);
> +
> +	so->aux_batch_offset = i * sizeof(u32);
> +
> +	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
> +	so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;
> +
> +	/*
> +	 * Since we are sending length, we need to strictly conform to
> +	 * all requirements. For Gen2 this must be a multiple of 8.
> +	 */
> +	so->aux_batch_size = ALIGN(so->aux_batch_size, 8);
> +
>  	kunmap(page);
>  
>  	ret = i915_gem_object_set_to_gtt_domain(so->obj, false);
> @@ -128,6 +161,8 @@ err_out:
>  	return ret;
>  }
>  
> +#undef OUT_BATCH
> +
>  void i915_gem_render_state_fini(struct render_state *so)
>  {
>  	i915_gem_object_ggtt_unpin(so->obj);
> @@ -176,6 +211,16 @@ int i915_gem_render_state_init(struct drm_i915_gem_request *req)
>  	if (ret)
>  		goto out;
>  
> +	if (so.aux_batch_size > 8) {
> +		ret = req->ring->dispatch_execbuffer(req,
> +						     (so.ggtt_offset +
> +						      so.aux_batch_offset),
> +						     so.aux_batch_size,
> +						     I915_DISPATCH_SECURE);
> +		if (ret)
> +			goto out;
> +	}
> +
>  	i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
>  
>  out:
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.h b/drivers/gpu/drm/i915/i915_gem_render_state.h
> index 7aa7372..79de101 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.h
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.h
> @@ -37,6 +37,8 @@ struct render_state {
>  	struct drm_i915_gem_object *obj;
>  	u64 ggtt_offset;
>  	int gen;
> +	u32 aux_batch_size;
> +	u64 aux_batch_offset;

u64!!!! That's a mighty big page.

From a code inspection pov, you've addressed all of my concerns (and it
would be nice to fixup that rogue u64 above).

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

for the series
-Chris

-- 
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Re: [PATCH v2 2/4] drm/i915: Add provision to extend Golden context batch

[Siluvery, Arun]

On 17/07/2015 21:03, Chris Wilson wrote:
> On Fri, Jul 17, 2015 at 07:13:32PM +0100, Arun Siluvery wrote:
>> The Golden batch carries 3D state at the beginning so that HW starts with
>> a known state. It is carried as a binary blob which is auto-generated from
>> source. The idea was it would be easier to maintain and keep the complexity
>> out of the kernel which makes sense as we don't really touch it. However if
>> you really need to update it then you need to update generator source and
>> keep the binary blob in sync with it.
>>
>> There is a need to patch this in bxt to send one additional command to enable
>> a feature. A solution was to patch the binary data with some additional
>> data structures (included as part of auto-generator source) but it was
>> unnecessarily complicated.
>>
>> Chris suggested the idea of having a secondary batch and execute two batch
>> buffers. It has clear advantages as we needn't touch the base golden batch,
>> can customize secondary/auxiliary batch depending on Gen and can be carried
>> in the driver with no dependencies.
>>
>> This patch adds support for this auxiliary batch which is inserted at the
>> end of golden batch and is completely independent from it. Thanks to Mika
>> for the preliminary review.
>>
>> v2: Strictly conform to the batch size requirements to cover Gen2 and
>> add comments to clarify overflow check in macro (Chris, Mika).
>>
>> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Cc: Armin Reese <armin.c.reese@intel.com>
>> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
>> ---
>>   drivers/gpu/drm/i915/i915_gem_render_state.c | 45 ++++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/i915_gem_render_state.h |  2 ++
>>   drivers/gpu/drm/i915/intel_lrc.c             |  6 ++++
>>   3 files changed, 53 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
>> index b6492fe..5026a62 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
>> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
>> @@ -73,6 +73,24 @@ free_gem:
>>   	return ret;
>>   }
>>
>> +/*
>> + * Macro to add commands to auxiliary batch.
>> + * This macro only checks for page overflow before inserting the commands,
>> + * this is sufficient as the null state generator makes the final batch
>> + * with two passes to build command and state separately. At this point
>> + * the size of both are known and it compacts them by relocating the state
>> + * right after the commands taking care of aligment so we should sufficient
>> + * space below them for adding new commands.
>> + */
>> +#define OUT_BATCH(batch, i, val)				\
>> +	do {							\
>> +		if (WARN_ON((i) >= PAGE_SIZE / sizeof(u32))) {	\
>> +			ret = -ENOSPC;				\
>> +			goto err_out;				\
>> +		}						\
>> +		(batch)[(i)++] = (val);				\
>> +	} while(0)
>> +
>>   static int render_state_setup(struct render_state *so)
>>   {
>>   	const struct intel_renderstate_rodata *rodata = so->rodata;
>> @@ -110,6 +128,21 @@ static int render_state_setup(struct render_state *so)
>>
>>   		d[i++] = s;
>>   	}
>> +
>> +	while (i % CACHELINE_DWORDS)
>> +		OUT_BATCH(d, i, MI_NOOP);
>> +
>> +	so->aux_batch_offset = i * sizeof(u32);
>> +
>> +	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
>> +	so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;
>> +
>> +	/*
>> +	 * Since we are sending length, we need to strictly conform to
>> +	 * all requirements. For Gen2 this must be a multiple of 8.
>> +	 */
>> +	so->aux_batch_size = ALIGN(so->aux_batch_size, 8);
>> +
>>   	kunmap(page);
>>
>>   	ret = i915_gem_object_set_to_gtt_domain(so->obj, false);
>> @@ -128,6 +161,8 @@ err_out:
>>   	return ret;
>>   }
>>
>> +#undef OUT_BATCH
>> +
>>   void i915_gem_render_state_fini(struct render_state *so)
>>   {
>>   	i915_gem_object_ggtt_unpin(so->obj);
>> @@ -176,6 +211,16 @@ int i915_gem_render_state_init(struct drm_i915_gem_request *req)
>>   	if (ret)
>>   		goto out;
>>
>> +	if (so.aux_batch_size > 8) {
>> +		ret = req->ring->dispatch_execbuffer(req,
>> +						     (so.ggtt_offset +
>> +						      so.aux_batch_offset),
>> +						     so.aux_batch_size,
>> +						     I915_DISPATCH_SECURE);
>> +		if (ret)
>> +			goto out;
>> +	}
>> +
>>   	i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req);
>>
>>   out:
>> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.h b/drivers/gpu/drm/i915/i915_gem_render_state.h
>> index 7aa7372..79de101 100644
>> --- a/drivers/gpu/drm/i915/i915_gem_render_state.h
>> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.h
>> @@ -37,6 +37,8 @@ struct render_state {
>>   	struct drm_i915_gem_object *obj;
>>   	u64 ggtt_offset;
>>   	int gen;
>> +	u32 aux_batch_size;
>> +	u64 aux_batch_offset;
>
> u64!!!! That's a mighty big page.
>
>>From a code inspection pov, you've addressed all of my concerns (and it
> would be nice to fixup that rogue u64 above).
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>

Thank you Chris for the review.
With that corrected and with your r-b tag, I will send all three patches 
for completion.

regards
Arun


> for the series
> -Chris
>

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[PATCH v2 3/4] drm/i915/bxt: Add get_param to query Pooled EU availability

[Arun Siluvery]

User space clients need to know when the pooled EU feature is present
and enabled on the hardware so that they can adapt work submissions.
Create a new device info flag for this purpose, and create a new GETPARAM
entry to allow user space to query its setting.

Set has_pooled_eu to true in the Broxton static device info - Broxton
supports the feature in hardware and the driver will enable it by
default.

Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c | 3 +++
 drivers/gpu/drm/i915/i915_drv.c | 1 +
 drivers/gpu/drm/i915/i915_drv.h | 5 ++++-
 include/uapi/drm/i915_drm.h     | 1 +
 4 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 5e63076..6c31beb 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -170,6 +170,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
 	case I915_PARAM_HAS_RESOURCE_STREAMER:
 		value = HAS_RESOURCE_STREAMER(dev);
 		break;
+	case I915_PARAM_HAS_POOLED_EU:
+		value = HAS_POOLED_EU(dev);
+		break;
 	default:
 		DRM_DEBUG("Unknown parameter %d\n", param->param);
 		return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e44dc0d..213f74d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -389,6 +389,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.num_pipes = 3,
 	.has_ddi = 1,
 	.has_fbc = 1,
+	.has_pooled_eu = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 };
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 768d1db..32850a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -775,7 +775,8 @@ struct intel_csr {
 	func(supports_tv) sep \
 	func(has_llc) sep \
 	func(has_ddi) sep \
-	func(has_fpga_dbg)
+	func(has_fpga_dbg) sep \
+	func(has_pooled_eu)
 
 #define DEFINE_FLAG(name) u8 name:1
 #define SEP_SEMICOLON ;
@@ -2549,6 +2550,8 @@ struct drm_i915_cmd_table {
 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
 				    INTEL_INFO(dev)->gen >= 8)
 
+#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
+
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index e7c29f1..9649577 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -356,6 +356,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_EU_TOTAL		 34
 #define I915_PARAM_HAS_GPU_RESET	 35
 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
+#define I915_PARAM_HAS_POOLED_EU         37
 
 typedef struct drm_i915_getparam {
 	int param;
-- 
1.9.1

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Re: [PATCH v2 3/4] drm/i915/bxt: Add get_param to query Pooled EU availability

[Siluvery, Arun]

On 17/07/2015 19:13, Arun Siluvery wrote:
> User space clients need to know when the pooled EU feature is present
> and enabled on the hardware so that they can adapt work submissions.
> Create a new device info flag for this purpose, and create a new GETPARAM
> entry to allow user space to query its setting.
>
> Set has_pooled_eu to true in the Broxton static device info - Broxton
> supports the feature in hardware and the driver will enable it by
> default.
>
> Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---

Please ignore this patch, this is squashed with Patch4 "drm/i915:bxt: 
Enable Pooled EU support" to keep all enabling changes in the same place 
otherwise we would've announced support to userspace before enabling it 
in kernel.

regards
Arun

>   drivers/gpu/drm/i915/i915_dma.c | 3 +++
>   drivers/gpu/drm/i915/i915_drv.c | 1 +
>   drivers/gpu/drm/i915/i915_drv.h | 5 ++++-
>   include/uapi/drm/i915_drm.h     | 1 +
>   4 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
> index 5e63076..6c31beb 100644
> --- a/drivers/gpu/drm/i915/i915_dma.c
> +++ b/drivers/gpu/drm/i915/i915_dma.c
> @@ -170,6 +170,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
>   	case I915_PARAM_HAS_RESOURCE_STREAMER:
>   		value = HAS_RESOURCE_STREAMER(dev);
>   		break;
> +	case I915_PARAM_HAS_POOLED_EU:
> +		value = HAS_POOLED_EU(dev);
> +		break;
>   	default:
>   		DRM_DEBUG("Unknown parameter %d\n", param->param);
>   		return -EINVAL;
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index e44dc0d..213f74d 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -389,6 +389,7 @@ static const struct intel_device_info intel_broxton_info = {
>   	.num_pipes = 3,
>   	.has_ddi = 1,
>   	.has_fbc = 1,
> +	.has_pooled_eu = 1,
>   	GEN_DEFAULT_PIPEOFFSETS,
>   	IVB_CURSOR_OFFSETS,
>   };
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 768d1db..32850a8 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -775,7 +775,8 @@ struct intel_csr {
>   	func(supports_tv) sep \
>   	func(has_llc) sep \
>   	func(has_ddi) sep \
> -	func(has_fpga_dbg)
> +	func(has_fpga_dbg) sep \
> +	func(has_pooled_eu)
>
>   #define DEFINE_FLAG(name) u8 name:1
>   #define SEP_SEMICOLON ;
> @@ -2549,6 +2550,8 @@ struct drm_i915_cmd_table {
>   #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
>   				    INTEL_INFO(dev)->gen >= 8)
>
> +#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
> +
>   #define INTEL_PCH_DEVICE_ID_MASK		0xff00
>   #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
>   #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index e7c29f1..9649577 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -356,6 +356,7 @@ typedef struct drm_i915_irq_wait {
>   #define I915_PARAM_EU_TOTAL		 34
>   #define I915_PARAM_HAS_GPU_RESET	 35
>   #define I915_PARAM_HAS_RESOURCE_STREAMER 36
> +#define I915_PARAM_HAS_POOLED_EU         37
>
>   typedef struct drm_i915_getparam {
>   	int param;
>

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[PATCH v2 4/4] drm/i915:bxt: Enable Pooled EU support

[Arun Siluvery]

This mode allows to assign EUs to pools which can process work collectively.
The command to enable this mode should be issued as part of context initialization.

The pooled mode is global, once enabled it has to stay the same across all
contexts until HW reset hence this is sent in auxiliary golden context batch.
Thanks to Mika for the preliminary review and comments.

v2: explain why this is enabled in golden context, use feature flag while
enabling the support (Chris)

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Armin Reese <armin.c.reese@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_render_state.c | 15 +++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h              |  2 ++
 2 files changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 5026a62..e4ff342 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -93,6 +93,7 @@ free_gem:
 
 static int render_state_setup(struct render_state *so)
 {
+	struct drm_device *dev = so->obj->base.dev;
 	const struct intel_renderstate_rodata *rodata = so->rodata;
 	unsigned int i = 0, reloc_index = 0;
 	struct page *page;
@@ -134,6 +135,20 @@ static int render_state_setup(struct render_state *so)
 
 	so->aux_batch_offset = i * sizeof(u32);
 
+	if (HAS_POOLED_EU(dev)) {
+		u32 pool_config = 0;
+		struct drm_i915_private *dev_priv = to_i915(dev);
+
+		OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
+		OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
+		if (dev_priv->info.subslice_total == 3)
+			pool_config = 0x00777000;
+		OUT_BATCH(d, i, pool_config);
+		OUT_BATCH(d, i, 0);
+		OUT_BATCH(d, i, 0);
+		OUT_BATCH(d, i, 0);
+	}
+
 	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
 	so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9a2ffad..e052499 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -379,6 +379,8 @@
  */
 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
 
+#define GEN9_MEDIA_POOL_STATE     ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
+#define   GEN9_MEDIA_POOL_ENABLE  (1 << 31)
 #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 #define   SC_UPDATE_SCISSOR       (0x1<<1)
-- 
1.9.1

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Re: [PATCH v2 4/4] drm/i915:bxt: Enable Pooled EU support

[Chris Wilson]

On Fri, Jul 17, 2015 at 07:13:34PM +0100, Arun Siluvery wrote:
> This mode allows to assign EUs to pools which can process work collectively.
> The command to enable this mode should be issued as part of context initialization.
> 
> The pooled mode is global, once enabled it has to stay the same across all
> contexts until HW reset hence this is sent in auxiliary golden context batch.
> Thanks to Mika for the preliminary review and comments.
> 
> v2: explain why this is enabled in golden context, use feature flag while
> enabling the support (Chris)

You fell into the trap of telling userspace this was setup before we
actually do so.
 
> Cc: Mika Kuoppala <mika.kuoppala@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Armin Reese <armin.c.reese@intel.com>
> Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_render_state.c | 15 +++++++++++++++
>  drivers/gpu/drm/i915/i915_reg.h              |  2 ++
>  2 files changed, 17 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
> index 5026a62..e4ff342 100644
> --- a/drivers/gpu/drm/i915/i915_gem_render_state.c
> +++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
> @@ -93,6 +93,7 @@ free_gem:
>  
>  static int render_state_setup(struct render_state *so)
>  {
> +	struct drm_device *dev = so->obj->base.dev;
>  	const struct intel_renderstate_rodata *rodata = so->rodata;
>  	unsigned int i = 0, reloc_index = 0;
>  	struct page *page;
> @@ -134,6 +135,20 @@ static int render_state_setup(struct render_state *so)
>  
>  	so->aux_batch_offset = i * sizeof(u32);
>  
> +	if (HAS_POOLED_EU(dev)) {
> +		u32 pool_config = 0;
> +		struct drm_i915_private *dev_priv = to_i915(dev);

Just a minor, as this would be neater as

		u32 pool_config =
			INTEL_INFO(dev)->subslice_total == 3 ? 0x00777000 : 0;

At the very least keep both paths to set pool_config next to each other,
e.g.
u32 pool_config;
...
pool_config = 0;
if (INTEL_INFO(dev)->subslice_total == 3)
	pool_config = 0x00777000;

Then we just have

> +		OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
> +		OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
> +		OUT_BATCH(d, i, pool_config);
> +		OUT_BATCH(d, i, 0);
> +		OUT_BATCH(d, i, 0);
> +		OUT_BATCH(d, i, 0);

Which is much easier to read.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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[PATCH v3 3/3] drm/i915:bxt: Enable Pooled EU support

[Arun Siluvery]

This mode allows to assign EUs to pools which can process work collectively.
The command to enable this mode should be issued as part of context initialization.

The pooled mode is global, once enabled it has to stay the same across all
contexts until HW reset hence this is sent in auxiliary golden context batch.
Thanks to Mika for the preliminary review and comments.

v2: explain why this is enabled in golden context, use feature flag while
enabling the support (Chris)

v3: Pooled EU support announced in userspace before enabling in kernel,
to simplify include all changes in the same patch.

User space clients need to know when the pooled EU feature is present
and enabled on the hardware so that they can adapt work submissions.
Create a new device info flag for this purpose, and create a new GETPARAM
entry to allow user space to query its setting.

Set has_pooled_eu to true in the Broxton static device info - Broxton
supports the feature in hardware and the driver will enable it by
default.

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Armin Reese <armin.c.reese@intel.com>
Signed-off-by: Jeff McGee <jeff.mcgee@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_dma.c              |  3 +++
 drivers/gpu/drm/i915/i915_drv.c              |  1 +
 drivers/gpu/drm/i915/i915_drv.h              |  5 ++++-
 drivers/gpu/drm/i915/i915_gem_render_state.c | 13 +++++++++++++
 drivers/gpu/drm/i915/i915_reg.h              |  2 ++
 include/uapi/drm/i915_drm.h                  |  1 +
 6 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 5e63076..6c31beb 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -170,6 +170,9 @@ static int i915_getparam(struct drm_device *dev, void *data,
 	case I915_PARAM_HAS_RESOURCE_STREAMER:
 		value = HAS_RESOURCE_STREAMER(dev);
 		break;
+	case I915_PARAM_HAS_POOLED_EU:
+		value = HAS_POOLED_EU(dev);
+		break;
 	default:
 		DRM_DEBUG("Unknown parameter %d\n", param->param);
 		return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e44dc0d..213f74d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -389,6 +389,7 @@ static const struct intel_device_info intel_broxton_info = {
 	.num_pipes = 3,
 	.has_ddi = 1,
 	.has_fbc = 1,
+	.has_pooled_eu = 1,
 	GEN_DEFAULT_PIPEOFFSETS,
 	IVB_CURSOR_OFFSETS,
 };
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 768d1db..32850a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -775,7 +775,8 @@ struct intel_csr {
 	func(supports_tv) sep \
 	func(has_llc) sep \
 	func(has_ddi) sep \
-	func(has_fpga_dbg)
+	func(has_fpga_dbg) sep \
+	func(has_pooled_eu)
 
 #define DEFINE_FLAG(name) u8 name:1
 #define SEP_SEMICOLON ;
@@ -2549,6 +2550,8 @@ struct drm_i915_cmd_table {
 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
 				    INTEL_INFO(dev)->gen >= 8)
 
+#define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
+
 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
 #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
diff --git a/drivers/gpu/drm/i915/i915_gem_render_state.c b/drivers/gpu/drm/i915/i915_gem_render_state.c
index 5026a62..8866040 100644
--- a/drivers/gpu/drm/i915/i915_gem_render_state.c
+++ b/drivers/gpu/drm/i915/i915_gem_render_state.c
@@ -93,6 +93,7 @@ free_gem:
 
 static int render_state_setup(struct render_state *so)
 {
+	struct drm_device *dev = so->obj->base.dev;
 	const struct intel_renderstate_rodata *rodata = so->rodata;
 	unsigned int i = 0, reloc_index = 0;
 	struct page *page;
@@ -134,6 +135,18 @@ static int render_state_setup(struct render_state *so)
 
 	so->aux_batch_offset = i * sizeof(u32);
 
+	if (HAS_POOLED_EU(dev)) {
+		u32 pool_config = (INTEL_INFO(dev)->subslice_total == 3 ?
+				   0x00777000 : 0);
+
+		OUT_BATCH(d, i, GEN9_MEDIA_POOL_STATE);
+		OUT_BATCH(d, i, GEN9_MEDIA_POOL_ENABLE);
+		OUT_BATCH(d, i, pool_config);
+		OUT_BATCH(d, i, 0);
+		OUT_BATCH(d, i, 0);
+		OUT_BATCH(d, i, 0);
+	}
+
 	OUT_BATCH(d, i, MI_BATCH_BUFFER_END);
 	so->aux_batch_size = (i * sizeof(u32)) - so->aux_batch_offset;
 
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9a2ffad..e052499 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -379,6 +379,8 @@
  */
 #define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
 
+#define GEN9_MEDIA_POOL_STATE     ((0x3 << 29) | (0x2 << 27) | (0x5 << 16) | 4)
+#define   GEN9_MEDIA_POOL_ENABLE  (1 << 31)
 #define GFX_OP_RASTER_RULES    ((0x3<<29)|(0x7<<24))
 #define GFX_OP_SCISSOR         ((0x3<<29)|(0x1c<<24)|(0x10<<19))
 #define   SC_UPDATE_SCISSOR       (0x1<<1)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index e7c29f1..9649577 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -356,6 +356,7 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_EU_TOTAL		 34
 #define I915_PARAM_HAS_GPU_RESET	 35
 #define I915_PARAM_HAS_RESOURCE_STREAMER 36
+#define I915_PARAM_HAS_POOLED_EU         37
 
 typedef struct drm_i915_getparam {
 	int param;
-- 
1.9.1

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