All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Souza, Jose" <jose.souza@intel.com>
To: "pebolle@tiscali.nl" <pebolle@tiscali.nl>,
	"James.Bottomley@HansenPartnership.com" 
	<James.Bottomley@HansenPartnership.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"chris@chris-wilson.co.uk" <chris@chris-wilson.co.uk>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [Intel-gfx] screen freeze with 5.2-rc6 Dell XPS-13 skylake i915
Date: Thu, 11 Jul 2019 23:28:26 +0000	[thread overview]
Message-ID: <55f4d1c242d684ca2742e8c14613d810a9ee9504.camel@intel.com> (raw)
In-Reply-To: <2c4edfabf49998eb5da3a6adcabc006eb64bfe90.camel@tiscali.nl>

[-- Attachment #1: Type: text/plain, Size: 1071 bytes --]

On Fri, 2019-07-12 at 01:03 +0200, Paul Bolle wrote:
> James Bottomley schreef op do 11-07-2019 om 15:38 [-0700]:
> > On Thu, 2019-07-11 at 22:26 +0000, Souza, Jose wrote:
> > > It eventually comes back from screen freeze? Like moving the
> > > mouse or
> > > typing brings it back?
> > 
> > No, it seems to be frozen for all time (at least until I got bored
> > waiting, which was probably 20 minutes).  Even if I reboot the
> > machine,
> > the current screen state stays until the system powers off.
> 
> As I mentioned earlier, a suspend/resume cycle unfreezes the screen.
> 
> And I seem to remember that, if the gnome screen-locking eventually
> kicks in,
> unlocking the screen still works, as the screen then isn't frozen
> anymore.
> 
> Thanks,

Thanks for all the information Paul.

Could test with the patch attached?

If the issue happens again could send the output of:

/sys/kernel/debug/dri/0/eDP-1/i915_psr_sink_status
/sys/kernel/debug/dri/0/i915_edp_psr_status

Thanks so much for all the help

> 
> 
> Paul Bolle
> 

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: 0001-hack-drm-i915-psr-Always-set-PSR1-training-times-to-.patch --]
[-- Type: text/x-patch; name="0001-hack-drm-i915-psr-Always-set-PSR1-training-times-to-.patch", Size: 1330 bytes --]

From ee495e2e879e718183d1b65af37393b535eeb966 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= <jose.souza@intel.com>
Date: Thu, 11 Jul 2019 16:19:12 -0700
Subject: [PATCH] hack: drm/i915/psr: Always set PSR1 training times to max
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 963663ba0edf..83ca26e119b6 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -444,6 +444,7 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
 	if (INTEL_GEN(dev_priv) >= 11)
 		val |= EDP_PSR_TP4_TIME_0US;
 
+	/*
 	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)
 		val |= EDP_PSR_TP1_TIME_0us;
 	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)
@@ -461,6 +462,9 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp)
 		val |= EDP_PSR_TP2_TP3_TIME_500us;
 	else
 		val |= EDP_PSR_TP2_TP3_TIME_2500us;
+	*/
+	val |= EDP_PSR_TP1_TIME_2500us;
+	val |= EDP_PSR_TP2_TP3_TIME_2500us;
 
 	if (intel_dp_source_supports_hbr2(intel_dp) &&
 	    drm_dp_tps3_supported(intel_dp->dpcd))
-- 
2.22.0


  reply	other threads:[~2019-07-11 23:28 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-29 18:56 screen freeze with 5.2-rc6 Dell XPS-13 skylake i915 James Bottomley
2019-07-09 13:52 ` Paul Bolle
2019-07-10 15:01 ` James Bottomley
2019-07-10 16:16   ` Paul Bolle
2019-07-10 16:32     ` James Bottomley
2019-07-10 16:32       ` James Bottomley
2019-07-10 16:45       ` Paul Bolle
2019-07-10 16:45         ` Paul Bolle
2019-07-10 17:35         ` James Bottomley
2019-07-10 21:59           ` Paul Bolle
2019-07-10 22:18             ` James Bottomley
2019-07-11 19:32               ` [Intel-gfx] " Souza, Jose
2019-07-11 19:32                 ` Souza, Jose
2019-07-11  9:29 ` Chris Wilson
2019-07-11 11:20   ` Paul Bolle
2019-07-11 11:20     ` Paul Bolle
2019-07-12 10:32     ` Paul Bolle
2019-07-11 20:11   ` James Bottomley
2019-07-11 20:25     ` [Intel-gfx] " Souza, Jose
2019-07-11 20:25       ` Souza, Jose
2019-07-11 20:28       ` [Intel-gfx] " James Bottomley
2019-07-11 21:57         ` James Bottomley
2019-07-11 22:26           ` Souza, Jose
2019-07-11 22:26             ` Souza, Jose
2019-07-11 22:38             ` James Bottomley
2019-07-11 23:03               ` Paul Bolle
2019-07-11 23:28                 ` Souza, Jose [this message]
2019-07-11 23:28                   ` Souza, Jose
2019-07-11 23:40                   ` James Bottomley
2019-07-11 23:40                     ` James Bottomley
2019-07-12 14:19                     ` [Intel-gfx] " James Bottomley
2019-07-12 14:19                       ` James Bottomley
2019-07-12 14:28                       ` [Intel-gfx] " Paul Bolle
2019-07-15 21:03                         ` Souza, Jose
2019-07-15 21:03                           ` Souza, Jose
2019-07-15 21:34                           ` [Intel-gfx] " Paul Bolle
2019-07-15 21:34                             ` Paul Bolle
2019-07-16 16:32                             ` [Intel-gfx] " Souza, Jose
2019-07-16 16:32                               ` Souza, Jose
2019-07-17 21:27                               ` Paul Bolle
2019-07-17 21:27                                 ` Paul Bolle
2019-07-17 21:29                                 ` James Bottomley
2019-07-24 19:23                                   ` Paul Bolle
2019-07-24 20:27                                     ` Souza, Jose
2019-07-24 20:27                                       ` Souza, Jose
2019-07-24 20:39                                       ` [Intel-gfx] " Paul Bolle
2019-07-24 20:39                                         ` Paul Bolle
2019-07-24 20:42                                         ` Souza, Jose
2019-07-24 20:42                                           ` Souza, Jose
2019-08-09 17:16                                         ` Souza, Jose
2019-08-09 17:16                                           ` Souza, Jose
2019-08-10 19:40                                           ` Paul Bolle

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=55f4d1c242d684ca2742e8c14613d810a9ee9504.camel@intel.com \
    --to=jose.souza@intel.com \
    --cc=James.Bottomley@HansenPartnership.com \
    --cc=chris@chris-wilson.co.uk \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=pebolle@tiscali.nl \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.