[PATCH 1/2] drm/i915/bxt: Set oscaledcompmethod to enable scale value

[PATCH 1/2] drm/i915/bxt: Set oscaledcompmethod to enable scale value

[Sonika Jindal]

Bspec update tells that we have to enable oscaledcompmethod instead of
ouniqetrangenmethod for enabling scale value during swing programming.
Also, scale value is 'don't care' for other levels except the last entry
translation table. So, make it 0 instead of 0x9A.

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  |    2 +-
 drivers/gpu/drm/i915/intel_ddi.c |   22 +++++++++++-----------
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 812b7b2..cec6546 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1395,7 +1395,7 @@ enum skl_disp_power_wells {
 #define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
 						     _PORT_TX_DW3_LN0_B,  \
 						     _PORT_TX_DW3_LN0_C)
-#define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
+#define   SCALE_DCOMP_METHOD		(1 << 26)
 
 #define _PORT_TX_DW4_LN0_A		0x162510
 #define _PORT_TX_DW4_LN0_B		0x6C510
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index fec51df..0d9b304 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -261,15 +261,15 @@ struct bxt_ddi_buf_trans {
  */
 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 					/* Idx	NT mV diff	db  */
-	{ 52,  0x9A, 0, 128, true  },	/* 0:	400		0   */
-	{ 78,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
-	{ 104, 0x9A, 0, 64,  false },	/* 2:	400		6   */
-	{ 154, 0x9A, 0, 43,  false },	/* 3:	400		9.5 */
-	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
-	{ 116, 0x9A, 0, 85,  false },	/* 5:	600		3.5 */
-	{ 154, 0x9A, 0, 64,  false },	/* 6:	600		6   */
-	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
-	{ 154, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
+	{ 52,  0, 0, 128, true  },	/* 0:	400		0   */
+	{ 78,  0, 0, 85,  false },	/* 1:	400		3.5 */
+	{ 104, 0, 0, 64,  false },	/* 2:	400		6   */
+	{ 154, 0, 0, 43,  false },	/* 3:	400		9.5 */
+	{ 77,  0, 0, 128, false },	/* 4:	600		0   */
+	{ 116, 0, 0, 85,  false },	/* 5:	600		3.5 */
+	{ 154, 0, 0, 64,  false },	/* 6:	600		6   */
+	{ 102, 0, 0, 128, false },	/* 7:	800		0   */
+	{ 154, 0, 0, 85,  false },	/* 8:	800		3.5 */
 	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
 };
 
@@ -2151,9 +2151,9 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
 	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
 
 	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
-	val &= ~UNIQE_TRANGE_EN_METHOD;
+	val &= ~SCALE_DCOMP_METHOD;
 	if (ddi_translations[level].enable)
-		val |= UNIQE_TRANGE_EN_METHOD;
+		val |= SCALE_DCOMP_METHOD;
 	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
 
 	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
-- 
1.7.10.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 2/2] drm/i915/bxt: eDP low vswing support

[Sonika Jindal]

Adding voltage swing table for edp to support low vswings.

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |   23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 0d9b304..17281bc 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -256,9 +256,6 @@ struct bxt_ddi_buf_trans {
 	bool default_index; /* true if the entry represents default value */
 };
 
-/* BSpec does not define separate vswing/pre-emphasis values for eDP.
- * Using DP values for eDP as well.
- */
 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 					/* Idx	NT mV diff	db  */
 	{ 52,  0, 0, 128, true  },	/* 0:	400		0   */
@@ -273,6 +270,20 @@ static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
 };
 
+static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
+					/* Idx	NT mV diff	db  */
+	{ 26, 0, 0, 128, false },	/* 0:	200		0   */
+	{ 38, 0, 0, 112, false },	/* 1:	200		1.5 */
+	{ 48, 0, 0, 96,  false },	/* 2:	200		4   */
+	{ 54, 0, 0, 69,  false },	/* 3:	200		6   */
+	{ 32, 0, 0, 128, false },	/* 4:	250		0   */
+	{ 48, 0, 0, 104, false },	/* 5:	250		1.5 */
+	{ 54, 0, 0, 85,  false },	/* 6:	250		4   */
+	{ 43, 0, 0, 128, false },	/* 7:	300		0   */
+	{ 54, 0, 0, 101, false },	/* 8:	300		1.5 */
+	{ 48, 0, 0, 128, false },	/* 9:	300		0   */
+};
+
 /* BSpec has 2 recommended values - entries 0 and 8.
  * Using the entry with higher vswing.
  */
@@ -2113,7 +2124,11 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
 	u32 n_entries, i;
 	uint32_t val;
 
-	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
+	if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
+		n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
+		ddi_translations = bxt_ddi_translations_edp;
+	} else if (type == INTEL_OUTPUT_DISPLAYPORT
+			|| type == INTEL_OUTPUT_EDP) {
 		n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 		ddi_translations = bxt_ddi_translations_dp;
 	} else if (type == INTEL_OUTPUT_HDMI) {
-- 
1.7.10.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/2] drm/i915/bxt: Set oscaledcompmethod to enable scale value

[Sivakumar Thulasimani]

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 9/18/2015 2:11 PM, Sonika Jindal wrote:
> Bspec update tells that we have to enable oscaledcompmethod instead of
> ouniqetrangenmethod for enabling scale value during swing programming.
> Also, scale value is 'don't care' for other levels except the last entry
> translation table. So, make it 0 instead of 0x9A.
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h  |    2 +-
>   drivers/gpu/drm/i915/intel_ddi.c |   22 +++++++++++-----------
>   2 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 812b7b2..cec6546 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1395,7 +1395,7 @@ enum skl_disp_power_wells {
>   #define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
>   						     _PORT_TX_DW3_LN0_B,  \
>   						     _PORT_TX_DW3_LN0_C)
> -#define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
> +#define   SCALE_DCOMP_METHOD		(1 << 26)
>   
>   #define _PORT_TX_DW4_LN0_A		0x162510
>   #define _PORT_TX_DW4_LN0_B		0x6C510
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index fec51df..0d9b304 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -261,15 +261,15 @@ struct bxt_ddi_buf_trans {
>    */
>   static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
>   					/* Idx	NT mV diff	db  */
> -	{ 52,  0x9A, 0, 128, true  },	/* 0:	400		0   */
> -	{ 78,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
> -	{ 104, 0x9A, 0, 64,  false },	/* 2:	400		6   */
> -	{ 154, 0x9A, 0, 43,  false },	/* 3:	400		9.5 */
> -	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
> -	{ 116, 0x9A, 0, 85,  false },	/* 5:	600		3.5 */
> -	{ 154, 0x9A, 0, 64,  false },	/* 6:	600		6   */
> -	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
> -	{ 154, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
> +	{ 52,  0, 0, 128, true  },	/* 0:	400		0   */
> +	{ 78,  0, 0, 85,  false },	/* 1:	400		3.5 */
> +	{ 104, 0, 0, 64,  false },	/* 2:	400		6   */
> +	{ 154, 0, 0, 43,  false },	/* 3:	400		9.5 */
> +	{ 77,  0, 0, 128, false },	/* 4:	600		0   */
> +	{ 116, 0, 0, 85,  false },	/* 5:	600		3.5 */
> +	{ 154, 0, 0, 64,  false },	/* 6:	600		6   */
> +	{ 102, 0, 0, 128, false },	/* 7:	800		0   */
> +	{ 154, 0, 0, 85,  false },	/* 8:	800		3.5 */
>   	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
>   };
>   
> @@ -2151,9 +2151,9 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
>   	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
>   
>   	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
> -	val &= ~UNIQE_TRANGE_EN_METHOD;
> +	val &= ~SCALE_DCOMP_METHOD;
>   	if (ddi_translations[level].enable)
> -		val |= UNIQE_TRANGE_EN_METHOD;
> +		val |= SCALE_DCOMP_METHOD;
>   	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
>   
>   	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));

-- 
regards,
Sivakumar

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 2/2] drm/i915/bxt: eDP low vswing support

[Sivakumar Thulasimani]

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

On 9/18/2015 2:11 PM, Sonika Jindal wrote:
> Adding voltage swing table for edp to support low vswings.
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_ddi.c |   23 +++++++++++++++++++----
>   1 file changed, 19 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 0d9b304..17281bc 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -256,9 +256,6 @@ struct bxt_ddi_buf_trans {
>   	bool default_index; /* true if the entry represents default value */
>   };
>   
> -/* BSpec does not define separate vswing/pre-emphasis values for eDP.
> - * Using DP values for eDP as well.
> - */
>   static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
>   					/* Idx	NT mV diff	db  */
>   	{ 52,  0, 0, 128, true  },	/* 0:	400		0   */
> @@ -273,6 +270,20 @@ static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
>   	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
>   };
>   
> +static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
> +					/* Idx	NT mV diff	db  */
> +	{ 26, 0, 0, 128, false },	/* 0:	200		0   */
> +	{ 38, 0, 0, 112, false },	/* 1:	200		1.5 */
> +	{ 48, 0, 0, 96,  false },	/* 2:	200		4   */
> +	{ 54, 0, 0, 69,  false },	/* 3:	200		6   */
> +	{ 32, 0, 0, 128, false },	/* 4:	250		0   */
> +	{ 48, 0, 0, 104, false },	/* 5:	250		1.5 */
> +	{ 54, 0, 0, 85,  false },	/* 6:	250		4   */
> +	{ 43, 0, 0, 128, false },	/* 7:	300		0   */
> +	{ 54, 0, 0, 101, false },	/* 8:	300		1.5 */
> +	{ 48, 0, 0, 128, false },	/* 9:	300		0   */
> +};
> +
>   /* BSpec has 2 recommended values - entries 0 and 8.
>    * Using the entry with higher vswing.
>    */
> @@ -2113,7 +2124,11 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
>   	u32 n_entries, i;
>   	uint32_t val;
>   
> -	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
> +	if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
> +		n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
> +		ddi_translations = bxt_ddi_translations_edp;
> +	} else if (type == INTEL_OUTPUT_DISPLAYPORT
> +			|| type == INTEL_OUTPUT_EDP) {
>   		n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
>   		ddi_translations = bxt_ddi_translations_dp;
>   	} else if (type == INTEL_OUTPUT_HDMI) {

-- 
regards,
Sivakumar

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/2] drm/i915/bxt: Set oscaledcompmethod to enable scale value

[Imre Deak]

On ma, 2015-09-21 at 23:00 +0530, Sivakumar Thulasimani wrote:
> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> 
> On 9/18/2015 2:11 PM, Sonika Jindal wrote:
> > Bspec update tells that we have to enable oscaledcompmethod instead of
> > ouniqetrangenmethod for enabling scale value during swing programming.
> > Also, scale value is 'don't care' for other levels except the last entry
> > translation table. So, make it 0 instead of 0x9A.
> >
> > Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_reg.h  |    2 +-
> >   drivers/gpu/drm/i915/intel_ddi.c |   22 +++++++++++-----------
> >   2 files changed, 12 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 812b7b2..cec6546 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1395,7 +1395,7 @@ enum skl_disp_power_wells {
> >   #define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
> >   						     _PORT_TX_DW3_LN0_B,  \
> >   						     _PORT_TX_DW3_LN0_C)
> > -#define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
> > +#define   SCALE_DCOMP_METHOD		(1 << 26)
> >   
> >   #define _PORT_TX_DW4_LN0_A		0x162510
> >   #define _PORT_TX_DW4_LN0_B		0x6C510
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index fec51df..0d9b304 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -261,15 +261,15 @@ struct bxt_ddi_buf_trans {
> >    */
> >   static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
> >   					/* Idx	NT mV diff	db  */
> > -	{ 52,  0x9A, 0, 128, true  },	/* 0:	400		0   */
> > -	{ 78,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
> > -	{ 104, 0x9A, 0, 64,  false },	/* 2:	400		6   */
> > -	{ 154, 0x9A, 0, 43,  false },	/* 3:	400		9.5 */
> > -	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
> > -	{ 116, 0x9A, 0, 85,  false },	/* 5:	600		3.5 */
> > -	{ 154, 0x9A, 0, 64,  false },	/* 6:	600		6   */
> > -	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
> > -	{ 154, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
> > +	{ 52,  0, 0, 128, true  },	/* 0:	400		0   */
> > +	{ 78,  0, 0, 85,  false },	/* 1:	400		3.5 */
> > +	{ 104, 0, 0, 64,  false },	/* 2:	400		6   */
> > +	{ 154, 0, 0, 43,  false },	/* 3:	400		9.5 */
> > +	{ 77,  0, 0, 128, false },	/* 4:	600		0   */
> > +	{ 116, 0, 0, 85,  false },	/* 5:	600		3.5 */
> > +	{ 154, 0, 0, 64,  false },	/* 6:	600		6   */
> > +	{ 102, 0, 0, 128, false },	/* 7:	800		0   */
> > +	{ 154, 0, 0, 85,  false },	/* 8:	800		3.5 */

There is no point in changing the above values as they are don't-care in
any case. In fact the reset value is 0x98 so I'd program that for these
cases if we ever wanted to change them. For now I'd leave this as-is to
keep in sync with the bxt_ddi_translations_hdmi table and also what CHV
does.

> >   	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
> >   };


> >   
> > @@ -2151,9 +2151,9 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
> >   	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
> >   
> >   	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
> > -	val &= ~UNIQE_TRANGE_EN_METHOD;
> > +	val &= ~SCALE_DCOMP_METHOD;
> >   	if (ddi_translations[level].enable)
> > -		val |= UNIQE_TRANGE_EN_METHOD;
> > +		val |= SCALE_DCOMP_METHOD;

Please still leave behind a DRM_ERROR in case UNIQE_TRANGE_EN_METHOD was
set in the register and we are disabling scaling. The scaling value does
seem to depend on this bit too, so seeing if it was set can help
tracking down problems.

> >   	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
> >   
> >   	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
> 


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/2] drm/i915/bxt: Set oscaledcompmethod to enable scale value

[Sivakumar Thulasimani]

On 9/22/2015 6:32 PM, Imre Deak wrote:
> On ma, 2015-09-21 at 23:00 +0530, Sivakumar Thulasimani wrote:
>> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
>>
>> On 9/18/2015 2:11 PM, Sonika Jindal wrote:
>>> Bspec update tells that we have to enable oscaledcompmethod instead of
>>> ouniqetrangenmethod for enabling scale value during swing programming.
>>> Also, scale value is 'don't care' for other levels except the last entry
>>> translation table. So, make it 0 instead of 0x9A.
>>>
>>> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/i915_reg.h  |    2 +-
>>>    drivers/gpu/drm/i915/intel_ddi.c |   22 +++++++++++-----------
>>>    2 files changed, 12 insertions(+), 12 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>> index 812b7b2..cec6546 100644
>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>> @@ -1395,7 +1395,7 @@ enum skl_disp_power_wells {
>>>    #define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
>>>    						     _PORT_TX_DW3_LN0_B,  \
>>>    						     _PORT_TX_DW3_LN0_C)
>>> -#define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
>>> +#define   SCALE_DCOMP_METHOD		(1 << 26)
>>>    
>>>    #define _PORT_TX_DW4_LN0_A		0x162510
>>>    #define _PORT_TX_DW4_LN0_B		0x6C510
>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>>> index fec51df..0d9b304 100644
>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>>> @@ -261,15 +261,15 @@ struct bxt_ddi_buf_trans {
>>>     */
>>>    static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
>>>    					/* Idx	NT mV diff	db  */
>>> -	{ 52,  0x9A, 0, 128, true  },	/* 0:	400		0   */
>>> -	{ 78,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
>>> -	{ 104, 0x9A, 0, 64,  false },	/* 2:	400		6   */
>>> -	{ 154, 0x9A, 0, 43,  false },	/* 3:	400		9.5 */
>>> -	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
>>> -	{ 116, 0x9A, 0, 85,  false },	/* 5:	600		3.5 */
>>> -	{ 154, 0x9A, 0, 64,  false },	/* 6:	600		6   */
>>> -	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
>>> -	{ 154, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
>>> +	{ 52,  0, 0, 128, true  },	/* 0:	400		0   */
>>> +	{ 78,  0, 0, 85,  false },	/* 1:	400		3.5 */
>>> +	{ 104, 0, 0, 64,  false },	/* 2:	400		6   */
>>> +	{ 154, 0, 0, 43,  false },	/* 3:	400		9.5 */
>>> +	{ 77,  0, 0, 128, false },	/* 4:	600		0   */
>>> +	{ 116, 0, 0, 85,  false },	/* 5:	600		3.5 */
>>> +	{ 154, 0, 0, 64,  false },	/* 6:	600		6   */
>>> +	{ 102, 0, 0, 128, false },	/* 7:	800		0   */
>>> +	{ 154, 0, 0, 85,  false },	/* 8:	800		3.5 */
> There is no point in changing the above values as they are don't-care in
> any case. In fact the reset value is 0x98 so I'd program that for these
> cases if we ever wanted to change them. For now I'd leave this as-is to
> keep in sync with the bxt_ddi_translations_hdmi table and also what CHV
> does.
>
>>>    	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
>>>    };
>
>>>    
>>> @@ -2151,9 +2151,9 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
>>>    	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
>>>    
>>>    	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
>>> -	val &= ~UNIQE_TRANGE_EN_METHOD;
>>> +	val &= ~SCALE_DCOMP_METHOD;
>>>    	if (ddi_translations[level].enable)
>>> -		val |= UNIQE_TRANGE_EN_METHOD;
>>> +		val |= SCALE_DCOMP_METHOD;
> Please still leave behind a DRM_ERROR in case UNIQE_TRANGE_EN_METHOD was
> set in the register and we are disabling scaling. The scaling value does
> seem to depend on this bit too, so seeing if it was set can help
> tracking down problems.
>
This was the only place UNIQE_TRANGE_EN_METHOD was set before, with that 
removed
only possibility for it to be set is by GOP/VBIOS. (who are also 
expected to make this change
if not done already.) in such a scenario wont an error message be 
useless here ?
>>>    	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
>>>    
>>>    	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
>
>
>


-- 
regards,
Sivakumar


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/2] drm/i915/bxt: Set oscaledcompmethod to enable scale value

[Imre Deak]

On Wed, 2015-09-23 at 00:01 +0530, Sivakumar Thulasimani wrote:
> 
> On 9/22/2015 6:32 PM, Imre Deak wrote:
> > On ma, 2015-09-21 at 23:00 +0530, Sivakumar Thulasimani wrote:
> >> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> >>
> >> On 9/18/2015 2:11 PM, Sonika Jindal wrote:
> >>> Bspec update tells that we have to enable oscaledcompmethod instead of
> >>> ouniqetrangenmethod for enabling scale value during swing programming.
> >>> Also, scale value is 'don't care' for other levels except the last entry
> >>> translation table. So, make it 0 instead of 0x9A.
> >>>
> >>> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> >>> ---
> >>>    drivers/gpu/drm/i915/i915_reg.h  |    2 +-
> >>>    drivers/gpu/drm/i915/intel_ddi.c |   22 +++++++++++-----------
> >>>    2 files changed, 12 insertions(+), 12 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >>> index 812b7b2..cec6546 100644
> >>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>> @@ -1395,7 +1395,7 @@ enum skl_disp_power_wells {
> >>>    #define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
> >>>    						     _PORT_TX_DW3_LN0_B,  \
> >>>    						     _PORT_TX_DW3_LN0_C)
> >>> -#define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
> >>> +#define   SCALE_DCOMP_METHOD		(1 << 26)
> >>>    
> >>>    #define _PORT_TX_DW4_LN0_A		0x162510
> >>>    #define _PORT_TX_DW4_LN0_B		0x6C510
> >>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> >>> index fec51df..0d9b304 100644
> >>> --- a/drivers/gpu/drm/i915/intel_ddi.c
> >>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> >>> @@ -261,15 +261,15 @@ struct bxt_ddi_buf_trans {
> >>>     */
> >>>    static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
> >>>    					/* Idx	NT mV diff	db  */
> >>> -	{ 52,  0x9A, 0, 128, true  },	/* 0:	400		0   */
> >>> -	{ 78,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
> >>> -	{ 104, 0x9A, 0, 64,  false },	/* 2:	400		6   */
> >>> -	{ 154, 0x9A, 0, 43,  false },	/* 3:	400		9.5 */
> >>> -	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
> >>> -	{ 116, 0x9A, 0, 85,  false },	/* 5:	600		3.5 */
> >>> -	{ 154, 0x9A, 0, 64,  false },	/* 6:	600		6   */
> >>> -	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
> >>> -	{ 154, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
> >>> +	{ 52,  0, 0, 128, true  },	/* 0:	400		0   */
> >>> +	{ 78,  0, 0, 85,  false },	/* 1:	400		3.5 */
> >>> +	{ 104, 0, 0, 64,  false },	/* 2:	400		6   */
> >>> +	{ 154, 0, 0, 43,  false },	/* 3:	400		9.5 */
> >>> +	{ 77,  0, 0, 128, false },	/* 4:	600		0   */
> >>> +	{ 116, 0, 0, 85,  false },	/* 5:	600		3.5 */
> >>> +	{ 154, 0, 0, 64,  false },	/* 6:	600		6   */
> >>> +	{ 102, 0, 0, 128, false },	/* 7:	800		0   */
> >>> +	{ 154, 0, 0, 85,  false },	/* 8:	800		3.5 */
> > There is no point in changing the above values as they are don't-care in
> > any case. In fact the reset value is 0x98 so I'd program that for these
> > cases if we ever wanted to change them. For now I'd leave this as-is to
> > keep in sync with the bxt_ddi_translations_hdmi table and also what CHV
> > does.
> >
> >>>    	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
> >>>    };
> >
> >>>    
> >>> @@ -2151,9 +2151,9 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
> >>>    	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
> >>>    
> >>>    	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
> >>> -	val &= ~UNIQE_TRANGE_EN_METHOD;
> >>> +	val &= ~SCALE_DCOMP_METHOD;
> >>>    	if (ddi_translations[level].enable)
> >>> -		val |= UNIQE_TRANGE_EN_METHOD;
> >>> +		val |= SCALE_DCOMP_METHOD;
> > Please still leave behind a DRM_ERROR in case UNIQE_TRANGE_EN_METHOD was
> > set in the register and we are disabling scaling. The scaling value does
> > seem to depend on this bit too, so seeing if it was set can help
> > tracking down problems.
> >
> This was the only place UNIQE_TRANGE_EN_METHOD was set before, with that 
> removed
> only possibility for it to be set is by GOP/VBIOS. (who are also 
> expected to make this change
> if not done already.) in such a scenario wont an error message be 
> useless here ?

Yes, this is exactly a check for BIOS settings. It wouldn't be the first
case that BIOS didn't program something according to our expectations,
especially given the multiple versions out there. 

> >>>    	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
> >>>    
> >>>    	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
> >
> >
> >
> 
> 


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/2] drm/i915/bxt: Set oscaledcompmethod to enable scale value

[Jindal, Sonika]

On 9/23/2015 1:02 AM, Imre Deak wrote:
> On Wed, 2015-09-23 at 00:01 +0530, Sivakumar Thulasimani wrote:
>>
>> On 9/22/2015 6:32 PM, Imre Deak wrote:
>>> On ma, 2015-09-21 at 23:00 +0530, Sivakumar Thulasimani wrote:
>>>> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
>>>>
>>>> On 9/18/2015 2:11 PM, Sonika Jindal wrote:
>>>>> Bspec update tells that we have to enable oscaledcompmethod instead of
>>>>> ouniqetrangenmethod for enabling scale value during swing programming.
>>>>> Also, scale value is 'don't care' for other levels except the last entry
>>>>> translation table. So, make it 0 instead of 0x9A.
>>>>>
>>>>> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
>>>>> ---
>>>>>     drivers/gpu/drm/i915/i915_reg.h  |    2 +-
>>>>>     drivers/gpu/drm/i915/intel_ddi.c |   22 +++++++++++-----------
>>>>>     2 files changed, 12 insertions(+), 12 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>>>>> index 812b7b2..cec6546 100644
>>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
>>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>>>>> @@ -1395,7 +1395,7 @@ enum skl_disp_power_wells {
>>>>>     #define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
>>>>>     						     _PORT_TX_DW3_LN0_B,  \
>>>>>     						     _PORT_TX_DW3_LN0_C)
>>>>> -#define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
>>>>> +#define   SCALE_DCOMP_METHOD		(1 << 26)
>>>>>
>>>>>     #define _PORT_TX_DW4_LN0_A		0x162510
>>>>>     #define _PORT_TX_DW4_LN0_B		0x6C510
>>>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
>>>>> index fec51df..0d9b304 100644
>>>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
>>>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
>>>>> @@ -261,15 +261,15 @@ struct bxt_ddi_buf_trans {
>>>>>      */
>>>>>     static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
>>>>>     					/* Idx	NT mV diff	db  */
>>>>> -	{ 52,  0x9A, 0, 128, true  },	/* 0:	400		0   */
>>>>> -	{ 78,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
>>>>> -	{ 104, 0x9A, 0, 64,  false },	/* 2:	400		6   */
>>>>> -	{ 154, 0x9A, 0, 43,  false },	/* 3:	400		9.5 */
>>>>> -	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
>>>>> -	{ 116, 0x9A, 0, 85,  false },	/* 5:	600		3.5 */
>>>>> -	{ 154, 0x9A, 0, 64,  false },	/* 6:	600		6   */
>>>>> -	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
>>>>> -	{ 154, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
>>>>> +	{ 52,  0, 0, 128, true  },	/* 0:	400		0   */
>>>>> +	{ 78,  0, 0, 85,  false },	/* 1:	400		3.5 */
>>>>> +	{ 104, 0, 0, 64,  false },	/* 2:	400		6   */
>>>>> +	{ 154, 0, 0, 43,  false },	/* 3:	400		9.5 */
>>>>> +	{ 77,  0, 0, 128, false },	/* 4:	600		0   */
>>>>> +	{ 116, 0, 0, 85,  false },	/* 5:	600		3.5 */
>>>>> +	{ 154, 0, 0, 64,  false },	/* 6:	600		6   */
>>>>> +	{ 102, 0, 0, 128, false },	/* 7:	800		0   */
>>>>> +	{ 154, 0, 0, 85,  false },	/* 8:	800		3.5 */
>>> There is no point in changing the above values as they are don't-care in
>>> any case. In fact the reset value is 0x98 so I'd program that for these
>>> cases if we ever wanted to change them. For now I'd leave this as-is to
>>> keep in sync with the bxt_ddi_translations_hdmi table and also what CHV
>>> does.
>>>
Now it doesn't make a difference after we have set the oscalecompmethod 
correctly. But when we were not doing that, this 'don't care' value was 
making a difference. It was being considered.
I am sure of this because with low vswing table, only when I added 0x9A, 
it worked for me because we were not unsetting the oscaledcompmenthod.

So, I think its better to reset it to some value other than 0x9A.
Regarding 0x98 being the reset value, is it mentioned in bspec? I 
couldn't find that in the table. If that is the case, we can make it 
0x98 instead of 0x9A.

>>>>>     	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
>>>>>     };
>>>
>>>>>
>>>>> @@ -2151,9 +2151,9 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
>>>>>     	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
>>>>>
>>>>>     	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
>>>>> -	val &= ~UNIQE_TRANGE_EN_METHOD;
>>>>> +	val &= ~SCALE_DCOMP_METHOD;
>>>>>     	if (ddi_translations[level].enable)
>>>>> -		val |= UNIQE_TRANGE_EN_METHOD;
>>>>> +		val |= SCALE_DCOMP_METHOD;
>>> Please still leave behind a DRM_ERROR in case UNIQE_TRANGE_EN_METHOD was
>>> set in the register and we are disabling scaling. The scaling value does
>>> seem to depend on this bit too, so seeing if it was set can help
>>> tracking down problems.
>>>
Again, I couldn't find it mentioned anywhere that scaling value depends 
on "ouniqetrangenmethod" ? Is it in bspec?
Although it does seem to make a difference in case of low vswing table.
With default table, it edp continues to work if set or not set this bit.
I will add back the unsetting of this bit and then setting of this bit 
when 'enable' is set.

Regards,
Sonik
>> This was the only place UNIQE_TRANGE_EN_METHOD was set before, with that
>> removed
>> only possibility for it to be set is by GOP/VBIOS. (who are also
>> expected to make this change
>> if not done already.) in such a scenario wont an error message be
>> useless here ?
>
> Yes, this is exactly a check for BIOS settings. It wouldn't be the first
> case that BIOS didn't program something according to our expectations,
> especially given the multiple versions out there.
>
>>>>>     	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
>>>>>
>>>>>     	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
>>>
>>>
>>>
>>
>>
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/2] drm/i915/bxt: Set oscaledcompmethod to enable scale value

[Imre Deak]

On ke, 2015-09-23 at 09:37 +0530, Jindal, Sonika wrote:
> 
> On 9/23/2015 1:02 AM, Imre Deak wrote:
> > On Wed, 2015-09-23 at 00:01 +0530, Sivakumar Thulasimani wrote:
> >>
> >> On 9/22/2015 6:32 PM, Imre Deak wrote:
> >>> On ma, 2015-09-21 at 23:00 +0530, Sivakumar Thulasimani wrote:
> >>>> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
> >>>>
> >>>> On 9/18/2015 2:11 PM, Sonika Jindal wrote:
> >>>>> Bspec update tells that we have to enable oscaledcompmethod instead of
> >>>>> ouniqetrangenmethod for enabling scale value during swing programming.
> >>>>> Also, scale value is 'don't care' for other levels except the last entry
> >>>>> translation table. So, make it 0 instead of 0x9A.
> >>>>>
> >>>>> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> >>>>> ---
> >>>>>     drivers/gpu/drm/i915/i915_reg.h  |    2 +-
> >>>>>     drivers/gpu/drm/i915/intel_ddi.c |   22 +++++++++++-----------
> >>>>>     2 files changed, 12 insertions(+), 12 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >>>>> index 812b7b2..cec6546 100644
> >>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>>>> @@ -1395,7 +1395,7 @@ enum skl_disp_power_wells {
> >>>>>     #define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
> >>>>>     						     _PORT_TX_DW3_LN0_B,  \
> >>>>>     						     _PORT_TX_DW3_LN0_C)
> >>>>> -#define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
> >>>>> +#define   SCALE_DCOMP_METHOD		(1 << 26)
> >>>>>
> >>>>>     #define _PORT_TX_DW4_LN0_A		0x162510
> >>>>>     #define _PORT_TX_DW4_LN0_B		0x6C510
> >>>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> >>>>> index fec51df..0d9b304 100644
> >>>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
> >>>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> >>>>> @@ -261,15 +261,15 @@ struct bxt_ddi_buf_trans {
> >>>>>      */
> >>>>>     static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
> >>>>>     					/* Idx	NT mV diff	db  */
> >>>>> -	{ 52,  0x9A, 0, 128, true  },	/* 0:	400		0   */
> >>>>> -	{ 78,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
> >>>>> -	{ 104, 0x9A, 0, 64,  false },	/* 2:	400		6   */
> >>>>> -	{ 154, 0x9A, 0, 43,  false },	/* 3:	400		9.5 */
> >>>>> -	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
> >>>>> -	{ 116, 0x9A, 0, 85,  false },	/* 5:	600		3.5 */
> >>>>> -	{ 154, 0x9A, 0, 64,  false },	/* 6:	600		6   */
> >>>>> -	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
> >>>>> -	{ 154, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
> >>>>> +	{ 52,  0, 0, 128, true  },	/* 0:	400		0   */
> >>>>> +	{ 78,  0, 0, 85,  false },	/* 1:	400		3.5 */
> >>>>> +	{ 104, 0, 0, 64,  false },	/* 2:	400		6   */
> >>>>> +	{ 154, 0, 0, 43,  false },	/* 3:	400		9.5 */
> >>>>> +	{ 77,  0, 0, 128, false },	/* 4:	600		0   */
> >>>>> +	{ 116, 0, 0, 85,  false },	/* 5:	600		3.5 */
> >>>>> +	{ 154, 0, 0, 64,  false },	/* 6:	600		6   */
> >>>>> +	{ 102, 0, 0, 128, false },	/* 7:	800		0   */
> >>>>> +	{ 154, 0, 0, 85,  false },	/* 8:	800		3.5 */
> >>> There is no point in changing the above values as they are don't-care in
> >>> any case. In fact the reset value is 0x98 so I'd program that for these
> >>> cases if we ever wanted to change them. For now I'd leave this as-is to
> >>> keep in sync with the bxt_ddi_translations_hdmi table and also what CHV
> >>> does.
> >>>
> Now it doesn't make a difference after we have set the oscalecompmethod 
> correctly. But when we were not doing that, this 'don't care' value was 
> making a difference. It was being considered.
> I am sure of this because with low vswing table, only when I added 0x9A, 
> it worked for me because we were not unsetting the oscaledcompmenthod.

Yes, that's expected. BIOS has set oscaledcompmethod and the driver
didn't change it, so it remained set. With that bit set the scale value
does matter, so setting the scale value to zero (or some other low
value) will definitely not work.

> So, I think its better to reset it to some value other than 0x9A.

It wouldn't make sense based on the updated Bspec and test results. It
would also be different from what we do for HDMI and CHV (which has the
same PHY) again without any explanation.

> Regarding 0x98 being the reset value, is it mentioned in bspec?

You can check this by reading out the register right after toggling the
relevant power well. Bspec doesn't seem to provide the reset values for
any of the PHY registers.

> I couldn't find that in the table. If that is the case, we can make it 
> 0x98 instead of 0x9A.

I wouldn't change these values for now. If in the future testing shows
that these values matter even if both oscaledcompmethod and
ouniqetrangenmethod is clear, we could change them in a separate patch
explaining the reason for the change, considering also HDMI and other
platforms (CHV). Also we should then get an explanation from the HW
people why things don't work according to the specification.

> >>>>>     	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
> >>>>>     };
> >>>
> >>>>>
> >>>>> @@ -2151,9 +2151,9 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
> >>>>>     	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
> >>>>>
> >>>>>     	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
> >>>>> -	val &= ~UNIQE_TRANGE_EN_METHOD;
> >>>>> +	val &= ~SCALE_DCOMP_METHOD;
> >>>>>     	if (ddi_translations[level].enable)
> >>>>> -		val |= UNIQE_TRANGE_EN_METHOD;
> >>>>> +		val |= SCALE_DCOMP_METHOD;
> >>> Please still leave behind a DRM_ERROR in case UNIQE_TRANGE_EN_METHOD was
> >>> set in the register and we are disabling scaling. The scaling value does
> >>> seem to depend on this bit too, so seeing if it was set can help
> >>> tracking down problems.
> >>>
> Again, I couldn't find it mentioned anywhere that scaling value depends 
> on "ouniqetrangenmethod" ? Is it in bspec?

This can be seen just by setting ouniqetrangenmethod and leaving
oscaledcompmethod clear. Setting a low scale value in this case will
result in no valid signal and blank screen.

> Although it does seem to make a difference in case of low vswing table.
> With default table, it edp continues to work if set or not set this bit.
> I will add back the unsetting of this bit and then setting of this bit 
> when 'enable' is set.

According to Bspec we should do an RMW on this register and don't change
ouniqetrangenmethod. So I wouldn't set or clear it, but have the check
and DRM_ERROR in case BIOS has set it for some reason (maybe old/buggy
BIOS) which could help understanding if things don't work.

--Imre

> Regards,
> Sonik
> >> This was the only place UNIQE_TRANGE_EN_METHOD was set before, with that
> >> removed
> >> only possibility for it to be set is by GOP/VBIOS. (who are also
> >> expected to make this change
> >> if not done already.) in such a scenario wont an error message be
> >> useless here ?
> >
> > Yes, this is exactly a check for BIOS settings. It wouldn't be the first
> > case that BIOS didn't program something according to our expectations,
> > especially given the multiple versions out there.
> >
> >>>>>     	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
> >>>>>
> >>>>>     	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
> >>>
> >>>
> >>>
> >>
> >>
> >
> >


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] drm/i915/bxt: Set oscaledcompmethod to enable scale value

[Sonika Jindal]

Bspec update tells that we have to enable oscaledcompmethod instead of
ouniqetrangenmethod for enabling scale value during swing programming.

v2: Adding back 'don't care' values to bxt_ddi_translations_dp and add
error message if ouniquetrangemethod was set (Imre)

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>(v1)
---
 drivers/gpu/drm/i915/i915_reg.h  |    3 ++-
 drivers/gpu/drm/i915/intel_ddi.c |    8 ++++++--
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 812b7b2..3f2135d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1395,7 +1395,8 @@ enum skl_disp_power_wells {
 #define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
 						     _PORT_TX_DW3_LN0_B,  \
 						     _PORT_TX_DW3_LN0_C)
-#define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
+#define   SCALE_DCOMP_METHOD		(1 << 26)
+#define   UNIQUE_TRANGE_EN_METHOD	(1 << 27)
 
 #define _PORT_TX_DW4_LN0_A		0x162510
 #define _PORT_TX_DW4_LN0_B		0x6C510
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index fec51df..7705bc9 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2151,9 +2151,13 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
 	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
 
 	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
-	val &= ~UNIQE_TRANGE_EN_METHOD;
+	val &= ~SCALE_DCOMP_METHOD;
 	if (ddi_translations[level].enable)
-		val |= UNIQE_TRANGE_EN_METHOD;
+		val |= SCALE_DCOMP_METHOD;
+
+	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
+		DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
+
 	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
 
 	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
-- 
1.7.10.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH] drm/i915/bxt: eDP low vswing support

[Sonika Jindal]

Adding voltage swing table for edp to support low vswings.

v2: Rebased.

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c |   23 +++++++++++++++++++----
 1 file changed, 19 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 7705bc9..4be1c2b 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -256,9 +256,6 @@ struct bxt_ddi_buf_trans {
 	bool default_index; /* true if the entry represents default value */
 };
 
-/* BSpec does not define separate vswing/pre-emphasis values for eDP.
- * Using DP values for eDP as well.
- */
 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 					/* Idx	NT mV diff	db  */
 	{ 52,  0x9A, 0, 128, true  },	/* 0:	400		0   */
@@ -273,6 +270,20 @@ static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
 };
 
+static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
+					/* Idx	NT mV diff	db  */
+	{ 26, 0, 0, 128, false },	/* 0:	200		0   */
+	{ 38, 0, 0, 112, false },	/* 1:	200		1.5 */
+	{ 48, 0, 0, 96,  false },	/* 2:	200		4   */
+	{ 54, 0, 0, 69,  false },	/* 3:	200		6   */
+	{ 32, 0, 0, 128, false },	/* 4:	250		0   */
+	{ 48, 0, 0, 104, false },	/* 5:	250		1.5 */
+	{ 54, 0, 0, 85,  false },	/* 6:	250		4   */
+	{ 43, 0, 0, 128, false },	/* 7:	300		0   */
+	{ 54, 0, 0, 101, false },	/* 8:	300		1.5 */
+	{ 48, 0, 0, 128, false },	/* 9:	300		0   */
+};
+
 /* BSpec has 2 recommended values - entries 0 and 8.
  * Using the entry with higher vswing.
  */
@@ -2113,7 +2124,11 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
 	u32 n_entries, i;
 	uint32_t val;
 
-	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
+	if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
+		n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
+		ddi_translations = bxt_ddi_translations_edp;
+	} else if (type == INTEL_OUTPUT_DISPLAYPORT
+			|| type == INTEL_OUTPUT_EDP) {
 		n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 		ddi_translations = bxt_ddi_translations_dp;
 	} else if (type == INTEL_OUTPUT_HDMI) {
-- 
1.7.10.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/2] drm/i915/bxt: Set oscaledcompmethod to enable scale value

[Jindal, Sonika]

Thanks Imre for the explanation.
I will repost the patch..

Regards,
Sonika

-----Original Message-----
From: Deak, Imre 
Sent: Wednesday, September 23, 2015 5:15 PM
To: Jindal, Sonika
Cc: Thulasimani, Sivakumar; intel-gfx@lists.freedesktop.org; Ville Syrjälä
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915/bxt: Set oscaledcompmethod to enable scale value

On ke, 2015-09-23 at 09:37 +0530, Jindal, Sonika wrote:
> 
> On 9/23/2015 1:02 AM, Imre Deak wrote:
> > On Wed, 2015-09-23 at 00:01 +0530, Sivakumar Thulasimani wrote:
> >>
> >> On 9/22/2015 6:32 PM, Imre Deak wrote:
> >>> On ma, 2015-09-21 at 23:00 +0530, Sivakumar Thulasimani wrote:
> >>>> Reviewed-by: Sivakumar Thulasimani 
> >>>> <sivakumar.thulasimani@intel.com>
> >>>>
> >>>> On 9/18/2015 2:11 PM, Sonika Jindal wrote:
> >>>>> Bspec update tells that we have to enable oscaledcompmethod 
> >>>>> instead of ouniqetrangenmethod for enabling scale value during swing programming.
> >>>>> Also, scale value is 'don't care' for other levels except the 
> >>>>> last entry translation table. So, make it 0 instead of 0x9A.
> >>>>>
> >>>>> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> >>>>> ---
> >>>>>     drivers/gpu/drm/i915/i915_reg.h  |    2 +-
> >>>>>     drivers/gpu/drm/i915/intel_ddi.c |   22 +++++++++++-----------
> >>>>>     2 files changed, 12 insertions(+), 12 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/gpu/drm/i915/i915_reg.h 
> >>>>> b/drivers/gpu/drm/i915/i915_reg.h index 812b7b2..cec6546 100644
> >>>>> --- a/drivers/gpu/drm/i915/i915_reg.h
> >>>>> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >>>>> @@ -1395,7 +1395,7 @@ enum skl_disp_power_wells {
> >>>>>     #define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
> >>>>>     						     _PORT_TX_DW3_LN0_B,  \
> >>>>>     						     _PORT_TX_DW3_LN0_C)
> >>>>> -#define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
> >>>>> +#define   SCALE_DCOMP_METHOD		(1 << 26)
> >>>>>
> >>>>>     #define _PORT_TX_DW4_LN0_A		0x162510
> >>>>>     #define _PORT_TX_DW4_LN0_B		0x6C510
> >>>>> diff --git a/drivers/gpu/drm/i915/intel_ddi.c 
> >>>>> b/drivers/gpu/drm/i915/intel_ddi.c
> >>>>> index fec51df..0d9b304 100644
> >>>>> --- a/drivers/gpu/drm/i915/intel_ddi.c
> >>>>> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> >>>>> @@ -261,15 +261,15 @@ struct bxt_ddi_buf_trans {
> >>>>>      */
> >>>>>     static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
> >>>>>     					/* Idx	NT mV diff	db  */
> >>>>> -	{ 52,  0x9A, 0, 128, true  },	/* 0:	400		0   */
> >>>>> -	{ 78,  0x9A, 0, 85,  false },	/* 1:	400		3.5 */
> >>>>> -	{ 104, 0x9A, 0, 64,  false },	/* 2:	400		6   */
> >>>>> -	{ 154, 0x9A, 0, 43,  false },	/* 3:	400		9.5 */
> >>>>> -	{ 77,  0x9A, 0, 128, false },	/* 4:	600		0   */
> >>>>> -	{ 116, 0x9A, 0, 85,  false },	/* 5:	600		3.5 */
> >>>>> -	{ 154, 0x9A, 0, 64,  false },	/* 6:	600		6   */
> >>>>> -	{ 102, 0x9A, 0, 128, false },	/* 7:	800		0   */
> >>>>> -	{ 154, 0x9A, 0, 85,  false },	/* 8:	800		3.5 */
> >>>>> +	{ 52,  0, 0, 128, true  },	/* 0:	400		0   */
> >>>>> +	{ 78,  0, 0, 85,  false },	/* 1:	400		3.5 */
> >>>>> +	{ 104, 0, 0, 64,  false },	/* 2:	400		6   */
> >>>>> +	{ 154, 0, 0, 43,  false },	/* 3:	400		9.5 */
> >>>>> +	{ 77,  0, 0, 128, false },	/* 4:	600		0   */
> >>>>> +	{ 116, 0, 0, 85,  false },	/* 5:	600		3.5 */
> >>>>> +	{ 154, 0, 0, 64,  false },	/* 6:	600		6   */
> >>>>> +	{ 102, 0, 0, 128, false },	/* 7:	800		0   */
> >>>>> +	{ 154, 0, 0, 85,  false },	/* 8:	800		3.5 */
> >>> There is no point in changing the above values as they are 
> >>> don't-care in any case. In fact the reset value is 0x98 so I'd 
> >>> program that for these cases if we ever wanted to change them. For 
> >>> now I'd leave this as-is to keep in sync with the 
> >>> bxt_ddi_translations_hdmi table and also what CHV does.
> >>>
> Now it doesn't make a difference after we have set the 
> oscalecompmethod correctly. But when we were not doing that, this 
> 'don't care' value was making a difference. It was being considered.
> I am sure of this because with low vswing table, only when I added 
> 0x9A, it worked for me because we were not unsetting the oscaledcompmenthod.

Yes, that's expected. BIOS has set oscaledcompmethod and the driver didn't change it, so it remained set. With that bit set the scale value does matter, so setting the scale value to zero (or some other low
value) will definitely not work.

> So, I think its better to reset it to some value other than 0x9A.

It wouldn't make sense based on the updated Bspec and test results. It would also be different from what we do for HDMI and CHV (which has the same PHY) again without any explanation.

> Regarding 0x98 being the reset value, is it mentioned in bspec?

You can check this by reading out the register right after toggling the relevant power well. Bspec doesn't seem to provide the reset values for any of the PHY registers.

> I couldn't find that in the table. If that is the case, we can make it
> 0x98 instead of 0x9A.

I wouldn't change these values for now. If in the future testing shows that these values matter even if both oscaledcompmethod and ouniqetrangenmethod is clear, we could change them in a separate patch explaining the reason for the change, considering also HDMI and other platforms (CHV). Also we should then get an explanation from the HW people why things don't work according to the specification.

> >>>>>     	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
> >>>>>     };
> >>>
> >>>>>
> >>>>> @@ -2151,9 +2151,9 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
> >>>>>     	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
> >>>>>
> >>>>>     	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
> >>>>> -	val &= ~UNIQE_TRANGE_EN_METHOD;
> >>>>> +	val &= ~SCALE_DCOMP_METHOD;
> >>>>>     	if (ddi_translations[level].enable)
> >>>>> -		val |= UNIQE_TRANGE_EN_METHOD;
> >>>>> +		val |= SCALE_DCOMP_METHOD;
> >>> Please still leave behind a DRM_ERROR in case 
> >>> UNIQE_TRANGE_EN_METHOD was set in the register and we are 
> >>> disabling scaling. The scaling value does seem to depend on this 
> >>> bit too, so seeing if it was set can help tracking down problems.
> >>>
> Again, I couldn't find it mentioned anywhere that scaling value 
> depends on "ouniqetrangenmethod" ? Is it in bspec?

This can be seen just by setting ouniqetrangenmethod and leaving oscaledcompmethod clear. Setting a low scale value in this case will result in no valid signal and blank screen.

> Although it does seem to make a difference in case of low vswing table.
> With default table, it edp continues to work if set or not set this bit.
> I will add back the unsetting of this bit and then setting of this bit 
> when 'enable' is set.

According to Bspec we should do an RMW on this register and don't change ouniqetrangenmethod. So I wouldn't set or clear it, but have the check and DRM_ERROR in case BIOS has set it for some reason (maybe old/buggy
BIOS) which could help understanding if things don't work.

--Imre

> Regards,
> Sonik
> >> This was the only place UNIQE_TRANGE_EN_METHOD was set before, with 
> >> that removed only possibility for it to be set is by GOP/VBIOS. 
> >> (who are also expected to make this change if not done already.) in 
> >> such a scenario wont an error message be useless here ?
> >
> > Yes, this is exactly a check for BIOS settings. It wouldn't be the 
> > first case that BIOS didn't program something according to our 
> > expectations, especially given the multiple versions out there.
> >
> >>>>>     	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
> >>>>>
> >>>>>     	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
> >>>
> >>>
> >>>
> >>
> >>
> >
> >


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915/bxt: Set oscaledcompmethod to enable scale value

[Imre Deak]

On to, 2015-09-24 at 10:22 +0530, Sonika Jindal wrote:
> Bspec update tells that we have to enable oscaledcompmethod instead of
> ouniqetrangenmethod for enabling scale value during swing programming.
> 
> v2: Adding back 'don't care' values to bxt_ddi_translations_dp and add
> error message if ouniquetrangemethod was set (Imre)
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>(v1)

Reviewed-by: Imre Deak <imre.deak@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h  |    3 ++-
>  drivers/gpu/drm/i915/intel_ddi.c |    8 ++++++--
>  2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 812b7b2..3f2135d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1395,7 +1395,8 @@ enum skl_disp_power_wells {
>  #define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
>  						     _PORT_TX_DW3_LN0_B,  \
>  						     _PORT_TX_DW3_LN0_C)
> -#define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
> +#define   SCALE_DCOMP_METHOD		(1 << 26)
> +#define   UNIQUE_TRANGE_EN_METHOD	(1 << 27)
>  
>  #define _PORT_TX_DW4_LN0_A		0x162510
>  #define _PORT_TX_DW4_LN0_B		0x6C510
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index fec51df..7705bc9 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2151,9 +2151,13 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
>  	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
>  
>  	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
> -	val &= ~UNIQE_TRANGE_EN_METHOD;
> +	val &= ~SCALE_DCOMP_METHOD;
>  	if (ddi_translations[level].enable)
> -		val |= UNIQE_TRANGE_EN_METHOD;
> +		val |= SCALE_DCOMP_METHOD;
> +
> +	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
> +		DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
> +
>  	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
>  
>  	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915/bxt: eDP low vswing support

[Daniel Vetter]

On Thu, Sep 24, 2015 at 10:24:56AM +0530, Sonika Jindal wrote:
> Adding voltage swing table for edp to support low vswings.
> 
> v2: Rebased.
> 
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>

Queued for -next, thanks for the patch.
-Daniel

> ---
>  drivers/gpu/drm/i915/intel_ddi.c |   23 +++++++++++++++++++----
>  1 file changed, 19 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 7705bc9..4be1c2b 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -256,9 +256,6 @@ struct bxt_ddi_buf_trans {
>  	bool default_index; /* true if the entry represents default value */
>  };
>  
> -/* BSpec does not define separate vswing/pre-emphasis values for eDP.
> - * Using DP values for eDP as well.
> - */
>  static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
>  					/* Idx	NT mV diff	db  */
>  	{ 52,  0x9A, 0, 128, true  },	/* 0:	400		0   */
> @@ -273,6 +270,20 @@ static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
>  	{ 154, 0x9A, 1, 128, false },	/* 9:	1200		0   */
>  };
>  
> +static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
> +					/* Idx	NT mV diff	db  */
> +	{ 26, 0, 0, 128, false },	/* 0:	200		0   */
> +	{ 38, 0, 0, 112, false },	/* 1:	200		1.5 */
> +	{ 48, 0, 0, 96,  false },	/* 2:	200		4   */
> +	{ 54, 0, 0, 69,  false },	/* 3:	200		6   */
> +	{ 32, 0, 0, 128, false },	/* 4:	250		0   */
> +	{ 48, 0, 0, 104, false },	/* 5:	250		1.5 */
> +	{ 54, 0, 0, 85,  false },	/* 6:	250		4   */
> +	{ 43, 0, 0, 128, false },	/* 7:	300		0   */
> +	{ 54, 0, 0, 101, false },	/* 8:	300		1.5 */
> +	{ 48, 0, 0, 128, false },	/* 9:	300		0   */
> +};
> +
>  /* BSpec has 2 recommended values - entries 0 and 8.
>   * Using the entry with higher vswing.
>   */
> @@ -2113,7 +2124,11 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
>  	u32 n_entries, i;
>  	uint32_t val;
>  
> -	if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
> +	if (type == INTEL_OUTPUT_EDP && dev_priv->edp_low_vswing) {
> +		n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
> +		ddi_translations = bxt_ddi_translations_edp;
> +	} else if (type == INTEL_OUTPUT_DISPLAYPORT
> +			|| type == INTEL_OUTPUT_EDP) {
>  		n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
>  		ddi_translations = bxt_ddi_translations_dp;
>  	} else if (type == INTEL_OUTPUT_HDMI) {
> -- 
> 1.7.10.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915/bxt: Set oscaledcompmethod to enable scale value

[Daniel Vetter]

On Thu, Sep 24, 2015 at 02:12:02PM +0300, Imre Deak wrote:
> On to, 2015-09-24 at 10:22 +0530, Sonika Jindal wrote:
> > Bspec update tells that we have to enable oscaledcompmethod instead of
> > ouniqetrangenmethod for enabling scale value during swing programming.
> > 
> > v2: Adding back 'don't care' values to bxt_ddi_translations_dp and add
> > error message if ouniquetrangemethod was set (Imre)
> > 
> > Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> > Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>(v1)
> 
> Reviewed-by: Imre Deak <imre.deak@intel.com>

Queued for -next, thanks for the patch.
-Daniel

> 
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h  |    3 ++-
> >  drivers/gpu/drm/i915/intel_ddi.c |    8 ++++++--
> >  2 files changed, 8 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 812b7b2..3f2135d 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1395,7 +1395,8 @@ enum skl_disp_power_wells {
> >  #define BXT_PORT_TX_DW3_LN0(port)	_PORT3(port, _PORT_TX_DW3_LN0_A,  \
> >  						     _PORT_TX_DW3_LN0_B,  \
> >  						     _PORT_TX_DW3_LN0_C)
> > -#define   UNIQE_TRANGE_EN_METHOD	(1 << 27)
> > +#define   SCALE_DCOMP_METHOD		(1 << 26)
> > +#define   UNIQUE_TRANGE_EN_METHOD	(1 << 27)
> >  
> >  #define _PORT_TX_DW4_LN0_A		0x162510
> >  #define _PORT_TX_DW4_LN0_B		0x6C510
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index fec51df..7705bc9 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2151,9 +2151,13 @@ static void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
> >  	I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
> >  
> >  	val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
> > -	val &= ~UNIQE_TRANGE_EN_METHOD;
> > +	val &= ~SCALE_DCOMP_METHOD;
> >  	if (ddi_translations[level].enable)
> > -		val |= UNIQE_TRANGE_EN_METHOD;
> > +		val |= SCALE_DCOMP_METHOD;
> > +
> > +	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
> > +		DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
> > +
> >  	I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
> >  
> >  	val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
> 
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx