[PATCH 0/4]

[PATCH 0/4]

[Caesar Wang]

We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.

Says:
The TSHUT temperature is setting more than 80 degree, the default
tshut polarity is HIGH.

If T > 80C, the OTP output the High Signal.
If T < 80C, the OTP output the Low Signal.

On the moment, the TSADC controller is reset, the tshut polarity will be
Low in a short period of time.

So:
If T < 80C, the OTP output the High Signal.
If T > 80C, the OTP output the Low Signal.

In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
accept the reset response time to avoid this issue.

In other words, the system will be always reboot if we make the OTP pin
is connected the others IC to control the power.

Tested on box board.



Caesar Wang (4):
  dt-bindings: Sync the dts to this document
  thermal: rockchip: ensure the otp state before resetting the
    controller
  thermal: rockchip: change the TSHUT default state
  ARM: dts: rockchip: Add the OTP gpio pinctrl

 .../bindings/thermal/rockchip-thermal.txt          |  5 ++--
 arch/arm/boot/dts/rk3288.dtsi                      |  9 ++++--
 drivers/thermal/rockchip_thermal.c                 | 34 +++++++++++++++++++++-
 3 files changed, 43 insertions(+), 5 deletions(-)

-- 
1.9.1

[PATCH 0/4]

[Caesar Wang]

We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.

Says:
The TSHUT temperature is setting more than 80 degree, the default
tshut polarity is HIGH.

If T > 80C, the OTP output the High Signal.
If T < 80C, the OTP output the Low Signal.

On the moment, the TSADC controller is reset, the tshut polarity will be
Low in a short period of time.

So:
If T < 80C, the OTP output the High Signal.
If T > 80C, the OTP output the Low Signal.

In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
accept the reset response time to avoid this issue.

In other words, the system will be always reboot if we make the OTP pin
is connected the others IC to control the power.

Tested on box board.



Caesar Wang (4):
  dt-bindings: Sync the dts to this document
  thermal: rockchip: ensure the otp state before resetting the
    controller
  thermal: rockchip: change the TSHUT default state
  ARM: dts: rockchip: Add the OTP gpio pinctrl

 .../bindings/thermal/rockchip-thermal.txt          |  5 ++--
 arch/arm/boot/dts/rk3288.dtsi                      |  9 ++++--
 drivers/thermal/rockchip_thermal.c                 | 34 +++++++++++++++++++++-
 3 files changed, 43 insertions(+), 5 deletions(-)

-- 
1.9.1

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[PATCH 0/4]

[Caesar Wang]

We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.

Says:
The TSHUT temperature is setting more than 80 degree, the default
tshut polarity is HIGH.

If T > 80C, the OTP output the High Signal.
If T < 80C, the OTP output the Low Signal.

On the moment, the TSADC controller is reset, the tshut polarity will be
Low in a short period of time.

So:
If T < 80C, the OTP output the High Signal.
If T > 80C, the OTP output the Low Signal.

In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
accept the reset response time to avoid this issue.

In other words, the system will be always reboot if we make the OTP pin
is connected the others IC to control the power.

Tested on box board.



Caesar Wang (4):
  dt-bindings: Sync the dts to this document
  thermal: rockchip: ensure the otp state before resetting the
    controller
  thermal: rockchip: change the TSHUT default state
  ARM: dts: rockchip: Add the OTP gpio pinctrl

 .../bindings/thermal/rockchip-thermal.txt          |  5 ++--
 arch/arm/boot/dts/rk3288.dtsi                      |  9 ++++--
 drivers/thermal/rockchip_thermal.c                 | 34 +++++++++++++++++++++-
 3 files changed, 43 insertions(+), 5 deletions(-)

-- 
1.9.1

[PATCH 1/4] dt-bindings: Sync the dts to this document

[Caesar Wang]

Add the OTP gpio state, we need switch the pin to gpio state
before the TSADC controller is reset.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
index ef802de..2587f34b 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
@@ -27,8 +27,9 @@ tsadc: tsadc@ff280000 {
 	clock-names = "tsadc", "apb_pclk";
 	resets = <&cru SRST_TSADC>;
 	reset-names = "tsadc-apb";
-	pinctrl-names = "default";
-	pinctrl-0 = <&otp_out>;
+	pinctrl-names = "default", "otp_out";
+	pinctrl-0 = <&otp_gpio>;
+	pinctrl-1 = <&otp_out>;
 	#thermal-sensor-cells = <1>;
 	rockchip,hw-tshut-temp = <95000>;
 	rockchip,hw-tshut-mode = <0>;
-- 
1.9.1

[PATCH 1/4] dt-bindings: Sync the dts to this document

[Caesar Wang]

Add the OTP gpio state, we need switch the pin to gpio state
before the TSADC controller is reset.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 Documentation/devicetree/bindings/thermal/rockchip-thermal.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
index ef802de..2587f34b 100644
--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.txt
@@ -27,8 +27,9 @@ tsadc: tsadc at ff280000 {
 	clock-names = "tsadc", "apb_pclk";
 	resets = <&cru SRST_TSADC>;
 	reset-names = "tsadc-apb";
-	pinctrl-names = "default";
-	pinctrl-0 = <&otp_out>;
+	pinctrl-names = "default", "otp_out";
+	pinctrl-0 = <&otp_gpio>;
+	pinctrl-1 = <&otp_out>;
 	#thermal-sensor-cells = <1>;
 	rockchip,hw-tshut-temp = <95000>;
 	rockchip,hw-tshut-mode = <0>;
-- 
1.9.1

[PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller

[Caesar Wang]

We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.

Says:
The TSHUT temperature is setting more than 80 degree, the default tshut
polarity is high.

If T > 80C, the OTP output the High Signal.
If T < 80C, the OTP output the Low Signal.

On the moment, the TSADC controller is reset, the tshut polarity will be
low in a short period of time.
So:

If T < 80C, the OTP output the High Signal.
If T > 80C, the OTP output the Low Signal.

In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the OTP pin
is connected the others IC to control the power.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 drivers/thermal/rockchip_thermal.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c
index c89ffb2..c53e318 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -22,6 +22,7 @@
 #include <linux/platform_device.h>
 #include <linux/reset.h>
 #include <linux/thermal.h>
+#include <linux/pinctrl/consumer.h>
 
 /**
  * If the temperature over a period of time High,
@@ -79,6 +80,9 @@ struct rockchip_thermal_sensor {
 
 struct rockchip_thermal_data {
 	const struct rockchip_tsadc_chip *chip;
+	struct pinctrl *pinctrl;
+	struct pinctrl_state *pins_default;
+	struct pinctrl_state *pins_otp;
 	struct platform_device *pdev;
 	struct reset_control *reset;
 
@@ -548,6 +552,28 @@ static int rockchip_thermal_probe(struct platform_device *pdev)
 		goto err_disable_clk;
 	}
 
+	/*
+	 * We need the OTP pin is gpio state before reset the TSADC controller
+	 * since the tshut polarity will generate a high signal.
+	 */
+
+	thermal->pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (IS_ERR(thermal->pinctrl)) {
+		error = PTR_ERR(thermal->pinctrl);
+		dev_err(&pdev->dev, "failed to get thermal pinctrl: %d\n",
+			error);
+		goto err_disable_pclk;
+	}
+
+	thermal->pins_default = pinctrl_lookup_state(thermal->pinctrl,
+						     "default");
+	if (IS_ERR(thermal->pins_default))
+		dev_warn(&pdev->dev, "could not get the pinctrl default state\n");
+
+	thermal->pins_otp = pinctrl_lookup_state(thermal->pinctrl, "otp_out");
+	if (IS_ERR(thermal->pins_otp))
+		dev_warn(&pdev->dev, "could not get otp state\n");
+
 	rockchip_thermal_reset_controller(thermal->reset);
 
 	error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
@@ -592,6 +618,8 @@ static int rockchip_thermal_probe(struct platform_device *pdev)
 	for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++)
 		rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
 
+	pinctrl_select_state(thermal->pinctrl, thermal->pins_otp);
+
 	platform_set_drvdata(pdev, thermal);
 
 	return 0;
@@ -660,6 +688,8 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev)
 	if (error)
 		return error;
 
+	pinctrl_select_state(thermal->pinctrl, thermal->pins_default);
+
 	rockchip_thermal_reset_controller(thermal->reset);
 
 	thermal->chip->initialize(thermal->regs, thermal->tshut_polarity);
@@ -678,6 +708,8 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev)
 	for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++)
 		rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
 
+	pinctrl_select_state(thermal->pinctrl, thermal->pins_otp);
+
 	return 0;
 }
 
-- 
1.9.1

[PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller

[Caesar Wang]

We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.

Says:
The TSHUT temperature is setting more than 80 degree, the default tshut
polarity is high.

If T > 80C, the OTP output the High Signal.
If T < 80C, the OTP output the Low Signal.

On the moment, the TSADC controller is reset, the tshut polarity will be
low in a short period of time.
So:

If T < 80C, the OTP output the High Signal.
If T > 80C, the OTP output the Low Signal.

In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the OTP pin
is connected the others IC to control the power.

Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---

 drivers/thermal/rockchip_thermal.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c
index c89ffb2..c53e318 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -22,6 +22,7 @@
 #include <linux/platform_device.h>
 #include <linux/reset.h>
 #include <linux/thermal.h>
+#include <linux/pinctrl/consumer.h>
 
 /**
  * If the temperature over a period of time High,
@@ -79,6 +80,9 @@ struct rockchip_thermal_sensor {
 
 struct rockchip_thermal_data {
 	const struct rockchip_tsadc_chip *chip;
+	struct pinctrl *pinctrl;
+	struct pinctrl_state *pins_default;
+	struct pinctrl_state *pins_otp;
 	struct platform_device *pdev;
 	struct reset_control *reset;
 
@@ -548,6 +552,28 @@ static int rockchip_thermal_probe(struct platform_device *pdev)
 		goto err_disable_clk;
 	}
 
+	/*
+	 * We need the OTP pin is gpio state before reset the TSADC controller
+	 * since the tshut polarity will generate a high signal.
+	 */
+
+	thermal->pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (IS_ERR(thermal->pinctrl)) {
+		error = PTR_ERR(thermal->pinctrl);
+		dev_err(&pdev->dev, "failed to get thermal pinctrl: %d\n",
+			error);
+		goto err_disable_pclk;
+	}
+
+	thermal->pins_default = pinctrl_lookup_state(thermal->pinctrl,
+						     "default");
+	if (IS_ERR(thermal->pins_default))
+		dev_warn(&pdev->dev, "could not get the pinctrl default state\n");
+
+	thermal->pins_otp = pinctrl_lookup_state(thermal->pinctrl, "otp_out");
+	if (IS_ERR(thermal->pins_otp))
+		dev_warn(&pdev->dev, "could not get otp state\n");
+
 	rockchip_thermal_reset_controller(thermal->reset);
 
 	error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
@@ -592,6 +618,8 @@ static int rockchip_thermal_probe(struct platform_device *pdev)
 	for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++)
 		rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
 
+	pinctrl_select_state(thermal->pinctrl, thermal->pins_otp);
+
 	platform_set_drvdata(pdev, thermal);
 
 	return 0;
@@ -660,6 +688,8 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev)
 	if (error)
 		return error;
 
+	pinctrl_select_state(thermal->pinctrl, thermal->pins_default);
+
 	rockchip_thermal_reset_controller(thermal->reset);
 
 	thermal->chip->initialize(thermal->regs, thermal->tshut_polarity);
@@ -678,6 +708,8 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev)
 	for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++)
 		rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
 
+	pinctrl_select_state(thermal->pinctrl, thermal->pins_otp);
+
 	return 0;
 }
 
-- 
1.9.1

[PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller

[Caesar Wang]

We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.

Says:
The TSHUT temperature is setting more than 80 degree, the default tshut
polarity is high.

If T > 80C, the OTP output the High Signal.
If T < 80C, the OTP output the Low Signal.

On the moment, the TSADC controller is reset, the tshut polarity will be
low in a short period of time.
So:

If T < 80C, the OTP output the High Signal.
If T > 80C, the OTP output the Low Signal.

In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
accept the reset response time to avoid this issue.
In other words, the system will be always reboot if we make the OTP pin
is connected the others IC to control the power.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 drivers/thermal/rockchip_thermal.c | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c
index c89ffb2..c53e318 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -22,6 +22,7 @@
 #include <linux/platform_device.h>
 #include <linux/reset.h>
 #include <linux/thermal.h>
+#include <linux/pinctrl/consumer.h>
 
 /**
  * If the temperature over a period of time High,
@@ -79,6 +80,9 @@ struct rockchip_thermal_sensor {
 
 struct rockchip_thermal_data {
 	const struct rockchip_tsadc_chip *chip;
+	struct pinctrl *pinctrl;
+	struct pinctrl_state *pins_default;
+	struct pinctrl_state *pins_otp;
 	struct platform_device *pdev;
 	struct reset_control *reset;
 
@@ -548,6 +552,28 @@ static int rockchip_thermal_probe(struct platform_device *pdev)
 		goto err_disable_clk;
 	}
 
+	/*
+	 * We need the OTP pin is gpio state before reset the TSADC controller
+	 * since the tshut polarity will generate a high signal.
+	 */
+
+	thermal->pinctrl = devm_pinctrl_get(&pdev->dev);
+	if (IS_ERR(thermal->pinctrl)) {
+		error = PTR_ERR(thermal->pinctrl);
+		dev_err(&pdev->dev, "failed to get thermal pinctrl: %d\n",
+			error);
+		goto err_disable_pclk;
+	}
+
+	thermal->pins_default = pinctrl_lookup_state(thermal->pinctrl,
+						     "default");
+	if (IS_ERR(thermal->pins_default))
+		dev_warn(&pdev->dev, "could not get the pinctrl default state\n");
+
+	thermal->pins_otp = pinctrl_lookup_state(thermal->pinctrl, "otp_out");
+	if (IS_ERR(thermal->pins_otp))
+		dev_warn(&pdev->dev, "could not get otp state\n");
+
 	rockchip_thermal_reset_controller(thermal->reset);
 
 	error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
@@ -592,6 +618,8 @@ static int rockchip_thermal_probe(struct platform_device *pdev)
 	for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++)
 		rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
 
+	pinctrl_select_state(thermal->pinctrl, thermal->pins_otp);
+
 	platform_set_drvdata(pdev, thermal);
 
 	return 0;
@@ -660,6 +688,8 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev)
 	if (error)
 		return error;
 
+	pinctrl_select_state(thermal->pinctrl, thermal->pins_default);
+
 	rockchip_thermal_reset_controller(thermal->reset);
 
 	thermal->chip->initialize(thermal->regs, thermal->tshut_polarity);
@@ -678,6 +708,8 @@ static int __maybe_unused rockchip_thermal_resume(struct device *dev)
 	for (i = 0; i < ARRAY_SIZE(thermal->sensors); i++)
 		rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
 
+	pinctrl_select_state(thermal->pinctrl, thermal->pins_otp);
+
 	return 0;
 }
 
-- 
1.9.1

[PATCH 3/4] thermal: rockchip: change the TSHUT default state

[Caesar Wang]

As the TRM says, the TSHUT default state is high active.
In general, the TSHUT state can get from the dts. Otherwise
it gets the state from this.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 drivers/thermal/rockchip_thermal.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c
index c53e318..776d668 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -326,7 +326,7 @@ static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
 
 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
 	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
-	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
+	.tshut_polarity = TSHUT_HIGH_ACTIVE, /* default TSHUT HIGH ACTIVE */
 	.tshut_temp = 95000,
 
 	.initialize = rk_tsadcv2_initialize,
-- 
1.9.1

[PATCH 3/4] thermal: rockchip: change the TSHUT default state

[Caesar Wang]

As the TRM says, the TSHUT default state is high active.
In general, the TSHUT state can get from the dts. Otherwise
it gets the state from this.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 drivers/thermal/rockchip_thermal.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_thermal.c
index c53e318..776d668 100644
--- a/drivers/thermal/rockchip_thermal.c
+++ b/drivers/thermal/rockchip_thermal.c
@@ -326,7 +326,7 @@ static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
 
 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
 	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
-	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
+	.tshut_polarity = TSHUT_HIGH_ACTIVE, /* default TSHUT HIGH ACTIVE */
 	.tshut_temp = 95000,
 
 	.initialize = rk_tsadcv2_initialize,
-- 
1.9.1

[PATCH 4/4] ARM: dts: rockchip: Add the OTP gpio pinctrl

[Caesar Wang]

We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 arch/arm/boot/dts/rk3288.dtsi | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..b59c451 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -447,8 +447,9 @@
 		clock-names = "tsadc", "apb_pclk";
 		resets = <&cru SRST_TSADC>;
 		reset-names = "tsadc-apb";
-		pinctrl-names = "default";
-		pinctrl-0 = <&otp_out>;
+		pinctrl-names = "default", "otp_out";
+		pinctrl-0 = <&otp_gpio>;
+		pinctrl-1 = <&otp_out>;
 		#thermal-sensor-cells = <1>;
 		rockchip,hw-tshut-temp = <95000>;
 		status = "disabled";
@@ -1273,6 +1274,10 @@
 		};
 
 		tsadc {
+			otp_gpio: otp-gpio {
+				rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
 			otp_out: otp-out {
 				rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
 			};
-- 
1.9.1

[PATCH 4/4] ARM: dts: rockchip: Add the OTP gpio pinctrl

[Caesar Wang]

We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.

Signed-off-by: Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---

 arch/arm/boot/dts/rk3288.dtsi | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..b59c451 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -447,8 +447,9 @@
 		clock-names = "tsadc", "apb_pclk";
 		resets = <&cru SRST_TSADC>;
 		reset-names = "tsadc-apb";
-		pinctrl-names = "default";
-		pinctrl-0 = <&otp_out>;
+		pinctrl-names = "default", "otp_out";
+		pinctrl-0 = <&otp_gpio>;
+		pinctrl-1 = <&otp_out>;
 		#thermal-sensor-cells = <1>;
 		rockchip,hw-tshut-temp = <95000>;
 		status = "disabled";
@@ -1273,6 +1274,10 @@
 		};
 
 		tsadc {
+			otp_gpio: otp-gpio {
+				rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
 			otp_out: otp-out {
 				rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
 			};
-- 
1.9.1

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[PATCH 4/4] ARM: dts: rockchip: Add the OTP gpio pinctrl

[Caesar Wang]

We need the OTP pin is gpio state before resetting the TSADC controller,
since the tshut polarity will generate a high signal.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
---

 arch/arm/boot/dts/rk3288.dtsi | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 906e938..b59c451 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -447,8 +447,9 @@
 		clock-names = "tsadc", "apb_pclk";
 		resets = <&cru SRST_TSADC>;
 		reset-names = "tsadc-apb";
-		pinctrl-names = "default";
-		pinctrl-0 = <&otp_out>;
+		pinctrl-names = "default", "otp_out";
+		pinctrl-0 = <&otp_gpio>;
+		pinctrl-1 = <&otp_out>;
 		#thermal-sensor-cells = <1>;
 		rockchip,hw-tshut-temp = <95000>;
 		status = "disabled";
@@ -1273,6 +1274,10 @@
 		};
 
 		tsadc {
+			otp_gpio: otp-gpio {
+				rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
+			};
+
 			otp_out: otp-out {
 				rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
 			};
-- 
1.9.1

Re: [PATCH 0/4] Add the OTP gpio pinctrl to fix the TSHUT issue

[Caesar Wang]

The subject is deleted by my finger.

在 2015年10月20日 17:11, Caesar Wang 写道:
> We need the OTP pin is gpio state before resetting the TSADC controller,
> since the tshut polarity will generate a high signal.
>
> Says:
> The TSHUT temperature is setting more than 80 degree, the default
> tshut polarity is HIGH.
>
> If T > 80C, the OTP output the High Signal.
> If T < 80C, the OTP output the Low Signal.
>
> On the moment, the TSADC controller is reset, the tshut polarity will be
> Low in a short period of time.
>
> So:
> If T < 80C, the OTP output the High Signal.
> If T > 80C, the OTP output the Low Signal.
>
> In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
> accept the reset response time to avoid this issue.
>
> In other words, the system will be always reboot if we make the OTP pin
> is connected the others IC to control the power.
>
> Tested on box board.
>
>
>
> Caesar Wang (4):
>    dt-bindings: Sync the dts to this document
>    thermal: rockchip: ensure the otp state before resetting the
>      controller
>    thermal: rockchip: change the TSHUT default state
>    ARM: dts: rockchip: Add the OTP gpio pinctrl
>
>   .../bindings/thermal/rockchip-thermal.txt          |  5 ++--
>   arch/arm/boot/dts/rk3288.dtsi                      |  9 ++++--
>   drivers/thermal/rockchip_thermal.c                 | 34 +++++++++++++++++++++-
>   3 files changed, 43 insertions(+), 5 deletions(-)
>

-- 
Thanks,
Caesar

[PATCH 0/4] Add the OTP gpio pinctrl to fix the TSHUT issue

[Caesar Wang]

The subject is deleted by my finger.

? 2015?10?20? 17:11, Caesar Wang ??:
> We need the OTP pin is gpio state before resetting the TSADC controller,
> since the tshut polarity will generate a high signal.
>
> Says:
> The TSHUT temperature is setting more than 80 degree, the default
> tshut polarity is HIGH.
>
> If T > 80C, the OTP output the High Signal.
> If T < 80C, the OTP output the Low Signal.
>
> On the moment, the TSADC controller is reset, the tshut polarity will be
> Low in a short period of time.
>
> So:
> If T < 80C, the OTP output the High Signal.
> If T > 80C, the OTP output the Low Signal.
>
> In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
> accept the reset response time to avoid this issue.
>
> In other words, the system will be always reboot if we make the OTP pin
> is connected the others IC to control the power.
>
> Tested on box board.
>
>
>
> Caesar Wang (4):
>    dt-bindings: Sync the dts to this document
>    thermal: rockchip: ensure the otp state before resetting the
>      controller
>    thermal: rockchip: change the TSHUT default state
>    ARM: dts: rockchip: Add the OTP gpio pinctrl
>
>   .../bindings/thermal/rockchip-thermal.txt          |  5 ++--
>   arch/arm/boot/dts/rk3288.dtsi                      |  9 ++++--
>   drivers/thermal/rockchip_thermal.c                 | 34 +++++++++++++++++++++-
>   3 files changed, 43 insertions(+), 5 deletions(-)
>

-- 
Thanks,
Caesar

Re: [PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller

[Doug Anderson]

Caesar,

On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
> We need the OTP pin is gpio state before resetting the TSADC controller,
> since the tshut polarity will generate a high signal.
>
> Says:
> The TSHUT temperature is setting more than 80 degree, the default tshut
> polarity is high.
>
> If T > 80C, the OTP output the High Signal.
> If T < 80C, the OTP output the Low Signal.
>
> On the moment, the TSADC controller is reset, the tshut polarity will be
> low in a short period of time.
> So:
>
> If T < 80C, the OTP output the High Signal.
> If T > 80C, the OTP output the Low Signal.
>
> In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
> accept the reset response time to avoid this issue.
> In other words, the system will be always reboot if we make the OTP pin
> is connected the others IC to control the power.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> ---
>
>  drivers/thermal/rockchip_thermal.c | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)

I think you could do this with no code changes to the thermal driver
if we simply convince Linus W. to apply a change that I posted up just
about a year ago.  See:

https://patchwork.kernel.org/patch/5055741/

In v1 of that patch at <https://patchwork.kernel.org/patch/5049041/>
Linus said he liked it "A lot" and was willing to merge it with Greg
KH's Ack and with a small comment fix.  I obtained the Ack and fixed
the comment, but then the patch didn't end up being needed for me and
so I never bumped it and it got lost...

Maybe you could re-test that patch?  It looks like it has a merge
conflict with current linuxnext but it looks trivial to resolve.  You
could re-post my patch or I could repost it and you could add your
Tested-by.

You'd still want to have a bindings change to describe "init", but at
least you shouldn't need any code changes.


-Doug

Re: [PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller

[Doug Anderson]

Caesar,

On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
> We need the OTP pin is gpio state before resetting the TSADC controller,
> since the tshut polarity will generate a high signal.
>
> Says:
> The TSHUT temperature is setting more than 80 degree, the default tshut
> polarity is high.
>
> If T > 80C, the OTP output the High Signal.
> If T < 80C, the OTP output the Low Signal.
>
> On the moment, the TSADC controller is reset, the tshut polarity will be
> low in a short period of time.
> So:
>
> If T < 80C, the OTP output the High Signal.
> If T > 80C, the OTP output the Low Signal.
>
> In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
> accept the reset response time to avoid this issue.
> In other words, the system will be always reboot if we make the OTP pin
> is connected the others IC to control the power.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> ---
>
>  drivers/thermal/rockchip_thermal.c | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)

I think you could do this with no code changes to the thermal driver
if we simply convince Linus W. to apply a change that I posted up just
about a year ago.  See:

https://patchwork.kernel.org/patch/5055741/

In v1 of that patch at <https://patchwork.kernel.org/patch/5049041/>
Linus said he liked it "A lot" and was willing to merge it with Greg
KH's Ack and with a small comment fix.  I obtained the Ack and fixed
the comment, but then the patch didn't end up being needed for me and
so I never bumped it and it got lost...

Maybe you could re-test that patch?  It looks like it has a merge
conflict with current linuxnext but it looks trivial to resolve.  You
could re-post my patch or I could repost it and you could add your
Tested-by.

You'd still want to have a bindings change to describe "init", but at
least you shouldn't need any code changes.


-Doug

[PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller

[Doug Anderson]

Caesar,

On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
> We need the OTP pin is gpio state before resetting the TSADC controller,
> since the tshut polarity will generate a high signal.
>
> Says:
> The TSHUT temperature is setting more than 80 degree, the default tshut
> polarity is high.
>
> If T > 80C, the OTP output the High Signal.
> If T < 80C, the OTP output the Low Signal.
>
> On the moment, the TSADC controller is reset, the tshut polarity will be
> low in a short period of time.
> So:
>
> If T < 80C, the OTP output the High Signal.
> If T > 80C, the OTP output the Low Signal.
>
> In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
> accept the reset response time to avoid this issue.
> In other words, the system will be always reboot if we make the OTP pin
> is connected the others IC to control the power.
>
> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
> ---
>
>  drivers/thermal/rockchip_thermal.c | 32 ++++++++++++++++++++++++++++++++
>  1 file changed, 32 insertions(+)

I think you could do this with no code changes to the thermal driver
if we simply convince Linus W. to apply a change that I posted up just
about a year ago.  See:

https://patchwork.kernel.org/patch/5055741/

In v1 of that patch at <https://patchwork.kernel.org/patch/5049041/>
Linus said he liked it "A lot" and was willing to merge it with Greg
KH's Ack and with a small comment fix.  I obtained the Ack and fixed
the comment, but then the patch didn't end up being needed for me and
so I never bumped it and it got lost...

Maybe you could re-test that patch?  It looks like it has a merge
conflict with current linuxnext but it looks trivial to resolve.  You
could re-post my patch or I could repost it and you could add your
Tested-by.

You'd still want to have a bindings change to describe "init", but at
least you shouldn't need any code changes.


-Doug

Re: [PATCH 3/4] thermal: rockchip: change the TSHUT default state

[Doug Anderson]

Caesar,

On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
> As the TRM says, the TSHUT default state is high active.
> In general, the TSHUT state can get from the dts. Otherwise
> it gets the state from this.

Can you point at where the TRM says that the default state is high active?

With the manual I have, I look at TSADC_AUTO_CON and I look at the
description of "Bit 8".  It says that "tshut polarity" is 0 for low
active and 1 for high active.  It then said that the Reset Value is 0.

...the "Reset Value" in tables like this is notoriously unreliable, so
I can totally believe that it's wrong.  If you can point me at the
part of the TRM that says that TSHUT is high active by default then I
can confirm that for you.  ;)


-Doug

Re: [PATCH 3/4] thermal: rockchip: change the TSHUT default state

[Doug Anderson]

Caesar,

On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
> As the TRM says, the TSHUT default state is high active.
> In general, the TSHUT state can get from the dts. Otherwise
> it gets the state from this.

Can you point at where the TRM says that the default state is high active?

With the manual I have, I look at TSADC_AUTO_CON and I look at the
description of "Bit 8".  It says that "tshut polarity" is 0 for low
active and 1 for high active.  It then said that the Reset Value is 0.

...the "Reset Value" in tables like this is notoriously unreliable, so
I can totally believe that it's wrong.  If you can point me at the
part of the TRM that says that TSHUT is high active by default then I
can confirm that for you.  ;)


-Doug

[PATCH 3/4] thermal: rockchip: change the TSHUT default state

[Doug Anderson]

Caesar,

On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
> As the TRM says, the TSHUT default state is high active.
> In general, the TSHUT state can get from the dts. Otherwise
> it gets the state from this.

Can you point at where the TRM says that the default state is high active?

With the manual I have, I look at TSADC_AUTO_CON and I look at the
description of "Bit 8".  It says that "tshut polarity" is 0 for low
active and 1 for high active.  It then said that the Reset Value is 0.

...the "Reset Value" in tables like this is notoriously unreliable, so
I can totally believe that it's wrong.  If you can point me at the
part of the TRM that says that TSHUT is high active by default then I
can confirm that for you.  ;)


-Doug

Re: [PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller

[Caesar Wang]

Doug,

在 2015年10月20日 23:52, Doug Anderson 写道:
> Caesar,
>
> On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
>> We need the OTP pin is gpio state before resetting the TSADC controller,
>> since the tshut polarity will generate a high signal.
>>
>> Says:
>> The TSHUT temperature is setting more than 80 degree, the default tshut
>> polarity is high.
>>
>> If T > 80C, the OTP output the High Signal.
>> If T < 80C, the OTP output the Low Signal.
>>
>> On the moment, the TSADC controller is reset, the tshut polarity will be
>> low in a short period of time.
>> So:
>>
>> If T < 80C, the OTP output the High Signal.
>> If T > 80C, the OTP output the Low Signal.
>>
>> In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
>> accept the reset response time to avoid this issue.
>> In other words, the system will be always reboot if we make the OTP pin
>> is connected the others IC to control the power.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> ---
>>
>>   drivers/thermal/rockchip_thermal.c | 32 ++++++++++++++++++++++++++++++++
>>   1 file changed, 32 insertions(+)
> I think you could do this with no code changes to the thermal driver
> if we simply convince Linus W. to apply a change that I posted up just
> about a year ago.  See:
>
> https://patchwork.kernel.org/patch/5055741/
>
> In v1 of that patch at <https://patchwork.kernel.org/patch/5049041/>
> Linus said he liked it "A lot" and was willing to merge it with Greg
> KH's Ack and with a small comment fix.  I obtained the Ack and fixed
> the comment, but then the patch didn't end up being needed for me and
> so I never bumped it and it got lost...
>
> Maybe you could re-test that patch?  It looks like it has a merge
> conflict with current linuxnext but it looks trivial to resolve.  You
> could re-post my patch or I could repost it and you could add your
> Tested-by.
>
> You'd still want to have a bindings change to describe "init", but at
> least you shouldn't need any code changes.

Okay, https://patchwork.kernel.org/patch/5055741/ that's working for me.
Fell free add my  test tag if you resend the patch. (Tested-by: Caesar 
Wang <wxt@rock-chips.com>)


1634ed8 FROMLIST: drivers/pinctrl: Add the concept of an "init" state
15158f8 FROMLIST: ARM: dts: rockchip: Add the OTP gpio pinctrl
e7d3b88 FROMLIST: thermal: rockchip: change the TSHUT default state
184b154 FROMLIST: thermal: rockchip: ensure the otp state before 
resetting the controller
9edbe15 FROMLIST: dt-bindings: Sync the dts to this document

Meanwhile, I change the dts as follows.

-               pinctrl-names = "default", "otp_out";
+               pinctrl-names = "init", "default";
                 pinctrl-0 = <&otp_gpio>;
                 pinctrl-1 = <&otp_out>;

>
> -Doug
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


-- 
Thanks,
Caesar

Re: [PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller

[Caesar Wang]

Doug,

在 2015年10月20日 23:52, Doug Anderson 写道:
> Caesar,
>
> On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
>> We need the OTP pin is gpio state before resetting the TSADC controller,
>> since the tshut polarity will generate a high signal.
>>
>> Says:
>> The TSHUT temperature is setting more than 80 degree, the default tshut
>> polarity is high.
>>
>> If T > 80C, the OTP output the High Signal.
>> If T < 80C, the OTP output the Low Signal.
>>
>> On the moment, the TSADC controller is reset, the tshut polarity will be
>> low in a short period of time.
>> So:
>>
>> If T < 80C, the OTP output the High Signal.
>> If T > 80C, the OTP output the Low Signal.
>>
>> In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
>> accept the reset response time to avoid this issue.
>> In other words, the system will be always reboot if we make the OTP pin
>> is connected the others IC to control the power.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> ---
>>
>>   drivers/thermal/rockchip_thermal.c | 32 ++++++++++++++++++++++++++++++++
>>   1 file changed, 32 insertions(+)
> I think you could do this with no code changes to the thermal driver
> if we simply convince Linus W. to apply a change that I posted up just
> about a year ago.  See:
>
> https://patchwork.kernel.org/patch/5055741/
>
> In v1 of that patch at <https://patchwork.kernel.org/patch/5049041/>
> Linus said he liked it "A lot" and was willing to merge it with Greg
> KH's Ack and with a small comment fix.  I obtained the Ack and fixed
> the comment, but then the patch didn't end up being needed for me and
> so I never bumped it and it got lost...
>
> Maybe you could re-test that patch?  It looks like it has a merge
> conflict with current linuxnext but it looks trivial to resolve.  You
> could re-post my patch or I could repost it and you could add your
> Tested-by.
>
> You'd still want to have a bindings change to describe "init", but at
> least you shouldn't need any code changes.

Okay, https://patchwork.kernel.org/patch/5055741/ that's working for me.
Fell free add my  test tag if you resend the patch. (Tested-by: Caesar 
Wang <wxt@rock-chips.com>)


1634ed8 FROMLIST: drivers/pinctrl: Add the concept of an "init" state
15158f8 FROMLIST: ARM: dts: rockchip: Add the OTP gpio pinctrl
e7d3b88 FROMLIST: thermal: rockchip: change the TSHUT default state
184b154 FROMLIST: thermal: rockchip: ensure the otp state before 
resetting the controller
9edbe15 FROMLIST: dt-bindings: Sync the dts to this document

Meanwhile, I change the dts as follows.

-               pinctrl-names = "default", "otp_out";
+               pinctrl-names = "init", "default";
                 pinctrl-0 = <&otp_gpio>;
                 pinctrl-1 = <&otp_out>;

>
> -Doug
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


-- 
Thanks,
Caesar

[PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller

[Caesar Wang]

Doug,

? 2015?10?20? 23:52, Doug Anderson ??:
> Caesar,
>
> On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
>> We need the OTP pin is gpio state before resetting the TSADC controller,
>> since the tshut polarity will generate a high signal.
>>
>> Says:
>> The TSHUT temperature is setting more than 80 degree, the default tshut
>> polarity is high.
>>
>> If T > 80C, the OTP output the High Signal.
>> If T < 80C, the OTP output the Low Signal.
>>
>> On the moment, the TSADC controller is reset, the tshut polarity will be
>> low in a short period of time.
>> So:
>>
>> If T < 80C, the OTP output the High Signal.
>> If T > 80C, the OTP output the Low Signal.
>>
>> In some cases, the OTP pin is connected to the PMIC, maybe the PMIC can
>> accept the reset response time to avoid this issue.
>> In other words, the system will be always reboot if we make the OTP pin
>> is connected the others IC to control the power.
>>
>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
>> ---
>>
>>   drivers/thermal/rockchip_thermal.c | 32 ++++++++++++++++++++++++++++++++
>>   1 file changed, 32 insertions(+)
> I think you could do this with no code changes to the thermal driver
> if we simply convince Linus W. to apply a change that I posted up just
> about a year ago.  See:
>
> https://patchwork.kernel.org/patch/5055741/
>
> In v1 of that patch at <https://patchwork.kernel.org/patch/5049041/>
> Linus said he liked it "A lot" and was willing to merge it with Greg
> KH's Ack and with a small comment fix.  I obtained the Ack and fixed
> the comment, but then the patch didn't end up being needed for me and
> so I never bumped it and it got lost...
>
> Maybe you could re-test that patch?  It looks like it has a merge
> conflict with current linuxnext but it looks trivial to resolve.  You
> could re-post my patch or I could repost it and you could add your
> Tested-by.
>
> You'd still want to have a bindings change to describe "init", but at
> least you shouldn't need any code changes.

Okay, https://patchwork.kernel.org/patch/5055741/ that's working for me.
Fell free add my  test tag if you resend the patch. (Tested-by: Caesar 
Wang <wxt@rock-chips.com>)


1634ed8 FROMLIST: drivers/pinctrl: Add the concept of an "init" state
15158f8 FROMLIST: ARM: dts: rockchip: Add the OTP gpio pinctrl
e7d3b88 FROMLIST: thermal: rockchip: change the TSHUT default state
184b154 FROMLIST: thermal: rockchip: ensure the otp state before 
resetting the controller
9edbe15 FROMLIST: dt-bindings: Sync the dts to this document

Meanwhile, I change the dts as follows.

-               pinctrl-names = "default", "otp_out";
+               pinctrl-names = "init", "default";
                 pinctrl-0 = <&otp_gpio>;
                 pinctrl-1 = <&otp_out>;

>
> -Doug
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip


-- 
Thanks,
Caesar

Re: [PATCH 3/4] thermal: rockchip: change the TSHUT default state

[Doug Anderson]

Caesar,

On Tue, Oct 20, 2015 at 6:47 PM, Caesar Wang <caesar.upstream@gmail.com> wrote:
> Doug,
>
> 在 2015年10月21日 00:01, Doug Anderson 写道:
>
> Caesar,
>
> On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
>
> As the TRM says, the TSHUT default state is high active.
> In general, the TSHUT state can get from the dts. Otherwise
> it gets the state from this.
>
> Can you point at where the TRM says that the default state is high active?
>
> With the manual I have, I look at TSADC_AUTO_CON and I look at the
> description of "Bit 8".  It says that "tshut polarity" is 0 for low
> active and 1 for high active.  It then said that the Reset Value is 0.
>
> ...the "Reset Value" in tables like this is notoriously unreliable, so
> I can totally believe that it's wrong.  If you can point me at the
> part of the TRM that says that TSHUT is high active by default then I
> can confirm that for you.  ;)
>
>
> Okay, I know that's my wrong, the polarity is high or low can be selected.
> :-(
>
> I remember the veyron why is the default HiGH active, since the opt is
> connected to the PMIC.(we need think about the devices)
>
> Why is the evb board LOW active, since the opt didn't connected to the
> devices. TSHUT is depend on the CRU to work.

I think we can drop this patch then, right?  Any boards that need a
change from the default can just set "rockchip,hw-tshut-polarity",
right?

-Doug

Re: [PATCH 3/4] thermal: rockchip: change the TSHUT default state

[Doug Anderson]

Caesar,

On Tue, Oct 20, 2015 at 6:47 PM, Caesar Wang <caesar.upstream@gmail.com> wrote:
> Doug,
>
> 在 2015年10月21日 00:01, Doug Anderson 写道:
>
> Caesar,
>
> On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
>
> As the TRM says, the TSHUT default state is high active.
> In general, the TSHUT state can get from the dts. Otherwise
> it gets the state from this.
>
> Can you point at where the TRM says that the default state is high active?
>
> With the manual I have, I look at TSADC_AUTO_CON and I look at the
> description of "Bit 8".  It says that "tshut polarity" is 0 for low
> active and 1 for high active.  It then said that the Reset Value is 0.
>
> ...the "Reset Value" in tables like this is notoriously unreliable, so
> I can totally believe that it's wrong.  If you can point me at the
> part of the TRM that says that TSHUT is high active by default then I
> can confirm that for you.  ;)
>
>
> Okay, I know that's my wrong, the polarity is high or low can be selected.
> :-(
>
> I remember the veyron why is the default HiGH active, since the opt is
> connected to the PMIC.(we need think about the devices)
>
> Why is the evb board LOW active, since the opt didn't connected to the
> devices. TSHUT is depend on the CRU to work.

I think we can drop this patch then, right?  Any boards that need a
change from the default can just set "rockchip,hw-tshut-polarity",
right?

-Doug

[PATCH 3/4] thermal: rockchip: change the TSHUT default state

[Doug Anderson]

Caesar,

On Tue, Oct 20, 2015 at 6:47 PM, Caesar Wang <caesar.upstream@gmail.com> wrote:
> Doug,
>
> ? 2015?10?21? 00:01, Doug Anderson ??:
>
> Caesar,
>
> On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
>
> As the TRM says, the TSHUT default state is high active.
> In general, the TSHUT state can get from the dts. Otherwise
> it gets the state from this.
>
> Can you point at where the TRM says that the default state is high active?
>
> With the manual I have, I look at TSADC_AUTO_CON and I look at the
> description of "Bit 8".  It says that "tshut polarity" is 0 for low
> active and 1 for high active.  It then said that the Reset Value is 0.
>
> ...the "Reset Value" in tables like this is notoriously unreliable, so
> I can totally believe that it's wrong.  If you can point me at the
> part of the TRM that says that TSHUT is high active by default then I
> can confirm that for you.  ;)
>
>
> Okay, I know that's my wrong, the polarity is high or low can be selected.
> :-(
>
> I remember the veyron why is the default HiGH active, since the opt is
> connected to the PMIC.(we need think about the devices)
>
> Why is the evb board LOW active, since the opt didn't connected to the
> devices. TSHUT is depend on the CRU to work.

I think we can drop this patch then, right?  Any boards that need a
change from the default can just set "rockchip,hw-tshut-polarity",
right?

-Doug

Re: [PATCH 3/4] thermal: rockchip: change the TSHUT default state

[Caesar Wang]

Doug,

在 2015年10月21日 10:14, Doug Anderson 写道:
> Caesar,
>
> On Tue, Oct 20, 2015 at 6:47 PM, Caesar Wang <caesar.upstream@gmail.com> wrote:
>> Doug,
>>
>> 在 2015年10月21日 00:01, Doug Anderson 写道:
>>
>> Caesar,
>>
>> On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
>>
>> As the TRM says, the TSHUT default state is high active.
>> In general, the TSHUT state can get from the dts. Otherwise
>> it gets the state from this.
>>
>> Can you point at where the TRM says that the default state is high active?
>>
>> With the manual I have, I look at TSADC_AUTO_CON and I look at the
>> description of "Bit 8".  It says that "tshut polarity" is 0 for low
>> active and 1 for high active.  It then said that the Reset Value is 0.
>>
>> ...the "Reset Value" in tables like this is notoriously unreliable, so
>> I can totally believe that it's wrong.  If you can point me at the
>> part of the TRM that says that TSHUT is high active by default then I
>> can confirm that for you.  ;)
>>
>>
>> Okay, I know that's my wrong, the polarity is high or low can be selected.
>> :-(
>>
>> I remember the veyron why is the default HiGH active, since the opt is
>> connected to the PMIC.(we need think about the devices)
>>
>> Why is the evb board LOW active, since the opt didn't connected to the
>> devices. TSHUT is depend on the CRU to work.
> I think we can drop this patch then, right?  Any boards that need a
> change from the default can just set "rockchip,hw-tshut-polarity",
> right?
Yep, we should drop this patch.
I'm ready resend the patchs.


> -Doug
>

-- 
Thanks,
Caesar

Re: [PATCH 3/4] thermal: rockchip: change the TSHUT default state

[Caesar Wang]

Doug,

在 2015年10月21日 10:14, Doug Anderson 写道:
> Caesar,
>
> On Tue, Oct 20, 2015 at 6:47 PM, Caesar Wang <caesar.upstream@gmail.com> wrote:
>> Doug,
>>
>> 在 2015年10月21日 00:01, Doug Anderson 写道:
>>
>> Caesar,
>>
>> On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
>>
>> As the TRM says, the TSHUT default state is high active.
>> In general, the TSHUT state can get from the dts. Otherwise
>> it gets the state from this.
>>
>> Can you point at where the TRM says that the default state is high active?
>>
>> With the manual I have, I look at TSADC_AUTO_CON and I look at the
>> description of "Bit 8".  It says that "tshut polarity" is 0 for low
>> active and 1 for high active.  It then said that the Reset Value is 0.
>>
>> ...the "Reset Value" in tables like this is notoriously unreliable, so
>> I can totally believe that it's wrong.  If you can point me at the
>> part of the TRM that says that TSHUT is high active by default then I
>> can confirm that for you.  ;)
>>
>>
>> Okay, I know that's my wrong, the polarity is high or low can be selected.
>> :-(
>>
>> I remember the veyron why is the default HiGH active, since the opt is
>> connected to the PMIC.(we need think about the devices)
>>
>> Why is the evb board LOW active, since the opt didn't connected to the
>> devices. TSHUT is depend on the CRU to work.
> I think we can drop this patch then, right?  Any boards that need a
> change from the default can just set "rockchip,hw-tshut-polarity",
> right?
Yep, we should drop this patch.
I'm ready resend the patchs.


> -Doug
>

-- 
Thanks,
Caesar

[PATCH 3/4] thermal: rockchip: change the TSHUT default state

[Caesar Wang]

Doug,

? 2015?10?21? 10:14, Doug Anderson ??:
> Caesar,
>
> On Tue, Oct 20, 2015 at 6:47 PM, Caesar Wang <caesar.upstream@gmail.com> wrote:
>> Doug,
>>
>> ? 2015?10?21? 00:01, Doug Anderson ??:
>>
>> Caesar,
>>
>> On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:
>>
>> As the TRM says, the TSHUT default state is high active.
>> In general, the TSHUT state can get from the dts. Otherwise
>> it gets the state from this.
>>
>> Can you point at where the TRM says that the default state is high active?
>>
>> With the manual I have, I look at TSADC_AUTO_CON and I look at the
>> description of "Bit 8".  It says that "tshut polarity" is 0 for low
>> active and 1 for high active.  It then said that the Reset Value is 0.
>>
>> ...the "Reset Value" in tables like this is notoriously unreliable, so
>> I can totally believe that it's wrong.  If you can point me at the
>> part of the TRM that says that TSHUT is high active by default then I
>> can confirm that for you.  ;)
>>
>>
>> Okay, I know that's my wrong, the polarity is high or low can be selected.
>> :-(
>>
>> I remember the veyron why is the default HiGH active, since the opt is
>> connected to the PMIC.(we need think about the devices)
>>
>> Why is the evb board LOW active, since the opt didn't connected to the
>> devices. TSHUT is depend on the CRU to work.
> I think we can drop this patch then, right?  Any boards that need a
> change from the default can just set "rockchip,hw-tshut-polarity",
> right?
Yep, we should drop this patch.
I'm ready resend the patchs.


> -Doug
>

-- 
Thanks,
Caesar

Re: [PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller

[Linus Walleij]

On Wed, Oct 21, 2015 at 3:41 AM, Caesar Wang <caesar.upstream@gmail.com> wrote:
>> On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:

>> You'd still want to have a bindings change to describe "init", but at
>> least you shouldn't need any code changes.
>
> Okay, https://patchwork.kernel.org/patch/5055741/ that's working for me.
> Fell free add my  test tag if you resend the patch. (Tested-by: Caesar Wang
> <wxt@rock-chips.com>)

Doug, can you resend this rebased version with Caesar's Test tag?
I kinda like this more than any alternatives.

Yours,
Linus Walleij

Re: [PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller

[Linus Walleij]

On Wed, Oct 21, 2015 at 3:41 AM, Caesar Wang <caesar.upstream@gmail.com> wrote:
>> On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:

>> You'd still want to have a bindings change to describe "init", but at
>> least you shouldn't need any code changes.
>
> Okay, https://patchwork.kernel.org/patch/5055741/ that's working for me.
> Fell free add my  test tag if you resend the patch. (Tested-by: Caesar Wang
> <wxt@rock-chips.com>)

Doug, can you resend this rebased version with Caesar's Test tag?
I kinda like this more than any alternatives.

Yours,
Linus Walleij

[PATCH 2/4] thermal: rockchip: ensure the otp state before resetting the controller

[Linus Walleij]

On Wed, Oct 21, 2015 at 3:41 AM, Caesar Wang <caesar.upstream@gmail.com> wrote:
>> On Tue, Oct 20, 2015 at 2:11 AM, Caesar Wang <wxt@rock-chips.com> wrote:

>> You'd still want to have a bindings change to describe "init", but at
>> least you shouldn't need any code changes.
>
> Okay, https://patchwork.kernel.org/patch/5055741/ that's working for me.
> Fell free add my  test tag if you resend the patch. (Tested-by: Caesar Wang
> <wxt@rock-chips.com>)

Doug, can you resend this rebased version with Caesar's Test tag?
I kinda like this more than any alternatives.

Yours,
Linus Walleij