* [igt-dev] [PATCH i-g-t 1/6] tests/gem_render_copy: Make subtest parameters more explicit
2019-11-29 10:38 [igt-dev] [PATCH i-g-t 0/6] lib: Add tests validating media compressed surfaces Imre Deak
@ 2019-11-29 10:38 ` Imre Deak
2019-12-03 11:52 ` Kahola, Mika
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 2/6] tests/gem_render_copy: Separate out mixed tiled ccs subtests Imre Deak
` (8 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2019-11-29 10:38 UTC (permalink / raw)
To: igt-dev; +Cc: Brian Welty
A follow-up patch will add more subtests with varying source and
destination memory compression format and a way to force using the vebox
engine instead of the render engine for blitting. Prepare for that by
describing the compression types explicitly. Also add a flag for
subtests that do a blit from multiple source buffers with different
tilings into the destination buffer. This is not supported by the vebox
copy function (added later) due to the restrictions on defining
arbitrary source,destination surface regions for vebox blits.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
lib/intel_batchbuffer.h | 5 ++
tests/i915/gem_render_copy.c | 129 ++++++++++++++++++++++++-----------
2 files changed, 93 insertions(+), 41 deletions(-)
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index e5f6e6d0..402e68bc 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -210,6 +210,11 @@ void intel_copy_bo(struct intel_batchbuffer *batch,
#define I915_TILING_Yf 3
#define I915_TILING_Ys 4
+enum i915_compression {
+ I915_COMPRESSION_NONE,
+ I915_COMPRESSION_RENDER,
+};
+
/**
* igt_buf:
* @bo: underlying libdrm buffer object
diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
index 67be079c..cc8af1e1 100644
--- a/tests/i915/gem_render_copy.c
+++ b/tests/i915/gem_render_copy.c
@@ -413,7 +413,8 @@ scratch_buf_copy(data_t *data,
static void scratch_buf_init(data_t *data, struct igt_buf *buf,
int width, int height,
- uint32_t req_tiling, bool ccs)
+ uint32_t req_tiling,
+ enum i915_compression compression)
{
uint32_t tiling = req_tiling;
unsigned long pitch;
@@ -421,7 +422,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf,
memset(buf, 0, sizeof(*buf));
- if (ccs) {
+ if (compression != I915_COMPRESSION_NONE) {
int aux_width, aux_height;
int size;
@@ -572,10 +573,11 @@ static void scratch_buf_aux_check(data_t *data,
"Aux surface indicates that nothing was compressed\n");
}
-#define SRC_COMPRESSED 1
-#define DST_COMPRESSED 2
+#define SOURCE_MIXED_TILED 1
static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
+ enum i915_compression src_compression,
+ enum i915_compression dst_compression,
int flags)
{
struct igt_buf dst, src_ccs, dst_ccs, ref;
@@ -608,14 +610,15 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
};
int opt_dump_aub = igt_aub_dump_enabled();
int num_src = ARRAY_SIZE(src);
- bool src_compressed = flags & SRC_COMPRESSED;
- bool dst_compressed = flags & DST_COMPRESSED;
+ const bool src_mixed_tiled = flags & SOURCE_MIXED_TILED;
+ const bool src_compressed = src_compression != I915_COMPRESSION_NONE;
+ const bool dst_compressed = dst_compression != I915_COMPRESSION_NONE;
/*
- * The tiling for uncompressed source buffers is determined by the
- * tiling of the src[] buffers above.
+ * The source tilings for mixed source tiling test cases are determined
+ * by the tiling of the src[] buffers above.
*/
- igt_assert(!src_tiling || src_compressed);
+ igt_assert(src_tiling == I915_TILING_NONE || !src_mixed_tiled);
/* no Yf before gen9 */
if (intel_gen(data->devid) < 9)
@@ -626,15 +629,18 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
igt_require(intel_gen(data->devid) >= 9);
for (int i = 0; i < num_src; i++)
- scratch_buf_init(data, &src[i].buf, WIDTH, HEIGHT, src[i].tiling, false);
- scratch_buf_init(data, &dst, WIDTH, HEIGHT, dst_tiling, false);
+ scratch_buf_init(data, &src[i].buf, WIDTH, HEIGHT, src[i].tiling,
+ I915_COMPRESSION_NONE);
+ scratch_buf_init(data, &dst, WIDTH, HEIGHT, dst_tiling,
+ I915_COMPRESSION_NONE);
if (src_compressed)
scratch_buf_init(data, &src_ccs, WIDTH, HEIGHT,
- src_tiling, true);
+ src_tiling, src_compression);
if (dst_compressed)
scratch_buf_init(data, &dst_ccs, WIDTH, HEIGHT,
- dst_tiling, true);
- scratch_buf_init(data, &ref, WIDTH, HEIGHT, I915_TILING_NONE, false);
+ dst_tiling, dst_compression);
+ scratch_buf_init(data, &ref, WIDTH, HEIGHT, I915_TILING_NONE,
+ I915_COMPRESSION_NONE);
for (int i = 0; i < num_src; i++)
scratch_buf_draw_pattern(data, &src[i].buf,
@@ -765,7 +771,8 @@ const char *help_str =
" -a\tCheck all pixels\n"
;
-static const char *buf_mode_str(uint32_t tiling, bool compressed)
+static const char *buf_mode_str(uint32_t tiling,
+ enum i915_compression compression)
{
switch (tiling) {
default:
@@ -774,9 +781,11 @@ static const char *buf_mode_str(uint32_t tiling, bool compressed)
case I915_TILING_X:
return "x-tiled";
case I915_TILING_Y:
- return compressed ? "y-tiled-ccs" : "y-tiled";
+ return compression == I915_COMPRESSION_RENDER ? "y-tiled-ccs" :
+ "y-tiled";
case I915_TILING_Yf:
- return compressed ? "yf-tiled-ccs" : "yf-tiled";
+ return compression == I915_COMPRESSION_RENDER ? "yf-tiled-ccs" :
+ "yf-tiled";
}
}
@@ -785,27 +794,61 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
static const struct test_desc {
int src_tiling;
int dst_tiling;
+ enum i915_compression src_compression;
+ enum i915_compression dst_compression;
int flags;
} tests[] = {
- { I915_TILING_NONE, I915_TILING_NONE, 0 },
- { I915_TILING_NONE, I915_TILING_X, 0 },
- { I915_TILING_NONE, I915_TILING_Y, 0 },
- { I915_TILING_NONE, I915_TILING_Yf, 0 },
-
- { I915_TILING_Y, I915_TILING_NONE, SRC_COMPRESSED },
- { I915_TILING_Y, I915_TILING_X, SRC_COMPRESSED },
- { I915_TILING_Y, I915_TILING_Y, SRC_COMPRESSED },
- { I915_TILING_Y, I915_TILING_Yf, SRC_COMPRESSED },
-
- { I915_TILING_Yf, I915_TILING_NONE, SRC_COMPRESSED },
- { I915_TILING_Yf, I915_TILING_X, SRC_COMPRESSED },
- { I915_TILING_Yf, I915_TILING_Y, SRC_COMPRESSED },
- { I915_TILING_Yf, I915_TILING_Yf, SRC_COMPRESSED },
-
- { I915_TILING_Y, I915_TILING_Y, SRC_COMPRESSED | DST_COMPRESSED },
- { I915_TILING_Yf, I915_TILING_Yf, SRC_COMPRESSED | DST_COMPRESSED },
- { I915_TILING_Y, I915_TILING_Yf, SRC_COMPRESSED | DST_COMPRESSED },
- { I915_TILING_Yf, I915_TILING_Y, SRC_COMPRESSED | DST_COMPRESSED },
+ { I915_TILING_NONE, I915_TILING_NONE,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ SOURCE_MIXED_TILED, },
+ { I915_TILING_NONE, I915_TILING_X,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ SOURCE_MIXED_TILED, },
+ { I915_TILING_NONE, I915_TILING_Y,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ SOURCE_MIXED_TILED, },
+ { I915_TILING_NONE, I915_TILING_Yf,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ SOURCE_MIXED_TILED, },
+
+ { I915_TILING_Y, I915_TILING_NONE,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE,
+ 0, },
+ { I915_TILING_Y, I915_TILING_X,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE,
+ 0, },
+ { I915_TILING_Y, I915_TILING_Y,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE,
+ 0, },
+ { I915_TILING_Y, I915_TILING_Yf,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE,
+ 0, },
+
+ { I915_TILING_Yf, I915_TILING_NONE,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE,
+ 0, },
+ { I915_TILING_Yf, I915_TILING_X,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE,
+ 0, },
+ { I915_TILING_Yf, I915_TILING_Y,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE,
+ 0, },
+ { I915_TILING_Yf, I915_TILING_Yf,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE,
+ 0, },
+
+ { I915_TILING_Y, I915_TILING_Y,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_RENDER,
+ 0, },
+ { I915_TILING_Yf, I915_TILING_Yf,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_RENDER,
+ 0, },
+ { I915_TILING_Y, I915_TILING_Yf,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_RENDER,
+ 0, },
+ { I915_TILING_Yf, I915_TILING_Y,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_RENDER,
+ 0, },
};
int i;
@@ -832,18 +875,22 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
for (i = 0; i < ARRAY_SIZE(tests); i++) {
const struct test_desc *t = &tests[i];
const char *src_mode = buf_mode_str(t->src_tiling,
- t->flags & SRC_COMPRESSED);
+ t->src_compression);
const char *dst_mode = buf_mode_str(t->dst_tiling,
- t->flags & DST_COMPRESSED);
+ t->dst_compression);
+ const bool src_mixed_tiled = t->flags & SOURCE_MIXED_TILED;
igt_describe_f("Test render_copy() from a %s to a %s buffer.",
src_mode, dst_mode);
igt_subtest_f("%s%s%s",
- t->flags ? src_mode : "",
- t->flags ? "-to-" : "",
+ src_mixed_tiled ? "" : src_mode,
+ src_mixed_tiled ? "" : "-to-",
dst_mode)
- test(&data, t->src_tiling, t->dst_tiling, t->flags);
+ test(&data,
+ t->src_tiling, t->dst_tiling,
+ t->src_compression, t->dst_compression,
+ t->flags);
}
igt_fixture {
--
2.17.1
_______________________________________________
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igt-dev@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [igt-dev] [PATCH i-g-t 1/6] tests/gem_render_copy: Make subtest parameters more explicit
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 1/6] tests/gem_render_copy: Make subtest parameters more explicit Imre Deak
@ 2019-12-03 11:52 ` Kahola, Mika
0 siblings, 0 replies; 25+ messages in thread
From: Kahola, Mika @ 2019-12-03 11:52 UTC (permalink / raw)
To: igt-dev, Deak, Imre; +Cc: Welty, Brian
On Fri, 2019-11-29 at 12:38 +0200, Imre Deak wrote:
> A follow-up patch will add more subtests with varying source and
> destination memory compression format and a way to force using the
> vebox
> engine instead of the render engine for blitting. Prepare for that by
> describing the compression types explicitly. Also add a flag for
> subtests that do a blit from multiple source buffers with different
> tilings into the destination buffer. This is not supported by the
> vebox
> copy function (added later) due to the restrictions on defining
> arbitrary source,destination surface regions for vebox blits.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> lib/intel_batchbuffer.h | 5 ++
> tests/i915/gem_render_copy.c | 129 ++++++++++++++++++++++++---------
> --
> 2 files changed, 93 insertions(+), 41 deletions(-)
>
> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
> index e5f6e6d0..402e68bc 100644
> --- a/lib/intel_batchbuffer.h
> +++ b/lib/intel_batchbuffer.h
> @@ -210,6 +210,11 @@ void intel_copy_bo(struct intel_batchbuffer
> *batch,
> #define I915_TILING_Yf 3
> #define I915_TILING_Ys 4
>
> +enum i915_compression {
> + I915_COMPRESSION_NONE,
> + I915_COMPRESSION_RENDER,
> +};
> +
> /**
> * igt_buf:
> * @bo: underlying libdrm buffer object
> diff --git a/tests/i915/gem_render_copy.c
> b/tests/i915/gem_render_copy.c
> index 67be079c..cc8af1e1 100644
> --- a/tests/i915/gem_render_copy.c
> +++ b/tests/i915/gem_render_copy.c
> @@ -413,7 +413,8 @@ scratch_buf_copy(data_t *data,
>
> static void scratch_buf_init(data_t *data, struct igt_buf *buf,
> int width, int height,
> - uint32_t req_tiling, bool ccs)
> + uint32_t req_tiling,
> + enum i915_compression compression)
> {
> uint32_t tiling = req_tiling;
> unsigned long pitch;
> @@ -421,7 +422,7 @@ static void scratch_buf_init(data_t *data, struct
> igt_buf *buf,
>
> memset(buf, 0, sizeof(*buf));
>
> - if (ccs) {
> + if (compression != I915_COMPRESSION_NONE) {
> int aux_width, aux_height;
> int size;
>
> @@ -572,10 +573,11 @@ static void scratch_buf_aux_check(data_t *data,
> "Aux surface indicates that nothing was
> compressed\n");
> }
>
> -#define SRC_COMPRESSED 1
> -#define DST_COMPRESSED 2
> +#define SOURCE_MIXED_TILED 1
>
> static void test(data_t *data, uint32_t src_tiling, uint32_t
> dst_tiling,
> + enum i915_compression src_compression,
> + enum i915_compression dst_compression,
> int flags)
> {
> struct igt_buf dst, src_ccs, dst_ccs, ref;
> @@ -608,14 +610,15 @@ static void test(data_t *data, uint32_t
> src_tiling, uint32_t dst_tiling,
> };
> int opt_dump_aub = igt_aub_dump_enabled();
> int num_src = ARRAY_SIZE(src);
> - bool src_compressed = flags & SRC_COMPRESSED;
> - bool dst_compressed = flags & DST_COMPRESSED;
> + const bool src_mixed_tiled = flags & SOURCE_MIXED_TILED;
> + const bool src_compressed = src_compression !=
> I915_COMPRESSION_NONE;
> + const bool dst_compressed = dst_compression !=
> I915_COMPRESSION_NONE;
>
> /*
> - * The tiling for uncompressed source buffers is determined by
> the
> - * tiling of the src[] buffers above.
> + * The source tilings for mixed source tiling test cases are
> determined
> + * by the tiling of the src[] buffers above.
> */
> - igt_assert(!src_tiling || src_compressed);
> + igt_assert(src_tiling == I915_TILING_NONE || !src_mixed_tiled);
>
> /* no Yf before gen9 */
> if (intel_gen(data->devid) < 9)
> @@ -626,15 +629,18 @@ static void test(data_t *data, uint32_t
> src_tiling, uint32_t dst_tiling,
> igt_require(intel_gen(data->devid) >= 9);
>
> for (int i = 0; i < num_src; i++)
> - scratch_buf_init(data, &src[i].buf, WIDTH, HEIGHT,
> src[i].tiling, false);
> - scratch_buf_init(data, &dst, WIDTH, HEIGHT, dst_tiling, false);
> + scratch_buf_init(data, &src[i].buf, WIDTH, HEIGHT,
> src[i].tiling,
> + I915_COMPRESSION_NONE);
> + scratch_buf_init(data, &dst, WIDTH, HEIGHT, dst_tiling,
> + I915_COMPRESSION_NONE);
> if (src_compressed)
> scratch_buf_init(data, &src_ccs, WIDTH, HEIGHT,
> - src_tiling, true);
> + src_tiling, src_compression);
> if (dst_compressed)
> scratch_buf_init(data, &dst_ccs, WIDTH, HEIGHT,
> - dst_tiling, true);
> - scratch_buf_init(data, &ref, WIDTH, HEIGHT, I915_TILING_NONE,
> false);
> + dst_tiling, dst_compression);
> + scratch_buf_init(data, &ref, WIDTH, HEIGHT, I915_TILING_NONE,
> + I915_COMPRESSION_NONE);
>
> for (int i = 0; i < num_src; i++)
> scratch_buf_draw_pattern(data, &src[i].buf,
> @@ -765,7 +771,8 @@ const char *help_str =
> " -a\tCheck all pixels\n"
> ;
>
> -static const char *buf_mode_str(uint32_t tiling, bool compressed)
> +static const char *buf_mode_str(uint32_t tiling,
> + enum i915_compression compression)
> {
> switch (tiling) {
> default:
> @@ -774,9 +781,11 @@ static const char *buf_mode_str(uint32_t tiling,
> bool compressed)
> case I915_TILING_X:
> return "x-tiled";
> case I915_TILING_Y:
> - return compressed ? "y-tiled-ccs" : "y-tiled";
> + return compression == I915_COMPRESSION_RENDER ? "y-
> tiled-ccs" :
> + "y-
> tiled";
> case I915_TILING_Yf:
> - return compressed ? "yf-tiled-ccs" : "yf-tiled";
> + return compression == I915_COMPRESSION_RENDER ? "yf-
> tiled-ccs" :
> + "yf-
> tiled";
> }
> }
>
> @@ -785,27 +794,61 @@ igt_main_args("da", NULL, help_str,
> opt_handler, NULL)
> static const struct test_desc {
> int src_tiling;
> int dst_tiling;
> + enum i915_compression src_compression;
> + enum i915_compression dst_compression;
> int flags;
> } tests[] = {
> - { I915_TILING_NONE, I915_TILING_NONE, 0 },
> - { I915_TILING_NONE, I915_TILING_X, 0 },
> - { I915_TILING_NONE, I915_TILING_Y, 0 },
> - { I915_TILING_NONE, I915_TILING_Yf, 0 },
> -
> - { I915_TILING_Y, I915_TILING_NONE, SRC_COMPRESSED },
> - { I915_TILING_Y, I915_TILING_X, SRC_COMPRESSED },
> - { I915_TILING_Y, I915_TILING_Y, SRC_COMPRESSED },
> - { I915_TILING_Y, I915_TILING_Yf, SRC_COMPRESSED },
> -
> - { I915_TILING_Yf, I915_TILING_NONE, SRC_COMPRESSED },
> - { I915_TILING_Yf, I915_TILING_X, SRC_COMPRESSED },
> - { I915_TILING_Yf, I915_TILING_Y, SRC_COMPRESSED },
> - { I915_TILING_Yf, I915_TILING_Yf, SRC_COMPRESSED },
> -
> - { I915_TILING_Y, I915_TILING_Y, SRC_COMPRESSED |
> DST_COMPRESSED },
> - { I915_TILING_Yf, I915_TILING_Yf, SRC_COMPRESSED |
> DST_COMPRESSED },
> - { I915_TILING_Y, I915_TILING_Yf, SRC_COMPRESSED |
> DST_COMPRESSED },
> - { I915_TILING_Yf, I915_TILING_Y, SRC_COMPRESSED |
> DST_COMPRESSED },
> + { I915_TILING_NONE, I915_TILING_NONE,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + SOURCE_MIXED_TILED, },
> + { I915_TILING_NONE, I915_TILING_X,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + SOURCE_MIXED_TILED, },
> + { I915_TILING_NONE, I915_TILING_Y,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + SOURCE_MIXED_TILED, },
> + { I915_TILING_NONE, I915_TILING_Yf,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + SOURCE_MIXED_TILED, },
> +
> + { I915_TILING_Y, I915_TILING_NONE,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE
> ,
> + 0, },
> + { I915_TILING_Y, I915_TILING_X,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE
> ,
> + 0, },
> + { I915_TILING_Y, I915_TILING_Y,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE
> ,
> + 0, },
> + { I915_TILING_Y, I915_TILING_Yf,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE
> ,
> + 0, },
> +
> + { I915_TILING_Yf, I915_TILING_NONE,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE
> ,
> + 0, },
> + { I915_TILING_Yf, I915_TILING_X,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE
> ,
> + 0, },
> + { I915_TILING_Yf, I915_TILING_Y,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE
> ,
> + 0, },
> + { I915_TILING_Yf, I915_TILING_Yf,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE
> ,
> + 0, },
> +
> + { I915_TILING_Y, I915_TILING_Y,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_REND
> ER,
> + 0, },
> + { I915_TILING_Yf, I915_TILING_Yf,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_REND
> ER,
> + 0, },
> + { I915_TILING_Y, I915_TILING_Yf,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_REND
> ER,
> + 0, },
> + { I915_TILING_Yf, I915_TILING_Y,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_REND
> ER,
> + 0, },
> };
> int i;
>
> @@ -832,18 +875,22 @@ igt_main_args("da", NULL, help_str,
> opt_handler, NULL)
> for (i = 0; i < ARRAY_SIZE(tests); i++) {
> const struct test_desc *t = &tests[i];
> const char *src_mode = buf_mode_str(t->src_tiling,
> - t->flags &
> SRC_COMPRESSED);
> + t-
> >src_compression);
> const char *dst_mode = buf_mode_str(t->dst_tiling,
> - t->flags &
> DST_COMPRESSED);
> + t-
> >dst_compression);
> + const bool src_mixed_tiled = t->flags &
> SOURCE_MIXED_TILED;
>
> igt_describe_f("Test render_copy() from a %s to a %s
> buffer.",
> src_mode, dst_mode);
>
> igt_subtest_f("%s%s%s",
> - t->flags ? src_mode : "",
> - t->flags ? "-to-" : "",
> + src_mixed_tiled ? "" : src_mode,
> + src_mixed_tiled ? "" : "-to-",
> dst_mode)
> - test(&data, t->src_tiling, t->dst_tiling, t-
> >flags);
> + test(&data,
> + t->src_tiling, t->dst_tiling,
> + t->src_compression, t->dst_compression,
> + t->flags);
> }
>
> igt_fixture {
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [igt-dev] [PATCH i-g-t 2/6] tests/gem_render_copy: Separate out mixed tiled ccs subtests
2019-11-29 10:38 [igt-dev] [PATCH i-g-t 0/6] lib: Add tests validating media compressed surfaces Imre Deak
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 1/6] tests/gem_render_copy: Make subtest parameters more explicit Imre Deak
@ 2019-11-29 10:38 ` Imre Deak
2019-12-03 14:31 ` Kahola, Mika
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 3/6] lib: Move aux pgtable state prepare/emit to intel_aux_pgtable.c Imre Deak
` (7 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2019-11-29 10:38 UTC (permalink / raw)
To: igt-dev; +Cc: Brian Welty
Add separate subtests for the subtests copying from multiple source
buffers with different tiling formats into the destination buffer. The
vebox engine has restrictions on specifying arbitrary regions in the
source and destination surfaces, so we can't run these tests using that
engine (at least in their current form).
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
tests/i915/gem_render_copy.c | 167 ++++++++++++++++++++++++++---------
1 file changed, 126 insertions(+), 41 deletions(-)
diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
index cc8af1e1..15ba1704 100644
--- a/tests/i915/gem_render_copy.c
+++ b/tests/i915/gem_render_copy.c
@@ -197,6 +197,26 @@ static void *linear_copy(data_t *data, struct igt_buf *buf)
return linear;
}
+static void
+copy_from_linear_buf(data_t *data, struct igt_buf *src, struct igt_buf *dst)
+{
+ void *linear;
+
+ igt_assert(src->tiling == I915_TILING_NONE);
+
+ gem_set_domain(data->drm_fd, src->bo->handle,
+ I915_GEM_DOMAIN_CPU, 0);
+ linear = gem_mmap__cpu(data->drm_fd, src->bo->handle, 0,
+ src->bo->size, PROT_READ);
+
+ if (dst->tiling == I915_TILING_Yf)
+ copy_linear_to_yf(data, dst, linear);
+ else
+ copy_linear_to_gtt(data, dst, linear);
+
+ munmap(linear, src->bo->size);
+}
+
static void scratch_buf_write_to_png(data_t *data, struct igt_buf *buf,
const char *filename)
{
@@ -580,7 +600,7 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
enum i915_compression dst_compression,
int flags)
{
- struct igt_buf dst, src_ccs, dst_ccs, ref;
+ struct igt_buf ref, src_tiled, src_ccs, dst_ccs, dst;
struct {
struct igt_buf buf;
const char *filename;
@@ -631,6 +651,9 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
for (int i = 0; i < num_src; i++)
scratch_buf_init(data, &src[i].buf, WIDTH, HEIGHT, src[i].tiling,
I915_COMPRESSION_NONE);
+ if (!src_mixed_tiled)
+ scratch_buf_init(data, &src_tiled, WIDTH, HEIGHT, src_tiling,
+ I915_COMPRESSION_NONE);
scratch_buf_init(data, &dst, WIDTH, HEIGHT, dst_tiling,
I915_COMPRESSION_NONE);
if (src_compressed)
@@ -658,9 +681,15 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
&src[i].buf, WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
&ref, src[i].x, src[i].y);
+ if (!src_mixed_tiled)
+ copy_from_linear_buf(data, &ref, &src_tiled);
+
if (opt_dump_png) {
for (int i = 0; i < num_src; i++)
scratch_buf_write_to_png(data, &src[i].buf, src[i].filename);
+ if (!src_mixed_tiled)
+ scratch_buf_write_to_png(data, &src_tiled,
+ "source-tiled.png");
scratch_buf_write_to_png(data, &dst, "destination.png");
scratch_buf_write_to_png(data, &ref, "reference.png");
}
@@ -679,31 +708,51 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
* |dst|src|
* -------
*/
- if (src_compressed)
- data->render_copy(data->batch, NULL,
- &dst, 0, 0, WIDTH, HEIGHT,
- &src_ccs, 0, 0);
+ if (src_mixed_tiled) {
+ if (dst_compressed)
+ data->render_copy(data->batch, NULL,
+ &dst, 0, 0, WIDTH, HEIGHT,
+ &dst_ccs, 0, 0);
- for (int i = 0; i < num_src; i++)
- data->render_copy(data->batch, NULL,
- &src[i].buf,
- WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
- src_compressed ? &src_ccs : &dst,
- src[i].x, src[i].y);
-
- if (src_compressed || dst_compressed)
- data->render_copy(data->batch, NULL,
- src_compressed ? &src_ccs : &dst,
- 0, 0, WIDTH, HEIGHT,
- dst_compressed ? &dst_ccs : &dst,
- 0, 0);
+ for (int i = 0; i < num_src; i++)
+ data->render_copy(data->batch, NULL,
+ &src[i].buf,
+ WIDTH/4, HEIGHT/4, WIDTH/2-2, HEIGHT/2-2,
+ dst_compressed ? &dst_ccs : &dst,
+ src[i].x, src[i].y);
- if (dst_compressed)
- data->render_copy(data->batch, NULL,
- &dst_ccs,
- 0, 0, WIDTH, HEIGHT,
- &dst,
- 0, 0);
+ if (dst_compressed)
+ data->render_copy(data->batch, NULL,
+ &dst_ccs, 0, 0, WIDTH, HEIGHT,
+ &dst, 0, 0);
+
+ } else {
+ if (src_compression == I915_COMPRESSION_RENDER)
+ data->render_copy(data->batch, NULL,
+ &src_tiled, 0, 0, WIDTH, HEIGHT,
+ &src_ccs,
+ 0, 0);
+
+ if (dst_compression == I915_COMPRESSION_RENDER) {
+ data->render_copy(data->batch, NULL,
+ src_compressed ? &src_ccs : &src_tiled,
+ 0, 0, WIDTH, HEIGHT,
+ &dst_ccs,
+ 0, 0);
+
+ data->render_copy(data->batch, NULL,
+ &dst_ccs,
+ 0, 0, WIDTH, HEIGHT,
+ &dst,
+ 0, 0);
+ } else {
+ data->render_copy(data->batch, NULL,
+ src_compressed ? &src_ccs : &src_tiled,
+ 0, 0, WIDTH, HEIGHT,
+ &dst,
+ 0, 0);
+ }
+ }
if (opt_dump_png){
scratch_buf_write_to_png(data, &dst, "result.png");
@@ -771,22 +820,45 @@ const char *help_str =
" -a\tCheck all pixels\n"
;
-static const char *buf_mode_str(uint32_t tiling,
- enum i915_compression compression)
+static void buf_mode_to_str(uint32_t tiling, bool mixed_tiled,
+ enum i915_compression compression,
+ char *buf, int buf_size)
{
- switch (tiling) {
- default:
+ const char *compression_str;
+ const char *tiling_str;
+
+ if (mixed_tiled)
+ tiling_str = "mixed-tiled";
+ else switch (tiling) {
case I915_TILING_NONE:
- return "linear";
+ tiling_str = "linear";
+ break;
case I915_TILING_X:
- return "x-tiled";
+ tiling_str = "x-tiled";
+ break;
case I915_TILING_Y:
- return compression == I915_COMPRESSION_RENDER ? "y-tiled-ccs" :
- "y-tiled";
+ tiling_str = "y-tiled";
+ break;
case I915_TILING_Yf:
- return compression == I915_COMPRESSION_RENDER ? "yf-tiled-ccs" :
- "yf-tiled";
+ tiling_str = "yf-tiled";
+ break;
+ default:
+ igt_assert(0);
}
+
+ switch (compression) {
+ case I915_COMPRESSION_NONE:
+ compression_str = "";
+ break;
+ case I915_COMPRESSION_RENDER:
+ compression_str = "ccs";
+ break;
+ default:
+ igt_assert(0);
+ }
+
+ snprintf(buf, buf_size, "%s%s%s",
+ tiling_str, compression_str[0] ? "-" : "", compression_str);
}
igt_main_args("da", NULL, help_str, opt_handler, NULL)
@@ -811,6 +883,13 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
SOURCE_MIXED_TILED, },
+ { I915_TILING_NONE, I915_TILING_Y,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_RENDER,
+ SOURCE_MIXED_TILED },
+ { I915_TILING_NONE, I915_TILING_Yf,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_RENDER,
+ SOURCE_MIXED_TILED },
+
{ I915_TILING_Y, I915_TILING_NONE,
I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE,
0, },
@@ -874,19 +953,25 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
for (i = 0; i < ARRAY_SIZE(tests); i++) {
const struct test_desc *t = &tests[i];
- const char *src_mode = buf_mode_str(t->src_tiling,
- t->src_compression);
- const char *dst_mode = buf_mode_str(t->dst_tiling,
- t->dst_compression);
+ char src_mode[32];
+ char dst_mode[32];
const bool src_mixed_tiled = t->flags & SOURCE_MIXED_TILED;
+ buf_mode_to_str(t->src_tiling, src_mixed_tiled,
+ t->src_compression, src_mode, sizeof(src_mode));
+ buf_mode_to_str(t->dst_tiling, false,
+ t->dst_compression, dst_mode, sizeof(dst_mode));
+
igt_describe_f("Test render_copy() from a %s to a %s buffer.",
src_mode, dst_mode);
+ /* Preserve original test names */
+ if (src_mixed_tiled &&
+ t->dst_compression == I915_COMPRESSION_NONE)
+ src_mode[0] = '\0';
+
igt_subtest_f("%s%s%s",
- src_mixed_tiled ? "" : src_mode,
- src_mixed_tiled ? "" : "-to-",
- dst_mode)
+ src_mode, src_mode[0] ? "-to-" : "", dst_mode)
test(&data,
t->src_tiling, t->dst_tiling,
t->src_compression, t->dst_compression,
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [igt-dev] [PATCH i-g-t 2/6] tests/gem_render_copy: Separate out mixed tiled ccs subtests
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 2/6] tests/gem_render_copy: Separate out mixed tiled ccs subtests Imre Deak
@ 2019-12-03 14:31 ` Kahola, Mika
0 siblings, 0 replies; 25+ messages in thread
From: Kahola, Mika @ 2019-12-03 14:31 UTC (permalink / raw)
To: igt-dev, Deak, Imre; +Cc: Welty, Brian
On Fri, 2019-11-29 at 12:38 +0200, Imre Deak wrote:
> Add separate subtests for the subtests copying from multiple source
> buffers with different tiling formats into the destination buffer.
> The
> vebox engine has restrictions on specifying arbitrary regions in the
> source and destination surfaces, so we can't run these tests using
> that
> engine (at least in their current form).
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> tests/i915/gem_render_copy.c | 167 ++++++++++++++++++++++++++-------
> --
> 1 file changed, 126 insertions(+), 41 deletions(-)
>
> diff --git a/tests/i915/gem_render_copy.c
> b/tests/i915/gem_render_copy.c
> index cc8af1e1..15ba1704 100644
> --- a/tests/i915/gem_render_copy.c
> +++ b/tests/i915/gem_render_copy.c
> @@ -197,6 +197,26 @@ static void *linear_copy(data_t *data, struct
> igt_buf *buf)
> return linear;
> }
>
> +static void
> +copy_from_linear_buf(data_t *data, struct igt_buf *src, struct
> igt_buf *dst)
> +{
> + void *linear;
> +
> + igt_assert(src->tiling == I915_TILING_NONE);
> +
> + gem_set_domain(data->drm_fd, src->bo->handle,
> + I915_GEM_DOMAIN_CPU, 0);
> + linear = gem_mmap__cpu(data->drm_fd, src->bo->handle, 0,
> + src->bo->size, PROT_READ);
> +
> + if (dst->tiling == I915_TILING_Yf)
> + copy_linear_to_yf(data, dst, linear);
> + else
> + copy_linear_to_gtt(data, dst, linear);
> +
> + munmap(linear, src->bo->size);
> +}
> +
> static void scratch_buf_write_to_png(data_t *data, struct igt_buf
> *buf,
> const char *filename)
> {
> @@ -580,7 +600,7 @@ static void test(data_t *data, uint32_t
> src_tiling, uint32_t dst_tiling,
> enum i915_compression dst_compression,
> int flags)
> {
> - struct igt_buf dst, src_ccs, dst_ccs, ref;
> + struct igt_buf ref, src_tiled, src_ccs, dst_ccs, dst;
> struct {
> struct igt_buf buf;
> const char *filename;
> @@ -631,6 +651,9 @@ static void test(data_t *data, uint32_t
> src_tiling, uint32_t dst_tiling,
> for (int i = 0; i < num_src; i++)
> scratch_buf_init(data, &src[i].buf, WIDTH, HEIGHT,
> src[i].tiling,
> I915_COMPRESSION_NONE);
> + if (!src_mixed_tiled)
> + scratch_buf_init(data, &src_tiled, WIDTH, HEIGHT,
> src_tiling,
> + I915_COMPRESSION_NONE);
> scratch_buf_init(data, &dst, WIDTH, HEIGHT, dst_tiling,
> I915_COMPRESSION_NONE);
> if (src_compressed)
> @@ -658,9 +681,15 @@ static void test(data_t *data, uint32_t
> src_tiling, uint32_t dst_tiling,
> &src[i].buf, WIDTH/4, HEIGHT/4,
> WIDTH/2-2, HEIGHT/2-2,
> &ref, src[i].x, src[i].y);
>
> + if (!src_mixed_tiled)
> + copy_from_linear_buf(data, &ref, &src_tiled);
> +
> if (opt_dump_png) {
> for (int i = 0; i < num_src; i++)
> scratch_buf_write_to_png(data, &src[i].buf,
> src[i].filename);
> + if (!src_mixed_tiled)
> + scratch_buf_write_to_png(data, &src_tiled,
> + "source-tiled.png");
> scratch_buf_write_to_png(data, &dst,
> "destination.png");
> scratch_buf_write_to_png(data, &ref, "reference.png");
> }
> @@ -679,31 +708,51 @@ static void test(data_t *data, uint32_t
> src_tiling, uint32_t dst_tiling,
> * |dst|src|
> * -------
> */
> - if (src_compressed)
> - data->render_copy(data->batch, NULL,
> - &dst, 0, 0, WIDTH, HEIGHT,
> - &src_ccs, 0, 0);
> + if (src_mixed_tiled) {
> + if (dst_compressed)
> + data->render_copy(data->batch, NULL,
> + &dst, 0, 0, WIDTH, HEIGHT,
> + &dst_ccs, 0, 0);
>
> - for (int i = 0; i < num_src; i++)
> - data->render_copy(data->batch, NULL,
> - &src[i].buf,
> - WIDTH/4, HEIGHT/4, WIDTH/2-2,
> HEIGHT/2-2,
> - src_compressed ? &src_ccs : &dst,
> - src[i].x, src[i].y);
> -
> - if (src_compressed || dst_compressed)
> - data->render_copy(data->batch, NULL,
> - src_compressed ? &src_ccs : &dst,
> - 0, 0, WIDTH, HEIGHT,
> - dst_compressed ? &dst_ccs : &dst,
> - 0, 0);
> + for (int i = 0; i < num_src; i++)
> + data->render_copy(data->batch, NULL,
> + &src[i].buf,
> + WIDTH/4, HEIGHT/4, WIDTH/2-2,
> HEIGHT/2-2,
> + dst_compressed ? &dst_ccs :
> &dst,
> + src[i].x, src[i].y);
>
> - if (dst_compressed)
> - data->render_copy(data->batch, NULL,
> - &dst_ccs,
> - 0, 0, WIDTH, HEIGHT,
> - &dst,
> - 0, 0);
> + if (dst_compressed)
> + data->render_copy(data->batch, NULL,
> + &dst_ccs, 0, 0, WIDTH,
> HEIGHT,
> + &dst, 0, 0);
> +
> + } else {
> + if (src_compression == I915_COMPRESSION_RENDER)
> + data->render_copy(data->batch, NULL,
> + &src_tiled, 0, 0, WIDTH,
> HEIGHT,
> + &src_ccs,
> + 0, 0);
> +
> + if (dst_compression == I915_COMPRESSION_RENDER) {
> + data->render_copy(data->batch, NULL,
> + src_compressed ? &src_ccs :
> &src_tiled,
> + 0, 0, WIDTH, HEIGHT,
> + &dst_ccs,
> + 0, 0);
> +
> + data->render_copy(data->batch, NULL,
> + &dst_ccs,
> + 0, 0, WIDTH, HEIGHT,
> + &dst,
> + 0, 0);
> + } else {
> + data->render_copy(data->batch, NULL,
> + src_compressed ? &src_ccs :
> &src_tiled,
> + 0, 0, WIDTH, HEIGHT,
> + &dst,
> + 0, 0);
> + }
> + }
>
> if (opt_dump_png){
> scratch_buf_write_to_png(data, &dst, "result.png");
> @@ -771,22 +820,45 @@ const char *help_str =
> " -a\tCheck all pixels\n"
> ;
>
> -static const char *buf_mode_str(uint32_t tiling,
> - enum i915_compression compression)
> +static void buf_mode_to_str(uint32_t tiling, bool mixed_tiled,
> + enum i915_compression compression,
> + char *buf, int buf_size)
> {
> - switch (tiling) {
> - default:
> + const char *compression_str;
> + const char *tiling_str;
> +
> + if (mixed_tiled)
> + tiling_str = "mixed-tiled";
> + else switch (tiling) {
> case I915_TILING_NONE:
> - return "linear";
> + tiling_str = "linear";
> + break;
> case I915_TILING_X:
> - return "x-tiled";
> + tiling_str = "x-tiled";
> + break;
> case I915_TILING_Y:
> - return compression == I915_COMPRESSION_RENDER ? "y-
> tiled-ccs" :
> - "y-
> tiled";
> + tiling_str = "y-tiled";
> + break;
> case I915_TILING_Yf:
> - return compression == I915_COMPRESSION_RENDER ? "yf-
> tiled-ccs" :
> - "yf-
> tiled";
> + tiling_str = "yf-tiled";
> + break;
> + default:
> + igt_assert(0);
> }
> +
> + switch (compression) {
> + case I915_COMPRESSION_NONE:
> + compression_str = "";
> + break;
> + case I915_COMPRESSION_RENDER:
> + compression_str = "ccs";
> + break;
> + default:
> + igt_assert(0);
> + }
> +
> + snprintf(buf, buf_size, "%s%s%s",
> + tiling_str, compression_str[0] ? "-" : "",
> compression_str);
> }
>
> igt_main_args("da", NULL, help_str, opt_handler, NULL)
> @@ -811,6 +883,13 @@ igt_main_args("da", NULL, help_str, opt_handler,
> NULL)
> I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> SOURCE_MIXED_TILED, },
>
> + { I915_TILING_NONE, I915_TILING_Y,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_RENDER,
> + SOURCE_MIXED_TILED },
> + { I915_TILING_NONE, I915_TILING_Yf,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_RENDER,
> + SOURCE_MIXED_TILED },
> +
> { I915_TILING_Y, I915_TILING_NONE,
> I915_COMPRESSION_RENDER, I915_COMPRESSION_NONE
> ,
> 0, },
> @@ -874,19 +953,25 @@ igt_main_args("da", NULL, help_str,
> opt_handler, NULL)
>
> for (i = 0; i < ARRAY_SIZE(tests); i++) {
> const struct test_desc *t = &tests[i];
> - const char *src_mode = buf_mode_str(t->src_tiling,
> - t-
> >src_compression);
> - const char *dst_mode = buf_mode_str(t->dst_tiling,
> - t-
> >dst_compression);
> + char src_mode[32];
> + char dst_mode[32];
> const bool src_mixed_tiled = t->flags &
> SOURCE_MIXED_TILED;
>
> + buf_mode_to_str(t->src_tiling, src_mixed_tiled,
> + t->src_compression, src_mode,
> sizeof(src_mode));
> + buf_mode_to_str(t->dst_tiling, false,
> + t->dst_compression, dst_mode,
> sizeof(dst_mode));
> +
> igt_describe_f("Test render_copy() from a %s to a %s
> buffer.",
> src_mode, dst_mode);
>
> + /* Preserve original test names */
> + if (src_mixed_tiled &&
> + t->dst_compression == I915_COMPRESSION_NONE)
> + src_mode[0] = '\0';
> +
> igt_subtest_f("%s%s%s",
> - src_mixed_tiled ? "" : src_mode,
> - src_mixed_tiled ? "" : "-to-",
> - dst_mode)
> + src_mode, src_mode[0] ? "-to-" : "",
> dst_mode)
> test(&data,
> t->src_tiling, t->dst_tiling,
> t->src_compression, t->dst_compression,
_______________________________________________
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^ permalink raw reply [flat|nested] 25+ messages in thread
* [igt-dev] [PATCH i-g-t 3/6] lib: Move aux pgtable state prepare/emit to intel_aux_pgtable.c
2019-11-29 10:38 [igt-dev] [PATCH i-g-t 0/6] lib: Add tests validating media compressed surfaces Imre Deak
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 1/6] tests/gem_render_copy: Make subtest parameters more explicit Imre Deak
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 2/6] tests/gem_render_copy: Separate out mixed tiled ccs subtests Imre Deak
@ 2019-11-29 10:38 ` Imre Deak
2019-12-03 14:50 ` Kahola, Mika
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 4/6] lib/intel_aux_pgtable: Set MMIO remap for write the AUX pagedir reg Imre Deak
` (6 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2019-11-29 10:38 UTC (permalink / raw)
To: igt-dev; +Cc: Brian Welty
The AUX pagetables need to be set up for blits using the vebox engine
too, so move the related helper functions to intel_aux_pgtable.c.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
lib/intel_aux_pgtable.c | 198 ++++++++++++++++++++++++++++++++++++++
lib/intel_aux_pgtable.h | 23 +++++
lib/rendercopy_gen9.c | 205 ----------------------------------------
3 files changed, 221 insertions(+), 205 deletions(-)
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index ea909ec0..319b2745 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -370,3 +370,201 @@ intel_aux_pgtable_create(drm_intel_bufmgr *bufmgr,
return pgt_bo;
}
+
+static void
+aux_pgtable_find_max_free_range(const struct igt_buf **bufs, int buf_count,
+ uint64_t *range_start, uint64_t *range_size)
+{
+ /*
+ * Keep the first page reserved, so we can differentiate pinned
+ * objects based on a non-NULL offset.
+ */
+ uint64_t start = 0x1000;
+ /* For now alloc only from the first 4GB address space. */
+ const uint64_t end = 1ULL << 32;
+ uint64_t max_range_start = 0;
+ uint64_t max_range_size = 0;
+ int i;
+
+ for (i = 0; i < buf_count; i++) {
+ if (bufs[i]->bo->offset64 >= end)
+ break;
+
+ if (bufs[i]->bo->offset64 - start > max_range_size) {
+ max_range_start = start;
+ max_range_size = bufs[i]->bo->offset64 - start;
+ }
+ start = bufs[i]->bo->offset64 + bufs[i]->bo->size;
+ }
+
+ if (start < end && end - start > max_range_size) {
+ max_range_start = start;
+ max_range_size = end - start;
+ }
+
+ *range_start = max_range_start;
+ *range_size = max_range_size;
+}
+
+static uint64_t
+aux_pgtable_find_free_range(const struct igt_buf **bufs, int buf_count,
+ uint32_t size)
+{
+ uint64_t range_start;
+ uint64_t range_size;
+ /* A compressed surface must be 64kB aligned. */
+ const uint32_t align = 0x10000;
+ int pad;
+
+ aux_pgtable_find_max_free_range(bufs, buf_count,
+ &range_start, &range_size);
+
+ pad = ALIGN(range_start, align) - range_start;
+ range_start += pad;
+ range_size -= pad;
+ igt_assert(range_size >= size);
+
+ return range_start +
+ ALIGN_DOWN(rand() % ((range_size - size) + 1), align);
+}
+
+static void
+aux_pgtable_reserve_range(const struct igt_buf **bufs, int buf_count,
+ const struct igt_buf *new_buf)
+{
+ int i;
+
+ if (new_buf->aux.stride) {
+ uint64_t pin_offset = new_buf->bo->offset64;
+
+ if (!pin_offset)
+ pin_offset = aux_pgtable_find_free_range(bufs,
+ buf_count,
+ new_buf->bo->size);
+ drm_intel_bo_set_softpin_offset(new_buf->bo, pin_offset);
+ igt_assert(new_buf->bo->offset64 == pin_offset);
+ }
+
+ for (i = 0; i < buf_count; i++)
+ if (bufs[i]->bo->offset64 > new_buf->bo->offset64)
+ break;
+
+ memmove(&bufs[i + 1], &bufs[i], sizeof(bufs[0]) * (buf_count - i));
+
+ bufs[i] = new_buf;
+}
+
+void
+gen12_aux_pgtable_init(struct aux_pgtable_info *info,
+ drm_intel_bufmgr *bufmgr,
+ const struct igt_buf *src_buf,
+ const struct igt_buf *dst_buf)
+{
+ const struct igt_buf *bufs[2];
+ const struct igt_buf *reserved_bufs[2];
+ int reserved_buf_count;
+ int i;
+
+ if (!src_buf->aux.stride && !dst_buf->aux.stride)
+ return;
+
+ bufs[0] = src_buf;
+ bufs[1] = dst_buf;
+
+ /*
+ * Ideally we'd need an IGT-wide GFX address space allocator, which
+ * would consider all allocations and thus avoid evictions. For now use
+ * a simpler scheme here, which only considers the buffers involved in
+ * the blit, which should at least minimize the chance for evictions
+ * in the case of subsequent blits:
+ * 1. If they were already bound (bo->offset64 != 0), use this
+ * address.
+ * 2. Pick a range randomly from the 4GB address space, that is not
+ * already occupied by a bound object, or an object we pinned.
+ */
+ reserved_buf_count = 0;
+ /* First reserve space for any bufs that are bound already. */
+ for (i = 0; i < ARRAY_SIZE(bufs); i++)
+ if (bufs[i]->bo->offset64)
+ aux_pgtable_reserve_range(reserved_bufs,
+ reserved_buf_count++,
+ bufs[i]);
+
+ /* Next, reserve space for unbound bufs with an AUX surface. */
+ for (i = 0; i < ARRAY_SIZE(bufs); i++)
+ if (!bufs[i]->bo->offset64 && bufs[i]->aux.stride)
+ aux_pgtable_reserve_range(reserved_bufs,
+ reserved_buf_count++,
+ bufs[i]);
+
+ /* Create AUX pgtable entries only for bufs with an AUX surface */
+ info->buf_count = 0;
+ for (i = 0; i < reserved_buf_count; i++) {
+ if (!reserved_bufs[i]->aux.stride)
+ continue;
+
+ info->bufs[info->buf_count] = reserved_bufs[i];
+ info->buf_pin_offsets[info->buf_count] =
+ reserved_bufs[i]->bo->offset64;
+ info->buf_count++;
+ }
+
+ info->pgtable_bo = intel_aux_pgtable_create(bufmgr,
+ info->bufs,
+ info->buf_count);
+ igt_assert(info->pgtable_bo);
+}
+
+void
+gen12_aux_pgtable_cleanup(struct aux_pgtable_info *info)
+{
+ int i;
+
+ /* Check that the pinned bufs kept their offset after the exec. */
+ for (i = 0; i < info->buf_count; i++)
+ igt_assert_eq_u64(info->bufs[i]->bo->offset64,
+ info->buf_pin_offsets[i]);
+
+ drm_intel_bo_unreference(info->pgtable_bo);
+}
+
+uint32_t
+gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
+ drm_intel_bo *aux_pgtable_bo)
+{
+ uint64_t *pgtable_ptr;
+ uint32_t pgtable_ptr_offset;
+ int ret;
+
+ if (!aux_pgtable_bo)
+ return 0;
+
+ pgtable_ptr = intel_batchbuffer_subdata_alloc(batch,
+ sizeof(*pgtable_ptr),
+ sizeof(*pgtable_ptr));
+ pgtable_ptr_offset = intel_batchbuffer_subdata_offset(batch,
+ pgtable_ptr);
+
+ *pgtable_ptr = aux_pgtable_bo->offset64;
+ ret = drm_intel_bo_emit_reloc(batch->bo, pgtable_ptr_offset,
+ aux_pgtable_bo, 0,
+ 0, 0);
+ assert(ret == 0);
+
+ return pgtable_ptr_offset;
+}
+
+void
+gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state)
+{
+ if (!state)
+ return;
+
+ OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
+ OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
+ OUT_RELOC(batch->bo, 0, 0, state);
+
+ OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
+ OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
+ OUT_RELOC(batch->bo, 0, 0, state + 4);
+}
diff --git a/lib/intel_aux_pgtable.h b/lib/intel_aux_pgtable.h
index c0f001b4..20278db0 100644
--- a/lib/intel_aux_pgtable.h
+++ b/lib/intel_aux_pgtable.h
@@ -4,9 +4,32 @@
#include "intel_bufmgr.h"
struct igt_buf;
+struct intel_batchbuffer;
+
+struct aux_pgtable_info {
+ int buf_count;
+ const struct igt_buf *bufs[2];
+ uint64_t buf_pin_offsets[2];
+ drm_intel_bo *pgtable_bo;
+};
drm_intel_bo *
intel_aux_pgtable_create(drm_intel_bufmgr *bufmgr,
const struct igt_buf **bufs, int buf_count);
+void
+gen12_aux_pgtable_init(struct aux_pgtable_info *info,
+ drm_intel_bufmgr *bufmgr,
+ const struct igt_buf *src_buf,
+ const struct igt_buf *dst_buf);
+
+void
+gen12_aux_pgtable_cleanup(struct aux_pgtable_info *info);
+
+uint32_t
+gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
+ drm_intel_bo *aux_pgtable_bo);
+void
+gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state);
+
#endif
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 3189594f..94e816b6 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -973,211 +973,6 @@ static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset
#define BATCH_STATE_SPLIT 2048
-static void
-aux_pgtable_find_max_free_range(const struct igt_buf **bufs, int buf_count,
- uint64_t *range_start, uint64_t *range_size)
-{
- /*
- * Keep the first page reserved, so we can differentiate pinned
- * objects based on a non-NULL offset.
- */
- uint64_t start = 0x1000;
- /* For now alloc only from the first 4GB address space. */
- const uint64_t end = 1ULL << 32;
- uint64_t max_range_start = 0;
- uint64_t max_range_size = 0;
- int i;
-
- for (i = 0; i < buf_count; i++) {
- if (bufs[i]->bo->offset64 >= end)
- break;
-
- if (bufs[i]->bo->offset64 - start > max_range_size) {
- max_range_start = start;
- max_range_size = bufs[i]->bo->offset64 - start;
- }
- start = bufs[i]->bo->offset64 + bufs[i]->bo->size;
- }
-
- if (start < end && end - start > max_range_size) {
- max_range_start = start;
- max_range_size = end - start;
- }
-
- *range_start = max_range_start;
- *range_size = max_range_size;
-}
-
-static uint64_t
-aux_pgtable_find_free_range(const struct igt_buf **bufs, int buf_count,
- uint32_t size)
-{
- uint64_t range_start;
- uint64_t range_size;
- /* A compressed surface must be 64kB aligned. */
- const uint32_t align = 0x10000;
- int pad;
-
- aux_pgtable_find_max_free_range(bufs, buf_count,
- &range_start, &range_size);
-
- pad = ALIGN(range_start, align) - range_start;
- range_start += pad;
- range_size -= pad;
- igt_assert(range_size >= size);
-
- return range_start +
- ALIGN_DOWN(rand() % ((range_size - size) + 1), align);
-}
-
-static void
-aux_pgtable_reserve_range(const struct igt_buf **bufs, int buf_count,
- const struct igt_buf *new_buf)
-{
- int i;
-
- if (new_buf->aux.stride) {
- uint64_t pin_offset = new_buf->bo->offset64;
-
- if (!pin_offset)
- pin_offset = aux_pgtable_find_free_range(bufs,
- buf_count,
- new_buf->bo->size);
- drm_intel_bo_set_softpin_offset(new_buf->bo, pin_offset);
- igt_assert(new_buf->bo->offset64 == pin_offset);
- }
-
- for (i = 0; i < buf_count; i++)
- if (bufs[i]->bo->offset64 > new_buf->bo->offset64)
- break;
-
- memmove(&bufs[i + 1], &bufs[i], sizeof(bufs[0]) * (buf_count - i));
-
- bufs[i] = new_buf;
-}
-
-struct aux_pgtable_info {
- int buf_count;
- const struct igt_buf *bufs[2];
- uint64_t buf_pin_offsets[2];
- drm_intel_bo *pgtable_bo;
-};
-
-static void
-gen12_aux_pgtable_init(struct aux_pgtable_info *info,
- drm_intel_bufmgr *bufmgr,
- const struct igt_buf *src_buf,
- const struct igt_buf *dst_buf)
-{
- const struct igt_buf *bufs[2];
- const struct igt_buf *reserved_bufs[2];
- int reserved_buf_count;
- int i;
-
- if (!src_buf->aux.stride && !dst_buf->aux.stride)
- return;
-
- bufs[0] = src_buf;
- bufs[1] = dst_buf;
-
- /*
- * Ideally we'd need an IGT-wide GFX address space allocator, which
- * would consider all allocations and thus avoid evictions. For now use
- * a simpler scheme here, which only considers the buffers involved in
- * the blit, which should at least minimize the chance for evictions
- * in the case of subsequent blits:
- * 1. If they were already bound (bo->offset64 != 0), use this
- * address.
- * 2. Pick a range randomly from the 4GB address space, that is not
- * already occupied by a bound object, or an object we pinned.
- */
- reserved_buf_count = 0;
- /* First reserve space for any bufs that are bound already. */
- for (i = 0; i < ARRAY_SIZE(bufs); i++)
- if (bufs[i]->bo->offset64)
- aux_pgtable_reserve_range(reserved_bufs,
- reserved_buf_count++,
- bufs[i]);
-
- /* Next, reserve space for unbound bufs with an AUX surface. */
- for (i = 0; i < ARRAY_SIZE(bufs); i++)
- if (!bufs[i]->bo->offset64 && bufs[i]->aux.stride)
- aux_pgtable_reserve_range(reserved_bufs,
- reserved_buf_count++,
- bufs[i]);
-
- /* Create AUX pgtable entries only for bufs with an AUX surface */
- info->buf_count = 0;
- for (i = 0; i < reserved_buf_count; i++) {
- if (!reserved_bufs[i]->aux.stride)
- continue;
-
- info->bufs[info->buf_count] = reserved_bufs[i];
- info->buf_pin_offsets[info->buf_count] =
- reserved_bufs[i]->bo->offset64;
- info->buf_count++;
- }
-
- info->pgtable_bo = intel_aux_pgtable_create(bufmgr,
- info->bufs,
- info->buf_count);
- igt_assert(info->pgtable_bo);
-}
-
-static void
-gen12_aux_pgtable_cleanup(struct aux_pgtable_info *info)
-{
- int i;
-
- /* Check that the pinned bufs kept their offset after the exec. */
- for (i = 0; i < info->buf_count; i++)
- igt_assert_eq_u64(info->bufs[i]->bo->offset64,
- info->buf_pin_offsets[i]);
-
- drm_intel_bo_unreference(info->pgtable_bo);
-}
-
-static uint32_t
-gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
- drm_intel_bo *aux_pgtable_bo)
-{
- uint64_t *pgtable_ptr;
- uint32_t pgtable_ptr_offset;
- int ret;
-
- if (!aux_pgtable_bo)
- return 0;
-
- pgtable_ptr = intel_batchbuffer_subdata_alloc(batch,
- sizeof(*pgtable_ptr),
- sizeof(*pgtable_ptr));
- pgtable_ptr_offset = intel_batchbuffer_subdata_offset(batch,
- pgtable_ptr);
-
- *pgtable_ptr = aux_pgtable_bo->offset64;
- ret = drm_intel_bo_emit_reloc(batch->bo, pgtable_ptr_offset,
- aux_pgtable_bo, 0,
- 0, 0);
- assert(ret == 0);
-
- return pgtable_ptr_offset;
-}
-
-static void
-gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state)
-{
- if (!state)
- return;
-
- OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
- OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
- OUT_RELOC(batch->bo, 0, 0, state);
-
- OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
- OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
- OUT_RELOC(batch->bo, 0, 0, state + 4);
-}
-
static
void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
drm_intel_context *context,
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [igt-dev] [PATCH i-g-t 3/6] lib: Move aux pgtable state prepare/emit to intel_aux_pgtable.c
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 3/6] lib: Move aux pgtable state prepare/emit to intel_aux_pgtable.c Imre Deak
@ 2019-12-03 14:50 ` Kahola, Mika
0 siblings, 0 replies; 25+ messages in thread
From: Kahola, Mika @ 2019-12-03 14:50 UTC (permalink / raw)
To: igt-dev, Deak, Imre; +Cc: Welty, Brian
On Fri, 2019-11-29 at 12:38 +0200, Imre Deak wrote:
> The AUX pagetables need to be set up for blits using the vebox engine
> too, so move the related helper functions to intel_aux_pgtable.c.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> lib/intel_aux_pgtable.c | 198 ++++++++++++++++++++++++++++++++++++++
> lib/intel_aux_pgtable.h | 23 +++++
> lib/rendercopy_gen9.c | 205 --------------------------------------
> --
> 3 files changed, 221 insertions(+), 205 deletions(-)
>
> diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
> index ea909ec0..319b2745 100644
> --- a/lib/intel_aux_pgtable.c
> +++ b/lib/intel_aux_pgtable.c
> @@ -370,3 +370,201 @@ intel_aux_pgtable_create(drm_intel_bufmgr
> *bufmgr,
>
> return pgt_bo;
> }
> +
> +static void
> +aux_pgtable_find_max_free_range(const struct igt_buf **bufs, int
> buf_count,
> + uint64_t *range_start, uint64_t
> *range_size)
> +{
> + /*
> + * Keep the first page reserved, so we can differentiate pinned
> + * objects based on a non-NULL offset.
> + */
> + uint64_t start = 0x1000;
> + /* For now alloc only from the first 4GB address space. */
> + const uint64_t end = 1ULL << 32;
> + uint64_t max_range_start = 0;
> + uint64_t max_range_size = 0;
> + int i;
> +
> + for (i = 0; i < buf_count; i++) {
> + if (bufs[i]->bo->offset64 >= end)
> + break;
> +
> + if (bufs[i]->bo->offset64 - start > max_range_size) {
> + max_range_start = start;
> + max_range_size = bufs[i]->bo->offset64 - start;
> + }
> + start = bufs[i]->bo->offset64 + bufs[i]->bo->size;
> + }
> +
> + if (start < end && end - start > max_range_size) {
> + max_range_start = start;
> + max_range_size = end - start;
> + }
> +
> + *range_start = max_range_start;
> + *range_size = max_range_size;
> +}
> +
> +static uint64_t
> +aux_pgtable_find_free_range(const struct igt_buf **bufs, int
> buf_count,
> + uint32_t size)
> +{
> + uint64_t range_start;
> + uint64_t range_size;
> + /* A compressed surface must be 64kB aligned. */
> + const uint32_t align = 0x10000;
> + int pad;
> +
> + aux_pgtable_find_max_free_range(bufs, buf_count,
> + &range_start, &range_size);
> +
> + pad = ALIGN(range_start, align) - range_start;
> + range_start += pad;
> + range_size -= pad;
> + igt_assert(range_size >= size);
> +
> + return range_start +
> + ALIGN_DOWN(rand() % ((range_size - size) + 1), align);
> +}
> +
> +static void
> +aux_pgtable_reserve_range(const struct igt_buf **bufs, int
> buf_count,
> + const struct igt_buf *new_buf)
> +{
> + int i;
> +
> + if (new_buf->aux.stride) {
> + uint64_t pin_offset = new_buf->bo->offset64;
> +
> + if (!pin_offset)
> + pin_offset = aux_pgtable_find_free_range(bufs,
> + buf_co
> unt,
> + new_bu
> f->bo->size);
> + drm_intel_bo_set_softpin_offset(new_buf->bo,
> pin_offset);
> + igt_assert(new_buf->bo->offset64 == pin_offset);
> + }
> +
> + for (i = 0; i < buf_count; i++)
> + if (bufs[i]->bo->offset64 > new_buf->bo->offset64)
> + break;
> +
> + memmove(&bufs[i + 1], &bufs[i], sizeof(bufs[0]) * (buf_count -
> i));
> +
> + bufs[i] = new_buf;
> +}
> +
> +void
> +gen12_aux_pgtable_init(struct aux_pgtable_info *info,
> + drm_intel_bufmgr *bufmgr,
> + const struct igt_buf *src_buf,
> + const struct igt_buf *dst_buf)
> +{
> + const struct igt_buf *bufs[2];
> + const struct igt_buf *reserved_bufs[2];
> + int reserved_buf_count;
> + int i;
> +
> + if (!src_buf->aux.stride && !dst_buf->aux.stride)
> + return;
> +
> + bufs[0] = src_buf;
> + bufs[1] = dst_buf;
> +
> + /*
> + * Ideally we'd need an IGT-wide GFX address space allocator,
> which
> + * would consider all allocations and thus avoid evictions. For
> now use
> + * a simpler scheme here, which only considers the buffers
> involved in
> + * the blit, which should at least minimize the chance for
> evictions
> + * in the case of subsequent blits:
> + * 1. If they were already bound (bo->offset64 != 0), use
> this
> + * address.
> + * 2. Pick a range randomly from the 4GB address space, that
> is not
> + * already occupied by a bound object, or an object we
> pinned.
> + */
> + reserved_buf_count = 0;
> + /* First reserve space for any bufs that are bound already. */
> + for (i = 0; i < ARRAY_SIZE(bufs); i++)
> + if (bufs[i]->bo->offset64)
> + aux_pgtable_reserve_range(reserved_bufs,
> + reserved_buf_count++,
> + bufs[i]);
> +
> + /* Next, reserve space for unbound bufs with an AUX surface. */
> + for (i = 0; i < ARRAY_SIZE(bufs); i++)
> + if (!bufs[i]->bo->offset64 && bufs[i]->aux.stride)
> + aux_pgtable_reserve_range(reserved_bufs,
> + reserved_buf_count++,
> + bufs[i]);
> +
> + /* Create AUX pgtable entries only for bufs with an AUX surface
> */
> + info->buf_count = 0;
> + for (i = 0; i < reserved_buf_count; i++) {
> + if (!reserved_bufs[i]->aux.stride)
> + continue;
> +
> + info->bufs[info->buf_count] = reserved_bufs[i];
> + info->buf_pin_offsets[info->buf_count] =
> + reserved_bufs[i]->bo->offset64;
> + info->buf_count++;
> + }
> +
> + info->pgtable_bo = intel_aux_pgtable_create(bufmgr,
> + info->bufs,
> + info->buf_count);
> + igt_assert(info->pgtable_bo);
> +}
> +
> +void
> +gen12_aux_pgtable_cleanup(struct aux_pgtable_info *info)
> +{
> + int i;
> +
> + /* Check that the pinned bufs kept their offset after the exec.
> */
> + for (i = 0; i < info->buf_count; i++)
> + igt_assert_eq_u64(info->bufs[i]->bo->offset64,
> + info->buf_pin_offsets[i]);
> +
> + drm_intel_bo_unreference(info->pgtable_bo);
> +}
> +
> +uint32_t
> +gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
> + drm_intel_bo *aux_pgtable_bo)
> +{
> + uint64_t *pgtable_ptr;
> + uint32_t pgtable_ptr_offset;
> + int ret;
> +
> + if (!aux_pgtable_bo)
> + return 0;
> +
> + pgtable_ptr = intel_batchbuffer_subdata_alloc(batch,
> + sizeof(*pgtable_p
> tr),
> + sizeof(*pgtable_p
> tr));
> + pgtable_ptr_offset = intel_batchbuffer_subdata_offset(batch,
> + pgtable_p
> tr);
> +
> + *pgtable_ptr = aux_pgtable_bo->offset64;
> + ret = drm_intel_bo_emit_reloc(batch->bo, pgtable_ptr_offset,
> + aux_pgtable_bo, 0,
> + 0, 0);
> + assert(ret == 0);
> +
> + return pgtable_ptr_offset;
> +}
> +
> +void
> +gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch,
> uint32_t state)
> +{
> + if (!state)
> + return;
> +
> + OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
> + OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
> + OUT_RELOC(batch->bo, 0, 0, state);
> +
> + OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
> + OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
> + OUT_RELOC(batch->bo, 0, 0, state + 4);
> +}
> diff --git a/lib/intel_aux_pgtable.h b/lib/intel_aux_pgtable.h
> index c0f001b4..20278db0 100644
> --- a/lib/intel_aux_pgtable.h
> +++ b/lib/intel_aux_pgtable.h
> @@ -4,9 +4,32 @@
> #include "intel_bufmgr.h"
>
> struct igt_buf;
> +struct intel_batchbuffer;
> +
> +struct aux_pgtable_info {
> + int buf_count;
> + const struct igt_buf *bufs[2];
> + uint64_t buf_pin_offsets[2];
> + drm_intel_bo *pgtable_bo;
> +};
>
> drm_intel_bo *
> intel_aux_pgtable_create(drm_intel_bufmgr *bufmgr,
> const struct igt_buf **bufs, int buf_count);
>
> +void
> +gen12_aux_pgtable_init(struct aux_pgtable_info *info,
> + drm_intel_bufmgr *bufmgr,
> + const struct igt_buf *src_buf,
> + const struct igt_buf *dst_buf);
> +
> +void
> +gen12_aux_pgtable_cleanup(struct aux_pgtable_info *info);
> +
> +uint32_t
> +gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
> + drm_intel_bo *aux_pgtable_bo);
> +void
> +gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch,
> uint32_t state);
> +
> #endif
> diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
> index 3189594f..94e816b6 100644
> --- a/lib/rendercopy_gen9.c
> +++ b/lib/rendercopy_gen9.c
> @@ -973,211 +973,6 @@ static void gen8_emit_primitive(struct
> intel_batchbuffer *batch, uint32_t offset
>
> #define BATCH_STATE_SPLIT 2048
>
> -static void
> -aux_pgtable_find_max_free_range(const struct igt_buf **bufs, int
> buf_count,
> - uint64_t *range_start, uint64_t
> *range_size)
> -{
> - /*
> - * Keep the first page reserved, so we can differentiate pinned
> - * objects based on a non-NULL offset.
> - */
> - uint64_t start = 0x1000;
> - /* For now alloc only from the first 4GB address space. */
> - const uint64_t end = 1ULL << 32;
> - uint64_t max_range_start = 0;
> - uint64_t max_range_size = 0;
> - int i;
> -
> - for (i = 0; i < buf_count; i++) {
> - if (bufs[i]->bo->offset64 >= end)
> - break;
> -
> - if (bufs[i]->bo->offset64 - start > max_range_size) {
> - max_range_start = start;
> - max_range_size = bufs[i]->bo->offset64 - start;
> - }
> - start = bufs[i]->bo->offset64 + bufs[i]->bo->size;
> - }
> -
> - if (start < end && end - start > max_range_size) {
> - max_range_start = start;
> - max_range_size = end - start;
> - }
> -
> - *range_start = max_range_start;
> - *range_size = max_range_size;
> -}
> -
> -static uint64_t
> -aux_pgtable_find_free_range(const struct igt_buf **bufs, int
> buf_count,
> - uint32_t size)
> -{
> - uint64_t range_start;
> - uint64_t range_size;
> - /* A compressed surface must be 64kB aligned. */
> - const uint32_t align = 0x10000;
> - int pad;
> -
> - aux_pgtable_find_max_free_range(bufs, buf_count,
> - &range_start, &range_size);
> -
> - pad = ALIGN(range_start, align) - range_start;
> - range_start += pad;
> - range_size -= pad;
> - igt_assert(range_size >= size);
> -
> - return range_start +
> - ALIGN_DOWN(rand() % ((range_size - size) + 1), align);
> -}
> -
> -static void
> -aux_pgtable_reserve_range(const struct igt_buf **bufs, int
> buf_count,
> - const struct igt_buf *new_buf)
> -{
> - int i;
> -
> - if (new_buf->aux.stride) {
> - uint64_t pin_offset = new_buf->bo->offset64;
> -
> - if (!pin_offset)
> - pin_offset = aux_pgtable_find_free_range(bufs,
> - buf_co
> unt,
> - new_bu
> f->bo->size);
> - drm_intel_bo_set_softpin_offset(new_buf->bo,
> pin_offset);
> - igt_assert(new_buf->bo->offset64 == pin_offset);
> - }
> -
> - for (i = 0; i < buf_count; i++)
> - if (bufs[i]->bo->offset64 > new_buf->bo->offset64)
> - break;
> -
> - memmove(&bufs[i + 1], &bufs[i], sizeof(bufs[0]) * (buf_count -
> i));
> -
> - bufs[i] = new_buf;
> -}
> -
> -struct aux_pgtable_info {
> - int buf_count;
> - const struct igt_buf *bufs[2];
> - uint64_t buf_pin_offsets[2];
> - drm_intel_bo *pgtable_bo;
> -};
> -
> -static void
> -gen12_aux_pgtable_init(struct aux_pgtable_info *info,
> - drm_intel_bufmgr *bufmgr,
> - const struct igt_buf *src_buf,
> - const struct igt_buf *dst_buf)
> -{
> - const struct igt_buf *bufs[2];
> - const struct igt_buf *reserved_bufs[2];
> - int reserved_buf_count;
> - int i;
> -
> - if (!src_buf->aux.stride && !dst_buf->aux.stride)
> - return;
> -
> - bufs[0] = src_buf;
> - bufs[1] = dst_buf;
> -
> - /*
> - * Ideally we'd need an IGT-wide GFX address space allocator,
> which
> - * would consider all allocations and thus avoid evictions. For
> now use
> - * a simpler scheme here, which only considers the buffers
> involved in
> - * the blit, which should at least minimize the chance for
> evictions
> - * in the case of subsequent blits:
> - * 1. If they were already bound (bo->offset64 != 0), use
> this
> - * address.
> - * 2. Pick a range randomly from the 4GB address space, that
> is not
> - * already occupied by a bound object, or an object we
> pinned.
> - */
> - reserved_buf_count = 0;
> - /* First reserve space for any bufs that are bound already. */
> - for (i = 0; i < ARRAY_SIZE(bufs); i++)
> - if (bufs[i]->bo->offset64)
> - aux_pgtable_reserve_range(reserved_bufs,
> - reserved_buf_count++,
> - bufs[i]);
> -
> - /* Next, reserve space for unbound bufs with an AUX surface. */
> - for (i = 0; i < ARRAY_SIZE(bufs); i++)
> - if (!bufs[i]->bo->offset64 && bufs[i]->aux.stride)
> - aux_pgtable_reserve_range(reserved_bufs,
> - reserved_buf_count++,
> - bufs[i]);
> -
> - /* Create AUX pgtable entries only for bufs with an AUX surface
> */
> - info->buf_count = 0;
> - for (i = 0; i < reserved_buf_count; i++) {
> - if (!reserved_bufs[i]->aux.stride)
> - continue;
> -
> - info->bufs[info->buf_count] = reserved_bufs[i];
> - info->buf_pin_offsets[info->buf_count] =
> - reserved_bufs[i]->bo->offset64;
> - info->buf_count++;
> - }
> -
> - info->pgtable_bo = intel_aux_pgtable_create(bufmgr,
> - info->bufs,
> - info->buf_count);
> - igt_assert(info->pgtable_bo);
> -}
> -
> -static void
> -gen12_aux_pgtable_cleanup(struct aux_pgtable_info *info)
> -{
> - int i;
> -
> - /* Check that the pinned bufs kept their offset after the exec.
> */
> - for (i = 0; i < info->buf_count; i++)
> - igt_assert_eq_u64(info->bufs[i]->bo->offset64,
> - info->buf_pin_offsets[i]);
> -
> - drm_intel_bo_unreference(info->pgtable_bo);
> -}
> -
> -static uint32_t
> -gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
> - drm_intel_bo *aux_pgtable_bo)
> -{
> - uint64_t *pgtable_ptr;
> - uint32_t pgtable_ptr_offset;
> - int ret;
> -
> - if (!aux_pgtable_bo)
> - return 0;
> -
> - pgtable_ptr = intel_batchbuffer_subdata_alloc(batch,
> - sizeof(*pgtable_p
> tr),
> - sizeof(*pgtable_p
> tr));
> - pgtable_ptr_offset = intel_batchbuffer_subdata_offset(batch,
> - pgtable_p
> tr);
> -
> - *pgtable_ptr = aux_pgtable_bo->offset64;
> - ret = drm_intel_bo_emit_reloc(batch->bo, pgtable_ptr_offset,
> - aux_pgtable_bo, 0,
> - 0, 0);
> - assert(ret == 0);
> -
> - return pgtable_ptr_offset;
> -}
> -
> -static void
> -gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch,
> uint32_t state)
> -{
> - if (!state)
> - return;
> -
> - OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
> - OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
> - OUT_RELOC(batch->bo, 0, 0, state);
> -
> - OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
> - OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
> - OUT_RELOC(batch->bo, 0, 0, state + 4);
> -}
> -
> static
> void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
> drm_intel_context *context,
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread
* [igt-dev] [PATCH i-g-t 4/6] lib/intel_aux_pgtable: Set MMIO remap for write the AUX pagedir reg
2019-11-29 10:38 [igt-dev] [PATCH i-g-t 0/6] lib: Add tests validating media compressed surfaces Imre Deak
` (2 preceding siblings ...)
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 3/6] lib: Move aux pgtable state prepare/emit to intel_aux_pgtable.c Imre Deak
@ 2019-11-29 10:38 ` Imre Deak
2019-12-04 12:35 ` Kahola, Mika
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 5/6] lib: Add vebox copy support Imre Deak
` (5 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2019-11-29 10:38 UTC (permalink / raw)
To: igt-dev; +Cc: Brian Welty
We're only using the first instance of the render engine, but the
standard way on GEN12 to read/write engine registers is to depend on the
MMIO remapping to select the proper instance based on which command
streamer the read/write instruction was run from.
Enable the MMIO remapping to align with the standard way to do reg
read/writes.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
lib/intel_aux_pgtable.c | 4 ++--
lib/intel_reg.h | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index 319b2745..2f22bb39 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -560,11 +560,11 @@ gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state)
if (!state)
return;
- OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
+ OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12);
OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
OUT_RELOC(batch->bo, 0, 0, state);
- OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
+ OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12);
OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
OUT_RELOC(batch->bo, 0, 0, state + 4);
}
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 96236828..cabfc879 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -2572,6 +2572,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_LOAD_SCAN_LINES_INCL (0x12<<23)
#define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1)
#define MI_LOAD_REGISTER_MEM_GEN8 ((0x29 << 23) | (4 - 2))
+#define MI_MMIO_REMAP_ENABLE_GEN12 (1 << 17)
/* Flush */
#define MI_FLUSH (0x04<<23)
--
2.17.1
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [igt-dev] [PATCH i-g-t 4/6] lib/intel_aux_pgtable: Set MMIO remap for write the AUX pagedir reg
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 4/6] lib/intel_aux_pgtable: Set MMIO remap for write the AUX pagedir reg Imre Deak
@ 2019-12-04 12:35 ` Kahola, Mika
0 siblings, 0 replies; 25+ messages in thread
From: Kahola, Mika @ 2019-12-04 12:35 UTC (permalink / raw)
To: igt-dev, Deak, Imre; +Cc: Welty, Brian
On Fri, 2019-11-29 at 12:38 +0200, Imre Deak wrote:
> We're only using the first instance of the render engine, but the
> standard way on GEN12 to read/write engine registers is to depend on
> the
> MMIO remapping to select the proper instance based on which command
> streamer the read/write instruction was run from.
>
> Enable the MMIO remapping to align with the standard way to do reg
> read/writes.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> lib/intel_aux_pgtable.c | 4 ++--
> lib/intel_reg.h | 1 +
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
> index 319b2745..2f22bb39 100644
> --- a/lib/intel_aux_pgtable.c
> +++ b/lib/intel_aux_pgtable.c
> @@ -560,11 +560,11 @@ gen12_emit_aux_pgtable_state(struct
> intel_batchbuffer *batch, uint32_t state)
> if (!state)
> return;
>
> - OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
> + OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 |
> MI_MMIO_REMAP_ENABLE_GEN12);
> OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
> OUT_RELOC(batch->bo, 0, 0, state);
>
> - OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8);
> + OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 |
> MI_MMIO_REMAP_ENABLE_GEN12);
> OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
> OUT_RELOC(batch->bo, 0, 0, state + 4);
> }
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index 96236828..cabfc879 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -2572,6 +2572,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> SOFTWARE.
> #define MI_LOAD_SCAN_LINES_INCL (0x12<<23)
> #define MI_LOAD_REGISTER_IMM ((0x22 << 23) | 1)
> #define MI_LOAD_REGISTER_MEM_GEN8 ((0x29 << 23) | (4 - 2))
> +#define MI_MMIO_REMAP_ENABLE_GEN12 (1 << 17)
>
> /* Flush */
> #define MI_FLUSH (0x04<<23)
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread
* [igt-dev] [PATCH i-g-t 5/6] lib: Add vebox copy support
2019-11-29 10:38 [igt-dev] [PATCH i-g-t 0/6] lib: Add tests validating media compressed surfaces Imre Deak
` (3 preceding siblings ...)
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 4/6] lib/intel_aux_pgtable: Set MMIO remap for write the AUX pagedir reg Imre Deak
@ 2019-11-29 10:38 ` Imre Deak
2019-12-04 13:09 ` Kahola, Mika
` (2 more replies)
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 6/6] tests/gem_render_copy: Add media compression subtests Imre Deak
` (4 subsequent siblings)
9 siblings, 3 replies; 25+ messages in thread
From: Imre Deak @ 2019-11-29 10:38 UTC (permalink / raw)
To: igt-dev; +Cc: Brian Welty
To produce surfaces that are compressed using the media compression
format we need to use one of the media engines. The simplest way for
this is to use the vebox engine's tiling convert command, so add support
for this.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
lib/Makefile.sources | 1 +
lib/igt_fb.c | 74 +++++++---
lib/intel_aux_pgtable.c | 10 +-
lib/intel_aux_pgtable.h | 3 +-
lib/intel_batchbuffer.c | 11 ++
lib/intel_batchbuffer.h | 30 +++-
lib/intel_reg.h | 1 +
lib/ioctl_wrappers.h | 1 +
lib/meson.build | 1 +
lib/rendercopy_gen9.c | 2 +-
lib/veboxcopy.h | 9 ++
lib/veboxcopy_gen12.c | 269 +++++++++++++++++++++++++++++++++++
tests/i915/gem_render_copy.c | 1 +
13 files changed, 387 insertions(+), 26 deletions(-)
create mode 100644 lib/veboxcopy.h
create mode 100644 lib/veboxcopy_gen12.c
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 9d1a4e06..0efaea1b 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -129,6 +129,7 @@ lib_source_list = \
igt_vc4.h \
igt_amd.c \
igt_amd.h \
+ veboxcopy_gen12.c \
$(NULL)
.PHONY: version.h.tmp
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 1d1e0d22..3bb4e5a1 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -402,6 +402,7 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
case LOCAL_I915_FORMAT_MOD_Y_TILED:
case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
igt_require_intel(fd);
if (intel_gen(intel_get_drm_devid(fd)) == 2) {
*width_ret = 128;
@@ -466,14 +467,19 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
}
}
+static bool is_gen12_mc_ccs_modifier(uint64_t modifier)
+{
+ return modifier == LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
+}
+
static bool is_gen12_ccs_modifier(uint64_t modifier)
{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+ return is_gen12_mc_ccs_modifier(modifier) ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
}
static bool is_ccs_modifier(uint64_t modifier)
{
-
return is_gen12_ccs_modifier(modifier) ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
@@ -719,6 +725,7 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
case LOCAL_I915_FORMAT_MOD_Y_TILED:
case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
case LOCAL_I915_FORMAT_MOD_Yf_TILED:
case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -1897,7 +1904,7 @@ static bool blitter_ok(const struct igt_fb *fb)
return true;
}
-static bool use_rendercopy(const struct igt_fb *fb)
+static bool use_enginecopy(const struct igt_fb *fb)
{
return is_ccs_modifier(fb->modifier) ||
(fb->modifier == I915_FORMAT_MOD_Yf_TILED &&
@@ -1943,25 +1950,52 @@ static void fini_buf(struct igt_buf *buf)
drm_intel_bo_unreference(buf->bo);
}
-static void rendercopy(struct fb_blit_upload *blit,
- const struct igt_fb *dst_fb,
- const struct igt_fb *src_fb)
+/**
+ * copy_with_engine:
+ * @blit: context for the copy operation
+ * @dst_fb: destination buffer
+ * @src_fb: source buffer
+ *
+ * Copy @src_fb to @dst_fb using either the render or vebox engine. The engine
+ * is selected based on the compression surface format required by the @dst_fb
+ * FB modifier. On GEN12+ a given compression format (render or media) can be
+ * produced only by the selected engine:
+ * - For GEN12 media compressed: vebox engine
+ * - For uncompressed, pre-GEN12 compressed, GEN12+ render compressed: render engine
+ * Note that both GEN12 engine is capable of reading either compression formats.
+ */
+static void copy_with_engine(struct fb_blit_upload *blit,
+ const struct igt_fb *dst_fb,
+ const struct igt_fb *src_fb)
{
struct igt_buf src = {}, dst = {};
- igt_render_copyfunc_t render_copy =
- igt_get_render_copyfunc(intel_get_drm_devid(blit->fd));
+ igt_render_copyfunc_t render_copy = NULL;
+ igt_vebox_copyfunc_t vebox_copy = NULL;
+
+ if (is_gen12_mc_ccs_modifier(dst_fb->modifier))
+ vebox_copy = igt_get_vebox_copyfunc(intel_get_drm_devid(blit->fd));
+ else
+ render_copy = igt_get_render_copyfunc(intel_get_drm_devid(blit->fd));
- igt_require(render_copy);
+ igt_require(vebox_copy || render_copy);
igt_assert_eq(dst_fb->offsets[0], 0);
igt_assert_eq(src_fb->offsets[0], 0);
- init_buf(blit, &src, src_fb, "cairo rendercopy src");
- init_buf(blit, &dst, dst_fb, "cairo rendercopy dst");
+ init_buf(blit, &src, src_fb, "cairo enginecopy src");
+ init_buf(blit, &dst, dst_fb, "cairo enginecopy dst");
- render_copy(blit->batch, NULL,
- &src, 0, 0, dst_fb->plane_width[0], dst_fb->plane_height[0],
- &dst, 0, 0);
+ if (vebox_copy)
+ vebox_copy(blit->batch, &src,
+ dst_fb->plane_width[0], dst_fb->plane_height[0],
+ &dst);
+ else
+ render_copy(blit->batch, NULL,
+ &src,
+ 0, 0,
+ dst_fb->plane_width[0], dst_fb->plane_height[0],
+ &dst,
+ 0, 0);
fini_buf(&dst);
fini_buf(&src);
@@ -2012,7 +2046,7 @@ static void free_linear_mapping(struct fb_blit_upload *blit)
I915_GEM_DOMAIN_GTT, 0);
if (blit->batch)
- rendercopy(blit, fb, &linear->fb);
+ copy_with_engine(blit, fb, &linear->fb);
else
blitcopy(fb, &linear->fb);
@@ -2043,7 +2077,7 @@ static void setup_linear_mapping(struct fb_blit_upload *blit)
struct igt_fb *fb = blit->fb;
struct fb_blit_linear *linear = &blit->linear;
- if (!igt_vc4_is_tiled(fb->modifier) && use_rendercopy(fb)) {
+ if (!igt_vc4_is_tiled(fb->modifier) && use_enginecopy(fb)) {
blit->bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
blit->batch = intel_batchbuffer_alloc(blit->bufmgr,
intel_get_drm_devid(fd));
@@ -2079,7 +2113,7 @@ static void setup_linear_mapping(struct fb_blit_upload *blit)
I915_GEM_DOMAIN_GTT, 0);
if (blit->batch)
- rendercopy(blit, &linear->fb, fb);
+ copy_with_engine(blit, &linear->fb, fb);
else
blitcopy(&linear->fb, fb);
@@ -3185,7 +3219,8 @@ static void create_cairo_surface__convert(int fd, struct igt_fb *fb)
&blit->shadow_fb);
igt_assert(blit->shadow_ptr);
- if (use_rendercopy(fb) || use_blitter(fb) || igt_vc4_is_tiled(fb->modifier)) {
+ if (use_enginecopy(fb) || use_blitter(fb) ||
+ igt_vc4_is_tiled(fb->modifier)) {
setup_linear_mapping(&blit->base);
} else {
blit->base.linear.fb = *fb;
@@ -3268,7 +3303,8 @@ cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb)
if (fb->cairo_surface == NULL) {
if (use_convert(fb))
create_cairo_surface__convert(fd, fb);
- else if (use_blitter(fb) || use_rendercopy(fb) || igt_vc4_is_tiled(fb->modifier))
+ else if (use_blitter(fb) || use_enginecopy(fb) ||
+ igt_vc4_is_tiled(fb->modifier))
create_cairo_surface__gpu(fd, fb);
else
create_cairo_surface__gtt(fd, fb);
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index 2f22bb39..cbb3c320 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -555,16 +555,20 @@ gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
}
void
-gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state)
+gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state,
+ bool render)
{
+ uint32_t table_base_reg = render ? GEN12_GFX_AUX_TABLE_BASE_ADDR :
+ GEN12_VEBOX_AUX_TABLE_BASE_ADDR;
+
if (!state)
return;
OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12);
- OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
+ OUT_BATCH(table_base_reg);
OUT_RELOC(batch->bo, 0, 0, state);
OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12);
- OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
+ OUT_BATCH(table_base_reg + 4);
OUT_RELOC(batch->bo, 0, 0, state + 4);
}
diff --git a/lib/intel_aux_pgtable.h b/lib/intel_aux_pgtable.h
index 20278db0..ac82b7d2 100644
--- a/lib/intel_aux_pgtable.h
+++ b/lib/intel_aux_pgtable.h
@@ -30,6 +30,7 @@ uint32_t
gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
drm_intel_bo *aux_pgtable_bo);
void
-gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state);
+gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state,
+ bool render);
#endif
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 3828ba75..51aae4dc 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -37,6 +37,7 @@
#include "intel_bufmgr.h"
#include "intel_chipset.h"
#include "intel_reg.h"
+#include "veboxcopy.h"
#include "rendercopy.h"
#include "media_fill.h"
#include "ioctl_wrappers.h"
@@ -850,6 +851,16 @@ igt_render_copyfunc_t igt_get_render_copyfunc(int devid)
return copy;
}
+igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid)
+{
+ igt_vebox_copyfunc_t copy = NULL;
+
+ if (IS_GEN12(devid))
+ copy = gen12_vebox_copyfunc;
+
+ return copy;
+}
+
/**
* igt_get_media_fillfunc:
* @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 402e68bc..e05e464b 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -213,6 +213,7 @@ void intel_copy_bo(struct intel_batchbuffer *batch,
enum i915_compression {
I915_COMPRESSION_NONE,
I915_COMPRESSION_RENDER,
+ I915_COMPRESSION_MEDIA,
};
/**
@@ -220,18 +221,20 @@ enum i915_compression {
* @bo: underlying libdrm buffer object
* @stride: stride of the buffer
* @tiling: tiling mode bits
+ * @compression: memory compression mode
* @bpp: bits per pixel, 8, 16 or 32.
* @data: pointer to the memory mapping of the buffer
* @size: size of the buffer object
*
* This is a i-g-t buffer object wrapper structure which augments the baseline
- * libdrm buffer object with suitable data needed by the render copy and the
- * fill functions.
+ * libdrm buffer object with suitable data needed by the render/vebox copy and
+ * the fill functions.
*/
struct igt_buf {
drm_intel_bo *bo;
uint32_t stride;
uint32_t tiling;
+ enum i915_compression compression;
uint32_t bpp;
uint32_t *data;
uint32_t size;
@@ -304,6 +307,29 @@ typedef void (*igt_render_copyfunc_t)(struct intel_batchbuffer *batch,
igt_render_copyfunc_t igt_get_render_copyfunc(int devid);
+
+/**
+ * igt_vebox_copyfunc_t:
+ * @batch: batchbuffer object
+ * @src: source i-g-t buffer object
+ * @width: width of the copied rectangle
+ * @height: height of the copied rectangle
+ * @dst: destination i-g-t buffer object
+ *
+ * This is the type of the per-platform vebox copy functions. The
+ * platform-specific implementation can be obtained by calling
+ * igt_get_vebox_copyfunc().
+ *
+ * A vebox copy function will emit a batchbuffer to the kernel which executes
+ * the specified blit copy operation using the vebox engine.
+ */
+typedef void (*igt_vebox_copyfunc_t)(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned width, unsigned height,
+ const struct igt_buf *dst);
+
+igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid);
+
/**
* igt_fillfunc_t:
* @batch: batchbuffer object
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index cabfc879..0a9ee34c 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -674,6 +674,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RING_INVALID 0x00000000
#define GEN12_GFX_AUX_TABLE_BASE_ADDR 0x4200
+#define GEN12_VEBOX_AUX_TABLE_BASE_ADDR 0x4230
/* BitBlt Instructions
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index f2412d78..7dd2a1e8 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -201,6 +201,7 @@ struct local_drm_mode_fb_cmd2 {
#define LOCAL_I915_FORMAT_MOD_Y_TILED_CCS local_fourcc_mod_code(INTEL, 4)
#define LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS local_fourcc_mod_code(INTEL, 5)
#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
#define LOCAL_DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, \
struct local_drm_mode_fb_cmd2)
diff --git a/lib/meson.build b/lib/meson.build
index 3f908912..f7fce905 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -63,6 +63,7 @@ lib_sources = [
'igt_edid.c',
'igt_eld.c',
'igt_infoframe.c',
+ 'veboxcopy_gen12.c',
]
lib_deps = [
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 94e816b6..e7fdd7a6 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -1026,7 +1026,7 @@ void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
GEN9_PIPELINE_SELECTION_MASK);
- gen12_emit_aux_pgtable_state(batch, aux_pgtable_state);
+ gen12_emit_aux_pgtable_state(batch, aux_pgtable_state, true);
gen8_emit_sip(batch);
diff --git a/lib/veboxcopy.h b/lib/veboxcopy.h
new file mode 100644
index 00000000..949d83bf
--- /dev/null
+++ b/lib/veboxcopy.h
@@ -0,0 +1,9 @@
+#ifndef __VEBOXCOPY_H__
+#define __VEBOXCOPY_H__
+
+void gen12_vebox_copyfunc(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned width, unsigned height,
+ const struct igt_buf *dst);
+
+#endif
diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c
new file mode 100644
index 00000000..87800941
--- /dev/null
+++ b/lib/veboxcopy_gen12.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_aux_pgtable.h"
+#include "veboxcopy.h"
+
+#define R8G8B8A8_UNORM 8
+
+struct vebox_surface_state {
+ struct {
+ uint32_t dw_count:12;
+ uint32_t pad:4;
+ uint32_t sub_opcode_b:5;
+ uint32_t sub_opcode_a:3;
+ uint32_t media_cmd_opcode:3;
+ uint32_t media_cmd_pipeline:2;
+ uint32_t cmd_type:3;
+ } ss0;
+ struct {
+#define VEBOX_SURFACE_INPUT 0
+#define VEBOX_SURFACE_OUTPUT 1
+ uint32_t surface_id:1;
+ uint32_t pad:31;
+ } ss1;
+ struct {
+ uint32_t pad:4;
+ uint32_t width:14;
+ uint32_t height:14;
+ } ss2;
+ struct {
+#define VEBOX_TILE_WALK_XMAJOR 0
+#define VEBOX_TILE_WALK_YMAJOR 1
+ uint32_t tile_walk:1;
+ uint32_t tiled_surface:1;
+ uint32_t chroma_half_pitch:1;
+ uint32_t surface_pitch:17;
+ uint32_t chroma_interleave:1;
+ uint32_t lsb_packed_enable:1;
+ uint32_t bayer_input_alignment:2;
+ uint32_t bayer_pattern_format:1;
+ uint32_t bayer_pattern_offset:2;
+ uint32_t surface_format:5;
+ } ss3;
+ struct {
+ uint32_t u_y_offset:15;
+ uint32_t u_x_offset:13;
+ uint32_t pad:4;
+ } ss4;
+ struct {
+ uint32_t v_y_offset:15;
+ uint32_t v_x_offset:13;
+ uint32_t pad:4;
+ } ss5;
+ struct {
+ uint32_t frame_y_offset:15;
+ uint32_t frame_x_offset:15;
+ uint32_t pad:2;
+ } ss6;
+ struct {
+ uint32_t derived_surface_pitch:17;
+ uint32_t pad:15;
+ } ss7;
+ struct {
+ uint32_t skin_score_output_surface_pitch:17;
+ uint32_t pad:15;
+ } ss8;
+} __attribute__((packed));
+
+struct vebox_tiling_convert {
+ struct {
+ uint32_t dw_count:12;
+ uint32_t pad:4;
+ uint32_t sub_opcode_b:5;
+ uint32_t sub_opcode_a:3;
+ uint32_t cmd_opcode:3;
+ uint32_t pipeline:2;
+ uint32_t cmd_type:3;
+ } tc0;
+ union {
+ struct {
+ uint64_t input_encrypted_data:1;
+ uint64_t input_mocs_idx:6;
+ uint64_t input_memory_compression_enable:1;
+#define COMPRESSION_TYPE_MEDIA 0
+#define COMPRESSION_TYPE_RENDER 1
+ uint64_t input_compression_type:1;
+#define TRMODE_NONE 0
+#define TRMODE_TILE_YF 1
+#define TRMODE_TILE_YS 2
+ uint64_t input_tiled_resource_mode:2;
+ uint64_t pad:1;
+ uint64_t input_address:52;
+ } tc1_2;
+ uint64_t tc1_2_l;
+ };
+ union {
+ struct {
+ uint64_t output_encrypted_data:1;
+ uint64_t output_mocs_idx:6;
+ uint64_t output_memory_compression_enable:1;
+ uint64_t output_compression_type:1;
+ uint64_t output_tiled_resource_mode:2;
+ uint64_t pad:1;
+ uint64_t output_address:52;
+ } tc3_4;
+ uint64_t tc3_4_l;
+ };
+} __attribute__((packed));
+
+static void emit_surface_state_cmd(struct intel_batchbuffer *batch,
+ int surface_id,
+ int width, int height, int bpp,
+ int pitch, uint32_t tiling, int format)
+{
+ struct vebox_surface_state *ss;
+
+ ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 4);
+
+ ss->ss0.cmd_type = 3;
+ ss->ss0.media_cmd_pipeline = 2;
+ ss->ss0.media_cmd_opcode = 4;
+ ss->ss0.dw_count = 7;
+
+ ss->ss1.surface_id = surface_id;
+
+ ss->ss2.height = height - 1;
+ ss->ss2.width = width - 1;
+
+ ss->ss3.surface_format = format;
+ ss->ss3.surface_pitch = pitch - 1;
+ ss->ss3.tile_walk = (tiling == I915_TILING_Y) ||
+ (tiling == I915_TILING_Yf);
+ ss->ss3.tiled_surface = tiling != I915_TILING_NONE;
+
+ ss->ss7.derived_surface_pitch = pitch - 1;
+}
+
+static void emit_tiling_convert_cmd(struct intel_batchbuffer *batch,
+ drm_intel_bo *input_bo,
+ uint32_t input_tiling,
+ uint32_t input_compression,
+ drm_intel_bo *output_bo,
+ uint32_t output_tiling,
+ uint32_t output_compression)
+{
+ uint32_t reloc_delta;
+ struct vebox_tiling_convert *tc;
+ int ret;
+
+ tc = intel_batchbuffer_subdata_alloc(batch, sizeof(*tc), 8);
+
+ tc->tc0.cmd_type = 3;
+ tc->tc0.pipeline = 2;
+ tc->tc0.cmd_opcode = 4;
+ tc->tc0.sub_opcode_b = 1;
+
+ tc->tc0.dw_count = 3;
+
+ if (input_compression != I915_COMPRESSION_NONE) {
+ tc->tc1_2.input_memory_compression_enable = 1;
+ tc->tc1_2.input_compression_type =
+ input_compression == I915_COMPRESSION_RENDER;
+ }
+ tc->tc1_2.input_tiled_resource_mode = input_tiling == I915_TILING_Yf;
+ reloc_delta = tc->tc1_2_l;
+
+ igt_assert(input_bo->offset64 == ALIGN(input_bo->offset64, 0x1000));
+ tc->tc1_2.input_address = input_bo->offset64 >> 12;
+ igt_assert(reloc_delta <= INT32_MAX);
+ ret = drm_intel_bo_emit_reloc(batch->bo,
+ intel_batchbuffer_subdata_offset(batch, tc) +
+ offsetof(typeof(*tc), tc1_2),
+ input_bo, reloc_delta,
+ 0, 0);
+ igt_assert(ret == 0);
+
+ if (output_compression != I915_COMPRESSION_NONE) {
+ tc->tc3_4.output_memory_compression_enable = 1;
+ tc->tc3_4.output_compression_type =
+ output_compression == I915_COMPRESSION_RENDER;
+ }
+ tc->tc3_4.output_tiled_resource_mode = output_tiling == I915_TILING_Yf;
+ reloc_delta = tc->tc3_4_l;
+
+ igt_assert(output_bo->offset64 == ALIGN(output_bo->offset64, 0x1000));
+ tc->tc3_4.output_address = output_bo->offset64 >> 12;
+ igt_assert(reloc_delta <= INT32_MAX);
+ ret = drm_intel_bo_emit_reloc(batch->bo,
+ intel_batchbuffer_subdata_offset(batch, tc) +
+ offsetof(typeof(*tc), tc3_4),
+ output_bo, reloc_delta,
+ 0, I915_GEM_DOMAIN_RENDER);
+ igt_assert(ret == 0);
+
+}
+
+/* Borrowing the idea from the rendercopy state setup. */
+#define BATCH_STATE_SPLIT 2048
+
+void gen12_vebox_copyfunc(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned width, unsigned height,
+ const struct igt_buf *dst)
+{
+ struct aux_pgtable_info aux_pgtable_info = { };
+ uint32_t aux_pgtable_state;
+
+ igt_assert(src->bpp == dst->bpp);
+
+ intel_batchbuffer_flush_on_ring(batch, I915_EXEC_VEBOX);
+
+ intel_batchbuffer_align(batch, 8);
+
+ batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
+
+ gen12_aux_pgtable_init(&aux_pgtable_info, batch->bufmgr, src, dst);
+
+ aux_pgtable_state = gen12_create_aux_pgtable_state(batch,
+ aux_pgtable_info.pgtable_bo);
+
+ assert(batch->ptr < &batch->buffer[4095]);
+ batch->ptr = batch->buffer;
+
+ gen12_emit_aux_pgtable_state(batch, aux_pgtable_state, false);
+
+ /* TODO: add support for more formats */
+ igt_assert(src->bpp == 32);
+ emit_surface_state_cmd(batch, VEBOX_SURFACE_INPUT,
+ width, height, src->bpp, src->stride,
+ src->tiling, R8G8B8A8_UNORM);
+
+ igt_assert(dst->bpp == 32);
+ emit_surface_state_cmd(batch, VEBOX_SURFACE_OUTPUT,
+ width, height, dst->bpp, dst->stride,
+ dst->tiling, R8G8B8A8_UNORM);
+
+ emit_tiling_convert_cmd(batch,
+ src->bo, src->tiling, src->compression,
+ dst->bo, dst->tiling, dst->compression);
+
+ OUT_BATCH(MI_BATCH_BUFFER_END);
+
+ intel_batchbuffer_flush_on_ring(batch, I915_EXEC_VEBOX);
+
+ gen12_aux_pgtable_cleanup(&aux_pgtable_info);
+ intel_batchbuffer_reset(batch);
+}
diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
index 15ba1704..9c36f38b 100644
--- a/tests/i915/gem_render_copy.c
+++ b/tests/i915/gem_render_copy.c
@@ -471,6 +471,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf,
aux_width = scratch_buf_aux_width(data->devid, buf);
aux_height = scratch_buf_aux_height(data->devid, buf);
+ buf->compression = compression;
buf->aux.offset = buf->stride * ALIGN(height, 32);
buf->aux.stride = aux_width;
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [igt-dev] [PATCH i-g-t 5/6] lib: Add vebox copy support
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 5/6] lib: Add vebox copy support Imre Deak
@ 2019-12-04 13:09 ` Kahola, Mika
2019-12-04 13:49 ` [igt-dev] [PATCH v2 " Imre Deak
2019-12-05 3:30 ` [igt-dev] [PATCH i-g-t " Bai, Guangyao
2 siblings, 0 replies; 25+ messages in thread
From: Kahola, Mika @ 2019-12-04 13:09 UTC (permalink / raw)
To: igt-dev, Deak, Imre; +Cc: Welty, Brian
On Fri, 2019-11-29 at 12:38 +0200, Imre Deak wrote:
> To produce surfaces that are compressed using the media compression
> format we need to use one of the media engines. The simplest way for
> this is to use the vebox engine's tiling convert command, so add
> support
> for this.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> lib/Makefile.sources | 1 +
> lib/igt_fb.c | 74 +++++++---
> lib/intel_aux_pgtable.c | 10 +-
> lib/intel_aux_pgtable.h | 3 +-
> lib/intel_batchbuffer.c | 11 ++
> lib/intel_batchbuffer.h | 30 +++-
> lib/intel_reg.h | 1 +
> lib/ioctl_wrappers.h | 1 +
> lib/meson.build | 1 +
> lib/rendercopy_gen9.c | 2 +-
> lib/veboxcopy.h | 9 ++
> lib/veboxcopy_gen12.c | 269
> +++++++++++++++++++++++++++++++++++
> tests/i915/gem_render_copy.c | 1 +
> 13 files changed, 387 insertions(+), 26 deletions(-)
> create mode 100644 lib/veboxcopy.h
> create mode 100644 lib/veboxcopy_gen12.c
>
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index 9d1a4e06..0efaea1b 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -129,6 +129,7 @@ lib_source_list = \
> igt_vc4.h \
> igt_amd.c \
> igt_amd.h \
> + veboxcopy_gen12.c \
> $(NULL)
>
> .PHONY: version.h.tmp
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
The patch doesn't apply. This is due to the fact that I merged my GEN12
CCS Clear Color patches that touches igt_fb.c too. I guess, we need to
fix this part of the patch. Otherwise, the patch looks ok to me.
> index 1d1e0d22..3bb4e5a1 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -402,6 +402,7 @@ void igt_get_fb_tile_size(int fd, uint64_t
> modifier, int fb_bpp,
> case LOCAL_I915_FORMAT_MOD_Y_TILED:
> case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
> case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> igt_require_intel(fd);
> if (intel_gen(intel_get_drm_devid(fd)) == 2) {
> *width_ret = 128;
> @@ -466,14 +467,19 @@ void igt_get_fb_tile_size(int fd, uint64_t
> modifier, int fb_bpp,
> }
> }
>
> +static bool is_gen12_mc_ccs_modifier(uint64_t modifier)
> +{
> + return modifier == LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> +}
> +
> static bool is_gen12_ccs_modifier(uint64_t modifier)
> {
> - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> + return is_gen12_mc_ccs_modifier(modifier) ||
> + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> }
>
> static bool is_ccs_modifier(uint64_t modifier)
> {
> -
> return is_gen12_ccs_modifier(modifier) ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> @@ -719,6 +725,7 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
> case LOCAL_I915_FORMAT_MOD_Y_TILED:
> case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
> case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> return I915_TILING_Y;
> case LOCAL_I915_FORMAT_MOD_Yf_TILED:
> case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -1897,7 +1904,7 @@ static bool blitter_ok(const struct igt_fb *fb)
> return true;
> }
>
> -static bool use_rendercopy(const struct igt_fb *fb)
> +static bool use_enginecopy(const struct igt_fb *fb)
> {
> return is_ccs_modifier(fb->modifier) ||
> (fb->modifier == I915_FORMAT_MOD_Yf_TILED &&
> @@ -1943,25 +1950,52 @@ static void fini_buf(struct igt_buf *buf)
> drm_intel_bo_unreference(buf->bo);
> }
>
> -static void rendercopy(struct fb_blit_upload *blit,
> - const struct igt_fb *dst_fb,
> - const struct igt_fb *src_fb)
> +/**
> + * copy_with_engine:
> + * @blit: context for the copy operation
> + * @dst_fb: destination buffer
> + * @src_fb: source buffer
> + *
> + * Copy @src_fb to @dst_fb using either the render or vebox engine.
> The engine
> + * is selected based on the compression surface format required by
> the @dst_fb
> + * FB modifier. On GEN12+ a given compression format (render or
> media) can be
> + * produced only by the selected engine:
> + * - For GEN12 media compressed: vebox engine
> + * - For uncompressed, pre-GEN12 compressed, GEN12+ render
> compressed: render engine
> + * Note that both GEN12 engine is capable of reading either
> compression formats.
> + */
> +static void copy_with_engine(struct fb_blit_upload *blit,
> + const struct igt_fb *dst_fb,
> + const struct igt_fb *src_fb)
> {
> struct igt_buf src = {}, dst = {};
> - igt_render_copyfunc_t render_copy =
> - igt_get_render_copyfunc(intel_get_drm_devid(blit->fd));
> + igt_render_copyfunc_t render_copy = NULL;
> + igt_vebox_copyfunc_t vebox_copy = NULL;
> +
> + if (is_gen12_mc_ccs_modifier(dst_fb->modifier))
> + vebox_copy =
> igt_get_vebox_copyfunc(intel_get_drm_devid(blit->fd));
> + else
> + render_copy =
> igt_get_render_copyfunc(intel_get_drm_devid(blit->fd));
>
> - igt_require(render_copy);
> + igt_require(vebox_copy || render_copy);
>
> igt_assert_eq(dst_fb->offsets[0], 0);
> igt_assert_eq(src_fb->offsets[0], 0);
>
> - init_buf(blit, &src, src_fb, "cairo rendercopy src");
> - init_buf(blit, &dst, dst_fb, "cairo rendercopy dst");
> + init_buf(blit, &src, src_fb, "cairo enginecopy src");
> + init_buf(blit, &dst, dst_fb, "cairo enginecopy dst");
>
> - render_copy(blit->batch, NULL,
> - &src, 0, 0, dst_fb->plane_width[0], dst_fb-
> >plane_height[0],
> - &dst, 0, 0);
> + if (vebox_copy)
> + vebox_copy(blit->batch, &src,
> + dst_fb->plane_width[0], dst_fb-
> >plane_height[0],
> + &dst);
> + else
> + render_copy(blit->batch, NULL,
> + &src,
> + 0, 0,
> + dst_fb->plane_width[0], dst_fb-
> >plane_height[0],
> + &dst,
> + 0, 0);
>
> fini_buf(&dst);
> fini_buf(&src);
> @@ -2012,7 +2046,7 @@ static void free_linear_mapping(struct
> fb_blit_upload *blit)
> I915_GEM_DOMAIN_GTT, 0);
>
> if (blit->batch)
> - rendercopy(blit, fb, &linear->fb);
> + copy_with_engine(blit, fb, &linear->fb);
> else
> blitcopy(fb, &linear->fb);
>
> @@ -2043,7 +2077,7 @@ static void setup_linear_mapping(struct
> fb_blit_upload *blit)
> struct igt_fb *fb = blit->fb;
> struct fb_blit_linear *linear = &blit->linear;
>
> - if (!igt_vc4_is_tiled(fb->modifier) && use_rendercopy(fb)) {
> + if (!igt_vc4_is_tiled(fb->modifier) && use_enginecopy(fb)) {
> blit->bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
> blit->batch = intel_batchbuffer_alloc(blit->bufmgr,
> intel_get_drm_dev
> id(fd));
> @@ -2079,7 +2113,7 @@ static void setup_linear_mapping(struct
> fb_blit_upload *blit)
> I915_GEM_DOMAIN_GTT, 0);
>
> if (blit->batch)
> - rendercopy(blit, &linear->fb, fb);
> + copy_with_engine(blit, &linear->fb, fb);
> else
> blitcopy(&linear->fb, fb);
>
> @@ -3185,7 +3219,8 @@ static void create_cairo_surface__convert(int
> fd, struct igt_fb *fb)
> &blit-
> >shadow_fb);
> igt_assert(blit->shadow_ptr);
>
> - if (use_rendercopy(fb) || use_blitter(fb) ||
> igt_vc4_is_tiled(fb->modifier)) {
> + if (use_enginecopy(fb) || use_blitter(fb) ||
> + igt_vc4_is_tiled(fb->modifier)) {
> setup_linear_mapping(&blit->base);
> } else {
> blit->base.linear.fb = *fb;
> @@ -3268,7 +3303,8 @@ cairo_surface_t *igt_get_cairo_surface(int fd,
> struct igt_fb *fb)
> if (fb->cairo_surface == NULL) {
> if (use_convert(fb))
> create_cairo_surface__convert(fd, fb);
> - else if (use_blitter(fb) || use_rendercopy(fb) ||
> igt_vc4_is_tiled(fb->modifier))
> + else if (use_blitter(fb) || use_enginecopy(fb) ||
> + igt_vc4_is_tiled(fb->modifier))
> create_cairo_surface__gpu(fd, fb);
> else
> create_cairo_surface__gtt(fd, fb);
> diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
> index 2f22bb39..cbb3c320 100644
> --- a/lib/intel_aux_pgtable.c
> +++ b/lib/intel_aux_pgtable.c
> @@ -555,16 +555,20 @@ gen12_create_aux_pgtable_state(struct
> intel_batchbuffer *batch,
> }
>
> void
> -gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch,
> uint32_t state)
> +gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch,
> uint32_t state,
> + bool render)
> {
> + uint32_t table_base_reg = render ?
> GEN12_GFX_AUX_TABLE_BASE_ADDR :
> + GEN12_VEBOX_AUX_TABLE_BASE_A
> DDR;
> +
> if (!state)
> return;
>
> OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 |
> MI_MMIO_REMAP_ENABLE_GEN12);
> - OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
> + OUT_BATCH(table_base_reg);
> OUT_RELOC(batch->bo, 0, 0, state);
>
> OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 |
> MI_MMIO_REMAP_ENABLE_GEN12);
> - OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
> + OUT_BATCH(table_base_reg + 4);
> OUT_RELOC(batch->bo, 0, 0, state + 4);
> }
> diff --git a/lib/intel_aux_pgtable.h b/lib/intel_aux_pgtable.h
> index 20278db0..ac82b7d2 100644
> --- a/lib/intel_aux_pgtable.h
> +++ b/lib/intel_aux_pgtable.h
> @@ -30,6 +30,7 @@ uint32_t
> gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
> drm_intel_bo *aux_pgtable_bo);
> void
> -gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch,
> uint32_t state);
> +gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch,
> uint32_t state,
> + bool render);
>
> #endif
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index 3828ba75..51aae4dc 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -37,6 +37,7 @@
> #include "intel_bufmgr.h"
> #include "intel_chipset.h"
> #include "intel_reg.h"
> +#include "veboxcopy.h"
> #include "rendercopy.h"
> #include "media_fill.h"
> #include "ioctl_wrappers.h"
> @@ -850,6 +851,16 @@ igt_render_copyfunc_t
> igt_get_render_copyfunc(int devid)
> return copy;
> }
>
> +igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid)
> +{
> + igt_vebox_copyfunc_t copy = NULL;
> +
> + if (IS_GEN12(devid))
> + copy = gen12_vebox_copyfunc;
> +
> + return copy;
> +}
> +
> /**
> * igt_get_media_fillfunc:
> * @devid: pci device id
> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
> index 402e68bc..e05e464b 100644
> --- a/lib/intel_batchbuffer.h
> +++ b/lib/intel_batchbuffer.h
> @@ -213,6 +213,7 @@ void intel_copy_bo(struct intel_batchbuffer
> *batch,
> enum i915_compression {
> I915_COMPRESSION_NONE,
> I915_COMPRESSION_RENDER,
> + I915_COMPRESSION_MEDIA,
> };
>
> /**
> @@ -220,18 +221,20 @@ enum i915_compression {
> * @bo: underlying libdrm buffer object
> * @stride: stride of the buffer
> * @tiling: tiling mode bits
> + * @compression: memory compression mode
> * @bpp: bits per pixel, 8, 16 or 32.
> * @data: pointer to the memory mapping of the buffer
> * @size: size of the buffer object
> *
> * This is a i-g-t buffer object wrapper structure which augments
> the baseline
> - * libdrm buffer object with suitable data needed by the render copy
> and the
> - * fill functions.
> + * libdrm buffer object with suitable data needed by the
> render/vebox copy and
> + * the fill functions.
> */
> struct igt_buf {
> drm_intel_bo *bo;
> uint32_t stride;
> uint32_t tiling;
> + enum i915_compression compression;
> uint32_t bpp;
> uint32_t *data;
> uint32_t size;
> @@ -304,6 +307,29 @@ typedef void (*igt_render_copyfunc_t)(struct
> intel_batchbuffer *batch,
>
> igt_render_copyfunc_t igt_get_render_copyfunc(int devid);
>
> +
> +/**
> + * igt_vebox_copyfunc_t:
> + * @batch: batchbuffer object
> + * @src: source i-g-t buffer object
> + * @width: width of the copied rectangle
> + * @height: height of the copied rectangle
> + * @dst: destination i-g-t buffer object
> + *
> + * This is the type of the per-platform vebox copy functions. The
> + * platform-specific implementation can be obtained by calling
> + * igt_get_vebox_copyfunc().
> + *
> + * A vebox copy function will emit a batchbuffer to the kernel which
> executes
> + * the specified blit copy operation using the vebox engine.
> + */
> +typedef void (*igt_vebox_copyfunc_t)(struct intel_batchbuffer
> *batch,
> + const struct igt_buf *src,
> + unsigned width, unsigned height,
> + const struct igt_buf *dst);
> +
> +igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid);
> +
> /**
> * igt_fillfunc_t:
> * @batch: batchbuffer object
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index cabfc879..0a9ee34c 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -674,6 +674,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> SOFTWARE.
> #define RING_INVALID 0x00000000
>
> #define GEN12_GFX_AUX_TABLE_BASE_ADDR 0x4200
> +#define GEN12_VEBOX_AUX_TABLE_BASE_ADDR 0x4230
>
>
> /* BitBlt Instructions
> diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
> index f2412d78..7dd2a1e8 100644
> --- a/lib/ioctl_wrappers.h
> +++ b/lib/ioctl_wrappers.h
> @@ -201,6 +201,7 @@ struct local_drm_mode_fb_cmd2 {
> #define LOCAL_I915_FORMAT_MOD_Y_TILED_CCS local_fourcc_mod_code(I
> NTEL, 4)
> #define LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS local_fourcc_mod_code(I
> NTEL, 5)
> #define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
> fourcc_mod_code(INTEL, 6)
> +#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> fourcc_mod_code(INTEL, 7)
>
> #define LOCAL_DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, \
> struct
> local_drm_mode_fb_cmd2)
> diff --git a/lib/meson.build b/lib/meson.build
> index 3f908912..f7fce905 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -63,6 +63,7 @@ lib_sources = [
> 'igt_edid.c',
> 'igt_eld.c',
> 'igt_infoframe.c',
> + 'veboxcopy_gen12.c',
> ]
>
> lib_deps = [
> diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
> index 94e816b6..e7fdd7a6 100644
> --- a/lib/rendercopy_gen9.c
> +++ b/lib/rendercopy_gen9.c
> @@ -1026,7 +1026,7 @@ void _gen9_render_copyfunc(struct
> intel_batchbuffer *batch,
> OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
> GEN9_PIPELINE_SELECTION_MASK);
>
> - gen12_emit_aux_pgtable_state(batch, aux_pgtable_state);
> + gen12_emit_aux_pgtable_state(batch, aux_pgtable_state, true);
>
> gen8_emit_sip(batch);
>
> diff --git a/lib/veboxcopy.h b/lib/veboxcopy.h
> new file mode 100644
> index 00000000..949d83bf
> --- /dev/null
> +++ b/lib/veboxcopy.h
> @@ -0,0 +1,9 @@
> +#ifndef __VEBOXCOPY_H__
> +#define __VEBOXCOPY_H__
> +
> +void gen12_vebox_copyfunc(struct intel_batchbuffer *batch,
> + const struct igt_buf *src,
> + unsigned width, unsigned height,
> + const struct igt_buf *dst);
> +
> +#endif
> diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c
> new file mode 100644
> index 00000000..87800941
> --- /dev/null
> +++ b/lib/veboxcopy_gen12.c
> @@ -0,0 +1,269 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person
> obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> the
> + * Software is furnished to do so, subject to the following
> conditions:
> + *
> + * The above copyright notice and this permission notice (including
> the next
> + * paragraph) shall be included in all copies or substantial
> portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
> OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +#include <drm.h>
> +
> +#include "igt.h"
> +#include "intel_aux_pgtable.h"
> +#include "veboxcopy.h"
> +
> +#define R8G8B8A8_UNORM 8
> +
> +struct vebox_surface_state {
> + struct {
> + uint32_t dw_count:12;
> + uint32_t pad:4;
> + uint32_t sub_opcode_b:5;
> + uint32_t sub_opcode_a:3;
> + uint32_t media_cmd_opcode:3;
> + uint32_t media_cmd_pipeline:2;
> + uint32_t cmd_type:3;
> + } ss0;
> + struct {
> +#define VEBOX_SURFACE_INPUT 0
> +#define VEBOX_SURFACE_OUTPUT 1
> + uint32_t surface_id:1;
> + uint32_t pad:31;
> + } ss1;
> + struct {
> + uint32_t pad:4;
> + uint32_t width:14;
> + uint32_t height:14;
> + } ss2;
> + struct {
> +#define VEBOX_TILE_WALK_XMAJOR 0
> +#define VEBOX_TILE_WALK_YMAJOR 1
> + uint32_t tile_walk:1;
> + uint32_t tiled_surface:1;
> + uint32_t chroma_half_pitch:1;
> + uint32_t surface_pitch:17;
> + uint32_t chroma_interleave:1;
> + uint32_t lsb_packed_enable:1;
> + uint32_t bayer_input_alignment:2;
> + uint32_t bayer_pattern_format:1;
> + uint32_t bayer_pattern_offset:2;
> + uint32_t surface_format:5;
> + } ss3;
> + struct {
> + uint32_t u_y_offset:15;
> + uint32_t u_x_offset:13;
> + uint32_t pad:4;
> + } ss4;
> + struct {
> + uint32_t v_y_offset:15;
> + uint32_t v_x_offset:13;
> + uint32_t pad:4;
> + } ss5;
> + struct {
> + uint32_t frame_y_offset:15;
> + uint32_t frame_x_offset:15;
> + uint32_t pad:2;
> + } ss6;
> + struct {
> + uint32_t derived_surface_pitch:17;
> + uint32_t pad:15;
> + } ss7;
> + struct {
> + uint32_t skin_score_output_surface_pitch:17;
> + uint32_t pad:15;
> + } ss8;
> +} __attribute__((packed));
> +
> +struct vebox_tiling_convert {
> + struct {
> + uint32_t dw_count:12;
> + uint32_t pad:4;
> + uint32_t sub_opcode_b:5;
> + uint32_t sub_opcode_a:3;
> + uint32_t cmd_opcode:3;
> + uint32_t pipeline:2;
> + uint32_t cmd_type:3;
> + } tc0;
> + union {
> + struct {
> + uint64_t input_encrypted_data:1;
> + uint64_t input_mocs_idx:6;
> + uint64_t input_memory_compression_enable:1;
> +#define COMPRESSION_TYPE_MEDIA 0
> +#define COMPRESSION_TYPE_RENDER 1
> + uint64_t input_compression_type:1;
> +#define TRMODE_NONE 0
> +#define TRMODE_TILE_YF 1
> +#define TRMODE_TILE_YS 2
> + uint64_t input_tiled_resource_mode:2;
> + uint64_t pad:1;
> + uint64_t input_address:52;
> + } tc1_2;
> + uint64_t tc1_2_l;
> + };
> + union {
> + struct {
> + uint64_t output_encrypted_data:1;
> + uint64_t output_mocs_idx:6;
> + uint64_t output_memory_compression_enable:1;
> + uint64_t output_compression_type:1;
> + uint64_t output_tiled_resource_mode:2;
> + uint64_t pad:1;
> + uint64_t output_address:52;
> + } tc3_4;
> + uint64_t tc3_4_l;
> + };
> +} __attribute__((packed));
> +
> +static void emit_surface_state_cmd(struct intel_batchbuffer *batch,
> + int surface_id,
> + int width, int height, int bpp,
> + int pitch, uint32_t tiling, int
> format)
> +{
> + struct vebox_surface_state *ss;
> +
> + ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 4);
> +
> + ss->ss0.cmd_type = 3;
> + ss->ss0.media_cmd_pipeline = 2;
> + ss->ss0.media_cmd_opcode = 4;
> + ss->ss0.dw_count = 7;
> +
> + ss->ss1.surface_id = surface_id;
> +
> + ss->ss2.height = height - 1;
> + ss->ss2.width = width - 1;
> +
> + ss->ss3.surface_format = format;
> + ss->ss3.surface_pitch = pitch - 1;
> + ss->ss3.tile_walk = (tiling == I915_TILING_Y) ||
> + (tiling == I915_TILING_Yf);
> + ss->ss3.tiled_surface = tiling != I915_TILING_NONE;
> +
> + ss->ss7.derived_surface_pitch = pitch - 1;
> +}
> +
> +static void emit_tiling_convert_cmd(struct intel_batchbuffer *batch,
> + drm_intel_bo *input_bo,
> + uint32_t input_tiling,
> + uint32_t input_compression,
> + drm_intel_bo *output_bo,
> + uint32_t output_tiling,
> + uint32_t output_compression)
> +{
> + uint32_t reloc_delta;
> + struct vebox_tiling_convert *tc;
> + int ret;
> +
> + tc = intel_batchbuffer_subdata_alloc(batch, sizeof(*tc), 8);
> +
> + tc->tc0.cmd_type = 3;
> + tc->tc0.pipeline = 2;
> + tc->tc0.cmd_opcode = 4;
> + tc->tc0.sub_opcode_b = 1;
> +
> + tc->tc0.dw_count = 3;
> +
> + if (input_compression != I915_COMPRESSION_NONE) {
> + tc->tc1_2.input_memory_compression_enable = 1;
> + tc->tc1_2.input_compression_type =
> + input_compression == I915_COMPRESSION_RENDER;
> + }
> + tc->tc1_2.input_tiled_resource_mode = input_tiling ==
> I915_TILING_Yf;
> + reloc_delta = tc->tc1_2_l;
> +
> + igt_assert(input_bo->offset64 == ALIGN(input_bo->offset64,
> 0x1000));
> + tc->tc1_2.input_address = input_bo->offset64 >> 12;
> + igt_assert(reloc_delta <= INT32_MAX);
> + ret = drm_intel_bo_emit_reloc(batch->bo,
> + intel_batchbuffer_subdata_offset(
> batch, tc) +
> + offsetof(typeof(*tc), tc1_2),
> + input_bo, reloc_delta,
> + 0, 0);
> + igt_assert(ret == 0);
> +
> + if (output_compression != I915_COMPRESSION_NONE) {
> + tc->tc3_4.output_memory_compression_enable = 1;
> + tc->tc3_4.output_compression_type =
> + output_compression == I915_COMPRESSION_RENDER;
> + }
> + tc->tc3_4.output_tiled_resource_mode = output_tiling ==
> I915_TILING_Yf;
> + reloc_delta = tc->tc3_4_l;
> +
> + igt_assert(output_bo->offset64 == ALIGN(output_bo->offset64,
> 0x1000));
> + tc->tc3_4.output_address = output_bo->offset64 >> 12;
> + igt_assert(reloc_delta <= INT32_MAX);
> + ret = drm_intel_bo_emit_reloc(batch->bo,
> + intel_batchbuffer_subdata_offset(
> batch, tc) +
> + offsetof(typeof(*tc), tc3_4),
> + output_bo, reloc_delta,
> + 0, I915_GEM_DOMAIN_RENDER);
> + igt_assert(ret == 0);
> +
> +}
> +
> +/* Borrowing the idea from the rendercopy state setup. */
> +#define BATCH_STATE_SPLIT 2048
> +
> +void gen12_vebox_copyfunc(struct intel_batchbuffer *batch,
> + const struct igt_buf *src,
> + unsigned width, unsigned height,
> + const struct igt_buf *dst)
> +{
> + struct aux_pgtable_info aux_pgtable_info = { };
> + uint32_t aux_pgtable_state;
> +
> + igt_assert(src->bpp == dst->bpp);
> +
> + intel_batchbuffer_flush_on_ring(batch, I915_EXEC_VEBOX);
> +
> + intel_batchbuffer_align(batch, 8);
> +
> + batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
> +
> + gen12_aux_pgtable_init(&aux_pgtable_info, batch->bufmgr, src,
> dst);
> +
> + aux_pgtable_state = gen12_create_aux_pgtable_state(batch,
> + aux_pgtable_
> info.pgtable_bo);
> +
> + assert(batch->ptr < &batch->buffer[4095]);
> + batch->ptr = batch->buffer;
> +
> + gen12_emit_aux_pgtable_state(batch, aux_pgtable_state, false);
> +
> + /* TODO: add support for more formats */
> + igt_assert(src->bpp == 32);
> + emit_surface_state_cmd(batch, VEBOX_SURFACE_INPUT,
> + width, height, src->bpp, src->stride,
> + src->tiling, R8G8B8A8_UNORM);
> +
> + igt_assert(dst->bpp == 32);
> + emit_surface_state_cmd(batch, VEBOX_SURFACE_OUTPUT,
> + width, height, dst->bpp, dst->stride,
> + dst->tiling, R8G8B8A8_UNORM);
> +
> + emit_tiling_convert_cmd(batch,
> + src->bo, src->tiling, src->compression,
> + dst->bo, dst->tiling, dst-
> >compression);
> +
> + OUT_BATCH(MI_BATCH_BUFFER_END);
> +
> + intel_batchbuffer_flush_on_ring(batch, I915_EXEC_VEBOX);
> +
> + gen12_aux_pgtable_cleanup(&aux_pgtable_info);
> + intel_batchbuffer_reset(batch);
> +}
> diff --git a/tests/i915/gem_render_copy.c
> b/tests/i915/gem_render_copy.c
> index 15ba1704..9c36f38b 100644
> --- a/tests/i915/gem_render_copy.c
> +++ b/tests/i915/gem_render_copy.c
> @@ -471,6 +471,7 @@ static void scratch_buf_init(data_t *data, struct
> igt_buf *buf,
> aux_width = scratch_buf_aux_width(data->devid, buf);
> aux_height = scratch_buf_aux_height(data->devid, buf);
>
> + buf->compression = compression;
> buf->aux.offset = buf->stride * ALIGN(height, 32);
> buf->aux.stride = aux_width;
>
_______________________________________________
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^ permalink raw reply [flat|nested] 25+ messages in thread* [igt-dev] [PATCH v2 5/6] lib: Add vebox copy support
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 5/6] lib: Add vebox copy support Imre Deak
2019-12-04 13:09 ` Kahola, Mika
@ 2019-12-04 13:49 ` Imre Deak
2019-12-05 10:30 ` Kahola, Mika
2019-12-05 3:30 ` [igt-dev] [PATCH i-g-t " Bai, Guangyao
2 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2019-12-04 13:49 UTC (permalink / raw)
To: igt-dev; +Cc: Brian Welty
To produce surfaces that are compressed using the media compression
format we need to use one of the media engines. The simplest way for
this is to use the vebox engine's tiling convert command, so add support
for this.
v2:
- Rebase on latest igt. (Mika)
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
lib/Makefile.sources | 1 +
lib/igt_fb.c | 77 +++++++---
lib/intel_aux_pgtable.c | 10 +-
lib/intel_aux_pgtable.h | 3 +-
lib/intel_batchbuffer.c | 11 ++
lib/intel_batchbuffer.h | 30 +++-
lib/intel_reg.h | 1 +
lib/ioctl_wrappers.h | 1 +
lib/meson.build | 1 +
lib/rendercopy_gen9.c | 2 +-
lib/veboxcopy.h | 9 ++
lib/veboxcopy_gen12.c | 269 +++++++++++++++++++++++++++++++++++
tests/i915/gem_render_copy.c | 1 +
13 files changed, 388 insertions(+), 28 deletions(-)
create mode 100644 lib/veboxcopy.h
create mode 100644 lib/veboxcopy_gen12.c
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 750e630b..5dd3962e 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -131,6 +131,7 @@ lib_source_list = \
igt_vc4.h \
igt_amd.c \
igt_amd.h \
+ veboxcopy_gen12.c \
$(NULL)
.PHONY: version.h.tmp
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index 6ce7cfea..3b141b93 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -403,6 +403,7 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
igt_require_intel(fd);
if (intel_gen(intel_get_drm_devid(fd)) == 2) {
*width_ret = 128;
@@ -467,17 +468,21 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int fb_bpp,
}
}
+static bool is_gen12_mc_ccs_modifier(uint64_t modifier)
+{
+ return modifier == LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
+}
+
static bool is_gen12_ccs_modifier(uint64_t modifier)
{
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
+ return is_gen12_mc_ccs_modifier(modifier) ||
+ modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
}
static bool is_ccs_modifier(uint64_t modifier)
{
-
- return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
- modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
+ return is_gen12_ccs_modifier(modifier) ||
modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
}
@@ -733,6 +738,7 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
return I915_TILING_Y;
case LOCAL_I915_FORMAT_MOD_Yf_TILED:
case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
@@ -1911,7 +1917,7 @@ static bool blitter_ok(const struct igt_fb *fb)
return true;
}
-static bool use_rendercopy(const struct igt_fb *fb)
+static bool use_enginecopy(const struct igt_fb *fb)
{
return is_ccs_modifier(fb->modifier) ||
(fb->modifier == I915_FORMAT_MOD_Yf_TILED &&
@@ -1960,25 +1966,52 @@ static void fini_buf(struct igt_buf *buf)
drm_intel_bo_unreference(buf->bo);
}
-static void rendercopy(struct fb_blit_upload *blit,
- const struct igt_fb *dst_fb,
- const struct igt_fb *src_fb)
+/**
+ * copy_with_engine:
+ * @blit: context for the copy operation
+ * @dst_fb: destination buffer
+ * @src_fb: source buffer
+ *
+ * Copy @src_fb to @dst_fb using either the render or vebox engine. The engine
+ * is selected based on the compression surface format required by the @dst_fb
+ * FB modifier. On GEN12+ a given compression format (render or media) can be
+ * produced only by the selected engine:
+ * - For GEN12 media compressed: vebox engine
+ * - For uncompressed, pre-GEN12 compressed, GEN12+ render compressed: render engine
+ * Note that both GEN12 engine is capable of reading either compression formats.
+ */
+static void copy_with_engine(struct fb_blit_upload *blit,
+ const struct igt_fb *dst_fb,
+ const struct igt_fb *src_fb)
{
struct igt_buf src = {}, dst = {};
- igt_render_copyfunc_t render_copy =
- igt_get_render_copyfunc(intel_get_drm_devid(blit->fd));
+ igt_render_copyfunc_t render_copy = NULL;
+ igt_vebox_copyfunc_t vebox_copy = NULL;
+
+ if (is_gen12_mc_ccs_modifier(dst_fb->modifier))
+ vebox_copy = igt_get_vebox_copyfunc(intel_get_drm_devid(blit->fd));
+ else
+ render_copy = igt_get_render_copyfunc(intel_get_drm_devid(blit->fd));
- igt_require(render_copy);
+ igt_require(vebox_copy || render_copy);
igt_assert_eq(dst_fb->offsets[0], 0);
igt_assert_eq(src_fb->offsets[0], 0);
- init_buf(blit, &src, src_fb, "cairo rendercopy src");
- init_buf(blit, &dst, dst_fb, "cairo rendercopy dst");
+ init_buf(blit, &src, src_fb, "cairo enginecopy src");
+ init_buf(blit, &dst, dst_fb, "cairo enginecopy dst");
- render_copy(blit->batch, NULL,
- &src, 0, 0, dst_fb->plane_width[0], dst_fb->plane_height[0],
- &dst, 0, 0);
+ if (vebox_copy)
+ vebox_copy(blit->batch, &src,
+ dst_fb->plane_width[0], dst_fb->plane_height[0],
+ &dst);
+ else
+ render_copy(blit->batch, NULL,
+ &src,
+ 0, 0,
+ dst_fb->plane_width[0], dst_fb->plane_height[0],
+ &dst,
+ 0, 0);
fini_buf(&dst);
fini_buf(&src);
@@ -2029,7 +2062,7 @@ static void free_linear_mapping(struct fb_blit_upload *blit)
I915_GEM_DOMAIN_GTT, 0);
if (blit->batch)
- rendercopy(blit, fb, &linear->fb);
+ copy_with_engine(blit, fb, &linear->fb);
else
blitcopy(fb, &linear->fb);
@@ -2060,7 +2093,7 @@ static void setup_linear_mapping(struct fb_blit_upload *blit)
struct igt_fb *fb = blit->fb;
struct fb_blit_linear *linear = &blit->linear;
- if (!igt_vc4_is_tiled(fb->modifier) && use_rendercopy(fb)) {
+ if (!igt_vc4_is_tiled(fb->modifier) && use_enginecopy(fb)) {
blit->bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
blit->batch = intel_batchbuffer_alloc(blit->bufmgr,
intel_get_drm_devid(fd));
@@ -2096,7 +2129,7 @@ static void setup_linear_mapping(struct fb_blit_upload *blit)
I915_GEM_DOMAIN_GTT, 0);
if (blit->batch)
- rendercopy(blit, &linear->fb, fb);
+ copy_with_engine(blit, &linear->fb, fb);
else
blitcopy(&linear->fb, fb);
@@ -3202,7 +3235,8 @@ static void create_cairo_surface__convert(int fd, struct igt_fb *fb)
&blit->shadow_fb);
igt_assert(blit->shadow_ptr);
- if (use_rendercopy(fb) || use_blitter(fb) || igt_vc4_is_tiled(fb->modifier)) {
+ if (use_enginecopy(fb) || use_blitter(fb) ||
+ igt_vc4_is_tiled(fb->modifier)) {
setup_linear_mapping(&blit->base);
} else {
blit->base.linear.fb = *fb;
@@ -3285,7 +3319,8 @@ cairo_surface_t *igt_get_cairo_surface(int fd, struct igt_fb *fb)
if (fb->cairo_surface == NULL) {
if (use_convert(fb))
create_cairo_surface__convert(fd, fb);
- else if (use_blitter(fb) || use_rendercopy(fb) || igt_vc4_is_tiled(fb->modifier))
+ else if (use_blitter(fb) || use_enginecopy(fb) ||
+ igt_vc4_is_tiled(fb->modifier))
create_cairo_surface__gpu(fd, fb);
else
create_cairo_surface__gtt(fd, fb);
diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
index 2f22bb39..cbb3c320 100644
--- a/lib/intel_aux_pgtable.c
+++ b/lib/intel_aux_pgtable.c
@@ -555,16 +555,20 @@ gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
}
void
-gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state)
+gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state,
+ bool render)
{
+ uint32_t table_base_reg = render ? GEN12_GFX_AUX_TABLE_BASE_ADDR :
+ GEN12_VEBOX_AUX_TABLE_BASE_ADDR;
+
if (!state)
return;
OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12);
- OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
+ OUT_BATCH(table_base_reg);
OUT_RELOC(batch->bo, 0, 0, state);
OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 | MI_MMIO_REMAP_ENABLE_GEN12);
- OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
+ OUT_BATCH(table_base_reg + 4);
OUT_RELOC(batch->bo, 0, 0, state + 4);
}
diff --git a/lib/intel_aux_pgtable.h b/lib/intel_aux_pgtable.h
index 20278db0..ac82b7d2 100644
--- a/lib/intel_aux_pgtable.h
+++ b/lib/intel_aux_pgtable.h
@@ -30,6 +30,7 @@ uint32_t
gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
drm_intel_bo *aux_pgtable_bo);
void
-gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state);
+gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state,
+ bool render);
#endif
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 3828ba75..51aae4dc 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -37,6 +37,7 @@
#include "intel_bufmgr.h"
#include "intel_chipset.h"
#include "intel_reg.h"
+#include "veboxcopy.h"
#include "rendercopy.h"
#include "media_fill.h"
#include "ioctl_wrappers.h"
@@ -850,6 +851,16 @@ igt_render_copyfunc_t igt_get_render_copyfunc(int devid)
return copy;
}
+igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid)
+{
+ igt_vebox_copyfunc_t copy = NULL;
+
+ if (IS_GEN12(devid))
+ copy = gen12_vebox_copyfunc;
+
+ return copy;
+}
+
/**
* igt_get_media_fillfunc:
* @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 888188f9..37e3affe 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -213,6 +213,7 @@ void intel_copy_bo(struct intel_batchbuffer *batch,
enum i915_compression {
I915_COMPRESSION_NONE,
I915_COMPRESSION_RENDER,
+ I915_COMPRESSION_MEDIA,
};
/**
@@ -220,18 +221,20 @@ enum i915_compression {
* @bo: underlying libdrm buffer object
* @stride: stride of the buffer
* @tiling: tiling mode bits
+ * @compression: memory compression mode
* @bpp: bits per pixel, 8, 16 or 32.
* @data: pointer to the memory mapping of the buffer
* @size: size of the buffer object
*
* This is a i-g-t buffer object wrapper structure which augments the baseline
- * libdrm buffer object with suitable data needed by the render copy and the
- * fill functions.
+ * libdrm buffer object with suitable data needed by the render/vebox copy and
+ * the fill functions.
*/
struct igt_buf {
drm_intel_bo *bo;
uint32_t stride;
uint32_t tiling;
+ enum i915_compression compression;
uint32_t bpp;
uint32_t *data;
uint32_t size;
@@ -307,6 +310,29 @@ typedef void (*igt_render_copyfunc_t)(struct intel_batchbuffer *batch,
igt_render_copyfunc_t igt_get_render_copyfunc(int devid);
+
+/**
+ * igt_vebox_copyfunc_t:
+ * @batch: batchbuffer object
+ * @src: source i-g-t buffer object
+ * @width: width of the copied rectangle
+ * @height: height of the copied rectangle
+ * @dst: destination i-g-t buffer object
+ *
+ * This is the type of the per-platform vebox copy functions. The
+ * platform-specific implementation can be obtained by calling
+ * igt_get_vebox_copyfunc().
+ *
+ * A vebox copy function will emit a batchbuffer to the kernel which executes
+ * the specified blit copy operation using the vebox engine.
+ */
+typedef void (*igt_vebox_copyfunc_t)(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned width, unsigned height,
+ const struct igt_buf *dst);
+
+igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid);
+
/**
* igt_fillfunc_t:
* @batch: batchbuffer object
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index cabfc879..0a9ee34c 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -674,6 +674,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define RING_INVALID 0x00000000
#define GEN12_GFX_AUX_TABLE_BASE_ADDR 0x4200
+#define GEN12_VEBOX_AUX_TABLE_BASE_ADDR 0x4230
/* BitBlt Instructions
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index e80e22f1..7614e688 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -202,6 +202,7 @@ struct local_drm_mode_fb_cmd2 {
#define LOCAL_I915_FORMAT_MOD_Y_TILED_CCS local_fourcc_mod_code(INTEL, 4)
#define LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS local_fourcc_mod_code(INTEL, 5)
#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
+#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
#define LOCAL_DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, \
struct local_drm_mode_fb_cmd2)
diff --git a/lib/meson.build b/lib/meson.build
index 62d61654..57eb7d93 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -64,6 +64,7 @@ lib_sources = [
'igt_edid.c',
'igt_eld.c',
'igt_infoframe.c',
+ 'veboxcopy_gen12.c',
]
lib_deps = [
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 991a6393..bf9d2ee1 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -1037,7 +1037,7 @@ void _gen9_render_copyfunc(struct intel_batchbuffer *batch,
OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
GEN9_PIPELINE_SELECTION_MASK);
- gen12_emit_aux_pgtable_state(batch, aux_pgtable_state);
+ gen12_emit_aux_pgtable_state(batch, aux_pgtable_state, true);
gen8_emit_sip(batch);
diff --git a/lib/veboxcopy.h b/lib/veboxcopy.h
new file mode 100644
index 00000000..949d83bf
--- /dev/null
+++ b/lib/veboxcopy.h
@@ -0,0 +1,9 @@
+#ifndef __VEBOXCOPY_H__
+#define __VEBOXCOPY_H__
+
+void gen12_vebox_copyfunc(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned width, unsigned height,
+ const struct igt_buf *dst);
+
+#endif
diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c
new file mode 100644
index 00000000..87800941
--- /dev/null
+++ b/lib/veboxcopy_gen12.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_aux_pgtable.h"
+#include "veboxcopy.h"
+
+#define R8G8B8A8_UNORM 8
+
+struct vebox_surface_state {
+ struct {
+ uint32_t dw_count:12;
+ uint32_t pad:4;
+ uint32_t sub_opcode_b:5;
+ uint32_t sub_opcode_a:3;
+ uint32_t media_cmd_opcode:3;
+ uint32_t media_cmd_pipeline:2;
+ uint32_t cmd_type:3;
+ } ss0;
+ struct {
+#define VEBOX_SURFACE_INPUT 0
+#define VEBOX_SURFACE_OUTPUT 1
+ uint32_t surface_id:1;
+ uint32_t pad:31;
+ } ss1;
+ struct {
+ uint32_t pad:4;
+ uint32_t width:14;
+ uint32_t height:14;
+ } ss2;
+ struct {
+#define VEBOX_TILE_WALK_XMAJOR 0
+#define VEBOX_TILE_WALK_YMAJOR 1
+ uint32_t tile_walk:1;
+ uint32_t tiled_surface:1;
+ uint32_t chroma_half_pitch:1;
+ uint32_t surface_pitch:17;
+ uint32_t chroma_interleave:1;
+ uint32_t lsb_packed_enable:1;
+ uint32_t bayer_input_alignment:2;
+ uint32_t bayer_pattern_format:1;
+ uint32_t bayer_pattern_offset:2;
+ uint32_t surface_format:5;
+ } ss3;
+ struct {
+ uint32_t u_y_offset:15;
+ uint32_t u_x_offset:13;
+ uint32_t pad:4;
+ } ss4;
+ struct {
+ uint32_t v_y_offset:15;
+ uint32_t v_x_offset:13;
+ uint32_t pad:4;
+ } ss5;
+ struct {
+ uint32_t frame_y_offset:15;
+ uint32_t frame_x_offset:15;
+ uint32_t pad:2;
+ } ss6;
+ struct {
+ uint32_t derived_surface_pitch:17;
+ uint32_t pad:15;
+ } ss7;
+ struct {
+ uint32_t skin_score_output_surface_pitch:17;
+ uint32_t pad:15;
+ } ss8;
+} __attribute__((packed));
+
+struct vebox_tiling_convert {
+ struct {
+ uint32_t dw_count:12;
+ uint32_t pad:4;
+ uint32_t sub_opcode_b:5;
+ uint32_t sub_opcode_a:3;
+ uint32_t cmd_opcode:3;
+ uint32_t pipeline:2;
+ uint32_t cmd_type:3;
+ } tc0;
+ union {
+ struct {
+ uint64_t input_encrypted_data:1;
+ uint64_t input_mocs_idx:6;
+ uint64_t input_memory_compression_enable:1;
+#define COMPRESSION_TYPE_MEDIA 0
+#define COMPRESSION_TYPE_RENDER 1
+ uint64_t input_compression_type:1;
+#define TRMODE_NONE 0
+#define TRMODE_TILE_YF 1
+#define TRMODE_TILE_YS 2
+ uint64_t input_tiled_resource_mode:2;
+ uint64_t pad:1;
+ uint64_t input_address:52;
+ } tc1_2;
+ uint64_t tc1_2_l;
+ };
+ union {
+ struct {
+ uint64_t output_encrypted_data:1;
+ uint64_t output_mocs_idx:6;
+ uint64_t output_memory_compression_enable:1;
+ uint64_t output_compression_type:1;
+ uint64_t output_tiled_resource_mode:2;
+ uint64_t pad:1;
+ uint64_t output_address:52;
+ } tc3_4;
+ uint64_t tc3_4_l;
+ };
+} __attribute__((packed));
+
+static void emit_surface_state_cmd(struct intel_batchbuffer *batch,
+ int surface_id,
+ int width, int height, int bpp,
+ int pitch, uint32_t tiling, int format)
+{
+ struct vebox_surface_state *ss;
+
+ ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 4);
+
+ ss->ss0.cmd_type = 3;
+ ss->ss0.media_cmd_pipeline = 2;
+ ss->ss0.media_cmd_opcode = 4;
+ ss->ss0.dw_count = 7;
+
+ ss->ss1.surface_id = surface_id;
+
+ ss->ss2.height = height - 1;
+ ss->ss2.width = width - 1;
+
+ ss->ss3.surface_format = format;
+ ss->ss3.surface_pitch = pitch - 1;
+ ss->ss3.tile_walk = (tiling == I915_TILING_Y) ||
+ (tiling == I915_TILING_Yf);
+ ss->ss3.tiled_surface = tiling != I915_TILING_NONE;
+
+ ss->ss7.derived_surface_pitch = pitch - 1;
+}
+
+static void emit_tiling_convert_cmd(struct intel_batchbuffer *batch,
+ drm_intel_bo *input_bo,
+ uint32_t input_tiling,
+ uint32_t input_compression,
+ drm_intel_bo *output_bo,
+ uint32_t output_tiling,
+ uint32_t output_compression)
+{
+ uint32_t reloc_delta;
+ struct vebox_tiling_convert *tc;
+ int ret;
+
+ tc = intel_batchbuffer_subdata_alloc(batch, sizeof(*tc), 8);
+
+ tc->tc0.cmd_type = 3;
+ tc->tc0.pipeline = 2;
+ tc->tc0.cmd_opcode = 4;
+ tc->tc0.sub_opcode_b = 1;
+
+ tc->tc0.dw_count = 3;
+
+ if (input_compression != I915_COMPRESSION_NONE) {
+ tc->tc1_2.input_memory_compression_enable = 1;
+ tc->tc1_2.input_compression_type =
+ input_compression == I915_COMPRESSION_RENDER;
+ }
+ tc->tc1_2.input_tiled_resource_mode = input_tiling == I915_TILING_Yf;
+ reloc_delta = tc->tc1_2_l;
+
+ igt_assert(input_bo->offset64 == ALIGN(input_bo->offset64, 0x1000));
+ tc->tc1_2.input_address = input_bo->offset64 >> 12;
+ igt_assert(reloc_delta <= INT32_MAX);
+ ret = drm_intel_bo_emit_reloc(batch->bo,
+ intel_batchbuffer_subdata_offset(batch, tc) +
+ offsetof(typeof(*tc), tc1_2),
+ input_bo, reloc_delta,
+ 0, 0);
+ igt_assert(ret == 0);
+
+ if (output_compression != I915_COMPRESSION_NONE) {
+ tc->tc3_4.output_memory_compression_enable = 1;
+ tc->tc3_4.output_compression_type =
+ output_compression == I915_COMPRESSION_RENDER;
+ }
+ tc->tc3_4.output_tiled_resource_mode = output_tiling == I915_TILING_Yf;
+ reloc_delta = tc->tc3_4_l;
+
+ igt_assert(output_bo->offset64 == ALIGN(output_bo->offset64, 0x1000));
+ tc->tc3_4.output_address = output_bo->offset64 >> 12;
+ igt_assert(reloc_delta <= INT32_MAX);
+ ret = drm_intel_bo_emit_reloc(batch->bo,
+ intel_batchbuffer_subdata_offset(batch, tc) +
+ offsetof(typeof(*tc), tc3_4),
+ output_bo, reloc_delta,
+ 0, I915_GEM_DOMAIN_RENDER);
+ igt_assert(ret == 0);
+
+}
+
+/* Borrowing the idea from the rendercopy state setup. */
+#define BATCH_STATE_SPLIT 2048
+
+void gen12_vebox_copyfunc(struct intel_batchbuffer *batch,
+ const struct igt_buf *src,
+ unsigned width, unsigned height,
+ const struct igt_buf *dst)
+{
+ struct aux_pgtable_info aux_pgtable_info = { };
+ uint32_t aux_pgtable_state;
+
+ igt_assert(src->bpp == dst->bpp);
+
+ intel_batchbuffer_flush_on_ring(batch, I915_EXEC_VEBOX);
+
+ intel_batchbuffer_align(batch, 8);
+
+ batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
+
+ gen12_aux_pgtable_init(&aux_pgtable_info, batch->bufmgr, src, dst);
+
+ aux_pgtable_state = gen12_create_aux_pgtable_state(batch,
+ aux_pgtable_info.pgtable_bo);
+
+ assert(batch->ptr < &batch->buffer[4095]);
+ batch->ptr = batch->buffer;
+
+ gen12_emit_aux_pgtable_state(batch, aux_pgtable_state, false);
+
+ /* TODO: add support for more formats */
+ igt_assert(src->bpp == 32);
+ emit_surface_state_cmd(batch, VEBOX_SURFACE_INPUT,
+ width, height, src->bpp, src->stride,
+ src->tiling, R8G8B8A8_UNORM);
+
+ igt_assert(dst->bpp == 32);
+ emit_surface_state_cmd(batch, VEBOX_SURFACE_OUTPUT,
+ width, height, dst->bpp, dst->stride,
+ dst->tiling, R8G8B8A8_UNORM);
+
+ emit_tiling_convert_cmd(batch,
+ src->bo, src->tiling, src->compression,
+ dst->bo, dst->tiling, dst->compression);
+
+ OUT_BATCH(MI_BATCH_BUFFER_END);
+
+ intel_batchbuffer_flush_on_ring(batch, I915_EXEC_VEBOX);
+
+ gen12_aux_pgtable_cleanup(&aux_pgtable_info);
+ intel_batchbuffer_reset(batch);
+}
diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
index 15ba1704..9c36f38b 100644
--- a/tests/i915/gem_render_copy.c
+++ b/tests/i915/gem_render_copy.c
@@ -471,6 +471,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf,
aux_width = scratch_buf_aux_width(data->devid, buf);
aux_height = scratch_buf_aux_height(data->devid, buf);
+ buf->compression = compression;
buf->aux.offset = buf->stride * ALIGN(height, 32);
buf->aux.stride = aux_width;
--
2.17.1
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [igt-dev] [PATCH v2 5/6] lib: Add vebox copy support
2019-12-04 13:49 ` [igt-dev] [PATCH v2 " Imre Deak
@ 2019-12-05 10:30 ` Kahola, Mika
0 siblings, 0 replies; 25+ messages in thread
From: Kahola, Mika @ 2019-12-05 10:30 UTC (permalink / raw)
To: igt-dev, Deak, Imre; +Cc: Welty, Brian
On Wed, 2019-12-04 at 15:49 +0200, Imre Deak wrote:
> To produce surfaces that are compressed using the media compression
> format we need to use one of the media engines. The simplest way for
> this is to use the vebox engine's tiling convert command, so add
> support
> for this.
>
> v2:
> - Rebase on latest igt. (Mika)
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> lib/Makefile.sources | 1 +
> lib/igt_fb.c | 77 +++++++---
> lib/intel_aux_pgtable.c | 10 +-
> lib/intel_aux_pgtable.h | 3 +-
> lib/intel_batchbuffer.c | 11 ++
> lib/intel_batchbuffer.h | 30 +++-
> lib/intel_reg.h | 1 +
> lib/ioctl_wrappers.h | 1 +
> lib/meson.build | 1 +
> lib/rendercopy_gen9.c | 2 +-
> lib/veboxcopy.h | 9 ++
> lib/veboxcopy_gen12.c | 269
> +++++++++++++++++++++++++++++++++++
> tests/i915/gem_render_copy.c | 1 +
> 13 files changed, 388 insertions(+), 28 deletions(-)
> create mode 100644 lib/veboxcopy.h
> create mode 100644 lib/veboxcopy_gen12.c
>
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index 750e630b..5dd3962e 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -131,6 +131,7 @@ lib_source_list = \
> igt_vc4.h \
> igt_amd.c \
> igt_amd.h \
> + veboxcopy_gen12.c \
> $(NULL)
>
> .PHONY: version.h.tmp
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index 6ce7cfea..3b141b93 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -403,6 +403,7 @@ void igt_get_fb_tile_size(int fd, uint64_t
> modifier, int fb_bpp,
> case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
> case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> igt_require_intel(fd);
> if (intel_gen(intel_get_drm_devid(fd)) == 2) {
> *width_ret = 128;
> @@ -467,17 +468,21 @@ void igt_get_fb_tile_size(int fd, uint64_t
> modifier, int fb_bpp,
> }
> }
>
> +static bool is_gen12_mc_ccs_modifier(uint64_t modifier)
> +{
> + return modifier == LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> +}
> +
> static bool is_gen12_ccs_modifier(uint64_t modifier)
> {
> - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> + return is_gen12_mc_ccs_modifier(modifier) ||
> + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC;
> }
>
> static bool is_ccs_modifier(uint64_t modifier)
> {
> -
> - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS ||
> - modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC ||
> + return is_gen12_ccs_modifier(modifier) ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
> }
> @@ -733,6 +738,7 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
> case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
> case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> + case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> return I915_TILING_Y;
> case LOCAL_I915_FORMAT_MOD_Yf_TILED:
> case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -1911,7 +1917,7 @@ static bool blitter_ok(const struct igt_fb *fb)
> return true;
> }
>
> -static bool use_rendercopy(const struct igt_fb *fb)
> +static bool use_enginecopy(const struct igt_fb *fb)
> {
> return is_ccs_modifier(fb->modifier) ||
> (fb->modifier == I915_FORMAT_MOD_Yf_TILED &&
> @@ -1960,25 +1966,52 @@ static void fini_buf(struct igt_buf *buf)
> drm_intel_bo_unreference(buf->bo);
> }
>
> -static void rendercopy(struct fb_blit_upload *blit,
> - const struct igt_fb *dst_fb,
> - const struct igt_fb *src_fb)
> +/**
> + * copy_with_engine:
> + * @blit: context for the copy operation
> + * @dst_fb: destination buffer
> + * @src_fb: source buffer
> + *
> + * Copy @src_fb to @dst_fb using either the render or vebox engine.
> The engine
> + * is selected based on the compression surface format required by
> the @dst_fb
> + * FB modifier. On GEN12+ a given compression format (render or
> media) can be
> + * produced only by the selected engine:
> + * - For GEN12 media compressed: vebox engine
> + * - For uncompressed, pre-GEN12 compressed, GEN12+ render
> compressed: render engine
> + * Note that both GEN12 engine is capable of reading either
> compression formats.
> + */
> +static void copy_with_engine(struct fb_blit_upload *blit,
> + const struct igt_fb *dst_fb,
> + const struct igt_fb *src_fb)
> {
> struct igt_buf src = {}, dst = {};
> - igt_render_copyfunc_t render_copy =
> - igt_get_render_copyfunc(intel_get_drm_devid(blit->fd));
> + igt_render_copyfunc_t render_copy = NULL;
> + igt_vebox_copyfunc_t vebox_copy = NULL;
> +
> + if (is_gen12_mc_ccs_modifier(dst_fb->modifier))
> + vebox_copy =
> igt_get_vebox_copyfunc(intel_get_drm_devid(blit->fd));
> + else
> + render_copy =
> igt_get_render_copyfunc(intel_get_drm_devid(blit->fd));
>
> - igt_require(render_copy);
> + igt_require(vebox_copy || render_copy);
>
> igt_assert_eq(dst_fb->offsets[0], 0);
> igt_assert_eq(src_fb->offsets[0], 0);
>
> - init_buf(blit, &src, src_fb, "cairo rendercopy src");
> - init_buf(blit, &dst, dst_fb, "cairo rendercopy dst");
> + init_buf(blit, &src, src_fb, "cairo enginecopy src");
> + init_buf(blit, &dst, dst_fb, "cairo enginecopy dst");
>
> - render_copy(blit->batch, NULL,
> - &src, 0, 0, dst_fb->plane_width[0], dst_fb-
> >plane_height[0],
> - &dst, 0, 0);
> + if (vebox_copy)
> + vebox_copy(blit->batch, &src,
> + dst_fb->plane_width[0], dst_fb-
> >plane_height[0],
> + &dst);
> + else
> + render_copy(blit->batch, NULL,
> + &src,
> + 0, 0,
> + dst_fb->plane_width[0], dst_fb-
> >plane_height[0],
> + &dst,
> + 0, 0);
>
> fini_buf(&dst);
> fini_buf(&src);
> @@ -2029,7 +2062,7 @@ static void free_linear_mapping(struct
> fb_blit_upload *blit)
> I915_GEM_DOMAIN_GTT, 0);
>
> if (blit->batch)
> - rendercopy(blit, fb, &linear->fb);
> + copy_with_engine(blit, fb, &linear->fb);
> else
> blitcopy(fb, &linear->fb);
>
> @@ -2060,7 +2093,7 @@ static void setup_linear_mapping(struct
> fb_blit_upload *blit)
> struct igt_fb *fb = blit->fb;
> struct fb_blit_linear *linear = &blit->linear;
>
> - if (!igt_vc4_is_tiled(fb->modifier) && use_rendercopy(fb)) {
> + if (!igt_vc4_is_tiled(fb->modifier) && use_enginecopy(fb)) {
> blit->bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
> blit->batch = intel_batchbuffer_alloc(blit->bufmgr,
> intel_get_drm_dev
> id(fd));
> @@ -2096,7 +2129,7 @@ static void setup_linear_mapping(struct
> fb_blit_upload *blit)
> I915_GEM_DOMAIN_GTT, 0);
>
> if (blit->batch)
> - rendercopy(blit, &linear->fb, fb);
> + copy_with_engine(blit, &linear->fb, fb);
> else
> blitcopy(&linear->fb, fb);
>
> @@ -3202,7 +3235,8 @@ static void create_cairo_surface__convert(int
> fd, struct igt_fb *fb)
> &blit-
> >shadow_fb);
> igt_assert(blit->shadow_ptr);
>
> - if (use_rendercopy(fb) || use_blitter(fb) ||
> igt_vc4_is_tiled(fb->modifier)) {
> + if (use_enginecopy(fb) || use_blitter(fb) ||
> + igt_vc4_is_tiled(fb->modifier)) {
> setup_linear_mapping(&blit->base);
> } else {
> blit->base.linear.fb = *fb;
> @@ -3285,7 +3319,8 @@ cairo_surface_t *igt_get_cairo_surface(int fd,
> struct igt_fb *fb)
> if (fb->cairo_surface == NULL) {
> if (use_convert(fb))
> create_cairo_surface__convert(fd, fb);
> - else if (use_blitter(fb) || use_rendercopy(fb) ||
> igt_vc4_is_tiled(fb->modifier))
> + else if (use_blitter(fb) || use_enginecopy(fb) ||
> + igt_vc4_is_tiled(fb->modifier))
> create_cairo_surface__gpu(fd, fb);
> else
> create_cairo_surface__gtt(fd, fb);
> diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c
> index 2f22bb39..cbb3c320 100644
> --- a/lib/intel_aux_pgtable.c
> +++ b/lib/intel_aux_pgtable.c
> @@ -555,16 +555,20 @@ gen12_create_aux_pgtable_state(struct
> intel_batchbuffer *batch,
> }
>
> void
> -gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch,
> uint32_t state)
> +gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch,
> uint32_t state,
> + bool render)
> {
> + uint32_t table_base_reg = render ?
> GEN12_GFX_AUX_TABLE_BASE_ADDR :
> + GEN12_VEBOX_AUX_TABLE_BASE_A
> DDR;
> +
> if (!state)
> return;
>
> OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 |
> MI_MMIO_REMAP_ENABLE_GEN12);
> - OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
> + OUT_BATCH(table_base_reg);
> OUT_RELOC(batch->bo, 0, 0, state);
>
> OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 |
> MI_MMIO_REMAP_ENABLE_GEN12);
> - OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
> + OUT_BATCH(table_base_reg + 4);
> OUT_RELOC(batch->bo, 0, 0, state + 4);
> }
> diff --git a/lib/intel_aux_pgtable.h b/lib/intel_aux_pgtable.h
> index 20278db0..ac82b7d2 100644
> --- a/lib/intel_aux_pgtable.h
> +++ b/lib/intel_aux_pgtable.h
> @@ -30,6 +30,7 @@ uint32_t
> gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
> drm_intel_bo *aux_pgtable_bo);
> void
> -gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch,
> uint32_t state);
> +gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch,
> uint32_t state,
> + bool render);
>
> #endif
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index 3828ba75..51aae4dc 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -37,6 +37,7 @@
> #include "intel_bufmgr.h"
> #include "intel_chipset.h"
> #include "intel_reg.h"
> +#include "veboxcopy.h"
> #include "rendercopy.h"
> #include "media_fill.h"
> #include "ioctl_wrappers.h"
> @@ -850,6 +851,16 @@ igt_render_copyfunc_t
> igt_get_render_copyfunc(int devid)
> return copy;
> }
>
> +igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid)
> +{
> + igt_vebox_copyfunc_t copy = NULL;
> +
> + if (IS_GEN12(devid))
> + copy = gen12_vebox_copyfunc;
> +
> + return copy;
> +}
> +
> /**
> * igt_get_media_fillfunc:
> * @devid: pci device id
> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
> index 888188f9..37e3affe 100644
> --- a/lib/intel_batchbuffer.h
> +++ b/lib/intel_batchbuffer.h
> @@ -213,6 +213,7 @@ void intel_copy_bo(struct intel_batchbuffer
> *batch,
> enum i915_compression {
> I915_COMPRESSION_NONE,
> I915_COMPRESSION_RENDER,
> + I915_COMPRESSION_MEDIA,
> };
>
> /**
> @@ -220,18 +221,20 @@ enum i915_compression {
> * @bo: underlying libdrm buffer object
> * @stride: stride of the buffer
> * @tiling: tiling mode bits
> + * @compression: memory compression mode
> * @bpp: bits per pixel, 8, 16 or 32.
> * @data: pointer to the memory mapping of the buffer
> * @size: size of the buffer object
> *
> * This is a i-g-t buffer object wrapper structure which augments
> the baseline
> - * libdrm buffer object with suitable data needed by the render copy
> and the
> - * fill functions.
> + * libdrm buffer object with suitable data needed by the
> render/vebox copy and
> + * the fill functions.
> */
> struct igt_buf {
> drm_intel_bo *bo;
> uint32_t stride;
> uint32_t tiling;
> + enum i915_compression compression;
> uint32_t bpp;
> uint32_t *data;
> uint32_t size;
> @@ -307,6 +310,29 @@ typedef void (*igt_render_copyfunc_t)(struct
> intel_batchbuffer *batch,
>
> igt_render_copyfunc_t igt_get_render_copyfunc(int devid);
>
> +
> +/**
> + * igt_vebox_copyfunc_t:
> + * @batch: batchbuffer object
> + * @src: source i-g-t buffer object
> + * @width: width of the copied rectangle
> + * @height: height of the copied rectangle
> + * @dst: destination i-g-t buffer object
> + *
> + * This is the type of the per-platform vebox copy functions. The
> + * platform-specific implementation can be obtained by calling
> + * igt_get_vebox_copyfunc().
> + *
> + * A vebox copy function will emit a batchbuffer to the kernel which
> executes
> + * the specified blit copy operation using the vebox engine.
> + */
> +typedef void (*igt_vebox_copyfunc_t)(struct intel_batchbuffer
> *batch,
> + const struct igt_buf *src,
> + unsigned width, unsigned height,
> + const struct igt_buf *dst);
> +
> +igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid);
> +
> /**
> * igt_fillfunc_t:
> * @batch: batchbuffer object
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h
> index cabfc879..0a9ee34c 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -674,6 +674,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> SOFTWARE.
> #define RING_INVALID 0x00000000
>
> #define GEN12_GFX_AUX_TABLE_BASE_ADDR 0x4200
> +#define GEN12_VEBOX_AUX_TABLE_BASE_ADDR 0x4230
>
>
> /* BitBlt Instructions
> diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
> index e80e22f1..7614e688 100644
> --- a/lib/ioctl_wrappers.h
> +++ b/lib/ioctl_wrappers.h
> @@ -202,6 +202,7 @@ struct local_drm_mode_fb_cmd2 {
> #define LOCAL_I915_FORMAT_MOD_Y_TILED_CCS local_fourcc_mod_code(I
> NTEL, 4)
> #define LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS local_fourcc_mod_code(I
> NTEL, 5)
> #define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
> fourcc_mod_code(INTEL, 6)
> +#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> fourcc_mod_code(INTEL, 7)
> #define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC
> fourcc_mod_code(INTEL, 8)
> #define LOCAL_DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8,
> \
> struct
> local_drm_mode_fb_cmd2)
> diff --git a/lib/meson.build b/lib/meson.build
> index 62d61654..57eb7d93 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -64,6 +64,7 @@ lib_sources = [
> 'igt_edid.c',
> 'igt_eld.c',
> 'igt_infoframe.c',
> + 'veboxcopy_gen12.c',
> ]
>
> lib_deps = [
> diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
> index 991a6393..bf9d2ee1 100644
> --- a/lib/rendercopy_gen9.c
> +++ b/lib/rendercopy_gen9.c
> @@ -1037,7 +1037,7 @@ void _gen9_render_copyfunc(struct
> intel_batchbuffer *batch,
> OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
> GEN9_PIPELINE_SELECTION_MASK);
>
> - gen12_emit_aux_pgtable_state(batch, aux_pgtable_state);
> + gen12_emit_aux_pgtable_state(batch, aux_pgtable_state, true);
>
> gen8_emit_sip(batch);
>
> diff --git a/lib/veboxcopy.h b/lib/veboxcopy.h
> new file mode 100644
> index 00000000..949d83bf
> --- /dev/null
> +++ b/lib/veboxcopy.h
> @@ -0,0 +1,9 @@
> +#ifndef __VEBOXCOPY_H__
> +#define __VEBOXCOPY_H__
> +
> +void gen12_vebox_copyfunc(struct intel_batchbuffer *batch,
> + const struct igt_buf *src,
> + unsigned width, unsigned height,
> + const struct igt_buf *dst);
> +
> +#endif
> diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c
> new file mode 100644
> index 00000000..87800941
> --- /dev/null
> +++ b/lib/veboxcopy_gen12.c
> @@ -0,0 +1,269 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person
> obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> the
> + * Software is furnished to do so, subject to the following
> conditions:
> + *
> + * The above copyright notice and this permission notice (including
> the next
> + * paragraph) shall be included in all copies or substantial
> portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES
> OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER DEALINGS
> + * IN THE SOFTWARE.
> + */
> +#include <drm.h>
> +
> +#include "igt.h"
> +#include "intel_aux_pgtable.h"
> +#include "veboxcopy.h"
> +
> +#define R8G8B8A8_UNORM 8
> +
> +struct vebox_surface_state {
> + struct {
> + uint32_t dw_count:12;
> + uint32_t pad:4;
> + uint32_t sub_opcode_b:5;
> + uint32_t sub_opcode_a:3;
> + uint32_t media_cmd_opcode:3;
> + uint32_t media_cmd_pipeline:2;
> + uint32_t cmd_type:3;
> + } ss0;
> + struct {
> +#define VEBOX_SURFACE_INPUT 0
> +#define VEBOX_SURFACE_OUTPUT 1
> + uint32_t surface_id:1;
> + uint32_t pad:31;
> + } ss1;
> + struct {
> + uint32_t pad:4;
> + uint32_t width:14;
> + uint32_t height:14;
> + } ss2;
> + struct {
> +#define VEBOX_TILE_WALK_XMAJOR 0
> +#define VEBOX_TILE_WALK_YMAJOR 1
> + uint32_t tile_walk:1;
> + uint32_t tiled_surface:1;
> + uint32_t chroma_half_pitch:1;
> + uint32_t surface_pitch:17;
> + uint32_t chroma_interleave:1;
> + uint32_t lsb_packed_enable:1;
> + uint32_t bayer_input_alignment:2;
> + uint32_t bayer_pattern_format:1;
> + uint32_t bayer_pattern_offset:2;
> + uint32_t surface_format:5;
> + } ss3;
> + struct {
> + uint32_t u_y_offset:15;
> + uint32_t u_x_offset:13;
> + uint32_t pad:4;
> + } ss4;
> + struct {
> + uint32_t v_y_offset:15;
> + uint32_t v_x_offset:13;
> + uint32_t pad:4;
> + } ss5;
> + struct {
> + uint32_t frame_y_offset:15;
> + uint32_t frame_x_offset:15;
> + uint32_t pad:2;
> + } ss6;
> + struct {
> + uint32_t derived_surface_pitch:17;
> + uint32_t pad:15;
> + } ss7;
> + struct {
> + uint32_t skin_score_output_surface_pitch:17;
> + uint32_t pad:15;
> + } ss8;
> +} __attribute__((packed));
> +
> +struct vebox_tiling_convert {
> + struct {
> + uint32_t dw_count:12;
> + uint32_t pad:4;
> + uint32_t sub_opcode_b:5;
> + uint32_t sub_opcode_a:3;
> + uint32_t cmd_opcode:3;
> + uint32_t pipeline:2;
> + uint32_t cmd_type:3;
> + } tc0;
> + union {
> + struct {
> + uint64_t input_encrypted_data:1;
> + uint64_t input_mocs_idx:6;
> + uint64_t input_memory_compression_enable:1;
> +#define COMPRESSION_TYPE_MEDIA 0
> +#define COMPRESSION_TYPE_RENDER 1
> + uint64_t input_compression_type:1;
> +#define TRMODE_NONE 0
> +#define TRMODE_TILE_YF 1
> +#define TRMODE_TILE_YS 2
> + uint64_t input_tiled_resource_mode:2;
> + uint64_t pad:1;
> + uint64_t input_address:52;
> + } tc1_2;
> + uint64_t tc1_2_l;
> + };
> + union {
> + struct {
> + uint64_t output_encrypted_data:1;
> + uint64_t output_mocs_idx:6;
> + uint64_t output_memory_compression_enable:1;
> + uint64_t output_compression_type:1;
> + uint64_t output_tiled_resource_mode:2;
> + uint64_t pad:1;
> + uint64_t output_address:52;
> + } tc3_4;
> + uint64_t tc3_4_l;
> + };
> +} __attribute__((packed));
> +
> +static void emit_surface_state_cmd(struct intel_batchbuffer *batch,
> + int surface_id,
> + int width, int height, int bpp,
> + int pitch, uint32_t tiling, int
> format)
> +{
> + struct vebox_surface_state *ss;
> +
> + ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 4);
> +
> + ss->ss0.cmd_type = 3;
> + ss->ss0.media_cmd_pipeline = 2;
> + ss->ss0.media_cmd_opcode = 4;
> + ss->ss0.dw_count = 7;
> +
> + ss->ss1.surface_id = surface_id;
> +
> + ss->ss2.height = height - 1;
> + ss->ss2.width = width - 1;
> +
> + ss->ss3.surface_format = format;
> + ss->ss3.surface_pitch = pitch - 1;
> + ss->ss3.tile_walk = (tiling == I915_TILING_Y) ||
> + (tiling == I915_TILING_Yf);
> + ss->ss3.tiled_surface = tiling != I915_TILING_NONE;
> +
> + ss->ss7.derived_surface_pitch = pitch - 1;
> +}
> +
> +static void emit_tiling_convert_cmd(struct intel_batchbuffer *batch,
> + drm_intel_bo *input_bo,
> + uint32_t input_tiling,
> + uint32_t input_compression,
> + drm_intel_bo *output_bo,
> + uint32_t output_tiling,
> + uint32_t output_compression)
> +{
> + uint32_t reloc_delta;
> + struct vebox_tiling_convert *tc;
> + int ret;
> +
> + tc = intel_batchbuffer_subdata_alloc(batch, sizeof(*tc), 8);
> +
> + tc->tc0.cmd_type = 3;
> + tc->tc0.pipeline = 2;
> + tc->tc0.cmd_opcode = 4;
> + tc->tc0.sub_opcode_b = 1;
> +
> + tc->tc0.dw_count = 3;
> +
> + if (input_compression != I915_COMPRESSION_NONE) {
> + tc->tc1_2.input_memory_compression_enable = 1;
> + tc->tc1_2.input_compression_type =
> + input_compression == I915_COMPRESSION_RENDER;
> + }
> + tc->tc1_2.input_tiled_resource_mode = input_tiling ==
> I915_TILING_Yf;
> + reloc_delta = tc->tc1_2_l;
> +
> + igt_assert(input_bo->offset64 == ALIGN(input_bo->offset64,
> 0x1000));
> + tc->tc1_2.input_address = input_bo->offset64 >> 12;
> + igt_assert(reloc_delta <= INT32_MAX);
> + ret = drm_intel_bo_emit_reloc(batch->bo,
> + intel_batchbuffer_subdata_offset(
> batch, tc) +
> + offsetof(typeof(*tc), tc1_2),
> + input_bo, reloc_delta,
> + 0, 0);
> + igt_assert(ret == 0);
> +
> + if (output_compression != I915_COMPRESSION_NONE) {
> + tc->tc3_4.output_memory_compression_enable = 1;
> + tc->tc3_4.output_compression_type =
> + output_compression == I915_COMPRESSION_RENDER;
> + }
> + tc->tc3_4.output_tiled_resource_mode = output_tiling ==
> I915_TILING_Yf;
> + reloc_delta = tc->tc3_4_l;
> +
> + igt_assert(output_bo->offset64 == ALIGN(output_bo->offset64,
> 0x1000));
> + tc->tc3_4.output_address = output_bo->offset64 >> 12;
> + igt_assert(reloc_delta <= INT32_MAX);
> + ret = drm_intel_bo_emit_reloc(batch->bo,
> + intel_batchbuffer_subdata_offset(
> batch, tc) +
> + offsetof(typeof(*tc), tc3_4),
> + output_bo, reloc_delta,
> + 0, I915_GEM_DOMAIN_RENDER);
> + igt_assert(ret == 0);
> +
> +}
> +
> +/* Borrowing the idea from the rendercopy state setup. */
> +#define BATCH_STATE_SPLIT 2048
> +
> +void gen12_vebox_copyfunc(struct intel_batchbuffer *batch,
> + const struct igt_buf *src,
> + unsigned width, unsigned height,
> + const struct igt_buf *dst)
> +{
> + struct aux_pgtable_info aux_pgtable_info = { };
> + uint32_t aux_pgtable_state;
> +
> + igt_assert(src->bpp == dst->bpp);
> +
> + intel_batchbuffer_flush_on_ring(batch, I915_EXEC_VEBOX);
> +
> + intel_batchbuffer_align(batch, 8);
> +
> + batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
> +
> + gen12_aux_pgtable_init(&aux_pgtable_info, batch->bufmgr, src,
> dst);
> +
> + aux_pgtable_state = gen12_create_aux_pgtable_state(batch,
> + aux_pgtable_
> info.pgtable_bo);
> +
> + assert(batch->ptr < &batch->buffer[4095]);
> + batch->ptr = batch->buffer;
> +
> + gen12_emit_aux_pgtable_state(batch, aux_pgtable_state, false);
> +
> + /* TODO: add support for more formats */
> + igt_assert(src->bpp == 32);
> + emit_surface_state_cmd(batch, VEBOX_SURFACE_INPUT,
> + width, height, src->bpp, src->stride,
> + src->tiling, R8G8B8A8_UNORM);
> +
> + igt_assert(dst->bpp == 32);
> + emit_surface_state_cmd(batch, VEBOX_SURFACE_OUTPUT,
> + width, height, dst->bpp, dst->stride,
> + dst->tiling, R8G8B8A8_UNORM);
> +
> + emit_tiling_convert_cmd(batch,
> + src->bo, src->tiling, src->compression,
> + dst->bo, dst->tiling, dst-
> >compression);
> +
> + OUT_BATCH(MI_BATCH_BUFFER_END);
> +
> + intel_batchbuffer_flush_on_ring(batch, I915_EXEC_VEBOX);
> +
> + gen12_aux_pgtable_cleanup(&aux_pgtable_info);
> + intel_batchbuffer_reset(batch);
> +}
> diff --git a/tests/i915/gem_render_copy.c
> b/tests/i915/gem_render_copy.c
> index 15ba1704..9c36f38b 100644
> --- a/tests/i915/gem_render_copy.c
> +++ b/tests/i915/gem_render_copy.c
> @@ -471,6 +471,7 @@ static void scratch_buf_init(data_t *data, struct
> igt_buf *buf,
> aux_width = scratch_buf_aux_width(data->devid, buf);
> aux_height = scratch_buf_aux_height(data->devid, buf);
>
> + buf->compression = compression;
> buf->aux.offset = buf->stride * ALIGN(height, 32);
> buf->aux.stride = aux_width;
>
_______________________________________________
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 5/6] lib: Add vebox copy support
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 5/6] lib: Add vebox copy support Imre Deak
2019-12-04 13:09 ` Kahola, Mika
2019-12-04 13:49 ` [igt-dev] [PATCH v2 " Imre Deak
@ 2019-12-05 3:30 ` Bai, Guangyao
2019-12-05 13:49 ` Imre Deak
2 siblings, 1 reply; 25+ messages in thread
From: Bai, Guangyao @ 2019-12-05 3:30 UTC (permalink / raw)
To: Deak, Imre, igt-dev; +Cc: Welty, Brian
> -----Original Message-----
> From: igt-dev [mailto:igt-dev-bounces@lists.freedesktop.org] On Behalf Of
> Deak, Imre
> Sent: Friday, November 29, 2019 6:39 PM
> To: igt-dev@lists.freedesktop.org
> Cc: Welty, Brian <brian.welty@intel.com>
> Subject: [igt-dev] [PATCH i-g-t 5/6] lib: Add vebox copy support
>
> To produce surfaces that are compressed using the media compression format
> we need to use one of the media engines. The simplest way for this is to use the
> vebox engine's tiling convert command, so add support for this.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> lib/Makefile.sources | 1 +
> lib/igt_fb.c | 74 +++++++---
> lib/intel_aux_pgtable.c | 10 +-
> lib/intel_aux_pgtable.h | 3 +-
> lib/intel_batchbuffer.c | 11 ++
> lib/intel_batchbuffer.h | 30 +++-
> lib/intel_reg.h | 1 +
> lib/ioctl_wrappers.h | 1 +
> lib/meson.build | 1 +
> lib/rendercopy_gen9.c | 2 +-
> lib/veboxcopy.h | 9 ++
> lib/veboxcopy_gen12.c | 269 +++++++++++++++++++++++++++++++++++
> tests/i915/gem_render_copy.c | 1 +
> 13 files changed, 387 insertions(+), 26 deletions(-) create mode 100644
> lib/veboxcopy.h create mode 100644 lib/veboxcopy_gen12.c
>
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources index
> 9d1a4e06..0efaea1b 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -129,6 +129,7 @@ lib_source_list = \
> igt_vc4.h \
> igt_amd.c \
> igt_amd.h \
> + veboxcopy_gen12.c \
> $(NULL)
>
> .PHONY: version.h.tmp
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c index 1d1e0d22..3bb4e5a1 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -402,6 +402,7 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int
> fb_bpp,
> case LOCAL_I915_FORMAT_MOD_Y_TILED:
> case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
> case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> igt_require_intel(fd);
> if (intel_gen(intel_get_drm_devid(fd)) == 2) {
> *width_ret = 128;
> @@ -466,14 +467,19 @@ void igt_get_fb_tile_size(int fd, uint64_t modifier, int
> fb_bpp,
> }
> }
>
> +static bool is_gen12_mc_ccs_modifier(uint64_t modifier) {
> + return modifier ==
> LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
> +}
> +
> static bool is_gen12_ccs_modifier(uint64_t modifier) {
> - return modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> + return is_gen12_mc_ccs_modifier(modifier) ||
> + modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> }
>
> static bool is_ccs_modifier(uint64_t modifier) {
> -
> return is_gen12_ccs_modifier(modifier) ||
> modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> modifier == I915_FORMAT_MOD_Yf_TILED_CCS; @@ -719,6
> +725,7 @@ uint64_t igt_fb_mod_to_tiling(uint64_t modifier)
> case LOCAL_I915_FORMAT_MOD_Y_TILED:
> case LOCAL_I915_FORMAT_MOD_Y_TILED_CCS:
> case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
> + case LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
> return I915_TILING_Y;
> case LOCAL_I915_FORMAT_MOD_Yf_TILED:
> case LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS:
> @@ -1897,7 +1904,7 @@ static bool blitter_ok(const struct igt_fb *fb)
> return true;
> }
>
> -static bool use_rendercopy(const struct igt_fb *fb)
> +static bool use_enginecopy(const struct igt_fb *fb)
> {
> return is_ccs_modifier(fb->modifier) ||
> (fb->modifier == I915_FORMAT_MOD_Yf_TILED && @@ -
> 1943,25 +1950,52 @@ static void fini_buf(struct igt_buf *buf)
> drm_intel_bo_unreference(buf->bo);
> }
>
> -static void rendercopy(struct fb_blit_upload *blit,
> - const struct igt_fb *dst_fb,
> - const struct igt_fb *src_fb)
> +/**
> + * copy_with_engine:
> + * @blit: context for the copy operation
> + * @dst_fb: destination buffer
> + * @src_fb: source buffer
> + *
> + * Copy @src_fb to @dst_fb using either the render or vebox engine. The
> +engine
> + * is selected based on the compression surface format required by the
> +@dst_fb
> + * FB modifier. On GEN12+ a given compression format (render or media)
> +can be
> + * produced only by the selected engine:
> + * - For GEN12 media compressed: vebox engine
> + * - For uncompressed, pre-GEN12 compressed, GEN12+ render compressed:
> +render engine
> + * Note that both GEN12 engine is capable of reading either compression
> formats.
> + */
> +static void copy_with_engine(struct fb_blit_upload *blit,
> + const struct igt_fb *dst_fb,
> + const struct igt_fb *src_fb)
> {
> struct igt_buf src = {}, dst = {};
> - igt_render_copyfunc_t render_copy =
> - igt_get_render_copyfunc(intel_get_drm_devid(blit->fd));
> + igt_render_copyfunc_t render_copy = NULL;
> + igt_vebox_copyfunc_t vebox_copy = NULL;
> +
> + if (is_gen12_mc_ccs_modifier(dst_fb->modifier))
> + vebox_copy =
> igt_get_vebox_copyfunc(intel_get_drm_devid(blit->fd));
> + else
> + render_copy =
> igt_get_render_copyfunc(intel_get_drm_devid(blit->fd));
>
> - igt_require(render_copy);
> + igt_require(vebox_copy || render_copy);
>
> igt_assert_eq(dst_fb->offsets[0], 0);
> igt_assert_eq(src_fb->offsets[0], 0);
>
> - init_buf(blit, &src, src_fb, "cairo rendercopy src");
> - init_buf(blit, &dst, dst_fb, "cairo rendercopy dst");
> + init_buf(blit, &src, src_fb, "cairo enginecopy src");
> + init_buf(blit, &dst, dst_fb, "cairo enginecopy dst");
>
> - render_copy(blit->batch, NULL,
> - &src, 0, 0, dst_fb->plane_width[0], dst_fb->plane_height[0],
> - &dst, 0, 0);
> + if (vebox_copy)
> + vebox_copy(blit->batch, &src,
> + dst_fb->plane_width[0], dst_fb->plane_height[0],
> + &dst);
> + else
> + render_copy(blit->batch, NULL,
> + &src,
> + 0, 0,
> + dst_fb->plane_width[0], dst_fb->plane_height[0],
> + &dst,
> + 0, 0);
>
> fini_buf(&dst);
> fini_buf(&src);
> @@ -2012,7 +2046,7 @@ static void free_linear_mapping(struct
> fb_blit_upload *blit)
> I915_GEM_DOMAIN_GTT, 0);
>
> if (blit->batch)
> - rendercopy(blit, fb, &linear->fb);
> + copy_with_engine(blit, fb, &linear->fb);
> else
> blitcopy(fb, &linear->fb);
>
> @@ -2043,7 +2077,7 @@ static void setup_linear_mapping(struct
> fb_blit_upload *blit)
> struct igt_fb *fb = blit->fb;
> struct fb_blit_linear *linear = &blit->linear;
>
> - if (!igt_vc4_is_tiled(fb->modifier) && use_rendercopy(fb)) {
> + if (!igt_vc4_is_tiled(fb->modifier) && use_enginecopy(fb)) {
> blit->bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
> blit->batch = intel_batchbuffer_alloc(blit->bufmgr,
> intel_get_drm_devid(fd));
> @@ -2079,7 +2113,7 @@ static void setup_linear_mapping(struct
> fb_blit_upload *blit)
> I915_GEM_DOMAIN_GTT, 0);
>
> if (blit->batch)
> - rendercopy(blit, &linear->fb, fb);
> + copy_with_engine(blit, &linear->fb, fb);
> else
> blitcopy(&linear->fb, fb);
>
> @@ -3185,7 +3219,8 @@ static void create_cairo_surface__convert(int fd,
> struct igt_fb *fb)
> &blit->shadow_fb);
> igt_assert(blit->shadow_ptr);
>
> - if (use_rendercopy(fb) || use_blitter(fb) || igt_vc4_is_tiled(fb-
> >modifier)) {
> + if (use_enginecopy(fb) || use_blitter(fb) ||
> + igt_vc4_is_tiled(fb->modifier)) {
> setup_linear_mapping(&blit->base);
> } else {
> blit->base.linear.fb = *fb;
> @@ -3268,7 +3303,8 @@ cairo_surface_t *igt_get_cairo_surface(int fd, struct
> igt_fb *fb)
> if (fb->cairo_surface == NULL) {
> if (use_convert(fb))
> create_cairo_surface__convert(fd, fb);
> - else if (use_blitter(fb) || use_rendercopy(fb) ||
> igt_vc4_is_tiled(fb->modifier))
> + else if (use_blitter(fb) || use_enginecopy(fb) ||
> + igt_vc4_is_tiled(fb->modifier))
> create_cairo_surface__gpu(fd, fb);
> else
> create_cairo_surface__gtt(fd, fb);
> diff --git a/lib/intel_aux_pgtable.c b/lib/intel_aux_pgtable.c index
> 2f22bb39..cbb3c320 100644
> --- a/lib/intel_aux_pgtable.c
> +++ b/lib/intel_aux_pgtable.c
> @@ -555,16 +555,20 @@ gen12_create_aux_pgtable_state(struct
> intel_batchbuffer *batch, }
>
> void
> -gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state)
> +gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state,
> + bool render)
> {
> + uint32_t table_base_reg = render ?
> GEN12_GFX_AUX_TABLE_BASE_ADDR :
> +
> GEN12_VEBOX_AUX_TABLE_BASE_ADDR;
> +
> if (!state)
> return;
>
> OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 |
> MI_MMIO_REMAP_ENABLE_GEN12);
> - OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR);
> + OUT_BATCH(table_base_reg);
> OUT_RELOC(batch->bo, 0, 0, state);
>
> OUT_BATCH(MI_LOAD_REGISTER_MEM_GEN8 |
> MI_MMIO_REMAP_ENABLE_GEN12);
> - OUT_BATCH(GEN12_GFX_AUX_TABLE_BASE_ADDR + 4);
> + OUT_BATCH(table_base_reg + 4);
> OUT_RELOC(batch->bo, 0, 0, state + 4); } diff --git
> a/lib/intel_aux_pgtable.h b/lib/intel_aux_pgtable.h index 20278db0..ac82b7d2
> 100644
> --- a/lib/intel_aux_pgtable.h
> +++ b/lib/intel_aux_pgtable.h
> @@ -30,6 +30,7 @@ uint32_t
> gen12_create_aux_pgtable_state(struct intel_batchbuffer *batch,
> drm_intel_bo *aux_pgtable_bo); void -
> gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state);
> +gen12_emit_aux_pgtable_state(struct intel_batchbuffer *batch, uint32_t state,
> + bool render);
>
> #endif
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c index
> 3828ba75..51aae4dc 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -37,6 +37,7 @@
> #include "intel_bufmgr.h"
> #include "intel_chipset.h"
> #include "intel_reg.h"
> +#include "veboxcopy.h"
> #include "rendercopy.h"
> #include "media_fill.h"
> #include "ioctl_wrappers.h"
> @@ -850,6 +851,16 @@ igt_render_copyfunc_t igt_get_render_copyfunc(int
> devid)
> return copy;
> }
>
> +igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid) {
> + igt_vebox_copyfunc_t copy = NULL;
> +
> + if (IS_GEN12(devid))
> + copy = gen12_vebox_copyfunc;
> +
> + return copy;
> +}
> +
> /**
> * igt_get_media_fillfunc:
> * @devid: pci device id
> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h index
> 402e68bc..e05e464b 100644
> --- a/lib/intel_batchbuffer.h
> +++ b/lib/intel_batchbuffer.h
> @@ -213,6 +213,7 @@ void intel_copy_bo(struct intel_batchbuffer *batch,
> enum i915_compression {
> I915_COMPRESSION_NONE,
> I915_COMPRESSION_RENDER,
> + I915_COMPRESSION_MEDIA,
> };
>
> /**
> @@ -220,18 +221,20 @@ enum i915_compression {
> * @bo: underlying libdrm buffer object
> * @stride: stride of the buffer
> * @tiling: tiling mode bits
> + * @compression: memory compression mode
> * @bpp: bits per pixel, 8, 16 or 32.
> * @data: pointer to the memory mapping of the buffer
> * @size: size of the buffer object
> *
> * This is a i-g-t buffer object wrapper structure which augments the baseline
> - * libdrm buffer object with suitable data needed by the render copy and the
> - * fill functions.
> + * libdrm buffer object with suitable data needed by the render/vebox
> + copy and
> + * the fill functions.
> */
> struct igt_buf {
> drm_intel_bo *bo;
> uint32_t stride;
> uint32_t tiling;
> + enum i915_compression compression;
> uint32_t bpp;
> uint32_t *data;
> uint32_t size;
> @@ -304,6 +307,29 @@ typedef void (*igt_render_copyfunc_t)(struct
> intel_batchbuffer *batch,
>
> igt_render_copyfunc_t igt_get_render_copyfunc(int devid);
>
> +
> +/**
> + * igt_vebox_copyfunc_t:
> + * @batch: batchbuffer object
> + * @src: source i-g-t buffer object
> + * @width: width of the copied rectangle
> + * @height: height of the copied rectangle
> + * @dst: destination i-g-t buffer object
> + *
> + * This is the type of the per-platform vebox copy functions. The
> + * platform-specific implementation can be obtained by calling
> + * igt_get_vebox_copyfunc().
> + *
> + * A vebox copy function will emit a batchbuffer to the kernel which
> +executes
> + * the specified blit copy operation using the vebox engine.
> + */
> +typedef void (*igt_vebox_copyfunc_t)(struct intel_batchbuffer *batch,
> + const struct igt_buf *src,
> + unsigned width, unsigned height,
> + const struct igt_buf *dst);
> +
> +igt_vebox_copyfunc_t igt_get_vebox_copyfunc(int devid);
> +
> /**
> * igt_fillfunc_t:
> * @batch: batchbuffer object
> diff --git a/lib/intel_reg.h b/lib/intel_reg.h index cabfc879..0a9ee34c 100644
> --- a/lib/intel_reg.h
> +++ b/lib/intel_reg.h
> @@ -674,6 +674,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> SOFTWARE.
> #define RING_INVALID 0x00000000
>
> #define GEN12_GFX_AUX_TABLE_BASE_ADDR 0x4200
> +#define GEN12_VEBOX_AUX_TABLE_BASE_ADDR 0x4230
>
>
> /* BitBlt Instructions
> diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h index
> f2412d78..7dd2a1e8 100644
> --- a/lib/ioctl_wrappers.h
> +++ b/lib/ioctl_wrappers.h
> @@ -201,6 +201,7 @@ struct local_drm_mode_fb_cmd2 {
> #define LOCAL_I915_FORMAT_MOD_Y_TILED_CCS
> local_fourcc_mod_code(INTEL, 4)
> #define LOCAL_I915_FORMAT_MOD_Yf_TILED_CCS
> local_fourcc_mod_code(INTEL, 5)
> #define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS
> fourcc_mod_code(INTEL, 6)
> +#define LOCAL_I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS
> +fourcc_mod_code(INTEL, 7)
>
> #define LOCAL_DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, \
> struct
> local_drm_mode_fb_cmd2)
> diff --git a/lib/meson.build b/lib/meson.build index 3f908912..f7fce905 100644
> --- a/lib/meson.build
> +++ b/lib/meson.build
> @@ -63,6 +63,7 @@ lib_sources = [
> 'igt_edid.c',
> 'igt_eld.c',
> 'igt_infoframe.c',
> + 'veboxcopy_gen12.c',
> ]
>
> lib_deps = [
> diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c index
> 94e816b6..e7fdd7a6 100644
> --- a/lib/rendercopy_gen9.c
> +++ b/lib/rendercopy_gen9.c
> @@ -1026,7 +1026,7 @@ void _gen9_render_copyfunc(struct
> intel_batchbuffer *batch,
> OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
> GEN9_PIPELINE_SELECTION_MASK);
>
> - gen12_emit_aux_pgtable_state(batch, aux_pgtable_state);
> + gen12_emit_aux_pgtable_state(batch, aux_pgtable_state, true);
>
> gen8_emit_sip(batch);
>
> diff --git a/lib/veboxcopy.h b/lib/veboxcopy.h new file mode 100644 index
> 00000000..949d83bf
> --- /dev/null
> +++ b/lib/veboxcopy.h
> @@ -0,0 +1,9 @@
> +#ifndef __VEBOXCOPY_H__
> +#define __VEBOXCOPY_H__
> +
> +void gen12_vebox_copyfunc(struct intel_batchbuffer *batch,
> + const struct igt_buf *src,
> + unsigned width, unsigned height,
> + const struct igt_buf *dst);
> +
> +#endif
> diff --git a/lib/veboxcopy_gen12.c b/lib/veboxcopy_gen12.c new file mode
> 100644 index 00000000..87800941
> --- /dev/null
> +++ b/lib/veboxcopy_gen12.c
> @@ -0,0 +1,269 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person
> +obtaining a
> + * copy of this software and associated documentation files (the
> +"Software"),
> + * to deal in the Software without restriction, including without
> +limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> +sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> +the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the
> +next
> + * paragraph) shall be included in all copies or substantial portions
> +of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> +EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> +MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT
> +SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES OR
> +OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> +ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> OTHER
> +DEALINGS
> + * IN THE SOFTWARE.
> + */
> +#include <drm.h>
> +
> +#include "igt.h"
> +#include "intel_aux_pgtable.h"
> +#include "veboxcopy.h"
> +
> +#define R8G8B8A8_UNORM 8
> +
> +struct vebox_surface_state {
> + struct {
> + uint32_t dw_count:12;
> + uint32_t pad:4;
> + uint32_t sub_opcode_b:5;
> + uint32_t sub_opcode_a:3;
> + uint32_t media_cmd_opcode:3;
> + uint32_t media_cmd_pipeline:2;
> + uint32_t cmd_type:3;
> + } ss0;
> + struct {
> +#define VEBOX_SURFACE_INPUT 0
> +#define VEBOX_SURFACE_OUTPUT 1
> + uint32_t surface_id:1;
> + uint32_t pad:31;
> + } ss1;
> + struct {
> + uint32_t pad:4;
> + uint32_t width:14;
> + uint32_t height:14;
> + } ss2;
> + struct {
> +#define VEBOX_TILE_WALK_XMAJOR 0
> +#define VEBOX_TILE_WALK_YMAJOR 1
> + uint32_t tile_walk:1;
> + uint32_t tiled_surface:1;
> + uint32_t chroma_half_pitch:1;
> + uint32_t surface_pitch:17;
> + uint32_t chroma_interleave:1;
> + uint32_t lsb_packed_enable:1;
> + uint32_t bayer_input_alignment:2;
> + uint32_t bayer_pattern_format:1;
> + uint32_t bayer_pattern_offset:2;
> + uint32_t surface_format:5;
> + } ss3;
> + struct {
> + uint32_t u_y_offset:15;
> + uint32_t u_x_offset:13;
> + uint32_t pad:4;
> + } ss4;
> + struct {
> + uint32_t v_y_offset:15;
> + uint32_t v_x_offset:13;
> + uint32_t pad:4;
> + } ss5;
> + struct {
> + uint32_t frame_y_offset:15;
> + uint32_t frame_x_offset:15;
> + uint32_t pad:2;
> + } ss6;
> + struct {
> + uint32_t derived_surface_pitch:17;
> + uint32_t pad:15;
> + } ss7;
> + struct {
> + uint32_t skin_score_output_surface_pitch:17;
> + uint32_t pad:15;
> + } ss8;
> +} __attribute__((packed));
> +
> +struct vebox_tiling_convert {
> + struct {
> + uint32_t dw_count:12;
> + uint32_t pad:4;
> + uint32_t sub_opcode_b:5;
> + uint32_t sub_opcode_a:3;
> + uint32_t cmd_opcode:3;
> + uint32_t pipeline:2;
> + uint32_t cmd_type:3;
> + } tc0;
> + union {
> + struct {
> + uint64_t input_encrypted_data:1;
> + uint64_t input_mocs_idx:6;
> + uint64_t input_memory_compression_enable:1;
> +#define COMPRESSION_TYPE_MEDIA 0
> +#define COMPRESSION_TYPE_RENDER 1
> + uint64_t input_compression_type:1;
> +#define TRMODE_NONE 0
> +#define TRMODE_TILE_YF 1
> +#define TRMODE_TILE_YS 2
> + uint64_t input_tiled_resource_mode:2;
> + uint64_t pad:1;
> + uint64_t input_address:52;
> + } tc1_2;
> + uint64_t tc1_2_l;
> + };
> + union {
> + struct {
> + uint64_t output_encrypted_data:1;
> + uint64_t output_mocs_idx:6;
> + uint64_t output_memory_compression_enable:1;
> + uint64_t output_compression_type:1;
> + uint64_t output_tiled_resource_mode:2;
> + uint64_t pad:1;
> + uint64_t output_address:52;
> + } tc3_4;
> + uint64_t tc3_4_l;
> + };
> +} __attribute__((packed));
> +
> +static void emit_surface_state_cmd(struct intel_batchbuffer *batch,
> + int surface_id,
> + int width, int height, int bpp,
> + int pitch, uint32_t tiling, int format) {
> + struct vebox_surface_state *ss;
> +
> + ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 4);
> +
> + ss->ss0.cmd_type = 3;
> + ss->ss0.media_cmd_pipeline = 2;
> + ss->ss0.media_cmd_opcode = 4;
> + ss->ss0.dw_count = 7;
> +
> + ss->ss1.surface_id = surface_id;
> +
> + ss->ss2.height = height - 1;
> + ss->ss2.width = width - 1;
> +
> + ss->ss3.surface_format = format;
> + ss->ss3.surface_pitch = pitch - 1;
> + ss->ss3.tile_walk = (tiling == I915_TILING_Y) ||
> + (tiling == I915_TILING_Yf);
> + ss->ss3.tiled_surface = tiling != I915_TILING_NONE;
> +
> + ss->ss7.derived_surface_pitch = pitch - 1; }
> +
> +static void emit_tiling_convert_cmd(struct intel_batchbuffer *batch,
> + drm_intel_bo *input_bo,
> + uint32_t input_tiling,
> + uint32_t input_compression,
> + drm_intel_bo *output_bo,
> + uint32_t output_tiling,
> + uint32_t output_compression)
> +{
> + uint32_t reloc_delta;
> + struct vebox_tiling_convert *tc;
> + int ret;
> +
> + tc = intel_batchbuffer_subdata_alloc(batch, sizeof(*tc), 8);
> +
> + tc->tc0.cmd_type = 3;
> + tc->tc0.pipeline = 2;
> + tc->tc0.cmd_opcode = 4;
> + tc->tc0.sub_opcode_b = 1;
> +
> + tc->tc0.dw_count = 3;
> +
> + if (input_compression != I915_COMPRESSION_NONE) {
> + tc->tc1_2.input_memory_compression_enable = 1;
> + tc->tc1_2.input_compression_type =
> + input_compression == I915_COMPRESSION_RENDER;
> + }
> + tc->tc1_2.input_tiled_resource_mode = input_tiling == I915_TILING_Yf;
> + reloc_delta = tc->tc1_2_l;
> +
> + igt_assert(input_bo->offset64 == ALIGN(input_bo->offset64, 0x1000));
> + tc->tc1_2.input_address = input_bo->offset64 >> 12;
> + igt_assert(reloc_delta <= INT32_MAX);
> + ret = drm_intel_bo_emit_reloc(batch->bo,
> + intel_batchbuffer_subdata_offset(batch, tc)
> +
> + offsetof(typeof(*tc), tc1_2),
> + input_bo, reloc_delta,
> + 0, 0);
> + igt_assert(ret == 0);
> +
> + if (output_compression != I915_COMPRESSION_NONE) {
> + tc->tc3_4.output_memory_compression_enable = 1;
> + tc->tc3_4.output_compression_type =
> + output_compression == I915_COMPRESSION_RENDER;
> + }
> + tc->tc3_4.output_tiled_resource_mode = output_tiling ==
> I915_TILING_Yf;
> + reloc_delta = tc->tc3_4_l;
> +
> + igt_assert(output_bo->offset64 == ALIGN(output_bo->offset64,
> 0x1000));
The Offset64 you gona to align with 4K? and for the Aux mapping stride(unit), you are using 4K also? Pls check the mapping unit and VA define, it should be both 4K or 64K
> + tc->tc3_4.output_address = output_bo->offset64 >> 12;
> + igt_assert(reloc_delta <= INT32_MAX);
> + ret = drm_intel_bo_emit_reloc(batch->bo,
> + intel_batchbuffer_subdata_offset(batch, tc)
> +
> + offsetof(typeof(*tc), tc3_4),
> + output_bo, reloc_delta,
> + 0, I915_GEM_DOMAIN_RENDER);
> + igt_assert(ret == 0);
> +
> +}
> +
> +/* Borrowing the idea from the rendercopy state setup. */ #define
> +BATCH_STATE_SPLIT 2048
> +
> +void gen12_vebox_copyfunc(struct intel_batchbuffer *batch,
> + const struct igt_buf *src,
> + unsigned width, unsigned height,
> + const struct igt_buf *dst)
> +{
> + struct aux_pgtable_info aux_pgtable_info = { };
> + uint32_t aux_pgtable_state;
> +
> + igt_assert(src->bpp == dst->bpp);
> +
> + intel_batchbuffer_flush_on_ring(batch, I915_EXEC_VEBOX);
> +
> + intel_batchbuffer_align(batch, 8);
> +
> + batch->ptr = &batch->buffer[BATCH_STATE_SPLIT];
> +
> + gen12_aux_pgtable_init(&aux_pgtable_info, batch->bufmgr, src, dst);
> +
> + aux_pgtable_state = gen12_create_aux_pgtable_state(batch,
> +
> aux_pgtable_info.pgtable_bo);
> +
> + assert(batch->ptr < &batch->buffer[4095]);
> + batch->ptr = batch->buffer;
> +
> + gen12_emit_aux_pgtable_state(batch, aux_pgtable_state, false);
> +
> + /* TODO: add support for more formats */
> + igt_assert(src->bpp == 32);
> + emit_surface_state_cmd(batch, VEBOX_SURFACE_INPUT,
> + width, height, src->bpp, src->stride,
> + src->tiling, R8G8B8A8_UNORM);
> +
> + igt_assert(dst->bpp == 32);
> + emit_surface_state_cmd(batch, VEBOX_SURFACE_OUTPUT,
> + width, height, dst->bpp, dst->stride,
> + dst->tiling, R8G8B8A8_UNORM);
> +
> + emit_tiling_convert_cmd(batch,
> + src->bo, src->tiling, src->compression,
> + dst->bo, dst->tiling, dst->compression);
> +
> + OUT_BATCH(MI_BATCH_BUFFER_END);
> +
> + intel_batchbuffer_flush_on_ring(batch, I915_EXEC_VEBOX);
> +
> + gen12_aux_pgtable_cleanup(&aux_pgtable_info);
> + intel_batchbuffer_reset(batch);
> +}
> diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
> index 15ba1704..9c36f38b 100644
> --- a/tests/i915/gem_render_copy.c
> +++ b/tests/i915/gem_render_copy.c
> @@ -471,6 +471,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf
> *buf,
> aux_width = scratch_buf_aux_width(data->devid, buf);
> aux_height = scratch_buf_aux_height(data->devid, buf);
>
> + buf->compression = compression;
> buf->aux.offset = buf->stride * ALIGN(height, 32);
> buf->aux.stride = aux_width;
>
> --
> 2.17.1
>
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
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^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [igt-dev] [PATCH i-g-t 5/6] lib: Add vebox copy support
2019-12-05 3:30 ` [igt-dev] [PATCH i-g-t " Bai, Guangyao
@ 2019-12-05 13:49 ` Imre Deak
0 siblings, 0 replies; 25+ messages in thread
From: Imre Deak @ 2019-12-05 13:49 UTC (permalink / raw)
To: Bai, Guangyao; +Cc: igt-dev, Welty, Brian
Hi Guangyao,
On Thu, Dec 05, 2019 at 05:30:49AM +0200, Bai, Guangyao wrote:
> > [...]
> > +
> > +static void emit_tiling_convert_cmd(struct intel_batchbuffer *batch,
> > + drm_intel_bo *input_bo,
> > + uint32_t input_tiling,
> > + uint32_t input_compression,
> > + drm_intel_bo *output_bo,
> > + uint32_t output_tiling,
> > + uint32_t output_compression)
> > +{
> > + uint32_t reloc_delta;
> > + struct vebox_tiling_convert *tc;
> > + int ret;
> > +
> > + tc = intel_batchbuffer_subdata_alloc(batch, sizeof(*tc), 8);
> > +
> > + tc->tc0.cmd_type = 3;
> > + tc->tc0.pipeline = 2;
> > + tc->tc0.cmd_opcode = 4;
> > + tc->tc0.sub_opcode_b = 1;
> > +
> > + tc->tc0.dw_count = 3;
> > +
> > + if (input_compression != I915_COMPRESSION_NONE) {
> > + tc->tc1_2.input_memory_compression_enable = 1;
> > + tc->tc1_2.input_compression_type =
> > + input_compression == I915_COMPRESSION_RENDER;
> > + }
> > + tc->tc1_2.input_tiled_resource_mode = input_tiling == I915_TILING_Yf;
> > + reloc_delta = tc->tc1_2_l;
> > +
> > + igt_assert(input_bo->offset64 == ALIGN(input_bo->offset64, 0x1000));
> > + tc->tc1_2.input_address = input_bo->offset64 >> 12;
> > + igt_assert(reloc_delta <= INT32_MAX);
> > + ret = drm_intel_bo_emit_reloc(batch->bo,
> > + intel_batchbuffer_subdata_offset(batch, tc)
> > +
> > + offsetof(typeof(*tc), tc1_2),
> > + input_bo, reloc_delta,
> > + 0, 0);
> > + igt_assert(ret == 0);
> > +
> > + if (output_compression != I915_COMPRESSION_NONE) {
> > + tc->tc3_4.output_memory_compression_enable = 1;
> > + tc->tc3_4.output_compression_type =
> > + output_compression == I915_COMPRESSION_RENDER;
> > + }
> > + tc->tc3_4.output_tiled_resource_mode = output_tiling == I915_TILING_Yf;
> > + reloc_delta = tc->tc3_4_l;
> > +
> > + igt_assert(output_bo->offset64 == ALIGN(output_bo->offset64, 0x1000));
>
> The Offset64 you gona to align with 4K?
This check here only makes sure that the main surface base address is
sufficiently aligned for the tiling convert command (which requires only
4K alignment).
The base address for main surfaces that are compressed (either render or
media) is already 64K aligned, see aux_pgtable_find_free_range().
> and for the Aux mapping stride(unit), you are using 4K also? Pls check
> the mapping unit and VA define, it should be both 4K or 64K
The main surface stride is aligned to 4 tiles. Since each tile is 32
pixels wide (for 32bpp formats), the main surface stride in bytes is
aligned to
4 tile * 32 pixel/tile * 4 byte/pixel = 512 byte
(or the tile row is aligned to 4 tile * 4kbyte/tile = 16kbyte).
This means the stride for the CCS AUX surface will be aligned to 64
bytes (as one cache line on the CCS AUX surface maps 4 tiles on the main
surface).
--Imre
>
> > + tc->tc3_4.output_address = output_bo->offset64 >> 12;
> > + igt_assert(reloc_delta <= INT32_MAX);
> > + ret = drm_intel_bo_emit_reloc(batch->bo,
> > + intel_batchbuffer_subdata_offset(batch, tc)
> > +
> > + offsetof(typeof(*tc), tc3_4),
> > + output_bo, reloc_delta,
> > + 0, I915_GEM_DOMAIN_RENDER);
> > + igt_assert(ret == 0);
> > +
> > +}
> > +
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread
* [igt-dev] [PATCH i-g-t 6/6] tests/gem_render_copy: Add media compression subtests
2019-11-29 10:38 [igt-dev] [PATCH i-g-t 0/6] lib: Add tests validating media compressed surfaces Imre Deak
` (4 preceding siblings ...)
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 5/6] lib: Add vebox copy support Imre Deak
@ 2019-11-29 10:38 ` Imre Deak
2019-12-04 13:50 ` [igt-dev] [PATCH v2 " Imre Deak
2019-11-29 11:19 ` [igt-dev] ✓ Fi.CI.BAT: success for lib: Add tests validating media compressed surfaces Patchwork
` (3 subsequent siblings)
9 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2019-11-29 10:38 UTC (permalink / raw)
To: igt-dev; +Cc: Brian Welty
Add subtests using the vebox copy function to test the blit
functionality involving media compressed source and destination buffers.
These cover all the source and destination tiling formats supported by
the vebox engine and validate the buffer sharing between the render and
vebox engine (a render compressed buffer used by the vebox engine and a
media compressed buffer used by the render engine).
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
lib/gen9_render.h | 44 ++++++++----
lib/rendercopy_gen9.c | 13 ++--
tests/i915/gem_render_copy.c | 127 ++++++++++++++++++++++++++++++++++-
3 files changed, 162 insertions(+), 22 deletions(-)
diff --git a/lib/gen9_render.h b/lib/gen9_render.h
index 9ee5782b..6fa2f32f 100644
--- a/lib/gen9_render.h
+++ b/lib/gen9_render.h
@@ -86,20 +86,36 @@ struct gen9_surface_state {
uint32_t pad1:1;
} ss6;
- struct {
- uint32_t resource_min_lod:12;
-
- /* Only on Haswell */
- uint32_t pad0:4;
- uint32_t shader_chanel_select_a:3;
- uint32_t shader_chanel_select_b:3;
- uint32_t shader_chanel_select_g:3;
- uint32_t shader_chanel_select_r:3;
-
- uint32_t alpha_clear_color:1;
- uint32_t blue_clear_color:1;
- uint32_t green_clear_color:1;
- uint32_t red_clear_color:1;
+ union {
+ struct {
+ uint32_t resource_min_lod:12;
+
+ /* Only on Haswell */
+ uint32_t pad0:4;
+ uint32_t shader_chanel_select_a:3;
+ uint32_t shader_chanel_select_b:3;
+ uint32_t shader_chanel_select_g:3;
+ uint32_t shader_chanel_select_r:3;
+
+ uint32_t alpha_clear_color:1;
+ uint32_t blue_clear_color:1;
+ uint32_t green_clear_color:1;
+ uint32_t red_clear_color:1;
+ } skl;
+ struct {
+ uint32_t resource_min_lod:12;
+
+ /* Only on Haswell */
+ uint32_t pad0:4;
+ uint32_t shader_chanel_select_a:3;
+ uint32_t shader_chanel_select_b:3;
+ uint32_t shader_chanel_select_g:3;
+ uint32_t shader_chanel_select_r:3;
+
+ uint32_t pad1:2;
+ uint32_t media_compression:1;
+ uint32_t pad2:1;
+ } tgl;
} ss7;
struct {
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index e7fdd7a6..807b6b3d 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -252,12 +252,12 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf,
ss->ss2.width = igt_buf_width(buf) - 1;
ss->ss3.pitch = buf->stride - 1;
- ss->ss7.shader_chanel_select_r = 4;
- ss->ss7.shader_chanel_select_g = 5;
- ss->ss7.shader_chanel_select_b = 6;
- ss->ss7.shader_chanel_select_a = 7;
+ ss->ss7.skl.shader_chanel_select_r = 4;
+ ss->ss7.skl.shader_chanel_select_g = 5;
+ ss->ss7.skl.shader_chanel_select_b = 6;
+ ss->ss7.skl.shader_chanel_select_a = 7;
- if (buf->aux.stride) {
+ if (buf->aux.stride && buf->compression != I915_COMPRESSION_MEDIA) {
ss->ss6.aux_mode = 0x5; /* AUX_CCS_E */
ss->ss6.aux_pitch = (buf->aux.stride / 128) - 1;
@@ -271,6 +271,9 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf,
assert(ret == 0);
}
+ if (buf->compression == I915_COMPRESSION_MEDIA)
+ ss->ss7.tgl.media_compression = 1;
+
return offset;
}
diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
index 9c36f38b..137c7c18 100644
--- a/tests/i915/gem_render_copy.c
+++ b/tests/i915/gem_render_copy.c
@@ -59,6 +59,7 @@ typedef struct {
drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
igt_render_copyfunc_t render_copy;
+ igt_vebox_copyfunc_t vebox_copy;
} data_t;
static int opt_dump_png = false;
static int check_all_pixels = false;
@@ -595,6 +596,7 @@ static void scratch_buf_aux_check(data_t *data,
}
#define SOURCE_MIXED_TILED 1
+#define FORCE_VEBOX_DST_COPY 2
static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
enum i915_compression src_compression,
@@ -634,6 +636,7 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
const bool src_mixed_tiled = flags & SOURCE_MIXED_TILED;
const bool src_compressed = src_compression != I915_COMPRESSION_NONE;
const bool dst_compressed = dst_compression != I915_COMPRESSION_NONE;
+ const bool force_vebox_dst_copy = flags & FORCE_VEBOX_DST_COPY;
/*
* The source tilings for mixed source tiling test cases are determined
@@ -641,6 +644,14 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
*/
igt_assert(src_tiling == I915_TILING_NONE || !src_mixed_tiled);
+ /*
+ * The vebox engine can produce only a media compressed or
+ * uncompressed surface.
+ */
+ igt_assert(!force_vebox_dst_copy ||
+ dst_compression == I915_COMPRESSION_MEDIA ||
+ dst_compression == I915_COMPRESSION_NONE);
+
/* no Yf before gen9 */
if (intel_gen(data->devid) < 9)
num_src--;
@@ -733,6 +744,10 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
&src_tiled, 0, 0, WIDTH, HEIGHT,
&src_ccs,
0, 0);
+ else if (src_compression == I915_COMPRESSION_MEDIA)
+ data->vebox_copy(data->batch,
+ &src_tiled, WIDTH, HEIGHT,
+ &src_ccs);
if (dst_compression == I915_COMPRESSION_RENDER) {
data->render_copy(data->batch, NULL,
@@ -746,6 +761,21 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
0, 0, WIDTH, HEIGHT,
&dst,
0, 0);
+ } else if (dst_compression == I915_COMPRESSION_MEDIA) {
+ data->vebox_copy(data->batch,
+ src_compressed ? &src_ccs : &src_tiled,
+ WIDTH, HEIGHT,
+ &dst_ccs);
+
+ data->vebox_copy(data->batch,
+ &dst_ccs,
+ WIDTH, HEIGHT,
+ &dst);
+ } else if (force_vebox_dst_copy) {
+ data->vebox_copy(data->batch,
+ src_compressed ? &src_ccs : &src_tiled,
+ WIDTH, HEIGHT,
+ &dst);
} else {
data->render_copy(data->batch, NULL,
src_compressed ? &src_ccs : &src_tiled,
@@ -854,6 +884,9 @@ static void buf_mode_to_str(uint32_t tiling, bool mixed_tiled,
case I915_COMPRESSION_RENDER:
compression_str = "ccs";
break;
+ case I915_COMPRESSION_MEDIA:
+ compression_str = "mc-ccs";
+ break;
default:
igt_assert(0);
}
@@ -929,6 +962,73 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
{ I915_TILING_Yf, I915_TILING_Y,
I915_COMPRESSION_RENDER, I915_COMPRESSION_RENDER,
0, },
+
+ { I915_TILING_NONE, I915_TILING_Yf,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_NONE, I915_TILING_Y,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+
+ { I915_TILING_X, I915_TILING_Yf,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_X, I915_TILING_Y,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+
+ { I915_TILING_Y, I915_TILING_NONE,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Y, I915_TILING_X,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Y, I915_TILING_Y,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Y, I915_TILING_Yf,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+
+ { I915_TILING_Yf, I915_TILING_NONE,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Yf, I915_TILING_X,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Yf, I915_TILING_Yf,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Yf, I915_TILING_Y,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+
+ { I915_TILING_Y, I915_TILING_Y,
+ I915_COMPRESSION_MEDIA, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Yf, I915_TILING_Yf,
+ I915_COMPRESSION_MEDIA, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Y, I915_TILING_Yf,
+ I915_COMPRESSION_MEDIA, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Yf, I915_TILING_Y,
+ I915_COMPRESSION_MEDIA, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+
+ { I915_TILING_Y, I915_TILING_Y,
+ I915_COMPRESSION_MEDIA, I915_COMPRESSION_RENDER,
+ 0, },
+ { I915_TILING_Y, I915_TILING_Yf,
+ I915_COMPRESSION_MEDIA, I915_COMPRESSION_RENDER,
+ 0, },
+
+ { I915_TILING_Y, I915_TILING_Y,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_MEDIA,
+ 0, },
+ { I915_TILING_Y, I915_TILING_Yf,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_MEDIA,
+ 0, },
};
int i;
@@ -946,6 +1046,8 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
igt_require_f(data.render_copy,
"no render-copy function\n");
+ data.vebox_copy = igt_get_vebox_copyfunc(data.devid);
+
data.batch = intel_batchbuffer_alloc(data.bufmgr, data.devid);
igt_assert(data.batch);
@@ -957,13 +1059,25 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
char src_mode[32];
char dst_mode[32];
const bool src_mixed_tiled = t->flags & SOURCE_MIXED_TILED;
+ const bool force_vebox_dst_copy = t->flags & FORCE_VEBOX_DST_COPY;
+ const bool vebox_copy_used =
+ t->src_compression == I915_COMPRESSION_MEDIA ||
+ t->dst_compression == I915_COMPRESSION_MEDIA ||
+ force_vebox_dst_copy;
+ const bool render_copy_used =
+ !vebox_copy_used ||
+ t->src_compression == I915_COMPRESSION_RENDER ||
+ t->dst_compression == I915_COMPRESSION_RENDER;
buf_mode_to_str(t->src_tiling, src_mixed_tiled,
t->src_compression, src_mode, sizeof(src_mode));
buf_mode_to_str(t->dst_tiling, false,
t->dst_compression, dst_mode, sizeof(dst_mode));
- igt_describe_f("Test render_copy() from a %s to a %s buffer.",
+ igt_describe_f("Test %s%s%s from a %s to a %s buffer.",
+ render_copy_used ? "render_copy()" : "",
+ render_copy_used && vebox_copy_used ? " and " : "",
+ vebox_copy_used ? "vebox_copy()" : "",
src_mode, dst_mode);
/* Preserve original test names */
@@ -971,12 +1085,19 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
t->dst_compression == I915_COMPRESSION_NONE)
src_mode[0] = '\0';
- igt_subtest_f("%s%s%s",
- src_mode, src_mode[0] ? "-to-" : "", dst_mode)
+ igt_subtest_f("%s%s%s%s",
+ src_mode,
+ src_mode[0] ? "-to-" : "",
+ force_vebox_dst_copy ? "vebox-" : "",
+ dst_mode) {
+ igt_require_f(data.vebox_copy || !vebox_copy_used,
+ "no vebox-copy function\n");
+
test(&data,
t->src_tiling, t->dst_tiling,
t->src_compression, t->dst_compression,
t->flags);
+ }
}
igt_fixture {
--
2.17.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 25+ messages in thread* [igt-dev] [PATCH v2 6/6] tests/gem_render_copy: Add media compression subtests
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 6/6] tests/gem_render_copy: Add media compression subtests Imre Deak
@ 2019-12-04 13:50 ` Imre Deak
2019-12-05 11:28 ` Kahola, Mika
0 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2019-12-04 13:50 UTC (permalink / raw)
To: igt-dev; +Cc: Brian Welty
Add subtests using the vebox copy function to test the blit
functionality involving media compressed source and destination buffers.
These cover all the source and destination tiling formats supported by
the vebox engine and validate the buffer sharing between the render and
vebox engine (a render compressed buffer used by the vebox engine and a
media compressed buffer used by the render engine).
v2:
- Rebase on latest igt.
Simplify the condition for enabling media compression in the surface
state.
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Brian Welty <brian.welty@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
lib/gen9_render.h | 44 ++++++++----
lib/rendercopy_gen9.c | 14 ++--
tests/i915/gem_render_copy.c | 127 ++++++++++++++++++++++++++++++++++-
3 files changed, 162 insertions(+), 23 deletions(-)
diff --git a/lib/gen9_render.h b/lib/gen9_render.h
index ab99563a..6274e902 100644
--- a/lib/gen9_render.h
+++ b/lib/gen9_render.h
@@ -86,20 +86,36 @@ struct gen9_surface_state {
uint32_t pad1:1;
} ss6;
- struct {
- uint32_t resource_min_lod:12;
-
- /* Only on Haswell */
- uint32_t pad0:4;
- uint32_t shader_chanel_select_a:3;
- uint32_t shader_chanel_select_b:3;
- uint32_t shader_chanel_select_g:3;
- uint32_t shader_chanel_select_r:3;
-
- uint32_t alpha_clear_color:1;
- uint32_t blue_clear_color:1;
- uint32_t green_clear_color:1;
- uint32_t red_clear_color:1;
+ union {
+ struct {
+ uint32_t resource_min_lod:12;
+
+ /* Only on Haswell */
+ uint32_t pad0:4;
+ uint32_t shader_chanel_select_a:3;
+ uint32_t shader_chanel_select_b:3;
+ uint32_t shader_chanel_select_g:3;
+ uint32_t shader_chanel_select_r:3;
+
+ uint32_t alpha_clear_color:1;
+ uint32_t blue_clear_color:1;
+ uint32_t green_clear_color:1;
+ uint32_t red_clear_color:1;
+ } skl;
+ struct {
+ uint32_t resource_min_lod:12;
+
+ /* Only on Haswell */
+ uint32_t pad0:4;
+ uint32_t shader_chanel_select_a:3;
+ uint32_t shader_chanel_select_b:3;
+ uint32_t shader_chanel_select_g:3;
+ uint32_t shader_chanel_select_r:3;
+
+ uint32_t pad1:2;
+ uint32_t media_compression:1;
+ uint32_t pad2:1;
+ } tgl;
} ss7;
struct {
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index bf9d2ee1..63b1023d 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -252,12 +252,14 @@ gen8_bind_buf(struct intel_batchbuffer *batch, const struct igt_buf *buf,
ss->ss2.width = igt_buf_width(buf) - 1;
ss->ss3.pitch = buf->stride - 1;
- ss->ss7.shader_chanel_select_r = 4;
- ss->ss7.shader_chanel_select_g = 5;
- ss->ss7.shader_chanel_select_b = 6;
- ss->ss7.shader_chanel_select_a = 7;
-
- if (buf->aux.stride) {
+ ss->ss7.skl.shader_chanel_select_r = 4;
+ ss->ss7.skl.shader_chanel_select_g = 5;
+ ss->ss7.skl.shader_chanel_select_b = 6;
+ ss->ss7.skl.shader_chanel_select_a = 7;
+
+ if (buf->compression == I915_COMPRESSION_MEDIA)
+ ss->ss7.tgl.media_compression = 1;
+ else if (buf->aux.stride) {
ss->ss6.aux_mode = 0x5; /* AUX_CCS_E */
ss->ss6.aux_pitch = (buf->aux.stride / 128) - 1;
diff --git a/tests/i915/gem_render_copy.c b/tests/i915/gem_render_copy.c
index 9c36f38b..137c7c18 100644
--- a/tests/i915/gem_render_copy.c
+++ b/tests/i915/gem_render_copy.c
@@ -59,6 +59,7 @@ typedef struct {
drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
igt_render_copyfunc_t render_copy;
+ igt_vebox_copyfunc_t vebox_copy;
} data_t;
static int opt_dump_png = false;
static int check_all_pixels = false;
@@ -595,6 +596,7 @@ static void scratch_buf_aux_check(data_t *data,
}
#define SOURCE_MIXED_TILED 1
+#define FORCE_VEBOX_DST_COPY 2
static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
enum i915_compression src_compression,
@@ -634,6 +636,7 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
const bool src_mixed_tiled = flags & SOURCE_MIXED_TILED;
const bool src_compressed = src_compression != I915_COMPRESSION_NONE;
const bool dst_compressed = dst_compression != I915_COMPRESSION_NONE;
+ const bool force_vebox_dst_copy = flags & FORCE_VEBOX_DST_COPY;
/*
* The source tilings for mixed source tiling test cases are determined
@@ -641,6 +644,14 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
*/
igt_assert(src_tiling == I915_TILING_NONE || !src_mixed_tiled);
+ /*
+ * The vebox engine can produce only a media compressed or
+ * uncompressed surface.
+ */
+ igt_assert(!force_vebox_dst_copy ||
+ dst_compression == I915_COMPRESSION_MEDIA ||
+ dst_compression == I915_COMPRESSION_NONE);
+
/* no Yf before gen9 */
if (intel_gen(data->devid) < 9)
num_src--;
@@ -733,6 +744,10 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
&src_tiled, 0, 0, WIDTH, HEIGHT,
&src_ccs,
0, 0);
+ else if (src_compression == I915_COMPRESSION_MEDIA)
+ data->vebox_copy(data->batch,
+ &src_tiled, WIDTH, HEIGHT,
+ &src_ccs);
if (dst_compression == I915_COMPRESSION_RENDER) {
data->render_copy(data->batch, NULL,
@@ -746,6 +761,21 @@ static void test(data_t *data, uint32_t src_tiling, uint32_t dst_tiling,
0, 0, WIDTH, HEIGHT,
&dst,
0, 0);
+ } else if (dst_compression == I915_COMPRESSION_MEDIA) {
+ data->vebox_copy(data->batch,
+ src_compressed ? &src_ccs : &src_tiled,
+ WIDTH, HEIGHT,
+ &dst_ccs);
+
+ data->vebox_copy(data->batch,
+ &dst_ccs,
+ WIDTH, HEIGHT,
+ &dst);
+ } else if (force_vebox_dst_copy) {
+ data->vebox_copy(data->batch,
+ src_compressed ? &src_ccs : &src_tiled,
+ WIDTH, HEIGHT,
+ &dst);
} else {
data->render_copy(data->batch, NULL,
src_compressed ? &src_ccs : &src_tiled,
@@ -854,6 +884,9 @@ static void buf_mode_to_str(uint32_t tiling, bool mixed_tiled,
case I915_COMPRESSION_RENDER:
compression_str = "ccs";
break;
+ case I915_COMPRESSION_MEDIA:
+ compression_str = "mc-ccs";
+ break;
default:
igt_assert(0);
}
@@ -929,6 +962,73 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
{ I915_TILING_Yf, I915_TILING_Y,
I915_COMPRESSION_RENDER, I915_COMPRESSION_RENDER,
0, },
+
+ { I915_TILING_NONE, I915_TILING_Yf,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_NONE, I915_TILING_Y,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+
+ { I915_TILING_X, I915_TILING_Yf,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_X, I915_TILING_Y,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+
+ { I915_TILING_Y, I915_TILING_NONE,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Y, I915_TILING_X,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Y, I915_TILING_Y,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Y, I915_TILING_Yf,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+
+ { I915_TILING_Yf, I915_TILING_NONE,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Yf, I915_TILING_X,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Yf, I915_TILING_Yf,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Yf, I915_TILING_Y,
+ I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+
+ { I915_TILING_Y, I915_TILING_Y,
+ I915_COMPRESSION_MEDIA, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Yf, I915_TILING_Yf,
+ I915_COMPRESSION_MEDIA, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Y, I915_TILING_Yf,
+ I915_COMPRESSION_MEDIA, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+ { I915_TILING_Yf, I915_TILING_Y,
+ I915_COMPRESSION_MEDIA, I915_COMPRESSION_NONE,
+ FORCE_VEBOX_DST_COPY, },
+
+ { I915_TILING_Y, I915_TILING_Y,
+ I915_COMPRESSION_MEDIA, I915_COMPRESSION_RENDER,
+ 0, },
+ { I915_TILING_Y, I915_TILING_Yf,
+ I915_COMPRESSION_MEDIA, I915_COMPRESSION_RENDER,
+ 0, },
+
+ { I915_TILING_Y, I915_TILING_Y,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_MEDIA,
+ 0, },
+ { I915_TILING_Y, I915_TILING_Yf,
+ I915_COMPRESSION_RENDER, I915_COMPRESSION_MEDIA,
+ 0, },
};
int i;
@@ -946,6 +1046,8 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
igt_require_f(data.render_copy,
"no render-copy function\n");
+ data.vebox_copy = igt_get_vebox_copyfunc(data.devid);
+
data.batch = intel_batchbuffer_alloc(data.bufmgr, data.devid);
igt_assert(data.batch);
@@ -957,13 +1059,25 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
char src_mode[32];
char dst_mode[32];
const bool src_mixed_tiled = t->flags & SOURCE_MIXED_TILED;
+ const bool force_vebox_dst_copy = t->flags & FORCE_VEBOX_DST_COPY;
+ const bool vebox_copy_used =
+ t->src_compression == I915_COMPRESSION_MEDIA ||
+ t->dst_compression == I915_COMPRESSION_MEDIA ||
+ force_vebox_dst_copy;
+ const bool render_copy_used =
+ !vebox_copy_used ||
+ t->src_compression == I915_COMPRESSION_RENDER ||
+ t->dst_compression == I915_COMPRESSION_RENDER;
buf_mode_to_str(t->src_tiling, src_mixed_tiled,
t->src_compression, src_mode, sizeof(src_mode));
buf_mode_to_str(t->dst_tiling, false,
t->dst_compression, dst_mode, sizeof(dst_mode));
- igt_describe_f("Test render_copy() from a %s to a %s buffer.",
+ igt_describe_f("Test %s%s%s from a %s to a %s buffer.",
+ render_copy_used ? "render_copy()" : "",
+ render_copy_used && vebox_copy_used ? " and " : "",
+ vebox_copy_used ? "vebox_copy()" : "",
src_mode, dst_mode);
/* Preserve original test names */
@@ -971,12 +1085,19 @@ igt_main_args("da", NULL, help_str, opt_handler, NULL)
t->dst_compression == I915_COMPRESSION_NONE)
src_mode[0] = '\0';
- igt_subtest_f("%s%s%s",
- src_mode, src_mode[0] ? "-to-" : "", dst_mode)
+ igt_subtest_f("%s%s%s%s",
+ src_mode,
+ src_mode[0] ? "-to-" : "",
+ force_vebox_dst_copy ? "vebox-" : "",
+ dst_mode) {
+ igt_require_f(data.vebox_copy || !vebox_copy_used,
+ "no vebox-copy function\n");
+
test(&data,
t->src_tiling, t->dst_tiling,
t->src_compression, t->dst_compression,
t->flags);
+ }
}
igt_fixture {
--
2.17.1
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^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [igt-dev] [PATCH v2 6/6] tests/gem_render_copy: Add media compression subtests
2019-12-04 13:50 ` [igt-dev] [PATCH v2 " Imre Deak
@ 2019-12-05 11:28 ` Kahola, Mika
0 siblings, 0 replies; 25+ messages in thread
From: Kahola, Mika @ 2019-12-05 11:28 UTC (permalink / raw)
To: igt-dev, Deak, Imre; +Cc: Welty, Brian
On Wed, 2019-12-04 at 15:50 +0200, Imre Deak wrote:
> Add subtests using the vebox copy function to test the blit
> functionality involving media compressed source and destination
> buffers.
>
> These cover all the source and destination tiling formats supported
> by
> the vebox engine and validate the buffer sharing between the render
> and
> vebox engine (a render compressed buffer used by the vebox engine and
> a
> media compressed buffer used by the render engine).
>
> v2:
> - Rebase on latest igt.
> Simplify the condition for enabling media compression in the
> surface
> state.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Brian Welty <brian.welty@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
> ---
> lib/gen9_render.h | 44 ++++++++----
> lib/rendercopy_gen9.c | 14 ++--
> tests/i915/gem_render_copy.c | 127
> ++++++++++++++++++++++++++++++++++-
> 3 files changed, 162 insertions(+), 23 deletions(-)
>
> diff --git a/lib/gen9_render.h b/lib/gen9_render.h
> index ab99563a..6274e902 100644
> --- a/lib/gen9_render.h
> +++ b/lib/gen9_render.h
> @@ -86,20 +86,36 @@ struct gen9_surface_state {
> uint32_t pad1:1;
> } ss6;
>
> - struct {
> - uint32_t resource_min_lod:12;
> -
> - /* Only on Haswell */
> - uint32_t pad0:4;
> - uint32_t shader_chanel_select_a:3;
> - uint32_t shader_chanel_select_b:3;
> - uint32_t shader_chanel_select_g:3;
> - uint32_t shader_chanel_select_r:3;
> -
> - uint32_t alpha_clear_color:1;
> - uint32_t blue_clear_color:1;
> - uint32_t green_clear_color:1;
> - uint32_t red_clear_color:1;
> + union {
> + struct {
> + uint32_t resource_min_lod:12;
> +
> + /* Only on Haswell */
> + uint32_t pad0:4;
> + uint32_t shader_chanel_select_a:3;
> + uint32_t shader_chanel_select_b:3;
> + uint32_t shader_chanel_select_g:3;
> + uint32_t shader_chanel_select_r:3;
> +
> + uint32_t alpha_clear_color:1;
> + uint32_t blue_clear_color:1;
> + uint32_t green_clear_color:1;
> + uint32_t red_clear_color:1;
> + } skl;
> + struct {
> + uint32_t resource_min_lod:12;
> +
> + /* Only on Haswell */
> + uint32_t pad0:4;
> + uint32_t shader_chanel_select_a:3;
> + uint32_t shader_chanel_select_b:3;
> + uint32_t shader_chanel_select_g:3;
> + uint32_t shader_chanel_select_r:3;
> +
> + uint32_t pad1:2;
> + uint32_t media_compression:1;
> + uint32_t pad2:1;
> + } tgl;
> } ss7;
>
> struct {
> diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
> index bf9d2ee1..63b1023d 100644
> --- a/lib/rendercopy_gen9.c
> +++ b/lib/rendercopy_gen9.c
> @@ -252,12 +252,14 @@ gen8_bind_buf(struct intel_batchbuffer *batch,
> const struct igt_buf *buf,
> ss->ss2.width = igt_buf_width(buf) - 1;
> ss->ss3.pitch = buf->stride - 1;
>
> - ss->ss7.shader_chanel_select_r = 4;
> - ss->ss7.shader_chanel_select_g = 5;
> - ss->ss7.shader_chanel_select_b = 6;
> - ss->ss7.shader_chanel_select_a = 7;
> -
> - if (buf->aux.stride) {
> + ss->ss7.skl.shader_chanel_select_r = 4;
> + ss->ss7.skl.shader_chanel_select_g = 5;
> + ss->ss7.skl.shader_chanel_select_b = 6;
> + ss->ss7.skl.shader_chanel_select_a = 7;
> +
> + if (buf->compression == I915_COMPRESSION_MEDIA)
> + ss->ss7.tgl.media_compression = 1;
> + else if (buf->aux.stride) {
> ss->ss6.aux_mode = 0x5; /* AUX_CCS_E */
> ss->ss6.aux_pitch = (buf->aux.stride / 128) - 1;
>
> diff --git a/tests/i915/gem_render_copy.c
> b/tests/i915/gem_render_copy.c
> index 9c36f38b..137c7c18 100644
> --- a/tests/i915/gem_render_copy.c
> +++ b/tests/i915/gem_render_copy.c
> @@ -59,6 +59,7 @@ typedef struct {
> drm_intel_bufmgr *bufmgr;
> struct intel_batchbuffer *batch;
> igt_render_copyfunc_t render_copy;
> + igt_vebox_copyfunc_t vebox_copy;
> } data_t;
> static int opt_dump_png = false;
> static int check_all_pixels = false;
> @@ -595,6 +596,7 @@ static void scratch_buf_aux_check(data_t *data,
> }
>
> #define SOURCE_MIXED_TILED 1
> +#define FORCE_VEBOX_DST_COPY 2
>
> static void test(data_t *data, uint32_t src_tiling, uint32_t
> dst_tiling,
> enum i915_compression src_compression,
> @@ -634,6 +636,7 @@ static void test(data_t *data, uint32_t
> src_tiling, uint32_t dst_tiling,
> const bool src_mixed_tiled = flags & SOURCE_MIXED_TILED;
> const bool src_compressed = src_compression !=
> I915_COMPRESSION_NONE;
> const bool dst_compressed = dst_compression !=
> I915_COMPRESSION_NONE;
> + const bool force_vebox_dst_copy = flags & FORCE_VEBOX_DST_COPY;
>
> /*
> * The source tilings for mixed source tiling test cases are
> determined
> @@ -641,6 +644,14 @@ static void test(data_t *data, uint32_t
> src_tiling, uint32_t dst_tiling,
> */
> igt_assert(src_tiling == I915_TILING_NONE || !src_mixed_tiled);
>
> + /*
> + * The vebox engine can produce only a media compressed or
> + * uncompressed surface.
> + */
> + igt_assert(!force_vebox_dst_copy ||
> + dst_compression == I915_COMPRESSION_MEDIA ||
> + dst_compression == I915_COMPRESSION_NONE);
> +
> /* no Yf before gen9 */
> if (intel_gen(data->devid) < 9)
> num_src--;
> @@ -733,6 +744,10 @@ static void test(data_t *data, uint32_t
> src_tiling, uint32_t dst_tiling,
> &src_tiled, 0, 0, WIDTH,
> HEIGHT,
> &src_ccs,
> 0, 0);
> + else if (src_compression == I915_COMPRESSION_MEDIA)
> + data->vebox_copy(data->batch,
> + &src_tiled, WIDTH, HEIGHT,
> + &src_ccs);
>
> if (dst_compression == I915_COMPRESSION_RENDER) {
> data->render_copy(data->batch, NULL,
> @@ -746,6 +761,21 @@ static void test(data_t *data, uint32_t
> src_tiling, uint32_t dst_tiling,
> 0, 0, WIDTH, HEIGHT,
> &dst,
> 0, 0);
> + } else if (dst_compression == I915_COMPRESSION_MEDIA) {
> + data->vebox_copy(data->batch,
> + src_compressed ? &src_ccs :
> &src_tiled,
> + WIDTH, HEIGHT,
> + &dst_ccs);
> +
> + data->vebox_copy(data->batch,
> + &dst_ccs,
> + WIDTH, HEIGHT,
> + &dst);
> + } else if (force_vebox_dst_copy) {
> + data->vebox_copy(data->batch,
> + src_compressed ? &src_ccs :
> &src_tiled,
> + WIDTH, HEIGHT,
> + &dst);
> } else {
> data->render_copy(data->batch, NULL,
> src_compressed ? &src_ccs :
> &src_tiled,
> @@ -854,6 +884,9 @@ static void buf_mode_to_str(uint32_t tiling, bool
> mixed_tiled,
> case I915_COMPRESSION_RENDER:
> compression_str = "ccs";
> break;
> + case I915_COMPRESSION_MEDIA:
> + compression_str = "mc-ccs";
> + break;
> default:
> igt_assert(0);
> }
> @@ -929,6 +962,73 @@ igt_main_args("da", NULL, help_str, opt_handler,
> NULL)
> { I915_TILING_Yf, I915_TILING_Y,
> I915_COMPRESSION_RENDER, I915_COMPRESSION_REND
> ER,
> 0, },
> +
> + { I915_TILING_NONE, I915_TILING_Yf,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> + { I915_TILING_NONE, I915_TILING_Y,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> +
> + { I915_TILING_X, I915_TILING_Yf,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> + { I915_TILING_X, I915_TILING_Y,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> +
> + { I915_TILING_Y, I915_TILING_NONE,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> + { I915_TILING_Y, I915_TILING_X,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> + { I915_TILING_Y, I915_TILING_Y,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> + { I915_TILING_Y, I915_TILING_Yf,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> +
> + { I915_TILING_Yf, I915_TILING_NONE,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> + { I915_TILING_Yf, I915_TILING_X,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> + { I915_TILING_Yf, I915_TILING_Yf,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> + { I915_TILING_Yf, I915_TILING_Y,
> + I915_COMPRESSION_NONE, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> +
> + { I915_TILING_Y, I915_TILING_Y,
> + I915_COMPRESSION_MEDIA, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> + { I915_TILING_Yf, I915_TILING_Yf,
> + I915_COMPRESSION_MEDIA, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> + { I915_TILING_Y, I915_TILING_Yf,
> + I915_COMPRESSION_MEDIA, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> + { I915_TILING_Yf, I915_TILING_Y,
> + I915_COMPRESSION_MEDIA, I915_COMPRESSION_NONE,
> + FORCE_VEBOX_DST_COPY, },
> +
> + { I915_TILING_Y, I915_TILING_Y,
> + I915_COMPRESSION_MEDIA, I915_COMPRESSION_RENDER,
> + 0, },
> + { I915_TILING_Y, I915_TILING_Yf,
> + I915_COMPRESSION_MEDIA, I915_COMPRESSION_RENDER,
> + 0, },
> +
> + { I915_TILING_Y, I915_TILING_Y,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_MEDI
> A,
> + 0, },
> + { I915_TILING_Y, I915_TILING_Yf,
> + I915_COMPRESSION_RENDER, I915_COMPRESSION_MEDI
> A,
> + 0, },
> };
> int i;
>
> @@ -946,6 +1046,8 @@ igt_main_args("da", NULL, help_str, opt_handler,
> NULL)
> igt_require_f(data.render_copy,
> "no render-copy function\n");
>
> + data.vebox_copy = igt_get_vebox_copyfunc(data.devid);
> +
> data.batch = intel_batchbuffer_alloc(data.bufmgr,
> data.devid);
> igt_assert(data.batch);
>
> @@ -957,13 +1059,25 @@ igt_main_args("da", NULL, help_str,
> opt_handler, NULL)
> char src_mode[32];
> char dst_mode[32];
> const bool src_mixed_tiled = t->flags &
> SOURCE_MIXED_TILED;
> + const bool force_vebox_dst_copy = t->flags &
> FORCE_VEBOX_DST_COPY;
> + const bool vebox_copy_used =
> + t->src_compression == I915_COMPRESSION_MEDIA ||
> + t->dst_compression == I915_COMPRESSION_MEDIA ||
> + force_vebox_dst_copy;
> + const bool render_copy_used =
> + !vebox_copy_used ||
> + t->src_compression == I915_COMPRESSION_RENDER
> ||
> + t->dst_compression == I915_COMPRESSION_RENDER;
>
> buf_mode_to_str(t->src_tiling, src_mixed_tiled,
> t->src_compression, src_mode,
> sizeof(src_mode));
> buf_mode_to_str(t->dst_tiling, false,
> t->dst_compression, dst_mode,
> sizeof(dst_mode));
>
> - igt_describe_f("Test render_copy() from a %s to a %s
> buffer.",
> + igt_describe_f("Test %s%s%s from a %s to a %s buffer.",
> + render_copy_used ? "render_copy()" : "",
> + render_copy_used && vebox_copy_used ? "
> and " : "",
> + vebox_copy_used ? "vebox_copy()" : "",
> src_mode, dst_mode);
>
> /* Preserve original test names */
> @@ -971,12 +1085,19 @@ igt_main_args("da", NULL, help_str,
> opt_handler, NULL)
> t->dst_compression == I915_COMPRESSION_NONE)
> src_mode[0] = '\0';
>
> - igt_subtest_f("%s%s%s",
> - src_mode, src_mode[0] ? "-to-" : "",
> dst_mode)
> + igt_subtest_f("%s%s%s%s",
> + src_mode,
> + src_mode[0] ? "-to-" : "",
> + force_vebox_dst_copy ? "vebox-" : "",
> + dst_mode) {
> + igt_require_f(data.vebox_copy ||
> !vebox_copy_used,
> + "no vebox-copy function\n");
> +
> test(&data,
> t->src_tiling, t->dst_tiling,
> t->src_compression, t->dst_compression,
> t->flags);
> + }
> }
>
> igt_fixture {
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for lib: Add tests validating media compressed surfaces
2019-11-29 10:38 [igt-dev] [PATCH i-g-t 0/6] lib: Add tests validating media compressed surfaces Imre Deak
` (5 preceding siblings ...)
2019-11-29 10:38 ` [igt-dev] [PATCH i-g-t 6/6] tests/gem_render_copy: Add media compression subtests Imre Deak
@ 2019-11-29 11:19 ` Patchwork
2019-11-30 6:06 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-29 11:19 UTC (permalink / raw)
To: Imre Deak; +Cc: igt-dev
== Series Details ==
Series: lib: Add tests validating media compressed surfaces
URL : https://patchwork.freedesktop.org/series/70201/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7440 -> IGTPW_3783
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/index.html
Known issues
------------
Here are the changes found in IGTPW_3783 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_gttfill@basic:
- fi-tgl-y: [PASS][1] -> [INCOMPLETE][2] ([fdo#111593])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/fi-tgl-y/igt@gem_exec_gttfill@basic.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/fi-tgl-y/igt@gem_exec_gttfill@basic.html
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [PASS][3] -> [SKIP][4] ([fdo#109271])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_sanitycheck:
- fi-skl-lmem: [PASS][5] -> [DMESG-WARN][6] ([fdo#112261])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/fi-skl-lmem/igt@i915_selftest@live_sanitycheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/fi-skl-lmem/igt@i915_selftest@live_sanitycheck.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-6770hq: [FAIL][7] ([fdo#108511]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_gt_heartbeat:
- fi-kbl-guc: [DMESG-FAIL][9] ([fdo#112405]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/fi-kbl-guc/igt@i915_selftest@live_gt_heartbeat.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/fi-kbl-guc/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][11] ([fdo#109483]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
- fi-kbl-7500u: [FAIL][13] ([fdo#111045] / [fdo#111096]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Warnings ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-x1275: [DMESG-WARN][15] ([fdo#103558] / [fdo#105602]) -> [DMESG-WARN][16] ([fdo#103558] / [fdo#105602] / [fdo#105763]) +4 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/fi-kbl-x1275/igt@i915_pm_rpm@basic-pci-d3-state.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/fi-kbl-x1275/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@kms_flip@basic-flip-vs-modeset:
- fi-kbl-x1275: [DMESG-WARN][17] ([fdo#103558] / [fdo#105602] / [fdo#105763]) -> [DMESG-WARN][18] ([fdo#103558] / [fdo#105602]) +7 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#112260]: https://bugs.freedesktop.org/show_bug.cgi?id=112260
[fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261
[fdo#112405]: https://bugs.freedesktop.org/show_bug.cgi?id=112405
Participating hosts (52 -> 46)
------------------------------
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5315 -> IGTPW_3783
CI-20190529: 20190529
CI_DRM_7440: 7b08e6efdddfcde8ea60a96d5a818af032b52b4d @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3783: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/index.html
IGT_5315: 58705eb1bd29414244f4d0cfa08a9f0ce42d6545 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@gem_render_copy@linear-to-vebox-yf-tiled
+igt@gem_render_copy@linear-to-vebox-y-tiled
+igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs
+igt@gem_render_copy@mixed-tiled-to-y-tiled-ccs
+igt@gem_render_copy@x-tiled-to-vebox-yf-tiled
+igt@gem_render_copy@x-tiled-to-vebox-y-tiled
+igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled
+igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled
+igt@gem_render_copy@yf-tiled-to-vebox-linear
+igt@gem_render_copy@yf-tiled-to-vebox-x-tiled
+igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled
+igt@gem_render_copy@yf-tiled-to-vebox-y-tiled
+igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs
+igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs
+igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled
+igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled
+igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs
+igt@gem_render_copy@y-tiled-to-vebox-linear
+igt@gem_render_copy@y-tiled-to-vebox-x-tiled
+igt@gem_render_copy@y-tiled-to-vebox-yf-tiled
+igt@gem_render_copy@y-tiled-to-vebox-y-tiled
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread* [igt-dev] ✗ Fi.CI.IGT: failure for lib: Add tests validating media compressed surfaces
2019-11-29 10:38 [igt-dev] [PATCH i-g-t 0/6] lib: Add tests validating media compressed surfaces Imre Deak
` (6 preceding siblings ...)
2019-11-29 11:19 ` [igt-dev] ✓ Fi.CI.BAT: success for lib: Add tests validating media compressed surfaces Patchwork
@ 2019-11-30 6:06 ` Patchwork
2019-12-04 15:19 ` [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add tests validating media compressed surfaces (rev3) Patchwork
2019-12-09 9:40 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-11-30 6:06 UTC (permalink / raw)
To: Imre Deak; +Cc: igt-dev
== Series Details ==
Series: lib: Add tests validating media compressed surfaces
URL : https://patchwork.freedesktop.org/series/70201/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7440_full -> IGTPW_3783_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_3783_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_3783_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_3783_full:
### IGT changes ###
#### Possible regressions ####
* {igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled} (NEW):
- shard-iclb: NOTRUN -> [SKIP][1] +7 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-iclb1/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html
* igt@kms_cursor_crc@pipe-c-cursor-256x85-onscreen:
- shard-apl: [PASS][2] -> [DMESG-WARN][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-256x85-onscreen.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-256x85-onscreen.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_exec_schedule@pi-distinct-iova-bsd}:
- shard-tglb: NOTRUN -> [SKIP][4]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-tglb8/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
New tests
---------
New tests have been introduced between CI_DRM_7440_full and IGTPW_3783_full:
### New IGT tests (22) ###
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@gem_render_copy@linear-to-vebox-yf-tiled:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@gem_render_copy@mixed-tiled-to-y-tiled-ccs:
- Statuses : 3 pass(s) 2 skip(s)
- Exec time: [0.0, 0.25] s
* igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs:
- Statuses : 3 pass(s) 2 skip(s)
- Exec time: [0.0, 0.23] s
* igt@gem_render_copy@x-tiled-to-vebox-y-tiled:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@gem_render_copy@x-tiled-to-vebox-yf-tiled:
- Statuses : 1 pass(s) 5 skip(s)
- Exec time: [0.0, 0.11] s
* igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs:
- Statuses : 1 pass(s) 5 skip(s)
- Exec time: [0.0, 0.11] s
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
- Statuses : 1 pass(s) 5 skip(s)
- Exec time: [0.0, 0.14] s
* igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
- Statuses : 1 pass(s) 6 skip(s)
- Exec time: [0.0, 0.12] s
* igt@gem_render_copy@y-tiled-to-vebox-linear:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@gem_render_copy@y-tiled-to-vebox-x-tiled:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@gem_render_copy@y-tiled-to-vebox-y-tiled:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
- Statuses : 6 skip(s)
- Exec time: [0.0] s
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
- Statuses : 1 pass(s) 6 skip(s)
- Exec time: [0.0, 0.11] s
* igt@gem_render_copy@yf-tiled-to-vebox-linear:
- Statuses : 1 pass(s) 5 skip(s)
- Exec time: [0.0, 0.12] s
* igt@gem_render_copy@yf-tiled-to-vebox-x-tiled:
- Statuses : 1 pass(s) 5 skip(s)
- Exec time: [0.0, 0.13] s
* igt@gem_render_copy@yf-tiled-to-vebox-y-tiled:
- Statuses : 1 pass(s) 5 skip(s)
- Exec time: [0.0, 0.14] s
* igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled:
- Statuses : 5 skip(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in IGTPW_3783_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_shared@exec-single-timeline-bsd1:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd1.html
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][7] -> [FAIL][8] ([fdo#109661])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-snb4/igt@gem_eio@reset-stress.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-snb7/igt@gem_eio@reset-stress.html
* igt@gem_exec_schedule@preempt-queue-chain-vebox:
- shard-iclb: [PASS][9] -> [INCOMPLETE][10] ([fdo#107713])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-iclb5/igt@gem_exec_schedule@preempt-queue-chain-vebox.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-iclb1/igt@gem_exec_schedule@preempt-queue-chain-vebox.html
* igt@gem_exec_store@cachelines-vcs1:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112080]) +4 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-iclb2/igt@gem_exec_store@cachelines-vcs1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-iclb6/igt@gem_exec_store@cachelines-vcs1.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-tglb: [PASS][13] -> [TIMEOUT][14] ([fdo#112068] / [fdo#112113] / [fdo#112126])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-tglb2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-tglb4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [PASS][15] -> [FAIL][16] ([fdo#112392])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-apl7/igt@gem_ppgtt@flink-and-close-vma-leak.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-apl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_sync@basic-each:
- shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([fdo#111880] / [fdo#111998])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-tglb6/igt@gem_sync@basic-each.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-tglb5/igt@gem_sync@basic-each.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-snb: [PASS][19] -> [DMESG-WARN][20] ([fdo#110789] / [fdo#111870])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup:
- shard-snb: [PASS][21] -> [DMESG-WARN][22] ([fdo#111870])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-snb7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy-gup.html
* igt@gem_userptr_blits@sync-unmap:
- shard-hsw: [PASS][23] -> [DMESG-WARN][24] ([fdo#111870])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-hsw7/igt@gem_userptr_blits@sync-unmap.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-hsw7/igt@gem_userptr_blits@sync-unmap.html
* igt@kms_cursor_crc@pipe-d-cursor-suspend:
- shard-tglb: [PASS][25] -> [INCOMPLETE][26] ([fdo#111850])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-tglb8/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][27] -> [DMESG-WARN][28] ([fdo#108566]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-kbl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-tglb: [PASS][29] -> [FAIL][30] ([fdo#103167]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite:
- shard-tglb: [PASS][31] -> [INCOMPLETE][32] ([fdo#112393])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-tglb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-pwrite.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-tglb: [PASS][33] -> [INCOMPLETE][34] ([fdo#111832] / [fdo#111850])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-tglb7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-tglb2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane@pixel-format-pipe-b-planes:
- shard-kbl: [PASS][35] -> [INCOMPLETE][36] ([fdo#103665]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-kbl3/igt@kms_plane@pixel-format-pipe-b-planes.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-kbl6/igt@kms_plane@pixel-format-pipe-b-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [PASS][37] -> [DMESG-WARN][38] ([fdo#108566])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][39] -> [FAIL][40] ([fdo#99912])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-apl4/igt@kms_setmode@basic.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-apl6/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gem_ctx_shared@q-smoketest-all:
- shard-tglb: [INCOMPLETE][41] ([fdo#111735]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-tglb4/igt@gem_ctx_shared@q-smoketest-all.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-tglb1/igt@gem_ctx_shared@q-smoketest-all.html
* igt@gem_exec_schedule@preempt-bsd2:
- shard-iclb: [SKIP][43] ([fdo#109276]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-iclb6/igt@gem_exec_schedule@preempt-bsd2.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-iclb1/igt@gem_exec_schedule@preempt-bsd2.html
* igt@gem_exec_schedule@preempt-queue-chain-vebox:
- shard-glk: [INCOMPLETE][45] ([fdo#103359] / [k.org#198133]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-glk4/igt@gem_exec_schedule@preempt-queue-chain-vebox.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-glk3/igt@gem_exec_schedule@preempt-queue-chain-vebox.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [DMESG-WARN][47] ([fdo#108566]) -> [PASS][48] +5 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-kbl6/igt@gem_exec_suspend@basic-s3.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-kbl7/igt@gem_exec_suspend@basic-s3.html
* igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
- shard-kbl: [TIMEOUT][49] ([fdo#112068]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-kbl7/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-kbl6/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [DMESG-WARN][51] ([fdo#111870]) -> [PASS][52] +5 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-hsw6/igt@gem_userptr_blits@sync-unmap-after-close.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-hsw5/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [DMESG-WARN][53] ([fdo#111870]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-snb1/igt@gem_userptr_blits@sync-unmap-cycles.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-snb1/igt@gem_userptr_blits@sync-unmap-cycles.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-tglb: [INCOMPLETE][55] ([fdo#111832] / [fdo#111850]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-tglb7/igt@i915_suspend@fence-restore-tiled2untiled.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-tglb8/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_color@pipe-c-ctm-blue-to-red:
- shard-kbl: [FAIL][57] ([fdo#107201]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-kbl7/igt@kms_color@pipe-c-ctm-blue-to-red.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-kbl4/igt@kms_color@pipe-c-ctm-blue-to-red.html
- shard-apl: [FAIL][59] ([fdo#107201]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-apl3/igt@kms_color@pipe-c-ctm-blue-to-red.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-apl8/igt@kms_color@pipe-c-ctm-blue-to-red.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
- shard-kbl: [FAIL][61] ([fdo#103232]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
- shard-apl: [FAIL][63] ([fdo#103232]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
* igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen:
- shard-hsw: [DMESG-WARN][65] -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-hsw6/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-hsw1/igt@kms_cursor_crc@pipe-b-cursor-64x21-offscreen.html
* igt@kms_draw_crc@draw-method-rgb565-render-untiled:
- shard-kbl: [INCOMPLETE][67] ([fdo#103665]) -> [PASS][68] +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-kbl6/igt@kms_draw_crc@draw-method-rgb565-render-untiled.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-kbl4/igt@kms_draw_crc@draw-method-rgb565-render-untiled.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [DMESG-WARN][69] ([fdo#108566]) -> [PASS][70] +4 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen:
- shard-glk: [FAIL][71] ([fdo#103167]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-glk1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-glk8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html
- shard-apl: [FAIL][73] ([fdo#103167]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-apl1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-apl8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html
- shard-kbl: [FAIL][75] ([fdo#103167]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-kbl6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-tglb: [FAIL][77] ([fdo#103167]) -> [PASS][78] +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@perf@disabled-read-error:
- shard-hsw: [INCOMPLETE][79] ([fdo#103540]) -> [PASS][80] +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-hsw8/igt@perf@disabled-read-error.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-hsw1/igt@perf@disabled-read-error.html
* igt@perf_pmu@render-node-busy-vcs1:
- shard-iclb: [SKIP][81] ([fdo#112080]) -> [PASS][82] +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-iclb6/igt@perf_pmu@render-node-busy-vcs1.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-iclb1/igt@perf_pmu@render-node-busy-vcs1.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv-switch:
- shard-iclb: [SKIP][83] ([fdo#109276] / [fdo#112080]) -> [FAIL][84] ([IGT#28])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-iclb7/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
* igt@gem_eio@kms:
- shard-snb: [DMESG-WARN][85] ([fdo#111781]) -> [DMESG-FAIL][86] ([fdo#111757])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-snb6/igt@gem_eio@kms.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-snb7/igt@gem_eio@kms.html
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [FAIL][87] ([fdo#103375]) -> [DMESG-WARN][88] ([fdo#108566])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7440/shard-kbl4/igt@gem_softpin@noreloc-s3.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/shard-kbl4/igt@gem_softpin@noreloc-s3.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#111757]: https://bugs.freedesktop.org/show_bug.cgi?id=111757
[fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
[fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
[fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#111998]: https://bugs.freedesktop.org/show_bug.cgi?id=111998
[fdo#112068]: https://bugs.freedesktop.org/show_bug.cgi?id=112068
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112113]: https://bugs.freedesktop.org/show_bug.cgi?id=112113
[fdo#112126]: https://bugs.freedesktop.org/show_bug.cgi?id=112126
[fdo#112392]: https://bugs.freedesktop.org/show_bug.cgi?id=112392
[fdo#112393]: https://bugs.freedesktop.org/show_bug.cgi?id=112393
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (11 -> 8)
------------------------------
Missing (3): pig-skl-6260u pig-glk-j5005 pig-hsw-4770r
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5315 -> IGTPW_3783
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_7440: 7b08e6efdddfcde8ea60a96d5a818af032b52b4d @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3783: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/index.html
IGT_5315: 58705eb1bd29414244f4d0cfa08a9f0ce42d6545 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3783/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread* [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add tests validating media compressed surfaces (rev3)
2019-11-29 10:38 [igt-dev] [PATCH i-g-t 0/6] lib: Add tests validating media compressed surfaces Imre Deak
` (7 preceding siblings ...)
2019-11-30 6:06 ` [igt-dev] ✗ Fi.CI.IGT: failure " Patchwork
@ 2019-12-04 15:19 ` Patchwork
2019-12-04 15:59 ` Imre Deak
2019-12-09 9:40 ` [igt-dev] ✓ Fi.CI.BAT: success " Patchwork
9 siblings, 1 reply; 25+ messages in thread
From: Patchwork @ 2019-12-04 15:19 UTC (permalink / raw)
To: Imre Deak; +Cc: igt-dev
== Series Details ==
Series: lib: Add tests validating media compressed surfaces (rev3)
URL : https://patchwork.freedesktop.org/series/70201/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7481 -> IGTPW_3809
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with IGTPW_3809 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_3809, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in IGTPW_3809:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_gem_contexts:
- fi-byt-n2820: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@reload-with-fault-injection:
- {fi-kbl-7560u}: [DMESG-WARN][3] ([i915#710]) -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
Known issues
------------
Here are the changes found in IGTPW_3809 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload-no-display:
- fi-skl-lmem: [PASS][5] -> [DMESG-WARN][6] ([i915#592])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770: [PASS][7] -> [DMESG-FAIL][8] ([i915#563])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-hsw-4770/igt@i915_selftest@live_blt.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-hsw-4770/igt@i915_selftest@live_blt.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-tgl-guc}: [INCOMPLETE][9] ([fdo#111735]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-tgl-guc/igt@gem_ctx_create@basic-files.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-tgl-guc/igt@gem_ctx_create@basic-files.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770: [DMESG-FAIL][11] ([i915#563]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-ivb-3770/igt@i915_selftest@live_blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-ivb-3770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-byt-j1900: [DMESG-FAIL][13] -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [FAIL][16] ([fdo#111096] / [i915#323])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +8 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_flip@basic-flip-vs-modeset:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +6 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#710]: https://gitlab.freedesktop.org/drm/intel/issues/710
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (54 -> 47)
------------------------------
Missing (7): fi-icl-1065g7 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5325 -> IGTPW_3809
CI-20190529: 20190529
CI_DRM_7481: 7370e8bfcbb19757750dcf6ceb521c11c1d2ec27 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3809: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
IGT_5325: 7b7189e9f56c17cc810dd63ce767d4715288b05a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@gem_render_copy@linear-to-vebox-yf-tiled
+igt@gem_render_copy@linear-to-vebox-y-tiled
+igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs
+igt@gem_render_copy@mixed-tiled-to-y-tiled-ccs
+igt@gem_render_copy@x-tiled-to-vebox-yf-tiled
+igt@gem_render_copy@x-tiled-to-vebox-y-tiled
+igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled
+igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled
+igt@gem_render_copy@yf-tiled-to-vebox-linear
+igt@gem_render_copy@yf-tiled-to-vebox-x-tiled
+igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled
+igt@gem_render_copy@yf-tiled-to-vebox-y-tiled
+igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs
+igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs
+igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled
+igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled
+igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs
+igt@gem_render_copy@y-tiled-to-vebox-linear
+igt@gem_render_copy@y-tiled-to-vebox-x-tiled
+igt@gem_render_copy@y-tiled-to-vebox-yf-tiled
+igt@gem_render_copy@y-tiled-to-vebox-y-tiled
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add tests validating media compressed surfaces (rev3)
2019-12-04 15:19 ` [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add tests validating media compressed surfaces (rev3) Patchwork
@ 2019-12-04 15:59 ` Imre Deak
2019-12-09 8:36 ` Imre Deak
0 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2019-12-04 15:59 UTC (permalink / raw)
To: igt-dev; +Cc: Lakshminarayana Vudum
On Wed, Dec 04, 2019 at 03:19:09PM +0000, Patchwork wrote:
> == Series Details ==
>
> Series: lib: Add tests validating media compressed surfaces (rev3)
> URL : https://patchwork.freedesktop.org/series/70201/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7481 -> IGTPW_3809
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with IGTPW_3809 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in IGTPW_3809, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in IGTPW_3809:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@i915_selftest@live_gem_contexts:
> - fi-byt-n2820: [PASS][1] -> [DMESG-FAIL][2]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
> [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
This looks unrelated, as BYT should not be affected by any GEN9 changes
and gem_render_copy was not run on this machine until the bug happened.
Similar PW failures were marked as a known issue with the following
bug reports associated with it:
https://gitlab.freedesktop.org/drm/intel/issues/45
https://bugs.freedesktop.org/show_bug.cgi?id=102657
>
> #### Suppressed ####
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@i915_module_load@reload-with-fault-injection:
> - {fi-kbl-7560u}: [DMESG-WARN][3] ([i915#710]) -> [INCOMPLETE][4]
> [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
> [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
>
>
> Known issues
> ------------
>
> Here are the changes found in IGTPW_3809 that come from known issues:
>
> ### IGT changes ###
>
> #### Issues hit ####
>
> * igt@i915_module_load@reload-no-display:
> - fi-skl-lmem: [PASS][5] -> [DMESG-WARN][6] ([i915#592])
> [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
> [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
>
> * igt@i915_selftest@live_blt:
> - fi-hsw-4770: [PASS][7] -> [DMESG-FAIL][8] ([i915#563])
> [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-hsw-4770/igt@i915_selftest@live_blt.html
> [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-hsw-4770/igt@i915_selftest@live_blt.html
>
>
> #### Possible fixes ####
>
> * igt@gem_ctx_create@basic-files:
> - {fi-tgl-guc}: [INCOMPLETE][9] ([fdo#111735]) -> [PASS][10]
> [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-tgl-guc/igt@gem_ctx_create@basic-files.html
> [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-tgl-guc/igt@gem_ctx_create@basic-files.html
>
> * igt@i915_selftest@live_blt:
> - fi-ivb-3770: [DMESG-FAIL][11] ([i915#563]) -> [PASS][12]
> [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-ivb-3770/igt@i915_selftest@live_blt.html
> [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-ivb-3770/igt@i915_selftest@live_blt.html
>
> * igt@i915_selftest@live_gem_contexts:
> - fi-byt-j1900: [DMESG-FAIL][13] -> [PASS][14]
> [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
> [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
>
>
> #### Warnings ####
>
> * igt@kms_chamelium@hdmi-hpd-fast:
> - fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [FAIL][16] ([fdo#111096] / [i915#323])
> [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
> [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
>
> * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
> - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +8 similar issues
> [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
> [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
>
> * igt@kms_flip@basic-flip-vs-modeset:
> - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +6 similar issues
> [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
> [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
>
>
> {name}: This element is suppressed. This means it is ignored when computing
> the status of the difference (SUCCESS, WARNING, or FAILURE).
>
> [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
> [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
> [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
> [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
> [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
> [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
> [i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
> [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
> [i915#710]: https://gitlab.freedesktop.org/drm/intel/issues/710
> [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
> [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
>
>
> Participating hosts (54 -> 47)
> ------------------------------
>
> Missing (7): fi-icl-1065g7 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
>
>
> Build changes
> -------------
>
> * CI: CI-20190529 -> None
> * IGT: IGT_5325 -> IGTPW_3809
>
> CI-20190529: 20190529
> CI_DRM_7481: 7370e8bfcbb19757750dcf6ceb521c11c1d2ec27 @ git://anongit.freedesktop.org/gfx-ci/linux
> IGTPW_3809: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
> IGT_5325: 7b7189e9f56c17cc810dd63ce767d4715288b05a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
>
>
>
> == Testlist changes ==
>
> +igt@gem_render_copy@linear-to-vebox-yf-tiled
> +igt@gem_render_copy@linear-to-vebox-y-tiled
> +igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs
> +igt@gem_render_copy@mixed-tiled-to-y-tiled-ccs
> +igt@gem_render_copy@x-tiled-to-vebox-yf-tiled
> +igt@gem_render_copy@x-tiled-to-vebox-y-tiled
> +igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled
> +igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled
> +igt@gem_render_copy@yf-tiled-to-vebox-linear
> +igt@gem_render_copy@yf-tiled-to-vebox-x-tiled
> +igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled
> +igt@gem_render_copy@yf-tiled-to-vebox-y-tiled
> +igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs
> +igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs
> +igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled
> +igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled
> +igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs
> +igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs
> +igt@gem_render_copy@y-tiled-to-vebox-linear
> +igt@gem_render_copy@y-tiled-to-vebox-x-tiled
> +igt@gem_render_copy@y-tiled-to-vebox-yf-tiled
> +igt@gem_render_copy@y-tiled-to-vebox-y-tiled
>
> == Logs ==
>
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add tests validating media compressed surfaces (rev3)
2019-12-04 15:59 ` Imre Deak
@ 2019-12-09 8:36 ` Imre Deak
2019-12-09 9:55 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 25+ messages in thread
From: Imre Deak @ 2019-12-09 8:36 UTC (permalink / raw)
To: igt-dev, Mika Kahola; +Cc: Lakshminarayana Vudum
On Wed, Dec 04, 2019 at 05:59:35PM +0200, Imre Deak wrote:
> On Wed, Dec 04, 2019 at 03:19:09PM +0000, Patchwork wrote:
> > == Series Details ==
> >
> > Series: lib: Add tests validating media compressed surfaces (rev3)
> > URL : https://patchwork.freedesktop.org/series/70201/
> > State : failure
Patchset is pushed, thanks for the review.
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_7481 -> IGTPW_3809
> > ====================================================
> >
> > Summary
> > -------
> >
> > **FAILURE**
> >
> > Serious unknown changes coming with IGTPW_3809 absolutely need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in IGTPW_3809, please notify your bug team to allow them
> > to document this new failure mode, which will reduce false positives in CI.
> >
> > External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
> >
> > Possible new issues
> > -------------------
> >
> > Here are the unknown changes that may have been introduced in IGTPW_3809:
> >
> > ### IGT changes ###
> >
> > #### Possible regressions ####
> >
> > * igt@i915_selftest@live_gem_contexts:
> > - fi-byt-n2820: [PASS][1] -> [DMESG-FAIL][2]
> > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
> > [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
>
> This looks unrelated, as BYT should not be affected by any GEN9 changes
> and gem_render_copy was not run on this machine until the bug happened.
> Similar PW failures were marked as a known issue with the following
> bug reports associated with it:
>
> https://gitlab.freedesktop.org/drm/intel/issues/45
> https://bugs.freedesktop.org/show_bug.cgi?id=102657
>
> >
> > #### Suppressed ####
> >
> > The following results come from untrusted machines, tests, or statuses.
> > They do not affect the overall result.
> >
> > * igt@i915_module_load@reload-with-fault-injection:
> > - {fi-kbl-7560u}: [DMESG-WARN][3] ([i915#710]) -> [INCOMPLETE][4]
> > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
> > [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
> >
> >
> > Known issues
> > ------------
> >
> > Here are the changes found in IGTPW_3809 that come from known issues:
> >
> > ### IGT changes ###
> >
> > #### Issues hit ####
> >
> > * igt@i915_module_load@reload-no-display:
> > - fi-skl-lmem: [PASS][5] -> [DMESG-WARN][6] ([i915#592])
> > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
> > [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
> >
> > * igt@i915_selftest@live_blt:
> > - fi-hsw-4770: [PASS][7] -> [DMESG-FAIL][8] ([i915#563])
> > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-hsw-4770/igt@i915_selftest@live_blt.html
> > [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-hsw-4770/igt@i915_selftest@live_blt.html
> >
> >
> > #### Possible fixes ####
> >
> > * igt@gem_ctx_create@basic-files:
> > - {fi-tgl-guc}: [INCOMPLETE][9] ([fdo#111735]) -> [PASS][10]
> > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-tgl-guc/igt@gem_ctx_create@basic-files.html
> > [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-tgl-guc/igt@gem_ctx_create@basic-files.html
> >
> > * igt@i915_selftest@live_blt:
> > - fi-ivb-3770: [DMESG-FAIL][11] ([i915#563]) -> [PASS][12]
> > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-ivb-3770/igt@i915_selftest@live_blt.html
> > [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-ivb-3770/igt@i915_selftest@live_blt.html
> >
> > * igt@i915_selftest@live_gem_contexts:
> > - fi-byt-j1900: [DMESG-FAIL][13] -> [PASS][14]
> > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
> > [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
> >
> >
> > #### Warnings ####
> >
> > * igt@kms_chamelium@hdmi-hpd-fast:
> > - fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [FAIL][16] ([fdo#111096] / [i915#323])
> > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
> > [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
> >
> > * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
> > - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +8 similar issues
> > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
> > [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
> >
> > * igt@kms_flip@basic-flip-vs-modeset:
> > - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +6 similar issues
> > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
> > [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
> >
> >
> > {name}: This element is suppressed. This means it is ignored when computing
> > the status of the difference (SUCCESS, WARNING, or FAILURE).
> >
> > [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
> > [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
> > [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
> > [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
> > [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
> > [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
> > [i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
> > [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
> > [i915#710]: https://gitlab.freedesktop.org/drm/intel/issues/710
> > [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
> > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
> >
> >
> > Participating hosts (54 -> 47)
> > ------------------------------
> >
> > Missing (7): fi-icl-1065g7 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
> >
> >
> > Build changes
> > -------------
> >
> > * CI: CI-20190529 -> None
> > * IGT: IGT_5325 -> IGTPW_3809
> >
> > CI-20190529: 20190529
> > CI_DRM_7481: 7370e8bfcbb19757750dcf6ceb521c11c1d2ec27 @ git://anongit.freedesktop.org/gfx-ci/linux
> > IGTPW_3809: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
> > IGT_5325: 7b7189e9f56c17cc810dd63ce767d4715288b05a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> >
> >
> >
> > == Testlist changes ==
> >
> > +igt@gem_render_copy@linear-to-vebox-yf-tiled
> > +igt@gem_render_copy@linear-to-vebox-y-tiled
> > +igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs
> > +igt@gem_render_copy@mixed-tiled-to-y-tiled-ccs
> > +igt@gem_render_copy@x-tiled-to-vebox-yf-tiled
> > +igt@gem_render_copy@x-tiled-to-vebox-y-tiled
> > +igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled
> > +igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled
> > +igt@gem_render_copy@yf-tiled-to-vebox-linear
> > +igt@gem_render_copy@yf-tiled-to-vebox-x-tiled
> > +igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled
> > +igt@gem_render_copy@yf-tiled-to-vebox-y-tiled
> > +igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs
> > +igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs
> > +igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled
> > +igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled
> > +igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs
> > +igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs
> > +igt@gem_render_copy@y-tiled-to-vebox-linear
> > +igt@gem_render_copy@y-tiled-to-vebox-x-tiled
> > +igt@gem_render_copy@y-tiled-to-vebox-yf-tiled
> > +igt@gem_render_copy@y-tiled-to-vebox-y-tiled
> >
> > == Logs ==
> >
> > For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
> _______________________________________________
> igt-dev mailing list
> igt-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/igt-dev
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 25+ messages in thread* Re: [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add tests validating media compressed surfaces (rev3)
2019-12-09 8:36 ` Imre Deak
@ 2019-12-09 9:55 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 25+ messages in thread
From: Vudum, Lakshminarayana @ 2019-12-09 9:55 UTC (permalink / raw)
To: Deak, Imre, igt-dev, Kahola, Mika
Imre, Re-reported the results after addressing the issue.
Lakshmi.
-----Original Message-----
From: Imre Deak <imre.deak@intel.com>
Sent: Monday, December 9, 2019 10:37 AM
To: igt-dev@lists.freedesktop.org; Kahola, Mika <mika.kahola@intel.com>
Cc: Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add tests validating media compressed surfaces (rev3)
On Wed, Dec 04, 2019 at 05:59:35PM +0200, Imre Deak wrote:
> On Wed, Dec 04, 2019 at 03:19:09PM +0000, Patchwork wrote:
> > == Series Details ==
> >
> > Series: lib: Add tests validating media compressed surfaces (rev3)
> > URL : https://patchwork.freedesktop.org/series/70201/
> > State : failure
Patchset is pushed, thanks for the review.
> >
> > == Summary ==
> >
> > CI Bug Log - changes from CI_DRM_7481 -> IGTPW_3809
> > ====================================================
> >
> > Summary
> > -------
> >
> > **FAILURE**
> >
> > Serious unknown changes coming with IGTPW_3809 absolutely need to be
> > verified manually.
> >
> > If you think the reported changes have nothing to do with the changes
> > introduced in IGTPW_3809, please notify your bug team to allow them
> > to document this new failure mode, which will reduce false positives in CI.
> >
> > External URL:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
> >
> > Possible new issues
> > -------------------
> >
> > Here are the unknown changes that may have been introduced in IGTPW_3809:
> >
> > ### IGT changes ###
> >
> > #### Possible regressions ####
> >
> > * igt@i915_selftest@live_gem_contexts:
> > - fi-byt-n2820: [PASS][1] -> [DMESG-FAIL][2]
> > [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
> > [2]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-byt-n2820/igt
> > @i915_selftest@live_gem_contexts.html
>
> This looks unrelated, as BYT should not be affected by any GEN9
> changes and gem_render_copy was not run on this machine until the bug happened.
> Similar PW failures were marked as a known issue with the following
> bug reports associated with it:
>
> https://gitlab.freedesktop.org/drm/intel/issues/45
> https://bugs.freedesktop.org/show_bug.cgi?id=102657
>
> >
> > #### Suppressed ####
> >
> > The following results come from untrusted machines, tests, or statuses.
> > They do not affect the overall result.
> >
> > * igt@i915_module_load@reload-with-fault-injection:
> > - {fi-kbl-7560u}: [DMESG-WARN][3] ([i915#710]) -> [INCOMPLETE][4]
> > [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
> > [4]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-7560u/igt
> > @i915_module_load@reload-with-fault-injection.html
> >
> >
> > Known issues
> > ------------
> >
> > Here are the changes found in IGTPW_3809 that come from known issues:
> >
> > ### IGT changes ###
> >
> > #### Issues hit ####
> >
> > * igt@i915_module_load@reload-no-display:
> > - fi-skl-lmem: [PASS][5] -> [DMESG-WARN][6] ([i915#592])
> > [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
> > [6]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-skl-lmem/igt@
> > i915_module_load@reload-no-display.html
> >
> > * igt@i915_selftest@live_blt:
> > - fi-hsw-4770: [PASS][7] -> [DMESG-FAIL][8] ([i915#563])
> > [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-hsw-4770/igt@i915_selftest@live_blt.html
> > [8]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-hsw-4770/igt@
> > i915_selftest@live_blt.html
> >
> >
> > #### Possible fixes ####
> >
> > * igt@gem_ctx_create@basic-files:
> > - {fi-tgl-guc}: [INCOMPLETE][9] ([fdo#111735]) -> [PASS][10]
> > [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-tgl-guc/igt@gem_ctx_create@basic-files.html
> > [10]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-tgl-guc/igt@g
> > em_ctx_create@basic-files.html
> >
> > * igt@i915_selftest@live_blt:
> > - fi-ivb-3770: [DMESG-FAIL][11] ([i915#563]) -> [PASS][12]
> > [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-ivb-3770/igt@i915_selftest@live_blt.html
> > [12]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-ivb-3770/igt@
> > i915_selftest@live_blt.html
> >
> > * igt@i915_selftest@live_gem_contexts:
> > - fi-byt-j1900: [DMESG-FAIL][13] -> [PASS][14]
> > [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
> > [14]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-byt-j1900/igt
> > @i915_selftest@live_gem_contexts.html
> >
> >
> > #### Warnings ####
> >
> > * igt@kms_chamelium@hdmi-hpd-fast:
> > - fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [FAIL][16] ([fdo#111096] / [i915#323])
> > [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
> > [16]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-7500u/igt
> > @kms_chamelium@hdmi-hpd-fast.html
> >
> > * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
> > - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +8 similar issues
> > [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
> > [18]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-x1275/igt
> > @kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
> >
> > * igt@kms_flip@basic-flip-vs-modeset:
> > - fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][20] ([i915#62] / [i915#92]) +6 similar issues
> > [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
> > [20]:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-x1275/igt
> > @kms_flip@basic-flip-vs-modeset.html
> >
> >
> > {name}: This element is suppressed. This means it is ignored when computing
> > the status of the difference (SUCCESS, WARNING, or FAILURE).
> >
> > [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
> > [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
> > [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
> > [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
> > [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
> > [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
> > [i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
> > [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
> > [i915#710]: https://gitlab.freedesktop.org/drm/intel/issues/710
> > [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
> > [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
> >
> >
> > Participating hosts (54 -> 47)
> > ------------------------------
> >
> > Missing (7): fi-icl-1065g7 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
> >
> >
> > Build changes
> > -------------
> >
> > * CI: CI-20190529 -> None
> > * IGT: IGT_5325 -> IGTPW_3809
> >
> > CI-20190529: 20190529
> > CI_DRM_7481: 7370e8bfcbb19757750dcf6ceb521c11c1d2ec27 @ git://anongit.freedesktop.org/gfx-ci/linux
> > IGTPW_3809: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
> > IGT_5325: 7b7189e9f56c17cc810dd63ce767d4715288b05a @
> > git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
> >
> >
> >
> > == Testlist changes ==
> >
> > +igt@gem_render_copy@linear-to-vebox-yf-tiled
> > +igt@gem_render_copy@linear-to-vebox-y-tiled
> > +igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs
> > +igt@gem_render_copy@mixed-tiled-to-y-tiled-ccs
> > +igt@gem_render_copy@x-tiled-to-vebox-yf-tiled
> > +igt@gem_render_copy@x-tiled-to-vebox-y-tiled
> > +igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled
> > +igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled
> > +igt@gem_render_copy@yf-tiled-to-vebox-linear
> > +igt@gem_render_copy@yf-tiled-to-vebox-x-tiled
> > +igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled
> > +igt@gem_render_copy@yf-tiled-to-vebox-y-tiled
> > +igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs
> > +igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs
> > +igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled
> > +igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled
> > +igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs
> > +igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs
> > +igt@gem_render_copy@y-tiled-to-vebox-linear
> > +igt@gem_render_copy@y-tiled-to-vebox-x-tiled
> > +igt@gem_render_copy@y-tiled-to-vebox-yf-tiled
> > +igt@gem_render_copy@y-tiled-to-vebox-y-tiled
> >
> > == Logs ==
> >
> > For more details see:
> > https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
> _______________________________________________
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* [igt-dev] ✓ Fi.CI.BAT: success for lib: Add tests validating media compressed surfaces (rev3)
2019-11-29 10:38 [igt-dev] [PATCH i-g-t 0/6] lib: Add tests validating media compressed surfaces Imre Deak
` (8 preceding siblings ...)
2019-12-04 15:19 ` [igt-dev] ✗ Fi.CI.BAT: failure for lib: Add tests validating media compressed surfaces (rev3) Patchwork
@ 2019-12-09 9:40 ` Patchwork
9 siblings, 0 replies; 25+ messages in thread
From: Patchwork @ 2019-12-09 9:40 UTC (permalink / raw)
To: Imre Deak; +Cc: igt-dev
== Series Details ==
Series: lib: Add tests validating media compressed surfaces (rev3)
URL : https://patchwork.freedesktop.org/series/70201/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7481 -> IGTPW_3809
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
Known issues
------------
Here are the changes found in IGTPW_3809 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload-no-display:
- fi-skl-lmem: [PASS][1] -> [DMESG-WARN][2] ([i915#592])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-skl-lmem/igt@i915_module_load@reload-no-display.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770: [PASS][3] -> [DMESG-FAIL][4] ([i915#563])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-hsw-4770/igt@i915_selftest@live_blt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-byt-n2820: [PASS][5] -> [DMESG-FAIL][6] ([i915#722])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-tgl-guc}: [INCOMPLETE][7] ([fdo#111735]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-tgl-guc/igt@gem_ctx_create@basic-files.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-tgl-guc/igt@gem_ctx_create@basic-files.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770: [DMESG-FAIL][9] ([i915#563]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-ivb-3770/igt@i915_selftest@live_blt.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-ivb-3770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-byt-j1900: [DMESG-FAIL][11] ([i915#722]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][13] ([fdo#111407]) -> [FAIL][14] ([fdo#111096] / [i915#323])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92]) -> [DMESG-WARN][16] ([i915#62] / [i915#92] / [i915#95]) +8 similar issues
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_flip@basic-flip-vs-modeset:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +6 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7481/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#710]: https://gitlab.freedesktop.org/drm/intel/issues/710
[i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
[i915#726]: https://gitlab.freedesktop.org/drm/intel/issues/726
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (54 -> 47)
------------------------------
Missing (7): fi-icl-1065g7 fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5325 -> IGTPW_3809
CI-20190529: 20190529
CI_DRM_7481: 7370e8bfcbb19757750dcf6ceb521c11c1d2ec27 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3809: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
IGT_5325: 7b7189e9f56c17cc810dd63ce767d4715288b05a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Testlist changes ==
+igt@gem_render_copy@linear-to-vebox-yf-tiled
+igt@gem_render_copy@linear-to-vebox-y-tiled
+igt@gem_render_copy@mixed-tiled-to-yf-tiled-ccs
+igt@gem_render_copy@mixed-tiled-to-y-tiled-ccs
+igt@gem_render_copy@x-tiled-to-vebox-yf-tiled
+igt@gem_render_copy@x-tiled-to-vebox-y-tiled
+igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled
+igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled
+igt@gem_render_copy@yf-tiled-to-vebox-linear
+igt@gem_render_copy@yf-tiled-to-vebox-x-tiled
+igt@gem_render_copy@yf-tiled-to-vebox-yf-tiled
+igt@gem_render_copy@yf-tiled-to-vebox-y-tiled
+igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-mc-ccs
+igt@gem_render_copy@y-tiled-ccs-to-y-tiled-mc-ccs
+igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-yf-tiled
+igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled
+igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs
+igt@gem_render_copy@y-tiled-mc-ccs-to-y-tiled-ccs
+igt@gem_render_copy@y-tiled-to-vebox-linear
+igt@gem_render_copy@y-tiled-to-vebox-x-tiled
+igt@gem_render_copy@y-tiled-to-vebox-yf-tiled
+igt@gem_render_copy@y-tiled-to-vebox-y-tiled
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3809/index.html
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