[PATCH v8 0/2] Sigma Designs Tango4 port

[PATCH v8 0/2] Sigma Designs Tango4 port

[Marc Gonzalez]

Hello,

I've added L2 cache enabling, and booting the second core (both via
smc calls to the firmware). I think all the "basic" features are now
supported. Future step will be adding drivers for peripheral devices.
(However, most of our drivers definitely do not meet the stringent
quality requirements of the Linux kernel, and are also not DT).

I'm hoping this patch set is close to being accepted :-)

Regards.


Marc Gonzalez (2):
  arm-soc: Import initial tango4 device tree
  arm-soc: Add support for arm-based tango4 platforms

 arch/arm/Kconfig                          |   2 +
 arch/arm/Makefile                         |   1 +
 arch/arm/boot/dts/Makefile                |   2 +
 arch/arm/boot/dts/tango4-common.dtsi      | 121 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/tango4-smp8758.dtsi     |  30 ++++++++
 arch/arm/boot/dts/tango4-vantage-1172.dts |  24 ++++++
 arch/arm/mach-tangox/Kconfig              |  12 +++
 arch/arm/mach-tangox/Makefile             |   2 +
 arch/arm/mach-tangox/setup.c              |  32 ++++++++
 arch/arm/mach-tangox/smc.S                |   9 +++
 arch/arm/mach-tangox/smc.h                |   5 ++
 11 files changed, 240 insertions(+)
 create mode 100644 arch/arm/boot/dts/tango4-common.dtsi
 create mode 100644 arch/arm/boot/dts/tango4-smp8758.dtsi
 create mode 100644 arch/arm/boot/dts/tango4-vantage-1172.dts
 create mode 100644 arch/arm/mach-tangox/Kconfig
 create mode 100644 arch/arm/mach-tangox/Makefile
 create mode 100644 arch/arm/mach-tangox/setup.c
 create mode 100644 arch/arm/mach-tangox/smc.S
 create mode 100644 arch/arm/mach-tangox/smc.h

-- 
2.4.5

[PATCH v8 1/2] arm-soc: Import initial tango4 device tree

[Marc Gonzalez]

This device tree was tested on a Sigma Designs SMP8758 Vantage-1172
development board.

Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
---
 arch/arm/boot/dts/Makefile                |   2 +
 arch/arm/boot/dts/tango4-common.dtsi      | 121 ++++++++++++++++++++++++++++++
 arch/arm/boot/dts/tango4-smp8758.dtsi     |  30 ++++++++
 arch/arm/boot/dts/tango4-vantage-1172.dts |  24 ++++++
 4 files changed, 177 insertions(+)
 create mode 100644 arch/arm/boot/dts/tango4-common.dtsi
 create mode 100644 arch/arm/boot/dts/tango4-smp8758.dtsi
 create mode 100644 arch/arm/boot/dts/tango4-vantage-1172.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 246473a244f6..2499295051d5 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -605,6 +605,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb
+dtb-$(CONFIG_ARCH_TANGOX) += \
+	tango4-vantage-1172.dtb
 dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
 	tegra20-harmony.dtb \
 	tegra20-iris-512.dtb \
diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi
new file mode 100644
index 000000000000..90e9a6e736ae
--- /dev/null
+++ b/arch/arm/boot/dts/tango4-common.dtsi
@@ -0,0 +1,121 @@
+/*
+ * Derived from Mans Rullgard's Tango3 DT
+ * https://github.com/mansr/linux-tangox
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	clocks {
+		ranges;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		xtal: xtal {
+			compatible = "fixed-clock";
+			clock-frequency = <27000000>;
+			#clock-cells = <0>;
+		};
+
+		clkgen: clkgen at 10000 {
+			compatible = "sigma,tango4-clkgen";
+			reg = <0x10000 0x40>;
+			clocks = <&xtal>;
+			clock-output-names = "cpuclk", "sysclk";
+			#clock-cells = <1>;
+		};
+	};
+
+	gic: interrupt-controller at 20001000 {
+		compatible = "arm,cortex-a9-gic";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0x20001000 0x1000>, <0x20000100 0x0100>;
+	};
+
+	l2cc: l2-cache-controller at 20100000 {
+		compatible = "arm,pl310-cache";
+		reg = <0x20100000 0x1000>;
+		cache-level = <2>;
+		cache-unified;
+	};
+
+	periphclk: periphclk {
+		compatible = "fixed-factor-clock";
+		clocks = <&clkgen 0>;
+		clock-mult = <1>;
+		clock-div  = <2>;
+		#clock-cells = <0>;
+	};
+
+	twd-timer at 20000600 {
+		compatible = "arm,cortex-a9-twd-timer";
+		reg = <0x20000600 0x10>;
+		interrupts = <GIC_PPI 13 0xf04>;
+		interrupt-parent = <&gic>;
+		clocks = <&periphclk>;
+		always-on;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		tick-counter at 10048 {
+			compatible = "sigma,tick-counter";
+			reg = <0x10048 0x4>;
+			clocks = <&xtal>;
+		};
+
+		uart: serial at 10700 {
+			compatible = "ralink,rt2880-uart";
+			reg = <0x10700 0x30>;
+			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&irq0>;
+			clock-frequency = <7372800>;
+			reg-shift = <2>;
+		};
+
+		eth0: ethernet at 26000 {
+			reg = <0x26000 0x800>;
+			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&irq0>;
+			clocks = <&clkgen 1>;
+		};
+
+		intc: interrupt-controller at 6e000 {
+			reg = <0x6e000 0x400>;
+			ranges = <0 0x6e000 0x400>;
+			interrupt-parent = <&gic>;
+			interrupt-controller;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			irq0: irq0 at 6e000 {
+				reg = <0x000 0x100>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			irq1: irq1 at 6e100 {
+				reg = <0x100 0x100>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			irq2: irq2 at 6e300 {
+				reg = <0x300 0x100>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/tango4-smp8758.dtsi b/arch/arm/boot/dts/tango4-smp8758.dtsi
new file mode 100644
index 000000000000..4eb23a12e27f
--- /dev/null
+++ b/arch/arm/boot/dts/tango4-smp8758.dtsi
@@ -0,0 +1,30 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "sigma,tango4-smp";
+
+		cpu0: cpu at 0 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <0>;
+		};
+
+		cpu1: cpu at 1 {
+			compatible = "arm,cortex-a9";
+			device_type = "cpu";
+			reg = <1>;
+		};
+	};
+
+	pmu {
+		compatible = "arm,cortex-a9-pmu";
+		interrupt-affinity = <&cpu0>, <&cpu1>;
+		interrupt-parent = <&gic>;
+		interrupts =
+			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+			<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+	};
+};
diff --git a/arch/arm/boot/dts/tango4-vantage-1172.dts b/arch/arm/boot/dts/tango4-vantage-1172.dts
new file mode 100644
index 000000000000..22de3624ed97
--- /dev/null
+++ b/arch/arm/boot/dts/tango4-vantage-1172.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+
+#include "tango4-smp8758.dtsi"
+#include "tango4-common.dtsi"
+
+/ {
+	model = "Sigma Designs SMP8758 Vantage-1172 dev board";
+	compatible = "sigma,vantage-1172", "sigma,smp8758", "sigma,tango4";
+
+	memory at 80000000 {
+		device_type = "memory";
+		reg = <0x80000000 0x80000000>; /* 2 GB */
+	};
+};
+
+&eth0 {
+	compatible = "sigma,smp8758-ethernet", "sigma,smp8734-ethernet", "sigma,smp8642-ethernet", "aurora,nb8800";
+	phy-connection-type = "rgmii";
+	max-speed = <1000>;
+};
+
+&intc {
+	compatible = "sigma,smp8758-intc", "sigma,smp8642-intc";
+};
-- 
2.4.5

[PATCH v8 2/2] arm-soc: Add support for arm-based tango4 platforms

[Marc Gonzalez]

Add support for Sigma Designs ARM-based Tango4 "Secure Media Processor"
platforms (i.e. smp8734, smp8756, smp8758, smp8759) built around the
Cortex-A9 MPCore r3p0 (dual-core SoCs, except the 8756).

Support for older MIPS-based platforms can be found elsewhere:
https://github.com/mansr/linux-tangox

Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
---
 arch/arm/Kconfig              |  2 ++
 arch/arm/Makefile             |  1 +
 arch/arm/mach-tangox/Kconfig  | 12 ++++++++++++
 arch/arm/mach-tangox/Makefile |  2 ++
 arch/arm/mach-tangox/setup.c  | 32 ++++++++++++++++++++++++++++++++
 arch/arm/mach-tangox/smc.S    |  9 +++++++++
 arch/arm/mach-tangox/smc.h    |  5 +++++
 7 files changed, 63 insertions(+)
 create mode 100644 arch/arm/mach-tangox/Kconfig
 create mode 100644 arch/arm/mach-tangox/Makefile
 create mode 100644 arch/arm/mach-tangox/setup.c
 create mode 100644 arch/arm/mach-tangox/smc.S
 create mode 100644 arch/arm/mach-tangox/smc.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 774dc59650c5..d8f0c31f521f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -934,6 +934,8 @@ source "arch/arm/mach-sunxi/Kconfig"
 
 source "arch/arm/mach-prima2/Kconfig"
 
+source "arch/arm/mach-tangox/Kconfig"
+
 source "arch/arm/mach-tegra/Kconfig"
 
 source "arch/arm/mach-u300/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 7451b447cc2d..7fcb4c63cdf7 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -203,6 +203,7 @@ machine-$(CONFIG_ARCH_SOCFPGA)		+= socfpga
 machine-$(CONFIG_ARCH_STI)		+= sti
 machine-$(CONFIG_ARCH_STM32)		+= stm32
 machine-$(CONFIG_ARCH_SUNXI)		+= sunxi
+machine-$(CONFIG_ARCH_TANGOX)		+= tangox
 machine-$(CONFIG_ARCH_TEGRA)		+= tegra
 machine-$(CONFIG_ARCH_U300)		+= u300
 machine-$(CONFIG_ARCH_U8500)		+= ux500
diff --git a/arch/arm/mach-tangox/Kconfig b/arch/arm/mach-tangox/Kconfig
new file mode 100644
index 000000000000..cf814d7336f3
--- /dev/null
+++ b/arch/arm/mach-tangox/Kconfig
@@ -0,0 +1,12 @@
+config ARCH_TANGOX
+	bool "Sigma Designs Tango4 (SMP87xx)" if ARCH_MULTI_V7
+	# Cortex-A9 MPCore r3p0, PL310 r3p2
+	select ARCH_HAS_HOLES_MEMORYMODEL
+	select ARM_ERRATA_754322
+	select ARM_ERRATA_764369 if SMP
+	select ARM_ERRATA_775420
+	select ARM_GIC
+	select CLKSRC_TANGO_XTAL
+	select GENERIC_IRQ_CHIP
+	select HAVE_ARM_SCU
+	select HAVE_ARM_TWD
diff --git a/arch/arm/mach-tangox/Makefile b/arch/arm/mach-tangox/Makefile
new file mode 100644
index 000000000000..0d7e2b5976e3
--- /dev/null
+++ b/arch/arm/mach-tangox/Makefile
@@ -0,0 +1,2 @@
+asflags-y += -mcpu=cortex-a9
+obj-y += setup.o smc.o
diff --git a/arch/arm/mach-tangox/setup.c b/arch/arm/mach-tangox/setup.c
new file mode 100644
index 000000000000..a90e04140a0e
--- /dev/null
+++ b/arch/arm/mach-tangox/setup.c
@@ -0,0 +1,32 @@
+#include <linux/smp.h>
+#include <asm/mach/arch.h>
+#include <asm/hardware/cache-l2x0.h>
+#include "smc.h"
+
+static int tango4_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	tango_set_aux_boot_addr(virt_to_phys(secondary_startup));
+	tango_start_aux_core();
+	return 0;
+}
+
+static struct smp_operations tango4_smp_ops __initdata = {
+	.smp_boot_secondary	= tango4_boot_secondary,
+};
+
+CPU_METHOD_OF_DECLARE(tango4_smp, "sigma,tango4-smp", &tango4_smp_ops);
+
+static void tango_l2c_write(unsigned long val, unsigned int reg)
+{
+	pr_debug("%s: reg=0x%x val=0x%lx\n", __func__, reg, val);
+	if (reg == L2X0_CTRL)
+		tango_set_l2_control(val);
+}
+
+static const char *tango_dt_compat[] = { "sigma,tango4", NULL };
+
+DT_MACHINE_START(TANGO_DT, "Sigma Tango DT")
+	.dt_compat	= tango_dt_compat,
+	.l2c_aux_mask	= ~0,
+	.l2c_write_sec	= tango_l2c_write,
+MACHINE_END
diff --git a/arch/arm/mach-tangox/smc.S b/arch/arm/mach-tangox/smc.S
new file mode 100644
index 000000000000..35f9623aedb1
--- /dev/null
+++ b/arch/arm/mach-tangox/smc.S
@@ -0,0 +1,9 @@
+#include <linux/linkage.h>
+
+ENTRY(tango_smc)
+	push	{lr}
+	mov	ip, r1
+	dsb
+	smc	#0
+	pop	{pc}
+ENDPROC(tango_smc)
diff --git a/arch/arm/mach-tangox/smc.h b/arch/arm/mach-tangox/smc.h
new file mode 100644
index 000000000000..4e704dcf8da8
--- /dev/null
+++ b/arch/arm/mach-tangox/smc.h
@@ -0,0 +1,5 @@
+extern int tango_smc(unsigned int val, unsigned int service);
+
+#define tango_set_l2_control(val)	tango_smc(val, 0x102)
+#define tango_start_aux_core()		tango_smc(666, 0x104)
+#define tango_set_aux_boot_addr(val)	tango_smc((unsigned int)val, 0x105)
-- 
2.4.5

[PATCH v8 0/2] Sigma Designs Tango4 port

[Marc Gonzalez]

And here's the boot log I get with the submitted code:

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.2.0+ (mgonzalez at summerrain) (gcc version 4.9.3 20141031 (prerelease) (Linaro GCC 2014.11) ) #303 SMP PREEMPT Mon Nov 2 16:27:25 CET 2015
[    0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[    0.000000] Machine model: Sigma Designs SMP8758 Vantage-1172 dev board
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] On node 0 totalpages: 163840
[    0.000000] free_area_init_node: node 0, pgdat c0374640, node_mem_map e7afa000
[    0.000000]   Normal zone: 1280 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 163840 pages, LIFO batch:31
[    0.000000] PERCPU: Embedded 10 pages/cpu @e7ade000 s9152 r8192 d23616 u40960
[    0.000000] pcpu-alloc: s9152 r8192 d23616 u40960 alloc=10*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1 
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 162560
[    0.000000] Kernel command line: ip=dhcp root=/dev/nfs rdinit=/none console=ttyS0,115200 mem=640M debug
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
[    0.000000] Memory: 645572K/655360K available (2531K kernel code, 84K rwdata, 728K rodata, 160K init, 218K bss, 9788K reserved, 0K cma-reserved, 0K highmem)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
[    0.000000]     vmalloc : 0xe8800000 - 0xff000000   ( 360 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xe8000000   ( 640 MB)
[    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
[    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)
[    0.000000]       .text : 0xc0008000 - 0xc033702c   (3261 kB)
[    0.000000]       .init : 0xc0338000 - 0xc0360000   ( 160 kB)
[    0.000000]       .data : 0xc0360000 - 0xc03752c0   (  85 kB)
[    0.000000]        .bss : 0xc03752c0 - 0xc03abe50   ( 219 kB)
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  Build-time adjustment of leaf fanout to 32.
[    0.000000]  RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] L2C-310 enabling early BRESP for Cortex-A9
[    0.000000] L2C-310 ID prefetch enabled, offset 4 lines
[    0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled
[    0.000000] L2C-310 cache controller enabled, 8 ways, 512 kB
[    0.000000] L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x72860401
[    0.000000] clocksource: tango-xtal: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 70787423951 ns
[    0.000004] sched_clock: 32 bits at 27MHz, resolution 37ns, wraps every 79536431085ns
[    0.000014] Switching to timer-based delay loop, resolution 37ns
[    0.000276] Console: colour dummy device 80x30
[    0.000296] Calibrating delay loop (skipped), value calculated using timer frequency.. 54.25 BogoMIPS (lpj=90000)
[    0.000307] pid_max: default: 32768 minimum: 301
[    0.000426] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000434] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[    0.000883] CPU: Testing write buffer coherency: ok
[    0.001097] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[    0.001152] Setting up static identity map for 0x80008280 - 0x800082b4
[    0.010308] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[    0.010364] Brought up 2 CPUs
[    0.010377] SMP: Total of 2 processors activated (108.50 BogoMIPS).
[    0.010383] CPU: All CPU(s) started in SVC mode.
[    0.010814] devtmpfs: initialized
[    0.014256] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[    0.014689] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 6370867519511994 ns
[    0.015140] NET: Registered protocol family 16
[    0.015894] DMA: preallocated 256 KiB pool for atomic coherent allocations
[    0.017808] hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
[    0.017821] hw-breakpoint: maximum watchpoint size is 4 bytes.
[    0.024985] clocksource: Switched to clocksource tango-xtal
[    0.034805] NET: Registered protocol family 2
[    0.035633] TCP established hash table entries: 8192 (order: 3, 32768 bytes)
[    0.035768] TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
[    0.035867] TCP: Hash tables configured (established 8192 bind 8192)
[    0.035995] UDP hash table entries: 512 (order: 2, 16384 bytes)
[    0.036044] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[    0.036305] NET: Registered protocol family 1
[    0.036581] RPC: Registered named UNIX socket transport module.
[    0.036589] RPC: Registered udp transport module.
[    0.036595] RPC: Registered tcp transport module.
[    0.036600] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    0.036715] NetWinder Floating Point Emulator V0.97 (double precision)
[    0.036860] hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
[    0.037969] futex hash table entries: 512 (order: 3, 32768 bytes)
[    0.080837] Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled
[    0.082049] console [ttyS0] disabled
[    0.082169] 10700.serial: ttyS0 at MMIO 0x10700 (irq = 18, base_baud = 460800) is a Palmchip BK-3103
[    0.586997] console [ttyS0] enabled
[    0.591384] tangox-enet 26000.ethernet: SMP86xx internal Ethernet at 0x26000
[    0.601390] libphy: tangox-mii: probed
[    0.665161] tangox-enet 26000.ethernet: PHY: found Atheros 8035 ethernet at 0x4
[    0.675815] tangox-enet 26000.ethernet eth0: MAC address 00:16:e8:02:08:42
[    0.683155] NET: Registered protocol family 17
[    0.687714] ThumbEE CPU extension supported.
[    0.692030] Registering SWP/SWPB emulation handler
[    1.211659] Sending DHCP requests ..
[    4.678605] tangox-enet 26000.ethernet eth0: Link is Up - 1Gbps/Full - flow control rx/tx
[    8.811641] ., OK
[    8.831647] IP-Config: Got DHCP answer from 172.27.200.1, my address is 172.27.64.49
[    8.839659] IP-Config: Complete: (snip)
[    8.885469] VFS: Mounted root (nfs filesystem) readonly on device 0:12.
[    8.892390] Freeing unused kernel memory: 160K (c0338000 - c0360000)
                                                  
Regards.

[PATCH v8 1/2] arm-soc: Import initial tango4 device tree

[Måns Rullgård]

Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes:

> This device tree was tested on a Sigma Designs SMP8758 Vantage-1172
> development board.
>
> Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
> ---
>  arch/arm/boot/dts/Makefile                |   2 +
>  arch/arm/boot/dts/tango4-common.dtsi      | 121 ++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/tango4-smp8758.dtsi     |  30 ++++++++
>  arch/arm/boot/dts/tango4-vantage-1172.dts |  24 ++++++
>  4 files changed, 177 insertions(+)
>  create mode 100644 arch/arm/boot/dts/tango4-common.dtsi
>  create mode 100644 arch/arm/boot/dts/tango4-smp8758.dtsi
>  create mode 100644 arch/arm/boot/dts/tango4-vantage-1172.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 246473a244f6..2499295051d5 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -605,6 +605,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>  dtb-$(CONFIG_MACH_SUN9I) += \
>  	sun9i-a80-optimus.dtb \
>  	sun9i-a80-cubieboard4.dtb
> +dtb-$(CONFIG_ARCH_TANGOX) += \
> +	tango4-vantage-1172.dtb
>  dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
>  	tegra20-harmony.dtb \
>  	tegra20-iris-512.dtb \
> diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi
> new file mode 100644
> index 000000000000..90e9a6e736ae
> --- /dev/null
> +++ b/arch/arm/boot/dts/tango4-common.dtsi
> @@ -0,0 +1,121 @@
> +/*
> + * Derived from Mans Rullgard's Tango3 DT
> + * https://github.com/mansr/linux-tangox
> + */

Why don't you take the tango4 one from the same repo?

> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	clocks {
> +		ranges;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		xtal: xtal {
> +			compatible = "fixed-clock";
> +			clock-frequency = <27000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		clkgen: clkgen at 10000 {
> +			compatible = "sigma,tango4-clkgen";
> +			reg = <0x10000 0x40>;
> +			clocks = <&xtal>;
> +			clock-output-names = "cpuclk", "sysclk";
> +			#clock-cells = <1>;
> +		};

There are about a dozen more clocks that will be needed eventually.  Do
you have a plan for how to add them?  (My driver already has support for
most of them.)

> +	};
> +
> +	gic: interrupt-controller at 20001000 {
> +		compatible = "arm,cortex-a9-gic";
> +		interrupt-controller;
> +		#interrupt-cells = <3>;
> +		reg = <0x20001000 0x1000>, <0x20000100 0x0100>;
> +	};
> +
> +	l2cc: l2-cache-controller at 20100000 {
> +		compatible = "arm,pl310-cache";
> +		reg = <0x20100000 0x1000>;
> +		cache-level = <2>;
> +		cache-unified;
> +	};
> +
> +	periphclk: periphclk {

Why is this not in the clocks block above?

> +		compatible = "fixed-factor-clock";
> +		clocks = <&clkgen 0>;
> +		clock-mult = <1>;
> +		clock-div  = <2>;

Some Sigma source code I found on the Internet uses a divisor of 3.
Which is correct?

> +		#clock-cells = <0>;
> +	};
> +
> +	twd-timer at 20000600 {
> +		compatible = "arm,cortex-a9-twd-timer";
> +		reg = <0x20000600 0x10>;
> +		interrupts = <GIC_PPI 13 0xf04>;
> +		interrupt-parent = <&gic>;
> +		clocks = <&periphclk>;
> +		always-on;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges;

Put interrupt-parent = <&irq0> here and save repeating it for each device.

> +		tick-counter at 10048 {
> +			compatible = "sigma,tick-counter";

This compatible name is too vague.  What if the next Sigma chip has a
completely different counter?

> +			reg = <0x10048 0x4>;
> +			clocks = <&xtal>;
> +		};
> +
> +		uart: serial at 10700 {
> +			compatible = "ralink,rt2880-uart";
> +			reg = <0x10700 0x30>;
> +			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-parent = <&irq0>;
> +			clock-frequency = <7372800>;
> +			reg-shift = <2>;
> +		};
> +
> +		eth0: ethernet at 26000 {
> +			reg = <0x26000 0x800>;
> +			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-parent = <&irq0>;
> +			clocks = <&clkgen 1>;
> +		};

Missing compatible string.

> +		intc: interrupt-controller at 6e000 {
> +			reg = <0x6e000 0x400>;
> +			ranges = <0 0x6e000 0x400>;
> +			interrupt-parent = <&gic>;
> +			interrupt-controller;
> +			#address-cells = <1>;
> +			#size-cells = <1>;

Missing compatible string.

> +			irq0: irq0 at 6e000 {

The node name should be interrupt-controller at 000, similarly below.

> +				reg = <0x000 0x100>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			irq1: irq1 at 6e100 {
> +				reg = <0x100 0x100>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			irq2: irq2 at 6e300 {
> +				reg = <0x300 0x100>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/tango4-smp8758.dtsi b/arch/arm/boot/dts/tango4-smp8758.dtsi
> new file mode 100644
> index 000000000000..4eb23a12e27f
> --- /dev/null
> +++ b/arch/arm/boot/dts/tango4-smp8758.dtsi
> @@ -0,0 +1,30 @@
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		enable-method = "sigma,tango4-smp";

This enable-method is too vague.  The next chip might be different.

> +		cpu0: cpu at 0 {
> +			compatible = "arm,cortex-a9";
> +			device_type = "cpu";
> +			reg = <0>;
> +		};
> +
> +		cpu1: cpu at 1 {
> +			compatible = "arm,cortex-a9";
> +			device_type = "cpu";
> +			reg = <1>;
> +		};
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a9-pmu";
> +		interrupt-affinity = <&cpu0>, <&cpu1>;
> +		interrupt-parent = <&gic>;
> +		interrupts =
> +			<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
> +			<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +	};
> +};

The device tree should mention the SCU.

> diff --git a/arch/arm/boot/dts/tango4-vantage-1172.dts b/arch/arm/boot/dts/tango4-vantage-1172.dts
> new file mode 100644
> index 000000000000..22de3624ed97
> --- /dev/null
> +++ b/arch/arm/boot/dts/tango4-vantage-1172.dts
> @@ -0,0 +1,24 @@
> +/dts-v1/;
> +
> +#include "tango4-smp8758.dtsi"
> +#include "tango4-common.dtsi"
> +
> +/ {
> +	model = "Sigma Designs SMP8758 Vantage-1172 dev board";
> +	compatible = "sigma,vantage-1172", "sigma,smp8758", "sigma,tango4";
> +
> +	memory at 80000000 {
> +		device_type = "memory";
> +		reg = <0x80000000 0x80000000>; /* 2 GB */
> +	};
> +};
> +
> +&eth0 {
> +	compatible = "sigma,smp8758-ethernet", "sigma,smp8734-ethernet", "sigma,smp8642-ethernet", "aurora,nb8800";

It's odd to specify the compatible string here.  It certainly won't
change between different boards using the same chip.  Also, in the
latest version of my driver, tango3 and tango4 are unfortunately not
compatible.  The incompatibility only showed up once I enabled the L2
cache.  I don't know quite what's going on.

> +	phy-connection-type = "rgmii";
> +	max-speed = <1000>;

You should have a node for the PHY here.

> +};
> +
> +&intc {
> +	compatible = "sigma,smp8758-intc", "sigma,smp8642-intc";

Wrong place for the compatible string.

> +};

-- 
M?ns Rullg?rd
mans at mansr.com

[PATCH v8 2/2] arm-soc: Add support for arm-based tango4 platforms

[Måns Rullgård]

Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes:

> diff --git a/arch/arm/mach-tangox/setup.c b/arch/arm/mach-tangox/setup.c
> new file mode 100644
> index 000000000000..a90e04140a0e
> --- /dev/null
> +++ b/arch/arm/mach-tangox/setup.c
> @@ -0,0 +1,32 @@
> +#include <linux/smp.h>
> +#include <asm/mach/arch.h>
> +#include <asm/hardware/cache-l2x0.h>
> +#include "smc.h"
> +
> +static int tango4_boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> +	tango_set_aux_boot_addr(virt_to_phys(secondary_startup));
> +	tango_start_aux_core();
> +	return 0;
> +}
> +
> +static struct smp_operations tango4_smp_ops __initdata = {
> +	.smp_boot_secondary	= tango4_boot_secondary,
> +};
> +
> +CPU_METHOD_OF_DECLARE(tango4_smp, "sigma,tango4-smp", &tango4_smp_ops);

Unless I'm missing something, you should enable the SCU before starting
secondary CPUs.  It's also a good idea to structure the code with
separate prepare and boot functions even if all the current chips are
only dual-core.

> +static void tango_l2c_write(unsigned long val, unsigned int reg)
> +{
> +	pr_debug("%s: reg=0x%x val=0x%lx\n", __func__, reg, val);
> +	if (reg == L2X0_CTRL)
> +		tango_set_l2_control(val);

What about other registers?  Does the firmware support setting the
prefetch control register?

> +}
> +
> +static const char *tango_dt_compat[] = { "sigma,tango4", NULL };
> +
> +DT_MACHINE_START(TANGO_DT, "Sigma Tango DT")
> +	.dt_compat	= tango_dt_compat,
> +	.l2c_aux_mask	= ~0,
> +	.l2c_write_sec	= tango_l2c_write,
> +MACHINE_END
> diff --git a/arch/arm/mach-tangox/smc.S b/arch/arm/mach-tangox/smc.S
> new file mode 100644
> index 000000000000..35f9623aedb1
> --- /dev/null
> +++ b/arch/arm/mach-tangox/smc.S
> @@ -0,0 +1,9 @@
> +#include <linux/linkage.h>
> +
> +ENTRY(tango_smc)
> +	push	{lr}
> +	mov	ip, r1
> +	dsb

Did you ever get a straight answer on the dsb here?

> +	smc	#0
> +	pop	{pc}
> +ENDPROC(tango_smc)
> diff --git a/arch/arm/mach-tangox/smc.h b/arch/arm/mach-tangox/smc.h
> new file mode 100644
> index 000000000000..4e704dcf8da8
> --- /dev/null
> +++ b/arch/arm/mach-tangox/smc.h
> @@ -0,0 +1,5 @@
> +extern int tango_smc(unsigned int val, unsigned int service);
> +
> +#define tango_set_l2_control(val)	tango_smc(val, 0x102)
> +#define tango_start_aux_core()		tango_smc(666, 0x104)

666?

> +#define tango_set_aux_boot_addr(val)	tango_smc((unsigned int)val, 0x105)
> -- 
> 2.4.5

-- 
M?ns Rullg?rd
mans at mansr.com

[PATCH v8 1/2] arm-soc: Import initial tango4 device tree

[Marc Gonzalez]

On 02/11/2015 17:01, M?ns Rullg?rd wrote:

> There are about a dozen more clocks that will be needed eventually.  Do
> you have a plan for how to add them?  (My driver already has support for
> most of them.)

Can you tell me which clocks (for which device) you've needed on the smp8759?

>> +	periphclk: periphclk {
> 
> Why is this not in the clocks block above?

It was something the clk maintainer said that made me move it, but I can't
find it anymore. I can move it back if that's the consensus.

>> +		compatible = "fixed-factor-clock";
>> +		clocks = <&clkgen 0>;
>> +		clock-mult = <1>;
>> +		clock-div  = <2>;
> 
> Some Sigma source code I found on the Internet uses a divisor of 3.
> Which is correct?

I was told 2.

>> +	soc {
>> +		compatible = "simple-bus";
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
> 
> Put interrupt-parent = <&irq0> here and save repeating it for each device.

Each device can have either irq0, irq1, or irq2 as the parent, right?
The old code tried to do IRQ load-balancing "by hand". I had the vague
idea that I would set some devices to irq0, others to irq1, and have
irq_i interrupt CPU_i. Does that make no sense?

>> +		tick-counter at 10048 {
>> +			compatible = "sigma,tick-counter";
> 
> This compatible name is too vague.  What if the next Sigma chip has a
> completely different counter?

When this happens, I could switch to the generic method you've proposed.

>> +		eth0: ethernet at 26000 {
>> +			reg = <0x26000 0x800>;
>> +			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-parent = <&irq0>;
>> +			clocks = <&clkgen 1>;
>> +		};
> 
> Missing compatible string.

It's not missing, it's elsewhere.
(But maybe I did it wrong.)

>> +		intc: interrupt-controller at 6e000 {
>> +			reg = <0x6e000 0x400>;
>> +			ranges = <0 0x6e000 0x400>;
>> +			interrupt-parent = <&gic>;
>> +			interrupt-controller;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
> 
> Missing compatible string.
> 
>> +			irq0: irq0 at 6e000 {
> 
> The node name should be interrupt-controller at 000, similarly below.

<confused> I changed that a long time ago, and Arnd didn't flag it.
I'll put whatever the arm-soc maintainers say.

>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +		enable-method = "sigma,tango4-smp";
> 
> This enable-method is too vague.  The next chip might be different.

What string do you propose?
What if I don't expect any other tango4 chip?

> The device tree should mention the SCU.

I left it out because I thought it was the firmware's responsibility.
I will double-check with the firmware author.

>> +&eth0 {
>> +	compatible = "sigma,smp8758-ethernet", "sigma,smp8734-ethernet", "sigma,smp8642-ethernet", "aurora,nb8800";
> 
> It's odd to specify the compatible string here.  It certainly won't
> change between different boards using the same chip.  Also, in the
> latest version of my driver, tango3 and tango4 are unfortunately not
> compatible.  The incompatibility only showed up once I enabled the L2
> cache.  I don't know quite what's going on.

IIUC, I should move the compatible string to the SoC-specific DTS?
And I should remove "sigma,smp8642-ethernet"?

>> +	phy-connection-type = "rgmii";
>> +	max-speed = <1000>;
> 
> You should have a node for the PHY here.

I'm using your old ethernet driver for the time being. I just compile the
appropriate PHY driver, and everything works as expected. What will the
PHY node in DT bring?

>> +&intc {
>> +	compatible = "sigma,smp8758-intc", "sigma,smp8642-intc";
> 
> Wrong place for the compatible string.

IIUC, I should move the compatible string to the SoC-specific DTS?

Regards.

[PATCH v8 2/2] arm-soc: Add support for arm-based tango4 platforms

[Marc Gonzalez]

On 02/11/2015 17:22, M?ns Rullg?rd wrote:

> Unless I'm missing something, you should enable the SCU before starting
> secondary CPUs.  It's also a good idea to structure the code with
> separate prepare and boot functions even if all the current chips are
> only dual-core.

About the SCU: I will check with the firmware author.
About prepare: this is the firmware's responsibility.
(Not all chips are dual-core, the 8756 is single-core.)

> What about other registers?  Does the firmware support setting the
> prefetch control register?

Yes, after masking out some bits.
My port uses the firmware-supplied value.

Regards.

[PATCH v8 1/2] arm-soc: Import initial tango4 device tree

[Måns Rullgård]

Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes:

> On 02/11/2015 17:01, M?ns Rullg?rd wrote:
>
>> There are about a dozen more clocks that will be needed eventually.  Do
>> you have a plan for how to add them?  (My driver already has support for
>> most of them.)
>
> Can you tell me which clocks (for which device) you've needed on the smp8759?

For the bare minimum functionality, none.  If you want USB or SATA,
you'll need those clocks defined.  All the media processing has a slew
of clocks as well.

>>> +	periphclk: periphclk {
>> 
>> Why is this not in the clocks block above?
>
> It was something the clk maintainer said that made me move it, but I can't
> find it anymore. I can move it back if that's the consensus.

Wait and see what others say.

>>> +		compatible = "fixed-factor-clock";
>>> +		clocks = <&clkgen 0>;
>>> +		clock-mult = <1>;
>>> +		clock-div  = <2>;
>> 
>> Some Sigma source code I found on the Internet uses a divisor of 3.
>> Which is correct?
>
> I was told 2.

OK.

>>> +	soc {
>>> +		compatible = "simple-bus";
>>> +		#address-cells = <1>;
>>> +		#size-cells = <1>;
>>> +		ranges;
>> 
>> Put interrupt-parent = <&irq0> here and save repeating it for each device.
>
> Each device can have either irq0, irq1, or irq2 as the parent, right?
> The old code tried to do IRQ load-balancing "by hand". I had the vague
> idea that I would set some devices to irq0, others to irq1, and have
> irq_i interrupt CPU_i. Does that make no sense?

Which devices to assign to which CPU would depend on the expected usage,
something only known at the board level at best.  I think it's better to
have them all default to irq0 here and let boards override if necessary.

>>> +		tick-counter at 10048 {
>>> +			compatible = "sigma,tick-counter";
>> 
>> This compatible name is too vague.  What if the next Sigma chip has a
>> completely different counter?
>
> When this happens, I could switch to the generic method you've proposed.

This name would still become misleading, and you're not allowed to
change a DT binding incompatibly once it's been established.

>>> +		eth0: ethernet at 26000 {
>>> +			reg = <0x26000 0x800>;
>>> +			interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
>>> +			interrupt-parent = <&irq0>;
>>> +			clocks = <&clkgen 1>;
>>> +		};
>> 
>> Missing compatible string.
>
> It's not missing, it's elsewhere.
> (But maybe I did it wrong.)
>
>>> +		intc: interrupt-controller at 6e000 {
>>> +			reg = <0x6e000 0x400>;
>>> +			ranges = <0 0x6e000 0x400>;
>>> +			interrupt-parent = <&gic>;
>>> +			interrupt-controller;
>>> +			#address-cells = <1>;
>>> +			#size-cells = <1>;
>> 
>> Missing compatible string.
>> 
>>> +			irq0: irq0 at 6e000 {
>> 
>> The node name should be interrupt-controller at 000, similarly below.
>
> <confused> I changed that a long time ago, and Arnd didn't flag it.
> I'll put whatever the arm-soc maintainers say.

They usually point to the ePAPR spec, which says interrupt controller
nodes should be called interrupt-controller@<addr>.  It also says the
<addr> following the @ should be the same as the first <reg> address,
which here is the offset from the base address.

>>> +	cpus {
>>> +		#address-cells = <1>;
>>> +		#size-cells = <0>;
>>> +		enable-method = "sigma,tango4-smp";
>> 
>> This enable-method is too vague.  The next chip might be different.
>
> What string do you propose?
> What if I don't expect any other tango4 chip?

Expectations are often wrong.  Use an actual chip number.

>> The device tree should mention the SCU.
>
> I left it out because I thought it was the firmware's responsibility.
> I will double-check with the firmware author.

It's still there, and the kernel might want to at least check how it's
configured.

>>> +&eth0 {
>>> +	compatible = "sigma,smp8758-ethernet", "sigma,smp8734-ethernet", "sigma,smp8642-ethernet", "aurora,nb8800";
>> 
>> It's odd to specify the compatible string here.  It certainly won't
>> change between different boards using the same chip.  Also, in the
>> latest version of my driver, tango3 and tango4 are unfortunately not
>> compatible.  The incompatibility only showed up once I enabled the L2
>> cache.  I don't know quite what's going on.
>
> IIUC, I should move the compatible string to the SoC-specific DTS?
> And I should remove "sigma,smp8642-ethernet"?
>
>>> +	phy-connection-type = "rgmii";
>>> +	max-speed = <1000>;
>> 
>> You should have a node for the PHY here.
>
> I'm using your old ethernet driver for the time being. I just compile the
> appropriate PHY driver, and everything works as expected. What will the
> PHY node in DT bring?

The new driver requires it for starters.  Also, the probing acts oddly
on my 8642 board, so it's probably best to avoid.

>>> +&intc {
>>> +	compatible = "sigma,smp8758-intc", "sigma,smp8642-intc";
>> 
>> Wrong place for the compatible string.
>
> IIUC, I should move the compatible string to the SoC-specific DTS?
>
> Regards.
>

-- 
M?ns Rullg?rd
mans at mansr.com

[PATCH v8 2/2] arm-soc: Add support for arm-based tango4 platforms

[Måns Rullgård]

Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes:

> On 02/11/2015 17:22, M?ns Rullg?rd wrote:
>
>> Unless I'm missing something, you should enable the SCU before starting
>> secondary CPUs.  It's also a good idea to structure the code with
>> separate prepare and boot functions even if all the current chips are
>> only dual-core.
>
> About the SCU: I will check with the firmware author.
> About prepare: this is the firmware's responsibility.
> (Not all chips are dual-core, the 8756 is single-core.)

Then the DT should say so.

Rule 0: never trust the firmware.

>> What about other registers?  Does the firmware support setting the
>> prefetch control register?
>
> Yes, after masking out some bits.

Then you should provide the kernel with a means of doing that.  Is the
SMC ID from OMAP4 correct?

-- 
M?ns Rullg?rd
mans at mansr.com

[PATCH v8 2/2] arm-soc: Add support for arm-based tango4 platforms

[Mark Rutland]

> > +ENTRY(tango_smc)
> > +	push	{lr}
> > +	mov	ip, r1
> > +	dsb
> 
> Did you ever get a straight answer on the dsb here?

We didn't. Having a look just now, the earliest example appears to be
in OMAP4 L2 support patches back in 2009 [1]. I was not able to find a
rationale.

Given that the MMU is on (and speculative accesses are permitted) I
can't see what the DSB achieves -- it can't quiesce the memory system.

Santosh, any idea?

Thanks,
Mark.

> > +	smc	#0
> > +	pop	{pc}
> > +ENDPROC(tango_smc)

[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2009-December/005815.html

[PATCH v8 2/2] arm-soc: Add support for arm-based tango4 platforms

[Måns Rullgård]

Mark Rutland <mark.rutland@arm.com> writes:

>> > +ENTRY(tango_smc)
>> > +	push	{lr}
>> > +	mov	ip, r1
>> > +	dsb
>> 
>> Did you ever get a straight answer on the dsb here?
>
> We didn't. Having a look just now, the earliest example appears to be
> in OMAP4 L2 support patches back in 2009 [1]. I was not able to find a
> rationale.

My guess is it was added out of frustration during early OMAP
development and forgotten.  Then it became cargo cult.

-- 
M?ns Rullg?rd
mans at mansr.com

[PATCH v8 2/2] arm-soc: Add support for arm-based tango4 platforms

[santosh shilimkar]

On 11/2/2015 10:26 AM, Mark Rutland wrote:
>>> +ENTRY(tango_smc)
>>> +	push	{lr}
>>> +	mov	ip, r1
>>> +	dsb
>>
>> Did you ever get a straight answer on the dsb here?
>
> We didn't. Having a look just now, the earliest example appears to be
> in OMAP4 L2 support patches back in 2009 [1]. I was not able to find a
> rationale.
>
> Given that the MMU is on (and speculative accesses are permitted) I
> can't see what the DSB achieves -- it can't quiesce the memory system.
>
> Santosh, any idea?
>
IIRC, it was requirement from the OMAP ROM code to have a dsb before
we call the SMC routine. I can't recollect more than that now.

Regards,
Santosh

[PATCH v8 1/2] arm-soc: Import initial tango4 device tree

[Florian Fainelli]

On 02/11/15 07:18, Marc Gonzalez wrote:
> This device tree was tested on a Sigma Designs SMP8758 Vantage-1172
> development board.
> 
> Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com>
> ---
>  arch/arm/boot/dts/Makefile                |   2 +
>  arch/arm/boot/dts/tango4-common.dtsi      | 121 ++++++++++++++++++++++++++++++
>  arch/arm/boot/dts/tango4-smp8758.dtsi     |  30 ++++++++
>  arch/arm/boot/dts/tango4-vantage-1172.dts |  24 ++++++
>  4 files changed, 177 insertions(+)
>  create mode 100644 arch/arm/boot/dts/tango4-common.dtsi
>  create mode 100644 arch/arm/boot/dts/tango4-smp8758.dtsi
>  create mode 100644 arch/arm/boot/dts/tango4-vantage-1172.dts

Since you are introducing DTS with compatible strings etc. you need to
document these in Documentation/devicetree/bindings/ as well for people
to know how to write their own for their Tango4-based designs.

> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 246473a244f6..2499295051d5 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -605,6 +605,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
>  dtb-$(CONFIG_MACH_SUN9I) += \
>  	sun9i-a80-optimus.dtb \
>  	sun9i-a80-cubieboard4.dtb
> +dtb-$(CONFIG_ARCH_TANGOX) += \
> +	tango4-vantage-1172.dtb
>  dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
>  	tegra20-harmony.dtb \
>  	tegra20-iris-512.dtb \
> diff --git a/arch/arm/boot/dts/tango4-common.dtsi b/arch/arm/boot/dts/tango4-common.dtsi
> new file mode 100644
> index 000000000000..90e9a6e736ae
> --- /dev/null
> +++ b/arch/arm/boot/dts/tango4-common.dtsi
> @@ -0,0 +1,121 @@
> +/*
> + * Derived from Mans Rullgard's Tango3 DT
> + * https://github.com/mansr/linux-tangox
> + */

Most DTSes these days contain a proper license, typically BSD, yours
should have one too.

> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	clocks {
> +		ranges;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +
> +		xtal: xtal {
> +			compatible = "fixed-clock";
> +			clock-frequency = <27000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		clkgen: clkgen at 10000 {
> +			compatible = "sigma,tango4-clkgen";
> +			reg = <0x10000 0x40>;
> +			clocks = <&xtal>;
> +			clock-output-names = "cpuclk", "sysclk";
> +			#clock-cells = <1>;
> +		};
> +	};

Do not you have some sort of internal bus/bridge which maps these ARM
peripherals to your SoC? You have a simple-bus node later on for your
internal and own IPs, it would seem logical to have such a thing here as
well for these ARM peripherals.

[snip]

> diff --git a/arch/arm/boot/dts/tango4-smp8758.dtsi b/arch/arm/boot/dts/tango4-smp8758.dtsi
> new file mode 100644
> index 000000000000..4eb23a12e27f
> --- /dev/null
> +++ b/arch/arm/boot/dts/tango4-smp8758.dtsi
> @@ -0,0 +1,30 @@
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		enable-method = "sigma,tango4-smp";
> +
> +		cpu0: cpu at 0 {
> +			compatible = "arm,cortex-a9";
> +			device_type = "cpu";
> +			reg = <0>;

Missing next-level-cache property and 'enable-method' property.
-- 
Florian

[PATCH v8 0/2] Sigma Designs Tango4 port

[Arnd Bergmann]

On Monday 02 November 2015 16:17:10 Marc Gonzalez wrote:
> Hello,
> 
> I've added L2 cache enabling, and booting the second core (both via
> smc calls to the firmware). I think all the "basic" features are now
> supported. Future step will be adding drivers for peripheral devices.
> (However, most of our drivers definitely do not meet the stringent
> quality requirements of the Linux kernel, and are also not DT).
> 
> I'm hoping this patch set is close to being accepted 
> 

Hi Marc,

Just to let you know about the process: The merge window is now
open, which means we are absolutely not accepting any new features
for Linux-4.4 any more but just push whatever we have in the arm-soc
tree (plus fixes for bugs we find) to Linus.

We will start merging new features after 4.4-rc1 is out, sometimes
it takes a little while before we get started. It should be no
problem to get your patches merged for 4.5 then.

	Arnd

[PATCH v8 1/2] arm-soc: Import initial tango4 device tree

[Måns Rullgård]

Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes:

>>> +		compatible = "fixed-factor-clock";
>>> +		clocks = <&clkgen 0>;
>>> +		clock-mult = <1>;
>>> +		clock-div  = <2>;
>> 
>> Some Sigma source code I found on the Internet uses a divisor of 3.
>> Which is correct?
>
> I was told 2.

Just to be sure, I measured it.  It's 2.

-- 
M?ns Rullg?rd
mans at mansr.com

[PATCH v8 2/2] arm-soc: Add support for arm-based tango4 platforms

[Marc Gonzalez]

Santosh Shilimkar wrote:

> Mark Rutland wrote:
> 
>> We didn't. Having a look just now, the earliest example appears to be
>> in OMAP4 L2 support patches back in 2009 [1]. I was not able to find a
>> rationale.
>> 
>> Given that the MMU is on (and speculative accesses are permitted) I
>> can't see what the DSB achieves -- it can't quiesce the memory system.
>> 
>> Santosh, any idea?
>
> IIRC, it was requirement from the OMAP ROM code to have a dsb before
> we call the SMC routine. I can't recollect more than that now.

In that case, shouldn't dsb have been added to the ROM code,
on the "other side" of the smc, so as to not depend on Linux
code "getting it right"?

Regards.

[PATCH v8 0/2] Sigma Designs Tango4 port

[Marc Gonzalez]

On 02/11/2015 22:40, Arnd Bergmann wrote:

> Just to let you know about the process: The merge window is now
> open, which means we are absolutely not accepting any new features
> for Linux-4.4 any more but just push whatever we have in the arm-soc
> tree (plus fixes for bugs we find) to Linus.
> 
> We will start merging new features after 4.4-rc1 is out, sometimes
> it takes a little while before we get started. It should be no
> problem to get your patches merged for 4.5 then.

Hello Arnd,

Thanks for pointing that out, as I'm not familiar with the details
of the process.

I'm hoping you'll be able to review my patches later, so I can make
the (hopefully final) appropriate changes.

Regards.

[PATCH v8 2/2] arm-soc: Add support for arm-based tango4 platforms

[Måns Rullgård]

Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes:

> Santosh Shilimkar wrote:
>
>> Mark Rutland wrote:
>> 
>>> We didn't. Having a look just now, the earliest example appears to be
>>> in OMAP4 L2 support patches back in 2009 [1]. I was not able to find a
>>> rationale.
>>> 
>>> Given that the MMU is on (and speculative accesses are permitted) I
>>> can't see what the DSB achieves -- it can't quiesce the memory system.
>>> 
>>> Santosh, any idea?
>>
>> IIRC, it was requirement from the OMAP ROM code to have a dsb before
>> we call the SMC routine. I can't recollect more than that now.
>
> In that case, shouldn't dsb have been added to the ROM code,
> on the "other side" of the smc, so as to not depend on Linux
> code "getting it right"?

You're new to this, aren't you? :)

-- 
M?ns Rullg?rd
mans at mansr.com

[PATCH v8 2/2] arm-soc: Add support for arm-based tango4 platforms

[santosh shilimkar]

On 11/3/2015 2:12 AM, M?ns Rullg?rd wrote:
> Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes:
>
>> Santosh Shilimkar wrote:
>>
>>> Mark Rutland wrote:
>>>
>>>> We didn't. Having a look just now, the earliest example appears to be
>>>> in OMAP4 L2 support patches back in 2009 [1]. I was not able to find a
>>>> rationale.
>>>>
>>>> Given that the MMU is on (and speculative accesses are permitted) I
>>>> can't see what the DSB achieves -- it can't quiesce the memory system.
>>>>
>>>> Santosh, any idea?
>>>
>>> IIRC, it was requirement from the OMAP ROM code to have a dsb before
>>> we call the SMC routine. I can't recollect more than that now.
>>
>> In that case, shouldn't dsb have been added to the ROM code,
>> on the "other side" of the smc, so as to not depend on Linux
>> code "getting it right"?
>
> You're new to this, aren't you? :)
>
:-) Indeed. ROM code is burned into the chip and can't be changed.

Regards,
Santosh

[PATCH v8 2/2] arm-soc: Add support for arm-based tango4 platforms

[Marc Gonzalez]

On 03/11/2015 17:37, Santosh Shilimkar wrote:
> On 11/3/2015 2:12 AM, M?ns Rullg?rd wrote:
>> Marc Gonzalez writes:
>>
>>> Santosh Shilimkar wrote:
>>>
>>>> Mark Rutland wrote:
>>>>
>>>>> We didn't. Having a look just now, the earliest example appears to be
>>>>> in OMAP4 L2 support patches back in 2009 [1]. I was not able to find a
>>>>> rationale.
>>>>>
>>>>> Given that the MMU is on (and speculative accesses are permitted) I
>>>>> can't see what the DSB achieves -- it can't quiesce the memory system.
>>>>>
>>>>> Santosh, any idea?
>>>>
>>>> IIRC, it was requirement from the OMAP ROM code to have a dsb before
>>>> we call the SMC routine. I can't recollect more than that now.
>>>
>>> In that case, shouldn't dsb have been added to the ROM code,
>>> on the "other side" of the smc, so as to not depend on Linux
>>> code "getting it right"?
>>
>> You're new to this, aren't you? :)
>
> :-) Indeed. ROM code is burned into the chip and can't be changed.

Oh, that kind of ROM... I thought EEPROM.
(Our secure OS is stored in NAND flash.)

If I'm bored, I'll try measuring the run-time difference with
and without dsb.

Regards.

[PATCH v8 2/2] arm-soc: Add support for arm-based tango4 platforms

[Måns Rullgård]

Marc Gonzalez <marc_gonzalez@sigmadesigns.com> writes:

> On 03/11/2015 17:37, Santosh Shilimkar wrote:
>> On 11/3/2015 2:12 AM, M?ns Rullg?rd wrote:
>>> Marc Gonzalez writes:
>>>
>>>> Santosh Shilimkar wrote:
>>>>
>>>>> Mark Rutland wrote:
>>>>>
>>>>>> We didn't. Having a look just now, the earliest example appears to be
>>>>>> in OMAP4 L2 support patches back in 2009 [1]. I was not able to find a
>>>>>> rationale.
>>>>>>
>>>>>> Given that the MMU is on (and speculative accesses are permitted) I
>>>>>> can't see what the DSB achieves -- it can't quiesce the memory system.
>>>>>>
>>>>>> Santosh, any idea?
>>>>>
>>>>> IIRC, it was requirement from the OMAP ROM code to have a dsb before
>>>>> we call the SMC routine. I can't recollect more than that now.
>>>>
>>>> In that case, shouldn't dsb have been added to the ROM code,
>>>> on the "other side" of the smc, so as to not depend on Linux
>>>> code "getting it right"?
>>>
>>> You're new to this, aren't you? :)
>>
>> :-) Indeed. ROM code is burned into the chip and can't be changed.
>
> Oh, that kind of ROM... I thought EEPROM.
> (Our secure OS is stored in NAND flash.)
>
> If I'm bored, I'll try measuring the run-time difference with
> and without dsb.

Don't bother.  This is only used during initialisation anyway.  If that
takes a few microseconds longer, you won't be able to tell.

-- 
M?ns Rullg?rd
mans at mansr.com