* [01/15] usb: dwc3: Device SoftReset PHY synchonization delay
@ 2018-01-05 20:13 Thinh Nguyen
0 siblings, 0 replies; 3+ messages in thread
From: Thinh Nguyen @ 2018-01-05 20:13 UTC (permalink / raw)
To: Felipe Balbi, Thinh Nguyen, linux-usb; +Cc: John Youn
From DWC_usb31 databook section 1.3.2, once DWC3_DCTL_CSFTRST bit is
cleared, we must wait at least 50ms before accessing the PHY domain
(synchronization delay).
Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
---
drivers/usb/dwc3/core.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 07832509584f..7d21f21707f5 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -228,12 +228,23 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
do {
reg = dwc3_readl(dwc->regs, DWC3_DCTL);
if (!(reg & DWC3_DCTL_CSFTRST))
- return 0;
+ goto done;
udelay(1);
} while (--retries);
return -ETIMEDOUT;
+
+done:
+ /*
+ * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
+ * we must wait at least 50ms before accessing the PHY domain
+ * (synchronization delay). DWC_usb31 Databook section 1.3.2.
+ */
+ if (dwc3_is_usb31(dwc))
+ mdelay(50);
+
+ return 0;
}
/*
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [01/15] usb: dwc3: Device SoftReset PHY synchonization delay
@ 2018-01-08 23:22 Thinh Nguyen
0 siblings, 0 replies; 3+ messages in thread
From: Thinh Nguyen @ 2018-01-08 23:22 UTC (permalink / raw)
To: Felipe Balbi, Thinh Nguyen, linux-usb; +Cc: John Youn
On 1/8/2018 4:01 AM, Felipe Balbi wrote:
>
> Hi,
>
> Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
>> From DWC_usb31 databook section 1.3.2, once DWC3_DCTL_CSFTRST bit is
>> cleared, we must wait at least 50ms before accessing the PHY domain
>> (synchronization delay).
>>
>> Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
>> ---
>> drivers/usb/dwc3/core.c | 13 ++++++++++++-
>> 1 file changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
>> index 07832509584f..7d21f21707f5 100644
>> --- a/drivers/usb/dwc3/core.c
>> +++ b/drivers/usb/dwc3/core.c
>> @@ -228,12 +228,23 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
>> do {
>> reg = dwc3_readl(dwc->regs, DWC3_DCTL);
>> if (!(reg & DWC3_DCTL_CSFTRST))
>> - return 0;
>> + goto done;
>>
>> udelay(1);
>> } while (--retries);
>>
>> return -ETIMEDOUT;
>> +
>> +done:
>> + /*
>> + * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
>> + * we must wait at least 50ms before accessing the PHY domain
>> + * (synchronization delay). DWC_usb31 Databook section 1.3.2.
>> + */
>> + if (dwc3_is_usb31(dwc))
>> + mdelay(50);
>
> we don't have any locks held. Why are you busy looping for an entire
> 50ms? Why don't you msleep() here?
>
You're right. I'll make an update.
Thanks,
Thinh
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^ permalink raw reply [flat|nested] 3+ messages in thread
* [01/15] usb: dwc3: Device SoftReset PHY synchonization delay
@ 2018-01-08 11:59 Felipe Balbi
0 siblings, 0 replies; 3+ messages in thread
From: Felipe Balbi @ 2018-01-08 11:59 UTC (permalink / raw)
To: Thinh Nguyen; +Cc: John Youn
Hi,
Thinh Nguyen <Thinh.Nguyen@synopsys.com> writes:
> From DWC_usb31 databook section 1.3.2, once DWC3_DCTL_CSFTRST bit is
> cleared, we must wait at least 50ms before accessing the PHY domain
> (synchronization delay).
>
> Signed-off-by: Thinh Nguyen <thinhn@synopsys.com>
> ---
> drivers/usb/dwc3/core.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index 07832509584f..7d21f21707f5 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -228,12 +228,23 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
> do {
> reg = dwc3_readl(dwc->regs, DWC3_DCTL);
> if (!(reg & DWC3_DCTL_CSFTRST))
> - return 0;
> + goto done;
>
> udelay(1);
> } while (--retries);
>
> return -ETIMEDOUT;
> +
> +done:
> + /*
> + * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
> + * we must wait at least 50ms before accessing the PHY domain
> + * (synchronization delay). DWC_usb31 Databook section 1.3.2.
> + */
> + if (dwc3_is_usb31(dwc))
> + mdelay(50);
we don't have any locks held. Why are you busy looping for an entire
50ms? Why don't you msleep() here?
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2018-01-08 23:22 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2018-01-08 23:22 Thinh Nguyen
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