* [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx
@ 2015-11-24 14:38 Bärtsch Peter
2015-11-25 10:40 ` Stefano Babic
0 siblings, 1 reply; 6+ messages in thread
From: Bärtsch Peter @ 2015-11-24 14:38 UTC (permalink / raw)
To: u-boot
Hello Stefano,
I have seen , that my patch already exist :o but not active in master branch.
Follow patch is the original from Ye.Le
Kind regards
Peter B?rtsch
On mx6sx, the CCM register bits for GPMI are different as other
mx6 platforms. Modify the GPMI clock function to support mx6sx.
Signed-off-by: Ye.Li <b37...@freescale.com>
---
arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index fd57f22..ce7f0f7 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg)
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+#if defined(CONFIG_MX6SX)
+ clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+
+ clrsetbits_le32(&imx_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
+ cfg);
+
+ setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+#else
clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
clrsetbits_le32(&imx_ccm->cs2cdr,
@@ -56,6 +67,7 @@ void setup_gpmi_io_clk(u32 cfg)
cfg);
setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+#endif
setbits_le32(&imx_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
--
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx
2015-11-24 14:38 [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx Bärtsch Peter
@ 2015-11-25 10:40 ` Stefano Babic
0 siblings, 0 replies; 6+ messages in thread
From: Stefano Babic @ 2015-11-25 10:40 UTC (permalink / raw)
To: u-boot
Hi Peter,
On 24/11/2015 15:38, B?rtsch Peter wrote:
> Hello Stefano,
>
>
>
> I have seen , that my patch already exist :o but not active in master
> branch.
>
> Follow patch is the original from Ye.Le
If you take a patch from someone else, you cannot change author.
Patch was ok, but it was part of a series where some changes were
requested. Anyway, patch is orthogonal to the other ones. I pick it up,
of course the one from Ye.
Best regards,
Stefano Babic
>
>
>
> Kind regards
>
> Peter B?rtsch
>
>
>
>
>
> On mx6sx, the CCM register bits for GPMI are different as other
>
> mx6 platforms. Modify the GPMI clock function to support mx6sx.
>
>
>
>
>
> Signed-off-by: Ye.Li <b37...@freescale.com>
>
> ---
>
> arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++
>
> 1 files changed, 12 insertions(+), 0 deletions(-)
>
>
>
> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
>
> index fd57f22..ce7f0f7 100644
>
> --- a/arch/arm/cpu/armv7/mx6/clock.c
>
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
>
> @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg)
>
> MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
>
> MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
>
> +#if defined(CONFIG_MX6SX)
>
> + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
>
> +
>
> + clrsetbits_le32(&imx_ccm->cs2cdr,
>
> + MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
>
> + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
>
> + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
>
> + cfg);
>
> +
>
> + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
>
> +#else
>
> clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
>
> clrsetbits_le32(&imx_ccm->cs2cdr,
>
> @@ -56,6 +67,7 @@ void setup_gpmi_io_clk(u32 cfg)
>
> cfg);
>
> setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
>
> +#endif
>
> setbits_le32(&imx_ccm->CCGR4,
>
> MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
>
> MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
>
> --
>
>
>
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/4] mx6sx: pins: Enable SION for I2C3 iomux setting
@ 2015-01-12 8:46 Ye.Li
2015-01-12 8:46 ` [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx Ye.Li
0 siblings, 1 reply; 6+ messages in thread
From: Ye.Li @ 2015-01-12 8:46 UTC (permalink / raw)
To: u-boot
The I2C SDA and SCL require the IOMUX SION bit set to get input signal.
Signed-off-by: Ye.Li <B37916@freescale.com>
---
arch/arm/include/asm/arch-mx6/mx6sx_pins.h | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
index 7c6c1e8..da8c698 100644
--- a/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sx_pins.h
@@ -420,7 +420,7 @@ enum {
MX6_PAD_KEY_COL4__KPP_COL_4 = IOMUX_PAD(0x03FC, 0x00B4, 0, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__ENET2_MDC = IOMUX_PAD(0x03FC, 0x00B4, 1, 0x0000, 0, 0),
- MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, 2, 0x07B8, 2, 0),
+ MX6_PAD_KEY_COL4__I2C3_SCL = IOMUX_PAD(0x03FC, 0x00B4, IOMUX_CONFIG_SION | 2, 0x07B8, 2, 0),
MX6_PAD_KEY_COL4__USDHC2_LCTL = IOMUX_PAD(0x03FC, 0x00B4, 3, 0x0000, 0, 0),
MX6_PAD_KEY_COL4__AUDMUX_AUD5_RXC = IOMUX_PAD(0x03FC, 0x00B4, 4, 0x0664, 0, 0),
MX6_PAD_KEY_COL4__GPIO2_IO_14 = IOMUX_PAD(0x03FC, 0x00B4, 5, 0x0000, 0, 0),
@@ -467,7 +467,7 @@ enum {
MX6_PAD_KEY_ROW4__KPP_ROW_4 = IOMUX_PAD(0x0410, 0x00C8, 0, 0x0000, 0, 0),
MX6_PAD_KEY_ROW4__ENET2_MDIO = IOMUX_PAD(0x0410, 0x00C8, 1, 0x0770, 3, 0),
- MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, 2, 0x07BC, 2, 0),
+ MX6_PAD_KEY_ROW4__I2C3_SDA = IOMUX_PAD(0x0410, 0x00C8, IOMUX_CONFIG_SION | 2, 0x07BC, 2, 0),
MX6_PAD_KEY_ROW4__USDHC1_LCTL = IOMUX_PAD(0x0410, 0x00C8, 3, 0x0000, 0, 0),
MX6_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS = IOMUX_PAD(0x0410, 0x00C8, 4, 0x0668, 0, 0),
MX6_PAD_KEY_ROW4__GPIO2_IO_19 = IOMUX_PAD(0x0410, 0x00C8, 5, 0x0000, 0, 0),
--
1.7.4.1
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx
2015-01-12 8:46 [U-Boot] [PATCH 1/4] mx6sx: pins: Enable SION for I2C3 iomux setting Ye.Li
@ 2015-01-12 8:46 ` Ye.Li
2015-02-10 10:26 ` Stefano Babic
0 siblings, 1 reply; 6+ messages in thread
From: Ye.Li @ 2015-01-12 8:46 UTC (permalink / raw)
To: u-boot
On mx6sx, the CCM register bits for GPMI are different as other
mx6 platforms. Modify the GPMI clock function to support mx6sx.
Signed-off-by: Ye.Li <B37916@freescale.com>
---
arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++
1 files changed, 12 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index fd57f22..ce7f0f7 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg)
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+#if defined(CONFIG_MX6SX)
+ clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+
+ clrsetbits_le32(&imx_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
+ cfg);
+
+ setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+#else
clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
clrsetbits_le32(&imx_ccm->cs2cdr,
@@ -56,6 +67,7 @@ void setup_gpmi_io_clk(u32 cfg)
cfg);
setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+#endif
setbits_le32(&imx_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
--
1.7.4.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx
2015-01-12 8:46 ` [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx Ye.Li
@ 2015-02-10 10:26 ` Stefano Babic
2015-02-11 3:14 ` Li Ye-B37916
0 siblings, 1 reply; 6+ messages in thread
From: Stefano Babic @ 2015-02-10 10:26 UTC (permalink / raw)
To: u-boot
Hi Ye,
On 12/01/2015 09:46, Ye.Li wrote:
> On mx6sx, the CCM register bits for GPMI are different as other
> mx6 platforms. Modify the GPMI clock function to support mx6sx.
>
> Signed-off-by: Ye.Li <B37916@freescale.com>
> ---
> arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++
> 1 files changed, 12 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
> index fd57f22..ce7f0f7 100644
> --- a/arch/arm/cpu/armv7/mx6/clock.c
> +++ b/arch/arm/cpu/armv7/mx6/clock.c
> @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg)
> MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
> MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
>
> +#if defined(CONFIG_MX6SX)
> + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
> +
> + clrsetbits_le32(&imx_ccm->cs2cdr,
> + MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
> + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
> + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
> + cfg);
> +
> + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
> +#els
If I have well understood, this code is protected by CONFIG_NAND_MXS,
and that conflicts with what you are willing to do (setting clocks for
QSPI). I suggest to split setup_gpmi_io_clk() function, that at the
moment is ony for NAND, having something like:
void setup_gpmi_io_clk()
{
#ifdef CONFIG_NAND_MXS
...setup nand
#endif
...setup qspi
}
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx
2015-02-10 10:26 ` Stefano Babic
@ 2015-02-11 3:14 ` Li Ye-B37916
2015-02-11 12:48 ` Stefano Babic
0 siblings, 1 reply; 6+ messages in thread
From: Li Ye-B37916 @ 2015-02-11 3:14 UTC (permalink / raw)
To: u-boot
Hi Stefano,
On 2/10/2015 6:26 PM, Stefano Babic wrote:
> Hi Ye,
>
> On 12/01/2015 09:46, Ye.Li wrote:
>> On mx6sx, the CCM register bits for GPMI are different as other
>> mx6 platforms. Modify the GPMI clock function to support mx6sx.
>>
>> Signed-off-by: Ye.Li <B37916@freescale.com>
>> ---
>> arch/arm/cpu/armv7/mx6/clock.c | 12 ++++++++++++
>> 1 files changed, 12 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
>> index fd57f22..ce7f0f7 100644
>> --- a/arch/arm/cpu/armv7/mx6/clock.c
>> +++ b/arch/arm/cpu/armv7/mx6/clock.c
>> @@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg)
>> MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
>> MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
>>
>> +#if defined(CONFIG_MX6SX)
>> + clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
>> +
>> + clrsetbits_le32(&imx_ccm->cs2cdr,
>> + MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
>> + MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
>> + MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
>> + cfg);
>> +
>> + setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
>> +#els
> If I have well understood, this code is protected by CONFIG_NAND_MXS,
> and that conflicts with what you are willing to do (setting clocks for
> QSPI). I suggest to split setup_gpmi_io_clk() function, that at the
> moment is ony for NAND, having something like:
>
> void setup_gpmi_io_clk()
> {
> #ifdef CONFIG_NAND_MXS
>
> ...setup nand
> #endif
>
> ...setup qspi
>
> }
>
> Best regards,
> Stefano Babic
>
I feel you misunderstand the patch. On i.MX6sx, the QSPI2 and GPMI shares the same clock root of QSPI2. So you can see the register bits are
named with "MXC_CCM_CS2CDR_QSPI2_xxx". Actually, not only the name, there is a little different in the CS2CDR register bits layout. The patch is used to fix the gap.
Also the the GPMI pins are multiplexed with QSPI2 pins, so either NAND or QSPI2 can work, there is no conflict.
Best regards,
Ye Li
^ permalink raw reply [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx
2015-02-11 3:14 ` Li Ye-B37916
@ 2015-02-11 12:48 ` Stefano Babic
0 siblings, 0 replies; 6+ messages in thread
From: Stefano Babic @ 2015-02-11 12:48 UTC (permalink / raw)
To: u-boot
Hi Ye.Li,
On 11/02/2015 04:14, Li Ye-B37916 wrote:
>>
> I feel you misunderstand the patch.
Thanks for clarifications.
> On i.MX6sx, the QSPI2 and GPMI shares the same clock root of QSPI2. So you can see the register bits are
> named with "MXC_CCM_CS2CDR_QSPI2_xxx". Actually, not only the name, there is a little different in the CS2CDR register bits layout. The patch is used to fix the gap.
>
> Also the the GPMI pins are multiplexed with QSPI2 pins, so either NAND or QSPI2 can work, there is no conflict.
Ok, understood - then it is fine with me.
Best regards,
Stefano Babic
--
=====================================================================
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2015-11-25 10:40 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-11-24 14:38 [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx Bärtsch Peter
2015-11-25 10:40 ` Stefano Babic
-- strict thread matches above, loose matches on Subject: below --
2015-01-12 8:46 [U-Boot] [PATCH 1/4] mx6sx: pins: Enable SION for I2C3 iomux setting Ye.Li
2015-01-12 8:46 ` [U-Boot] [PATCH 3/4] mx6: clock: Modify GPMI clock to support mx6sx Ye.Li
2015-02-10 10:26 ` Stefano Babic
2015-02-11 3:14 ` Li Ye-B37916
2015-02-11 12:48 ` Stefano Babic
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.