* [PATCH v3] x86/VPMU: Support only versions 2 through 4 of architectural performance monitoring
@ 2015-12-04 14:07 Boris Ostrovsky
2015-12-04 14:44 ` Jan Beulich
2015-12-10 11:42 ` Tian, Kevin
0 siblings, 2 replies; 3+ messages in thread
From: Boris Ostrovsky @ 2015-12-04 14:07 UTC (permalink / raw)
To: jbeulich, andrew.cooper3, kevin.tian, jun.nakajima
Cc: Boris Ostrovsky, dietmar.hahn, xen-devel
We need to have at least version 2 since it's the first version to
support various control and status registers (such as
MSR_CORE_PERF_GLOBAL_CTRL) that VPMU relies on always having.
We don't fully emulate version 4 but since it's back compatible with
earlier versions we can fall back to v3. At this point there is no
compatibility statement for v5 so anything above 4 is not supported.
For guests querying PMU version via CPUID leaf 0xa clip it at v3.
With explicit testing for PMU version we can now remove CPUID model
check.
Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
---
v3:
* Clip PMU version to 3 in CPUID op (as opposed to only checking for version
4 in previous posting)
* Convert 'if' statemnt to 'switch' in core2_vpmu_init()
* Update commit message
xen/arch/x86/cpu/vpmu_intel.c | 80 ++++++++++++++++---------------------------
1 file changed, 30 insertions(+), 50 deletions(-)
diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
index d5ea7fe..c27f095 100644
--- a/xen/arch/x86/cpu/vpmu_intel.c
+++ b/xen/arch/x86/cpu/vpmu_intel.c
@@ -733,11 +733,11 @@ static void core2_vpmu_do_cpuid(unsigned int input,
unsigned int *eax, unsigned int *ebx,
unsigned int *ecx, unsigned int *edx)
{
- if (input == 0x1)
+ switch ( input )
{
- struct vpmu_struct *vpmu = vcpu_vpmu(current);
+ case 0x1:
- if ( vpmu_is_set(vpmu, VPMU_CPU_HAS_DS) )
+ if ( vpmu_is_set(vcpu_vpmu(current), VPMU_CPU_HAS_DS) )
{
/* Switch on the 'Debug Store' feature in CPUID.EAX[1]:EDX[21] */
*edx |= cpufeat_mask(X86_FEATURE_DS);
@@ -746,6 +746,13 @@ static void core2_vpmu_do_cpuid(unsigned int input,
if ( cpu_has(¤t_cpu_data, X86_FEATURE_DSCPL) )
*ecx |= cpufeat_mask(X86_FEATURE_DSCPL);
}
+ break;
+
+ case 0xa:
+ /* Report at most version 3 since that's all we currently emulate */
+ if ( MASK_EXTR(*eax, PMU_VERSION_MASK) > 3 )
+ *eax = (*eax & ~PMU_VERSION_MASK) | MASK_INSR(3, PMU_VERSION_MASK);
+ break;
}
}
@@ -955,59 +962,32 @@ int vmx_vpmu_initialise(struct vcpu *v)
int __init core2_vpmu_init(void)
{
u64 caps;
+ unsigned int version = 0;
- if ( current_cpu_data.x86 != 6 )
+ if ( current_cpu_data.cpuid_level >= 0xa )
+ version = MASK_EXTR(cpuid_eax(0xa), PMU_VERSION_MASK);
+
+ switch ( version )
{
- printk(XENLOG_WARNING "VPMU: only family 6 is supported\n");
+ case 4:
+ printk(XENLOG_INFO "VPMU: PMU version 4 is not fully supported. "
+ "Emulating version 3\n");
+ /* FALLTHROUGH */
+
+ case 2:
+ case 3:
+ break;
+
+ default:
+ printk(XENLOG_WARNING "VPMU: PMU version %u is not supported\n",
+ version);
return -EINVAL;
}
- switch ( current_cpu_data.x86_model )
+ if ( current_cpu_data.x86 != 6 )
{
- /* Core2: */
- case 0x0f: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
- case 0x16: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
- case 0x17: /* 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
- case 0x1d: /* six-core 45 nm xeon "Dunnington" */
-
- case 0x2a: /* SandyBridge */
- case 0x2d: /* SandyBridge, "Romley-EP" */
-
- /* Nehalem: */
- case 0x1a: /* 45 nm nehalem, "Bloomfield" */
- case 0x1e: /* 45 nm nehalem, "Lynnfield", "Clarksfield", "Jasper Forest" */
- case 0x2e: /* 45 nm nehalem-ex, "Beckton" */
-
- /* Westmere: */
- case 0x25: /* 32 nm nehalem, "Clarkdale", "Arrandale" */
- case 0x2c: /* 32 nm nehalem, "Gulftown", "Westmere-EP" */
- case 0x2f: /* 32 nm Westmere-EX */
-
- case 0x3a: /* IvyBridge */
- case 0x3e: /* IvyBridge EP */
-
- /* Haswell: */
- case 0x3c:
- case 0x3f:
- case 0x45:
- case 0x46:
-
- /* Broadwell */
- case 0x3d:
- case 0x4f:
- case 0x56:
-
- /* future: */
- case 0x4e:
-
- /* next gen Xeon Phi */
- case 0x57:
- break;
-
- default:
- printk(XENLOG_WARNING "VPMU: Unsupported CPU model %#x\n",
- current_cpu_data.x86_model);
- return -EINVAL;
+ printk(XENLOG_WARNING "VPMU: only family 6 is supported\n");
+ return -EINVAL;
}
arch_pmc_cnt = core2_get_arch_pmc_count();
--
1.8.1.4
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH v3] x86/VPMU: Support only versions 2 through 4 of architectural performance monitoring
2015-12-04 14:07 [PATCH v3] x86/VPMU: Support only versions 2 through 4 of architectural performance monitoring Boris Ostrovsky
@ 2015-12-04 14:44 ` Jan Beulich
2015-12-10 11:42 ` Tian, Kevin
1 sibling, 0 replies; 3+ messages in thread
From: Jan Beulich @ 2015-12-04 14:44 UTC (permalink / raw)
To: Boris Ostrovsky
Cc: andrew.cooper3, kevin.tian, dietmar.hahn, jun.nakajima, xen-devel
>>> On 04.12.15 at 15:07, <boris.ostrovsky@oracle.com> wrote:
> We need to have at least version 2 since it's the first version to
> support various control and status registers (such as
> MSR_CORE_PERF_GLOBAL_CTRL) that VPMU relies on always having.
>
> We don't fully emulate version 4 but since it's back compatible with
> earlier versions we can fall back to v3. At this point there is no
> compatibility statement for v5 so anything above 4 is not supported.
>
> For guests querying PMU version via CPUID leaf 0xa clip it at v3.
>
> With explicit testing for PMU version we can now remove CPUID model
> check.
>
> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v3] x86/VPMU: Support only versions 2 through 4 of architectural performance monitoring
2015-12-04 14:07 [PATCH v3] x86/VPMU: Support only versions 2 through 4 of architectural performance monitoring Boris Ostrovsky
2015-12-04 14:44 ` Jan Beulich
@ 2015-12-10 11:42 ` Tian, Kevin
1 sibling, 0 replies; 3+ messages in thread
From: Tian, Kevin @ 2015-12-10 11:42 UTC (permalink / raw)
To: Boris Ostrovsky, jbeulich, andrew.cooper3, Nakajima, Jun
Cc: dietmar.hahn, xen-devel
> From: Boris Ostrovsky [mailto:boris.ostrovsky@oracle.com]
> Sent: Friday, December 04, 2015 10:08 PM
>
> We need to have at least version 2 since it's the first version to
> support various control and status registers (such as
> MSR_CORE_PERF_GLOBAL_CTRL) that VPMU relies on always having.
>
> We don't fully emulate version 4 but since it's back compatible with
> earlier versions we can fall back to v3. At this point there is no
> compatibility statement for v5 so anything above 4 is not supported.
>
> For guests querying PMU version via CPUID leaf 0xa clip it at v3.
>
> With explicit testing for PMU version we can now remove CPUID model
> check.
>
> Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2015-12-04 14:07 [PATCH v3] x86/VPMU: Support only versions 2 through 4 of architectural performance monitoring Boris Ostrovsky
2015-12-04 14:44 ` Jan Beulich
2015-12-10 11:42 ` Tian, Kevin
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