From: Mario Smarduch <m.smarduch@samsung.com> To: Christoffer Dall <christoffer.dall@linaro.org> Cc: marc.zyngier@arm.com, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v5 3/3] KVM/arm/arm64: enable enhanced armv8 fp/simd lazy switch Date: Tue, 22 Dec 2015 10:01:46 -0800 [thread overview] Message-ID: <5679900A.9080108@samsung.com> (raw) In-Reply-To: <20151222080612.GA3076@cbox> On 12/22/2015 12:06 AM, Christoffer Dall wrote: > On Mon, Dec 21, 2015 at 11:34:25AM -0800, Mario Smarduch wrote: >> >> >> On 12/18/2015 11:45 PM, Christoffer Dall wrote: >>> On Fri, Dec 18, 2015 at 05:17:00PM -0800, Mario Smarduch wrote: >>>> On 12/18/2015 5:54 AM, Christoffer Dall wrote: >>>>> On Sun, Dec 06, 2015 at 05:07:14PM -0800, Mario Smarduch wrote: [...] >>>>>> + * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit. >>>>>> + */ >>>>>> +ENTRY(__kvm_vcpu_enable_fpexc32) >>>>>> + mov x3, #(1 << 30) >>>>>> + msr fpexc32_el2, x3 >>>>>> + isb >>>>> >>>>> this is only called via a hypercall so do you really need the ISB? >>>> >>>> Same comment as in 2nd patch for the isb. >>>> >>> >>> Unless you can argue that something needs to take effect before >>> something else, where there's no other implicit barrier, you don't need >>> the ISB. >> >> Make sense an exception level change should be a barrier. It was not there >> before I put it in due to lack of info on meaning of 'implicit'. The manual has >> more info on implicit barriers for operations like DMB. > > if the effect from the register write just has to be visible after > taking an exception, then you don't need the ISB. Good definition, should be in the manual :) Thanks. > >> >> Speaking of ISB it doesn't appear like this one is needed, it's between couple >> register reads in 'save_time_state' macro. >> >> mrc p15, 0, r2, c14, c3, 1 @ CNTV_CTL >> str r2, [vcpu, #VCPU_TIMER_CNTV_CTL] >> >> isb >> >> mrrc p15, 3, rr_lo_hi(r2, r3), c14 @ CNTV_CVAL >> > > I think there was a reason for that one, so let's not worry about that > for now. > > -Christoffer >
WARNING: multiple messages have this Message-ID (diff)
From: m.smarduch@samsung.com (Mario Smarduch) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 3/3] KVM/arm/arm64: enable enhanced armv8 fp/simd lazy switch Date: Tue, 22 Dec 2015 10:01:46 -0800 [thread overview] Message-ID: <5679900A.9080108@samsung.com> (raw) In-Reply-To: <20151222080612.GA3076@cbox> On 12/22/2015 12:06 AM, Christoffer Dall wrote: > On Mon, Dec 21, 2015 at 11:34:25AM -0800, Mario Smarduch wrote: >> >> >> On 12/18/2015 11:45 PM, Christoffer Dall wrote: >>> On Fri, Dec 18, 2015 at 05:17:00PM -0800, Mario Smarduch wrote: >>>> On 12/18/2015 5:54 AM, Christoffer Dall wrote: >>>>> On Sun, Dec 06, 2015 at 05:07:14PM -0800, Mario Smarduch wrote: [...] >>>>>> + * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit. >>>>>> + */ >>>>>> +ENTRY(__kvm_vcpu_enable_fpexc32) >>>>>> + mov x3, #(1 << 30) >>>>>> + msr fpexc32_el2, x3 >>>>>> + isb >>>>> >>>>> this is only called via a hypercall so do you really need the ISB? >>>> >>>> Same comment as in 2nd patch for the isb. >>>> >>> >>> Unless you can argue that something needs to take effect before >>> something else, where there's no other implicit barrier, you don't need >>> the ISB. >> >> Make sense an exception level change should be a barrier. It was not there >> before I put it in due to lack of info on meaning of 'implicit'. The manual has >> more info on implicit barriers for operations like DMB. > > if the effect from the register write just has to be visible after > taking an exception, then you don't need the ISB. Good definition, should be in the manual :) Thanks. > >> >> Speaking of ISB it doesn't appear like this one is needed, it's between couple >> register reads in 'save_time_state' macro. >> >> mrc p15, 0, r2, c14, c3, 1 @ CNTV_CTL >> str r2, [vcpu, #VCPU_TIMER_CNTV_CTL] >> >> isb >> >> mrrc p15, 3, rr_lo_hi(r2, r3), c14 @ CNTV_CVAL >> > > I think there was a reason for that one, so let's not worry about that > for now. > > -Christoffer >
next prev parent reply other threads:[~2015-12-22 18:01 UTC|newest] Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top 2015-12-07 1:07 [PATCH v5 0/3] KVM/arm/arm64: enhance armv7/8 fp/simd lazy switch Mario Smarduch 2015-12-07 1:07 ` Mario Smarduch 2015-12-07 1:07 ` [PATCH v5 1/3] KVM/arm: add hooks for armv7 fp/simd lazy switch support Mario Smarduch 2015-12-07 1:07 ` Mario Smarduch 2015-12-18 13:07 ` Christoffer Dall 2015-12-18 13:07 ` Christoffer Dall 2015-12-18 22:27 ` Mario Smarduch 2015-12-18 22:27 ` Mario Smarduch 2015-12-07 1:07 ` [PATCH v5 2/3] KVM/arm/arm64: enable enhanced armv7 fp/simd lazy switch Mario Smarduch 2015-12-07 1:07 ` Mario Smarduch 2015-12-18 13:49 ` Christoffer Dall 2015-12-18 13:49 ` Christoffer Dall 2015-12-19 0:54 ` Mario Smarduch 2015-12-19 0:54 ` Mario Smarduch 2015-12-07 1:07 ` [PATCH v5 3/3] KVM/arm/arm64: enable enhanced armv8 " Mario Smarduch 2015-12-07 1:07 ` Mario Smarduch 2015-12-18 13:54 ` Christoffer Dall 2015-12-18 13:54 ` Christoffer Dall 2015-12-19 1:17 ` Mario Smarduch 2015-12-19 1:17 ` Mario Smarduch 2015-12-19 7:45 ` Christoffer Dall 2015-12-19 7:45 ` Christoffer Dall 2015-12-21 19:34 ` Mario Smarduch 2015-12-21 19:34 ` Mario Smarduch 2015-12-22 8:06 ` Christoffer Dall 2015-12-22 8:06 ` Christoffer Dall 2015-12-22 18:01 ` Mario Smarduch [this message] 2015-12-22 18:01 ` Mario Smarduch
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