* [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary
@ 2016-01-10 16:04 John Crispin
[not found] ` <1452441884-25882-1-git-send-email-blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
0 siblings, 1 reply; 12+ messages in thread
From: John Crispin @ 2016-01-10 16:04 UTC (permalink / raw)
To: Matthias Brugger; +Cc: linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
The MT6323 and possible other PMICs have a different DEW base addr. Change
the driver so that it handles the DEW registeres in the same manner as the
rest of the registers.
Signed-off-by: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
---
drivers/soc/mediatek/mtk-pmic-wrap.c | 166 +++++++++++++++++++++++++---------
1 file changed, 122 insertions(+), 44 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index 105597a..f3fccea 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -61,32 +61,85 @@
#define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
/* macro for slave device wrapper registers */
-#define PWRAP_DEW_BASE 0xbc00
-#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
-#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
-#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
-#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
-#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
-#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
-#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
-#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
-#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
-#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
-#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
-#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
-#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
-#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a)
-#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
-#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
-#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
-#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
-#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
-#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
-#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
-#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
-#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
-#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
-#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
+enum pwrap_dew_regs {
+ PWRAP_DEW_EVENT_OUT_EN,
+ PWRAP_DEW_DIO_EN,
+ PWRAP_DEW_EVENT_SRC_EN,
+ PWRAP_DEW_EVENT_SRC,
+ PWRAP_DEW_EVENT_FLAG,
+ PWRAP_DEW_READ_TEST,
+ PWRAP_DEW_WRITE_TEST,
+ PWRAP_DEW_CRC_EN,
+ PWRAP_DEW_CRC_VAL,
+ PWRAP_DEW_MON_GRP_SEL,
+ PWRAP_DEW_MON_FLAG_SEL,
+ PWRAP_DEW_EVENT_TEST,
+ PWRAP_DEW_CIPHER_KEY_SEL,
+ PWRAP_DEW_CIPHER_IV_SEL,
+ PWRAP_DEW_CIPHER_LOAD,
+ PWRAP_DEW_CIPHER_START,
+ PWRAP_DEW_CIPHER_RDY,
+ PWRAP_DEW_CIPHER_MODE,
+ PWRAP_DEW_CIPHER_SWRST,
+
+ /* MT8173 only regs */
+ PWRAP_DEW_CIPHER_IV0,
+ PWRAP_DEW_CIPHER_IV1,
+ PWRAP_DEW_CIPHER_IV2,
+ PWRAP_DEW_CIPHER_IV3,
+ PWRAP_DEW_CIPHER_IV4,
+ PWRAP_DEW_CIPHER_IV5,
+};
+
+static int mt8135_dew_regs[] = {
+ [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
+ [PWRAP_DEW_DIO_EN] = 0x2,
+ [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
+ [PWRAP_DEW_EVENT_SRC] = 0x6,
+ [PWRAP_DEW_EVENT_FLAG] = 0x8,
+ [PWRAP_DEW_READ_TEST] = 0xa,
+ [PWRAP_DEW_WRITE_TEST] = 0xc,
+ [PWRAP_DEW_CRC_EN] = 0xe,
+ [PWRAP_DEW_CRC_VAL] = 0x10,
+ [PWRAP_DEW_MON_GRP_SEL] = 0x12,
+ [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
+ [PWRAP_DEW_EVENT_TEST] = 0x16,
+ [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
+ [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
+ [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
+ [PWRAP_DEW_CIPHER_START] = 0x1e,
+ [PWRAP_DEW_CIPHER_RDY] = 0x20,
+ [PWRAP_DEW_CIPHER_MODE] = 0x22,
+ [PWRAP_DEW_CIPHER_SWRST] = 0x24,
+};
+
+static int mt8173_dew_regs[] = {
+ [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
+ [PWRAP_DEW_DIO_EN] = 0x2,
+ [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
+ [PWRAP_DEW_EVENT_SRC] = 0x6,
+ [PWRAP_DEW_EVENT_FLAG] = 0x8,
+ [PWRAP_DEW_READ_TEST] = 0xa,
+ [PWRAP_DEW_WRITE_TEST] = 0xc,
+ [PWRAP_DEW_CRC_EN] = 0xe,
+ [PWRAP_DEW_CRC_VAL] = 0x10,
+ [PWRAP_DEW_MON_GRP_SEL] = 0x12,
+ [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
+ [PWRAP_DEW_EVENT_TEST] = 0x16,
+ [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
+ [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
+ [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
+ [PWRAP_DEW_CIPHER_START] = 0x1e,
+ [PWRAP_DEW_CIPHER_RDY] = 0x20,
+ [PWRAP_DEW_CIPHER_MODE] = 0x22,
+ [PWRAP_DEW_CIPHER_SWRST] = 0x24,
+ [PWRAP_DEW_CIPHER_IV0] = 0x26,
+ [PWRAP_DEW_CIPHER_IV1] = 0x28,
+ [PWRAP_DEW_CIPHER_IV2] = 0x2a,
+ [PWRAP_DEW_CIPHER_IV3] = 0x2c,
+ [PWRAP_DEW_CIPHER_IV4] = 0x2e,
+ [PWRAP_DEW_CIPHER_IV5] = 0x30,
+};
enum pwrap_regs {
PWRAP_MUX_SEL,
@@ -347,18 +400,24 @@ enum pwrap_type {
struct pmic_wrapper_type {
int *regs;
+ int *dew_regs;
+ u32 dew_base;
enum pwrap_type type;
u32 arb_en_all;
};
static struct pmic_wrapper_type pwrap_mt8135 = {
.regs = mt8135_regs,
+ .dew_regs = mt8135_dew_regs,
+ .dew_base = 0xbc00,
.type = PWRAP_MT8135,
.arb_en_all = 0x1ff,
};
static struct pmic_wrapper_type pwrap_mt8173 = {
.regs = mt8173_regs,
+ .dew_regs = mt8173_dew_regs,
+ .dew_base = 0xbc00,
.type = PWRAP_MT8173,
.arb_en_all = 0x3f,
};
@@ -368,6 +427,8 @@ struct pmic_wrapper {
void __iomem *base;
struct regmap *regmap;
int *regs;
+ int *dew_regs;
+ u32 dew_base;
enum pwrap_type type;
u32 arb_en_all;
struct clk *clk_spi;
@@ -475,6 +536,18 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
return 0;
}
+static int pwrap_dew_write(struct pmic_wrapper *wrp, enum pwrap_dew_regs reg,
+ u32 wdata)
+{
+ return pwrap_write(wrp, wrp->dew_base + wrp->dew_regs[reg], wdata);
+}
+
+static int pwrap_dew_read(struct pmic_wrapper *wrp, enum pwrap_dew_regs reg,
+ u32 *rdata)
+{
+ return pwrap_read(wrp, wrp->dew_base + wrp->dew_regs[reg], rdata);
+}
+
static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
{
return pwrap_read(context, adr, rdata);
@@ -535,7 +608,7 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
for (i = 0; i < 4; i++) {
pwrap_writel(wrp, i, PWRAP_SIDLY);
- pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
+ pwrap_dew_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
if (rdata == PWRAP_DEW_READ_TEST_VAL) {
dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
pass |= 1 << i;
@@ -581,7 +654,7 @@ static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
u32 rdata;
int ret;
- ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
+ ret = pwrap_dew_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
if (ret)
return 0;
@@ -606,12 +679,12 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
}
/* Config cipher mode @PMIC */
- pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
- pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
- pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
- pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
- pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
- pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
+ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
+ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
+ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
+ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
+ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
+ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
/* wait for cipher data ready@AP */
ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
@@ -628,7 +701,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
}
/* wait for cipher mode idle */
- pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
+ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
if (ret) {
dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
@@ -638,9 +711,10 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
/* Write Test */
- if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
- pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
- (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
+ if (pwrap_dew_write(wrp, PWRAP_DEW_WRITE_TEST,
+ PWRAP_DEW_WRITE_TEST_VAL) ||
+ pwrap_dew_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
+ (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
return -EFAULT;
}
@@ -684,7 +758,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
return ret;
/* Enable dual IO mode */
- pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1);
+ pwrap_dew_write(wrp, PWRAP_DEW_DIO_EN, 1);
/* Check IDLE & INIT_DONE in advance */
ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
@@ -696,7 +770,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
pwrap_writel(wrp, 1, PWRAP_DIO_EN);
/* Read Test */
- pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
+ pwrap_dew_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
if (rdata != PWRAP_DEW_READ_TEST_VAL) {
dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
PWRAP_DEW_READ_TEST_VAL, rdata);
@@ -709,12 +783,13 @@ static int pwrap_init(struct pmic_wrapper *wrp)
return ret;
/* Signature checking - using CRC */
- if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
+ if (pwrap_dew_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
return -EFAULT;
pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
- pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
+ pwrap_writel(wrp, wrp->dew_base + wrp->dew_regs[PWRAP_DEW_CRC_VAL],
+ PWRAP_SIG_ADR);
pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN);
if (pwrap_is_mt8135(wrp))
@@ -739,8 +814,9 @@ static int pwrap_init(struct pmic_wrapper *wrp)
writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
/* enable PMIC event out and sources */
- if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
- pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
+ if (pwrap_dew_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
+ pwrap_dew_write(wrp, PWRAP_DEW_EVENT_SRC_EN,
+ 0xffff)) {
dev_err(wrp->dev, "enable dewrap fail\n");
return -EFAULT;
}
@@ -821,6 +897,8 @@ static int pwrap_probe(struct platform_device *pdev)
type = of_id->data;
wrp->regs = type->regs;
wrp->type = type->type;
+ wrp->dew_regs = type->dew_regs;
+ wrp->dew_base = type->dew_base;
wrp->arb_en_all = type->arb_en_all;
wrp->dev = &pdev->dev;
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH V2 2/4] soc: mediatek: PMIC wrap: INT_EN mask may vary
[not found] ` <1452441884-25882-1-git-send-email-blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
@ 2016-01-10 16:04 ` John Crispin
2016-01-10 16:04 ` [PATCH V2 3/4] soc: mediatek: PMIC wrap the SPI_W bit in PWRAP_MAN_CMD " John Crispin
` (2 subsequent siblings)
3 siblings, 0 replies; 12+ messages in thread
From: John Crispin @ 2016-01-10 16:04 UTC (permalink / raw)
To: Matthias Brugger; +Cc: linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
The MT7623 and possible other SoCs have a different INT_EN mask. Change
the driver so that it handles the interrupt mask in the same was as
arb_en_all.
Signed-off-by: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
---
drivers/soc/mediatek/mtk-pmic-wrap.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index f3fccea..82350d0 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -404,6 +404,7 @@ struct pmic_wrapper_type {
u32 dew_base;
enum pwrap_type type;
u32 arb_en_all;
+ u32 int_en_all;
};
static struct pmic_wrapper_type pwrap_mt8135 = {
@@ -412,6 +413,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
.dew_base = 0xbc00,
.type = PWRAP_MT8135,
.arb_en_all = 0x1ff,
+ .int_en_all = BIT(31) | BIT(1),
};
static struct pmic_wrapper_type pwrap_mt8173 = {
@@ -420,6 +422,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
.dew_base = 0xbc00,
.type = PWRAP_MT8173,
.arb_en_all = 0x3f,
+ .int_en_all = BIT(31) | BIT(1),
};
struct pmic_wrapper {
@@ -431,6 +434,7 @@ struct pmic_wrapper {
u32 dew_base;
enum pwrap_type type;
u32 arb_en_all;
+ u32 int_en_all;
struct clk *clk_spi;
struct clk *clk_wrap;
struct reset_control *rstc;
@@ -900,6 +904,7 @@ static int pwrap_probe(struct platform_device *pdev)
wrp->dew_regs = type->dew_regs;
wrp->dew_base = type->dew_base;
wrp->arb_en_all = type->arb_en_all;
+ wrp->int_en_all = type->int_en_all;
wrp->dev = &pdev->dev;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
@@ -974,7 +979,7 @@ static int pwrap_probe(struct platform_device *pdev)
pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
pwrap_writel(wrp, 0xffffffff, PWRAP_WDT_SRC_EN);
pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
- pwrap_writel(wrp, ~((1 << 31) | (1 << 1)), PWRAP_INT_EN);
+ pwrap_writel(wrp, ~wrp->int_en_all, PWRAP_INT_EN);
irq = platform_get_irq(pdev, 0);
ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt, IRQF_TRIGGER_HIGH,
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH V2 3/4] soc: mediatek: PMIC wrap the SPI_W bit in PWRAP_MAN_CMD may vary
[not found] ` <1452441884-25882-1-git-send-email-blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
2016-01-10 16:04 ` [PATCH V2 2/4] soc: mediatek: PMIC wrap: INT_EN mask " John Crispin
@ 2016-01-10 16:04 ` John Crispin
2016-01-10 16:04 ` [PATCH V2 4/4] soc: mediatek: PMIC wrap: add support for MT7623/6323 John Crispin
2016-01-12 4:28 ` [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary Henry Chen
3 siblings, 0 replies; 12+ messages in thread
From: John Crispin @ 2016-01-10 16:04 UTC (permalink / raw)
To: Matthias Brugger; +Cc: linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
MT2701 and MT7623 use bit 14 instead of 13. Bit 13 is used on these SoCs to
select the slave type.
Signed-off-by: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
---
drivers/soc/mediatek/mtk-pmic-wrap.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index 82350d0..ceeac3a 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -405,6 +405,7 @@ struct pmic_wrapper_type {
enum pwrap_type type;
u32 arb_en_all;
u32 int_en_all;
+ u32 man_cmd_spi_w;
};
static struct pmic_wrapper_type pwrap_mt8135 = {
@@ -414,6 +415,7 @@ static struct pmic_wrapper_type pwrap_mt8135 = {
.type = PWRAP_MT8135,
.arb_en_all = 0x1ff,
.int_en_all = BIT(31) | BIT(1),
+ .man_cmd_spi_w = PWRAP_MAN_CMD_SPI_WRITE,
};
static struct pmic_wrapper_type pwrap_mt8173 = {
@@ -423,6 +425,7 @@ static struct pmic_wrapper_type pwrap_mt8173 = {
.type = PWRAP_MT8173,
.arb_en_all = 0x3f,
.int_en_all = BIT(31) | BIT(1),
+ .man_cmd_spi_w = PWRAP_MAN_CMD_SPI_WRITE,
};
struct pmic_wrapper {
@@ -435,6 +438,7 @@ struct pmic_wrapper {
enum pwrap_type type;
u32 arb_en_all;
u32 int_en_all;
+ u32 man_cmd_spi_w;
struct clk *clk_spi;
struct clk *clk_wrap;
struct reset_control *rstc;
@@ -572,15 +576,15 @@ static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
pwrap_writel(wrp, 1, PWRAP_MAN_EN);
pwrap_writel(wrp, 0, PWRAP_DIO_EN);
- pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_CSL,
+ pwrap_writel(wrp, wrp->man_cmd_spi_w | PWRAP_MAN_CMD_OP_CSL,
PWRAP_MAN_CMD);
- pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_OUTS,
+ pwrap_writel(wrp, wrp->man_cmd_spi_w | PWRAP_MAN_CMD_OP_OUTS,
PWRAP_MAN_CMD);
- pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_CSH,
+ pwrap_writel(wrp, wrp->man_cmd_spi_w | PWRAP_MAN_CMD_OP_CSH,
PWRAP_MAN_CMD);
for (i = 0; i < 4; i++)
- pwrap_writel(wrp, PWRAP_MAN_CMD_SPI_WRITE | PWRAP_MAN_CMD_OP_OUTS,
+ pwrap_writel(wrp, wrp->man_cmd_spi_w | PWRAP_MAN_CMD_OP_OUTS,
PWRAP_MAN_CMD);
ret = pwrap_wait_for_state(wrp, pwrap_is_sync_idle);
@@ -905,6 +909,7 @@ static int pwrap_probe(struct platform_device *pdev)
wrp->dew_base = type->dew_base;
wrp->arb_en_all = type->arb_en_all;
wrp->int_en_all = type->int_en_all;
+ wrp->man_cmd_spi_w = type->man_cmd_spi_w;
wrp->dev = &pdev->dev;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwrap");
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH V2 4/4] soc: mediatek: PMIC wrap: add support for MT7623/6323
[not found] ` <1452441884-25882-1-git-send-email-blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
2016-01-10 16:04 ` [PATCH V2 2/4] soc: mediatek: PMIC wrap: INT_EN mask " John Crispin
2016-01-10 16:04 ` [PATCH V2 3/4] soc: mediatek: PMIC wrap the SPI_W bit in PWRAP_MAN_CMD " John Crispin
@ 2016-01-10 16:04 ` John Crispin
2016-01-12 4:28 ` [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary Henry Chen
3 siblings, 0 replies; 12+ messages in thread
From: John Crispin @ 2016-01-10 16:04 UTC (permalink / raw)
To: Matthias Brugger; +Cc: linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
MT6323 is yet another PMIC made by MTK. This version of the PMIC is used in
combination with MT7623.
Signed-off-by: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
---
drivers/soc/mediatek/mtk-pmic-wrap.c | 176 +++++++++++++++++++++++++++++++++-
1 file changed, 174 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index ceeac3a..556a531 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -52,6 +52,8 @@
#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
/* macro for manual command */
+#define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
+#define PWRAP_MAN_CMD_PMIC_SEL_NEW (1 << 13)
#define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
@@ -82,6 +84,12 @@ enum pwrap_dew_regs {
PWRAP_DEW_CIPHER_MODE,
PWRAP_DEW_CIPHER_SWRST,
+ /* MT6323 only regs */
+ PWRAP_DEW_CRC_SWRST,
+ PWRAP_DEW_CIPHER_EN,
+ PWRAP_DEW_RDDMY_NO,
+ PWRAP_DEW_RDATA_DLY_SEL,
+
/* MT8173 only regs */
PWRAP_DEW_CIPHER_IV0,
PWRAP_DEW_CIPHER_IV1,
@@ -91,6 +99,24 @@ enum pwrap_dew_regs {
PWRAP_DEW_CIPHER_IV5,
};
+static int mt6323_dew_regs[] = {
+ [PWRAP_DEW_DIO_EN] = 0xa,
+ [PWRAP_DEW_READ_TEST] = 0xc,
+ [PWRAP_DEW_WRITE_TEST] = 0xe,
+ [PWRAP_DEW_CRC_SWRST] = 0x10,
+ [PWRAP_DEW_CRC_EN] = 0x12,
+ [PWRAP_DEW_CRC_VAL] = 0x14,
+ [PWRAP_DEW_MON_GRP_SEL] = 0x16,
+ [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
+ [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
+ [PWRAP_DEW_CIPHER_EN] = 0x1c,
+ [PWRAP_DEW_CIPHER_RDY] = 0x1e,
+ [PWRAP_DEW_CIPHER_MODE] = 0x20,
+ [PWRAP_DEW_CIPHER_SWRST] = 0x22,
+ [PWRAP_DEW_RDDMY_NO] = 0x24,
+ [PWRAP_DEW_RDATA_DLY_SEL] = 0x26,
+};
+
static int mt8135_dew_regs[] = {
[PWRAP_DEW_EVENT_OUT_EN] = 0x0,
[PWRAP_DEW_DIO_EN] = 0x2,
@@ -236,6 +262,103 @@ enum pwrap_regs {
PWRAP_DVFS_WDATA7,
PWRAP_SPMINF_STA,
PWRAP_CIPHER_EN,
+
+ /* MT7623 only regs */
+ PWRAP_OP_TYPE,
+ PWRAP_MSB_FIRST,
+ PWRAP_ADC_CMD_ADDR,
+ PWRAP_ADC_CMD,
+ PWRAP_ADC_RDY_ADDR,
+ PWRAP_ADC_RDATA_ADDR1,
+ PWRAP_ADC_RDATA_ADDR2,
+};
+
+static int mt7623_regs[] = {
+ [PWRAP_MUX_SEL] = 0x0,
+ [PWRAP_WRAP_EN] = 0x4,
+ [PWRAP_DIO_EN] = 0x8,
+ [PWRAP_SIDLY] = 0xc,
+ [PWRAP_OP_TYPE] = 0x10,
+ [PWRAP_MSB_FIRST] = 0x14,
+ [PWRAP_RDDMY] = 0x18,
+ [PWRAP_SI_CK_CON] = 0x1c,
+ [PWRAP_CSHEXT_WRITE] = 0x20,
+ [PWRAP_CSHEXT_READ] = 0x24,
+ [PWRAP_CSLEXT_START] = 0x28,
+ [PWRAP_CSLEXT_END] = 0x2c,
+ [PWRAP_STAUPD_PRD] = 0x30,
+ [PWRAP_STAUPD_GRPEN] = 0x34,
+ [PWRAP_STAUPD_MAN_TRIG] = 0x38,
+ [PWRAP_STAUPD_STA] = 0x3C,
+ [PWRAP_WRAP_STA] = 0x44,
+ [PWRAP_HARB_INIT] = 0x48,
+ [PWRAP_HARB_HPRIO] = 0x4c,
+ [PWRAP_HIPRIO_ARB_EN] = 0x50,
+ [PWRAP_HARB_STA0] = 0x54,
+ [PWRAP_HARB_STA1] = 0x58,
+ [PWRAP_MAN_EN] = 0x5c,
+ [PWRAP_MAN_CMD] = 0x60,
+ [PWRAP_MAN_RDATA] = 0x6c,
+ [PWRAP_MAN_VLDCLR] = 0x68,
+ [PWRAP_WACS0_EN] = 0x6c,
+ [PWRAP_INIT_DONE0] = 0x70,
+ [PWRAP_WACS0_CMD] = 0x74,
+ [PWRAP_WACS0_RDATA] = 0x78,
+ [PWRAP_WACS0_VLDCLR] = 0x7c,
+ [PWRAP_WACS1_EN] = 0x80,
+ [PWRAP_INIT_DONE1] = 0x84,
+ [PWRAP_WACS1_CMD] = 0x88,
+ [PWRAP_WACS1_RDATA] = 0x9c,
+ [PWRAP_WACS1_VLDCLR] = 0x90,
+ [PWRAP_WACS2_EN] = 0x94,
+ [PWRAP_INIT_DONE2] = 0x98,
+ [PWRAP_WACS2_CMD] = 0x9c,
+ [PWRAP_WACS2_RDATA] = 0xa0,
+ [PWRAP_WACS2_VLDCLR] = 0xa4,
+ [PWRAP_INT_EN] = 0xa8,
+ [PWRAP_INT_FLG_RAW] = 0xac,
+ [PWRAP_INT_FLG] = 0xb0,
+ [PWRAP_INT_CLR] = 0xb4,
+ [PWRAP_SIG_ADR] = 0xb8,
+ [PWRAP_SIG_MODE] = 0xbc,
+ [PWRAP_SIG_VALUE] = 0xc0,
+ [PWRAP_SIG_ERRVAL] = 0xc4,
+ [PWRAP_CRC_EN] = 0xc8,
+ [PWRAP_TIMER_EN] = 0xcc,
+ [PWRAP_TIMER_STA] = 0xd0,
+ [PWRAP_WDT_UNIT] = 0xd4,
+ [PWRAP_WDT_SRC_EN] = 0xd8,
+ [PWRAP_WDT_FLG] = 0xdc,
+ [PWRAP_DEBUG_INT_SEL] = 0xe0,
+ [PWRAP_DVFS_ADR0] = 0xe4,
+ [PWRAP_DVFS_WDATA0] = 0xe8,
+ [PWRAP_DVFS_ADR1] = 0xec,
+ [PWRAP_DVFS_WDATA1] = 0xf0,
+ [PWRAP_DVFS_ADR2] = 0xf4,
+ [PWRAP_DVFS_WDATA2] = 0xf8,
+ [PWRAP_DVFS_ADR3] = 0xfc,
+ [PWRAP_DVFS_WDATA3] = 0x100,
+ [PWRAP_DVFS_ADR4] = 0x104,
+ [PWRAP_DVFS_WDATA4] = 0x108,
+ [PWRAP_DVFS_ADR5] = 0x10c,
+ [PWRAP_DVFS_WDATA5] = 0x110,
+ [PWRAP_DVFS_ADR6] = 0x114,
+ [PWRAP_DVFS_WDATA6] = 0x118,
+ [PWRAP_DVFS_ADR7] = 0x11c,
+ [PWRAP_DVFS_WDATA7] = 0x120,
+ [PWRAP_CIPHER_KEY_SEL] = 0x124,
+ [PWRAP_CIPHER_IV_SEL] = 0x128,
+ [PWRAP_CIPHER_EN] = 0x12c,
+ [PWRAP_CIPHER_RDY] = 0x130,
+ [PWRAP_CIPHER_MODE] = 0x134,
+ [PWRAP_CIPHER_SWRST] = 0x138,
+ [PWRAP_DCM_EN] = 0x13c,
+ [PWRAP_DCM_DBC_PRD] = 0x140,
+ [PWRAP_ADC_CMD_ADDR] = 0x144,
+ [PWRAP_ADC_CMD] = 0x148,
+ [PWRAP_ADC_RDY_ADDR] = 0x14C,
+ [PWRAP_ADC_RDATA_ADDR1] = 0x150,
+ [PWRAP_ADC_RDATA_ADDR2] = 0x154,
};
static int mt8173_regs[] = {
@@ -394,6 +517,7 @@ static int mt8135_regs[] = {
};
enum pwrap_type {
+ PWRAP_MT7623,
PWRAP_MT8135,
PWRAP_MT8173,
};
@@ -408,6 +532,17 @@ struct pmic_wrapper_type {
u32 man_cmd_spi_w;
};
+static struct pmic_wrapper_type pwrap_mt7623 = {
+ .regs = mt7623_regs,
+ .dew_regs = mt6323_dew_regs,
+ .dew_base = 0x180,
+ .type = PWRAP_MT7623,
+ .arb_en_all = 0x1ff,
+ .int_en_all = BIT(31) | BIT(2),
+ .man_cmd_spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW |
+ PWRAP_MAN_CMD_PMIC_SEL_NEW,
+};
+
static struct pmic_wrapper_type pwrap_mt8135 = {
.regs = mt8135_regs,
.dew_regs = mt8135_dew_regs,
@@ -447,6 +582,11 @@ struct pmic_wrapper {
void __iomem *bridge_base;
};
+static inline int pwrap_is_mt7623(struct pmic_wrapper *wrp)
+{
+ return wrp->type == PWRAP_MT7623;
+}
+
static inline int pwrap_is_mt8135(struct pmic_wrapper *wrp)
{
return wrp->type == PWRAP_MT8135;
@@ -642,6 +782,13 @@ static int pwrap_init_reg_clock(struct pmic_wrapper *wrp)
pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_START);
pwrap_writel(wrp, 0x0, PWRAP_CSLEXT_END);
+ } else if (pwrap_is_mt7623(wrp)) {
+ pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
+ pwrap_dew_write(wrp, 0x8, PWRAP_DEW_RDDMY_NO);
+ pwrap_writel(wrp, 0x5, PWRAP_CSHEXT_WRITE);
+ pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_READ);
+ pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_START);
+ pwrap_writel(wrp, 0x2, PWRAP_CSLEXT_END);
} else {
pwrap_writel(wrp, 0x0, PWRAP_CSHEXT_WRITE);
pwrap_writel(wrp, 0x4, PWRAP_CSHEXT_READ);
@@ -691,8 +838,12 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
- pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
- pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
+ if (pwrap_is_mt7623(wrp)) {
+ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_EN, 0x1);
+ } else {
+ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
+ pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
+ }
/* wait for cipher data ready@AP */
ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
@@ -743,6 +894,14 @@ static int pwrap_init(struct pmic_wrapper *wrp)
/* Enable DCM */
pwrap_writel(wrp, 3, PWRAP_DCM_EN);
pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
+ } else if (pwrap_is_mt7623(wrp)) {
+ /* Enable DCM */
+ pwrap_writel(wrp, 1, PWRAP_DCM_EN);
+ pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
+
+ /* Setup SPI for MT6323 */
+ pwrap_writel(wrp, 0, PWRAP_OP_TYPE);
+ pwrap_writel(wrp, 1, PWRAP_MSB_FIRST);
}
/* Reset SPI slave */
@@ -756,6 +915,10 @@ static int pwrap_init(struct pmic_wrapper *wrp)
pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
+ if (pwrap_is_mt7623(wrp))
+ /* MT6323 expects 0xf dummy cycles */
+ pwrap_writel(wrp, 0xf, PWRAP_RDDMY);
+
ret = pwrap_init_reg_clock(wrp);
if (ret)
return ret;
@@ -828,6 +991,12 @@ static int pwrap_init(struct pmic_wrapper *wrp)
dev_err(wrp->dev, "enable dewrap fail\n");
return -EFAULT;
}
+ } else if (pwrap_is_mt7623(wrp)) {
+ pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
+ pwrap_writel(wrp, 0x8000, PWRAP_ADC_CMD);
+ pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
+ pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
+ pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
} else {
/* PMIC_DEWRAP enables */
if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
@@ -875,6 +1044,9 @@ static const struct regmap_config pwrap_regmap_config = {
static struct of_device_id of_pwrap_match_tbl[] = {
{
+ .compatible = "mediatek,mt7623-pwrap",
+ .data = &pwrap_mt7623,
+ }, {
.compatible = "mediatek,mt8135-pwrap",
.data = &pwrap_mt8135,
}, {
--
1.7.10.4
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary
[not found] ` <1452441884-25882-1-git-send-email-blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
` (2 preceding siblings ...)
2016-01-10 16:04 ` [PATCH V2 4/4] soc: mediatek: PMIC wrap: add support for MT7623/6323 John Crispin
@ 2016-01-12 4:28 ` Henry Chen
2016-01-21 11:44 ` Matthias Brugger
3 siblings, 1 reply; 12+ messages in thread
From: Henry Chen @ 2016-01-12 4:28 UTC (permalink / raw)
To: John Crispin
Cc: Matthias Brugger, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Mon, 2016-01-11 at 00:04 +0800, John Crispin wrote:
> The MT6323 and possible other PMICs have a different DEW base addr. Change
> the driver so that it handles the DEW registeres in the same manner as the
> rest of the registers.
>
> Signed-off-by: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
> ---
> drivers/soc/mediatek/mtk-pmic-wrap.c | 166 +++++++++++++++++++++++++---------
> 1 file changed, 122 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> index 105597a..f3fccea 100644
> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> @@ -61,32 +61,85 @@
> #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
>
> /* macro for slave device wrapper registers */
> -#define PWRAP_DEW_BASE 0xbc00
> -#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
> -#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
> -#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
> -#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
> -#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
> -#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
> -#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
> -#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
> -#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
> -#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
> -#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
> -#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
> -#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
> -#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a)
> -#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
> -#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
> -#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
> -#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
> -#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
> -#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
> -#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
> -#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
> -#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
> -#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
> -#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
> +enum pwrap_dew_regs {
> + PWRAP_DEW_EVENT_OUT_EN,
> + PWRAP_DEW_DIO_EN,
> + PWRAP_DEW_EVENT_SRC_EN,
> + PWRAP_DEW_EVENT_SRC,
> + PWRAP_DEW_EVENT_FLAG,
> + PWRAP_DEW_READ_TEST,
> + PWRAP_DEW_WRITE_TEST,
> + PWRAP_DEW_CRC_EN,
> + PWRAP_DEW_CRC_VAL,
> + PWRAP_DEW_MON_GRP_SEL,
> + PWRAP_DEW_MON_FLAG_SEL,
> + PWRAP_DEW_EVENT_TEST,
> + PWRAP_DEW_CIPHER_KEY_SEL,
> + PWRAP_DEW_CIPHER_IV_SEL,
> + PWRAP_DEW_CIPHER_LOAD,
> + PWRAP_DEW_CIPHER_START,
> + PWRAP_DEW_CIPHER_RDY,
> + PWRAP_DEW_CIPHER_MODE,
> + PWRAP_DEW_CIPHER_SWRST,
> +
> + /* MT8173 only regs */
> + PWRAP_DEW_CIPHER_IV0,
> + PWRAP_DEW_CIPHER_IV1,
> + PWRAP_DEW_CIPHER_IV2,
> + PWRAP_DEW_CIPHER_IV3,
> + PWRAP_DEW_CIPHER_IV4,
> + PWRAP_DEW_CIPHER_IV5,
> +};
> +
> +static int mt8135_dew_regs[] = {
> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
> + [PWRAP_DEW_DIO_EN] = 0x2,
> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
> + [PWRAP_DEW_EVENT_SRC] = 0x6,
> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
> + [PWRAP_DEW_READ_TEST] = 0xa,
> + [PWRAP_DEW_WRITE_TEST] = 0xc,
> + [PWRAP_DEW_CRC_EN] = 0xe,
> + [PWRAP_DEW_CRC_VAL] = 0x10,
> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
> + [PWRAP_DEW_EVENT_TEST] = 0x16,
> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
> + [PWRAP_DEW_CIPHER_START] = 0x1e,
> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
> +};
> +
> +static int mt8173_dew_regs[] = {
> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
> + [PWRAP_DEW_DIO_EN] = 0x2,
> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
> + [PWRAP_DEW_EVENT_SRC] = 0x6,
> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
> + [PWRAP_DEW_READ_TEST] = 0xa,
> + [PWRAP_DEW_WRITE_TEST] = 0xc,
> + [PWRAP_DEW_CRC_EN] = 0xe,
> + [PWRAP_DEW_CRC_VAL] = 0x10,
> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
> + [PWRAP_DEW_EVENT_TEST] = 0x16,
> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
> + [PWRAP_DEW_CIPHER_START] = 0x1e,
> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
> + [PWRAP_DEW_CIPHER_IV0] = 0x26,
> + [PWRAP_DEW_CIPHER_IV1] = 0x28,
> + [PWRAP_DEW_CIPHER_IV2] = 0x2a,
> + [PWRAP_DEW_CIPHER_IV3] = 0x2c,
> + [PWRAP_DEW_CIPHER_IV4] = 0x2e,
> + [PWRAP_DEW_CIPHER_IV5] = 0x30,
> +};
>
> enum pwrap_regs {
> PWRAP_MUX_SEL,
> @@ -347,18 +400,24 @@ enum pwrap_type {
>
> struct pmic_wrapper_type {
> int *regs;
> + int *dew_regs;
> + u32 dew_base;
> enum pwrap_type type;
> u32 arb_en_all;
> };
>
> static struct pmic_wrapper_type pwrap_mt8135 = {
> .regs = mt8135_regs,
> + .dew_regs = mt8135_dew_regs,
> + .dew_base = 0xbc00,
> .type = PWRAP_MT8135,
> .arb_en_all = 0x1ff,
> };
>
> static struct pmic_wrapper_type pwrap_mt8173 = {
> .regs = mt8173_regs,
> + .dew_regs = mt8173_dew_regs,
> + .dew_base = 0xbc00,
> .type = PWRAP_MT8173,
> .arb_en_all = 0x3f,
> };
> @@ -368,6 +427,8 @@ struct pmic_wrapper {
> void __iomem *base;
> struct regmap *regmap;
> int *regs;
> + int *dew_regs;
> + u32 dew_base;
> enum pwrap_type type;
> u32 arb_en_all;
> struct clk *clk_spi;
> @@ -475,6 +536,18 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
> return 0;
> }
Hi John,
Because the DEW was the address of PMIC not the address of AP. I think
that dew_regs/dew_base was much better to define out of pmic_wrapper,
maybe create another structure for it.
struct pwrap_slv_type {
const u32 *dew_regs;
enum pmic_type type;
};
and define for different PMIC, something likes
static const struct pwrap_slv_type pmic_mt6397 = {
.dew_regs = mt6397_regs,
.type = PMIC_MT6397,
};
static const struct pwrap_slv_type pmic_mt6323 = {
.dew_regs = mt6323_regs,
.type = PMIC_MT6323,
};
Thanks,
Henry
>
> +static int pwrap_dew_write(struct pmic_wrapper *wrp, enum pwrap_dew_regs reg,
> + u32 wdata)
> +{
> + return pwrap_write(wrp, wrp->dew_base + wrp->dew_regs[reg], wdata);
> +}
> +
> +static int pwrap_dew_read(struct pmic_wrapper *wrp, enum pwrap_dew_regs reg,
> + u32 *rdata)
> +{
> + return pwrap_read(wrp, wrp->dew_base + wrp->dew_regs[reg], rdata);
> +}
> +
> static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
> {
> return pwrap_read(context, adr, rdata);
> @@ -535,7 +608,7 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
>
> for (i = 0; i < 4; i++) {
> pwrap_writel(wrp, i, PWRAP_SIDLY);
> - pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
> + pwrap_dew_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
> if (rdata == PWRAP_DEW_READ_TEST_VAL) {
> dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
> pass |= 1 << i;
> @@ -581,7 +654,7 @@ static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
> u32 rdata;
> int ret;
>
> - ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
> + ret = pwrap_dew_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
> if (ret)
> return 0;
>
> @@ -606,12 +679,12 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
> }
>
> /* Config cipher mode @PMIC */
> - pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
> - pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
> - pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
> - pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
> - pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
> - pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
>
> /* wait for cipher data ready@AP */
> ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
> @@ -628,7 +701,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
> }
>
> /* wait for cipher mode idle */
> - pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
> ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
> if (ret) {
> dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
> @@ -638,9 +711,10 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
> pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
>
> /* Write Test */
> - if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
> - pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
> - (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
> + if (pwrap_dew_write(wrp, PWRAP_DEW_WRITE_TEST,
> + PWRAP_DEW_WRITE_TEST_VAL) ||
> + pwrap_dew_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
> + (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
> dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
> return -EFAULT;
> }
> @@ -684,7 +758,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
> return ret;
>
> /* Enable dual IO mode */
> - pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1);
> + pwrap_dew_write(wrp, PWRAP_DEW_DIO_EN, 1);
>
> /* Check IDLE & INIT_DONE in advance */
> ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
> @@ -696,7 +770,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
> pwrap_writel(wrp, 1, PWRAP_DIO_EN);
>
> /* Read Test */
> - pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
> + pwrap_dew_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
> if (rdata != PWRAP_DEW_READ_TEST_VAL) {
> dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
> PWRAP_DEW_READ_TEST_VAL, rdata);
> @@ -709,12 +783,13 @@ static int pwrap_init(struct pmic_wrapper *wrp)
> return ret;
>
> /* Signature checking - using CRC */
> - if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
> + if (pwrap_dew_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
> return -EFAULT;
>
> pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
> pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
> - pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
> + pwrap_writel(wrp, wrp->dew_base + wrp->dew_regs[PWRAP_DEW_CRC_VAL],
> + PWRAP_SIG_ADR);
> pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN);
>
> if (pwrap_is_mt8135(wrp))
> @@ -739,8 +814,9 @@ static int pwrap_init(struct pmic_wrapper *wrp)
> writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
>
> /* enable PMIC event out and sources */
> - if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
> - pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
> + if (pwrap_dew_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
> + pwrap_dew_write(wrp, PWRAP_DEW_EVENT_SRC_EN,
> + 0xffff)) {
> dev_err(wrp->dev, "enable dewrap fail\n");
> return -EFAULT;
> }
> @@ -821,6 +897,8 @@ static int pwrap_probe(struct platform_device *pdev)
> type = of_id->data;
> wrp->regs = type->regs;
> wrp->type = type->type;
> + wrp->dew_regs = type->dew_regs;
> + wrp->dew_base = type->dew_base;
> wrp->arb_en_all = type->arb_en_all;
> wrp->dev = &pdev->dev;
>
> --
> 1.7.10.4
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary
2016-01-12 4:28 ` [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary Henry Chen
@ 2016-01-21 11:44 ` Matthias Brugger
[not found] ` <56A0C4B4.8090807-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 12+ messages in thread
From: Matthias Brugger @ 2016-01-21 11:44 UTC (permalink / raw)
To: Henry Chen, John Crispin; +Cc: linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 12/01/16 05:28, Henry Chen wrote:
> On Mon, 2016-01-11 at 00:04 +0800, John Crispin wrote:
>> The MT6323 and possible other PMICs have a different DEW base addr. Change
>> the driver so that it handles the DEW registeres in the same manner as the
>> rest of the registers.
>>
>> Signed-off-by: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
>> ---
>> drivers/soc/mediatek/mtk-pmic-wrap.c | 166 +++++++++++++++++++++++++---------
>> 1 file changed, 122 insertions(+), 44 deletions(-)
>>
>> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
>> index 105597a..f3fccea 100644
>> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
>> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
>> @@ -61,32 +61,85 @@
>> #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
>>
>> /* macro for slave device wrapper registers */
>> -#define PWRAP_DEW_BASE 0xbc00
>> -#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
>> -#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
>> -#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
>> -#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
>> -#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
>> -#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
>> -#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
>> -#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
>> -#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
>> -#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
>> -#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
>> -#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
>> -#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
>> -#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a)
>> -#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
>> -#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
>> -#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
>> -#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
>> -#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
>> -#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
>> -#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
>> -#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
>> -#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
>> -#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
>> -#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
>> +enum pwrap_dew_regs {
>> + PWRAP_DEW_EVENT_OUT_EN,
>> + PWRAP_DEW_DIO_EN,
>> + PWRAP_DEW_EVENT_SRC_EN,
>> + PWRAP_DEW_EVENT_SRC,
>> + PWRAP_DEW_EVENT_FLAG,
>> + PWRAP_DEW_READ_TEST,
>> + PWRAP_DEW_WRITE_TEST,
>> + PWRAP_DEW_CRC_EN,
>> + PWRAP_DEW_CRC_VAL,
>> + PWRAP_DEW_MON_GRP_SEL,
>> + PWRAP_DEW_MON_FLAG_SEL,
>> + PWRAP_DEW_EVENT_TEST,
>> + PWRAP_DEW_CIPHER_KEY_SEL,
>> + PWRAP_DEW_CIPHER_IV_SEL,
>> + PWRAP_DEW_CIPHER_LOAD,
>> + PWRAP_DEW_CIPHER_START,
>> + PWRAP_DEW_CIPHER_RDY,
>> + PWRAP_DEW_CIPHER_MODE,
>> + PWRAP_DEW_CIPHER_SWRST,
>> +
>> + /* MT8173 only regs */
>> + PWRAP_DEW_CIPHER_IV0,
>> + PWRAP_DEW_CIPHER_IV1,
>> + PWRAP_DEW_CIPHER_IV2,
>> + PWRAP_DEW_CIPHER_IV3,
>> + PWRAP_DEW_CIPHER_IV4,
>> + PWRAP_DEW_CIPHER_IV5,
>> +};
>> +
>> +static int mt8135_dew_regs[] = {
>> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
>> + [PWRAP_DEW_DIO_EN] = 0x2,
>> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
>> + [PWRAP_DEW_EVENT_SRC] = 0x6,
>> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
>> + [PWRAP_DEW_READ_TEST] = 0xa,
>> + [PWRAP_DEW_WRITE_TEST] = 0xc,
>> + [PWRAP_DEW_CRC_EN] = 0xe,
>> + [PWRAP_DEW_CRC_VAL] = 0x10,
>> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
>> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
>> + [PWRAP_DEW_EVENT_TEST] = 0x16,
>> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
>> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
>> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
>> + [PWRAP_DEW_CIPHER_START] = 0x1e,
>> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
>> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
>> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
>> +};
>> +
>> +static int mt8173_dew_regs[] = {
>> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
>> + [PWRAP_DEW_DIO_EN] = 0x2,
>> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
>> + [PWRAP_DEW_EVENT_SRC] = 0x6,
>> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
>> + [PWRAP_DEW_READ_TEST] = 0xa,
>> + [PWRAP_DEW_WRITE_TEST] = 0xc,
>> + [PWRAP_DEW_CRC_EN] = 0xe,
>> + [PWRAP_DEW_CRC_VAL] = 0x10,
>> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
>> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
>> + [PWRAP_DEW_EVENT_TEST] = 0x16,
>> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
>> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
>> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
>> + [PWRAP_DEW_CIPHER_START] = 0x1e,
>> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
>> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
>> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
>> + [PWRAP_DEW_CIPHER_IV0] = 0x26,
>> + [PWRAP_DEW_CIPHER_IV1] = 0x28,
>> + [PWRAP_DEW_CIPHER_IV2] = 0x2a,
>> + [PWRAP_DEW_CIPHER_IV3] = 0x2c,
>> + [PWRAP_DEW_CIPHER_IV4] = 0x2e,
>> + [PWRAP_DEW_CIPHER_IV5] = 0x30,
>> +};
>>
>> enum pwrap_regs {
>> PWRAP_MUX_SEL,
>> @@ -347,18 +400,24 @@ enum pwrap_type {
>>
>> struct pmic_wrapper_type {
>> int *regs;
>> + int *dew_regs;
>> + u32 dew_base;
>> enum pwrap_type type;
>> u32 arb_en_all;
>> };
>>
>> static struct pmic_wrapper_type pwrap_mt8135 = {
>> .regs = mt8135_regs,
>> + .dew_regs = mt8135_dew_regs,
>> + .dew_base = 0xbc00,
>> .type = PWRAP_MT8135,
>> .arb_en_all = 0x1ff,
>> };
>>
>> static struct pmic_wrapper_type pwrap_mt8173 = {
>> .regs = mt8173_regs,
>> + .dew_regs = mt8173_dew_regs,
>> + .dew_base = 0xbc00,
>> .type = PWRAP_MT8173,
>> .arb_en_all = 0x3f,
>> };
>> @@ -368,6 +427,8 @@ struct pmic_wrapper {
>> void __iomem *base;
>> struct regmap *regmap;
>> int *regs;
>> + int *dew_regs;
>> + u32 dew_base;
>> enum pwrap_type type;
>> u32 arb_en_all;
>> struct clk *clk_spi;
>> @@ -475,6 +536,18 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
>> return 0;
>> }
>
> Hi John,
>
> Because the DEW was the address of PMIC not the address of AP. I think
> that dew_regs/dew_base was much better to define out of pmic_wrapper,
> maybe create another structure for it.
>
> struct pwrap_slv_type {
> const u32 *dew_regs;
> enum pmic_type type;
> };
>
> and define for different PMIC, something likes
>
> static const struct pwrap_slv_type pmic_mt6397 = {
> .dew_regs = mt6397_regs,
> .type = PMIC_MT6397,
> };
>
> static const struct pwrap_slv_type pmic_mt6323 = {
> .dew_regs = mt6323_regs,
> .type = PMIC_MT6323,
> };
>
I would like to go one step further and actually get the DEW values
depending on the PMIC in the device tree, which is the child of the
pmic-wrapper.
Regards,
Matthias
> Thanks,
> Henry
>
>>
>> +static int pwrap_dew_write(struct pmic_wrapper *wrp, enum pwrap_dew_regs reg,
>> + u32 wdata)
>> +{
>> + return pwrap_write(wrp, wrp->dew_base + wrp->dew_regs[reg], wdata);
>> +}
>> +
>> +static int pwrap_dew_read(struct pmic_wrapper *wrp, enum pwrap_dew_regs reg,
>> + u32 *rdata)
>> +{
>> + return pwrap_read(wrp, wrp->dew_base + wrp->dew_regs[reg], rdata);
>> +}
>> +
>> static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
>> {
>> return pwrap_read(context, adr, rdata);
>> @@ -535,7 +608,7 @@ static int pwrap_init_sidly(struct pmic_wrapper *wrp)
>>
>> for (i = 0; i < 4; i++) {
>> pwrap_writel(wrp, i, PWRAP_SIDLY);
>> - pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
>> + pwrap_dew_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
>> if (rdata == PWRAP_DEW_READ_TEST_VAL) {
>> dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
>> pass |= 1 << i;
>> @@ -581,7 +654,7 @@ static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
>> u32 rdata;
>> int ret;
>>
>> - ret = pwrap_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
>> + ret = pwrap_dew_read(wrp, PWRAP_DEW_CIPHER_RDY, &rdata);
>> if (ret)
>> return 0;
>>
>> @@ -606,12 +679,12 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
>> }
>>
>> /* Config cipher mode @PMIC */
>> - pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
>> - pwrap_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
>> - pwrap_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
>> - pwrap_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
>> - pwrap_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
>> - pwrap_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
>> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x1);
>> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_SWRST, 0x0);
>> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_KEY_SEL, 0x1);
>> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_IV_SEL, 0x2);
>> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_LOAD, 0x1);
>> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_START, 0x1);
>>
>> /* wait for cipher data ready@AP */
>> ret = pwrap_wait_for_state(wrp, pwrap_is_cipher_ready);
>> @@ -628,7 +701,7 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
>> }
>>
>> /* wait for cipher mode idle */
>> - pwrap_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
>> + pwrap_dew_write(wrp, PWRAP_DEW_CIPHER_MODE, 0x1);
>> ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
>> if (ret) {
>> dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
>> @@ -638,9 +711,10 @@ static int pwrap_init_cipher(struct pmic_wrapper *wrp)
>> pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
>>
>> /* Write Test */
>> - if (pwrap_write(wrp, PWRAP_DEW_WRITE_TEST, PWRAP_DEW_WRITE_TEST_VAL) ||
>> - pwrap_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
>> - (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
>> + if (pwrap_dew_write(wrp, PWRAP_DEW_WRITE_TEST,
>> + PWRAP_DEW_WRITE_TEST_VAL) ||
>> + pwrap_dew_read(wrp, PWRAP_DEW_WRITE_TEST, &rdata) ||
>> + (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
>> dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
>> return -EFAULT;
>> }
>> @@ -684,7 +758,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
>> return ret;
>>
>> /* Enable dual IO mode */
>> - pwrap_write(wrp, PWRAP_DEW_DIO_EN, 1);
>> + pwrap_dew_write(wrp, PWRAP_DEW_DIO_EN, 1);
>>
>> /* Check IDLE & INIT_DONE in advance */
>> ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle_and_sync_idle);
>> @@ -696,7 +770,7 @@ static int pwrap_init(struct pmic_wrapper *wrp)
>> pwrap_writel(wrp, 1, PWRAP_DIO_EN);
>>
>> /* Read Test */
>> - pwrap_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
>> + pwrap_dew_read(wrp, PWRAP_DEW_READ_TEST, &rdata);
>> if (rdata != PWRAP_DEW_READ_TEST_VAL) {
>> dev_err(wrp->dev, "Read test failed after switch to DIO mode: 0x%04x != 0x%04x\n",
>> PWRAP_DEW_READ_TEST_VAL, rdata);
>> @@ -709,12 +783,13 @@ static int pwrap_init(struct pmic_wrapper *wrp)
>> return ret;
>>
>> /* Signature checking - using CRC */
>> - if (pwrap_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
>> + if (pwrap_dew_write(wrp, PWRAP_DEW_CRC_EN, 0x1))
>> return -EFAULT;
>>
>> pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
>> pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
>> - pwrap_writel(wrp, PWRAP_DEW_CRC_VAL, PWRAP_SIG_ADR);
>> + pwrap_writel(wrp, wrp->dew_base + wrp->dew_regs[PWRAP_DEW_CRC_VAL],
>> + PWRAP_SIG_ADR);
>> pwrap_writel(wrp, wrp->arb_en_all, PWRAP_HIPRIO_ARB_EN);
>>
>> if (pwrap_is_mt8135(wrp))
>> @@ -739,8 +814,9 @@ static int pwrap_init(struct pmic_wrapper *wrp)
>> writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
>>
>> /* enable PMIC event out and sources */
>> - if (pwrap_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
>> - pwrap_write(wrp, PWRAP_DEW_EVENT_SRC_EN, 0xffff)) {
>> + if (pwrap_dew_write(wrp, PWRAP_DEW_EVENT_OUT_EN, 0x1) ||
>> + pwrap_dew_write(wrp, PWRAP_DEW_EVENT_SRC_EN,
>> + 0xffff)) {
>> dev_err(wrp->dev, "enable dewrap fail\n");
>> return -EFAULT;
>> }
>> @@ -821,6 +897,8 @@ static int pwrap_probe(struct platform_device *pdev)
>> type = of_id->data;
>> wrp->regs = type->regs;
>> wrp->type = type->type;
>> + wrp->dew_regs = type->dew_regs;
>> + wrp->dew_base = type->dew_base;
>> wrp->arb_en_all = type->arb_en_all;
>> wrp->dev = &pdev->dev;
>>
>> --
>> 1.7.10.4
>>
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary
[not found] ` <56A0C4B4.8090807-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2016-01-21 13:05 ` John Crispin
[not found] ` <56A0D7AA.3010301-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
0 siblings, 1 reply; 12+ messages in thread
From: John Crispin @ 2016-01-21 13:05 UTC (permalink / raw)
To: Matthias Brugger, Henry Chen
Cc: linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 21/01/2016 12:44, Matthias Brugger wrote:
>
>
> On 12/01/16 05:28, Henry Chen wrote:
>> On Mon, 2016-01-11 at 00:04 +0800, John Crispin wrote:
>>> The MT6323 and possible other PMICs have a different DEW base addr.
>>> Change
>>> the driver so that it handles the DEW registeres in the same manner
>>> as the
>>> rest of the registers.
>>>
>>> Signed-off-by: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
>>> ---
>>> drivers/soc/mediatek/mtk-pmic-wrap.c | 166
>>> +++++++++++++++++++++++++---------
>>> 1 file changed, 122 insertions(+), 44 deletions(-)
>>>
>>> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c
>>> b/drivers/soc/mediatek/mtk-pmic-wrap.c
>>> index 105597a..f3fccea 100644
>>> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
>>> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
>>> @@ -61,32 +61,85 @@
>>> #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
>>>
>>> /* macro for slave device wrapper registers */
>>> -#define PWRAP_DEW_BASE 0xbc00
>>> -#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
>>> -#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
>>> -#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
>>> -#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
>>> -#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
>>> -#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
>>> -#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
>>> -#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
>>> -#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
>>> -#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
>>> -#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
>>> -#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
>>> -#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
>>> -#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a)
>>> -#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
>>> -#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
>>> -#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
>>> -#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
>>> -#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
>>> -#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
>>> -#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
>>> -#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
>>> -#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
>>> -#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
>>> -#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
>>> +enum pwrap_dew_regs {
>>> + PWRAP_DEW_EVENT_OUT_EN,
>>> + PWRAP_DEW_DIO_EN,
>>> + PWRAP_DEW_EVENT_SRC_EN,
>>> + PWRAP_DEW_EVENT_SRC,
>>> + PWRAP_DEW_EVENT_FLAG,
>>> + PWRAP_DEW_READ_TEST,
>>> + PWRAP_DEW_WRITE_TEST,
>>> + PWRAP_DEW_CRC_EN,
>>> + PWRAP_DEW_CRC_VAL,
>>> + PWRAP_DEW_MON_GRP_SEL,
>>> + PWRAP_DEW_MON_FLAG_SEL,
>>> + PWRAP_DEW_EVENT_TEST,
>>> + PWRAP_DEW_CIPHER_KEY_SEL,
>>> + PWRAP_DEW_CIPHER_IV_SEL,
>>> + PWRAP_DEW_CIPHER_LOAD,
>>> + PWRAP_DEW_CIPHER_START,
>>> + PWRAP_DEW_CIPHER_RDY,
>>> + PWRAP_DEW_CIPHER_MODE,
>>> + PWRAP_DEW_CIPHER_SWRST,
>>> +
>>> + /* MT8173 only regs */
>>> + PWRAP_DEW_CIPHER_IV0,
>>> + PWRAP_DEW_CIPHER_IV1,
>>> + PWRAP_DEW_CIPHER_IV2,
>>> + PWRAP_DEW_CIPHER_IV3,
>>> + PWRAP_DEW_CIPHER_IV4,
>>> + PWRAP_DEW_CIPHER_IV5,
>>> +};
>>> +
>>> +static int mt8135_dew_regs[] = {
>>> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
>>> + [PWRAP_DEW_DIO_EN] = 0x2,
>>> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
>>> + [PWRAP_DEW_EVENT_SRC] = 0x6,
>>> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
>>> + [PWRAP_DEW_READ_TEST] = 0xa,
>>> + [PWRAP_DEW_WRITE_TEST] = 0xc,
>>> + [PWRAP_DEW_CRC_EN] = 0xe,
>>> + [PWRAP_DEW_CRC_VAL] = 0x10,
>>> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
>>> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
>>> + [PWRAP_DEW_EVENT_TEST] = 0x16,
>>> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
>>> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
>>> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
>>> + [PWRAP_DEW_CIPHER_START] = 0x1e,
>>> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
>>> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
>>> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
>>> +};
>>> +
>>> +static int mt8173_dew_regs[] = {
>>> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
>>> + [PWRAP_DEW_DIO_EN] = 0x2,
>>> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
>>> + [PWRAP_DEW_EVENT_SRC] = 0x6,
>>> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
>>> + [PWRAP_DEW_READ_TEST] = 0xa,
>>> + [PWRAP_DEW_WRITE_TEST] = 0xc,
>>> + [PWRAP_DEW_CRC_EN] = 0xe,
>>> + [PWRAP_DEW_CRC_VAL] = 0x10,
>>> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
>>> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
>>> + [PWRAP_DEW_EVENT_TEST] = 0x16,
>>> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
>>> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
>>> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
>>> + [PWRAP_DEW_CIPHER_START] = 0x1e,
>>> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
>>> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
>>> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
>>> + [PWRAP_DEW_CIPHER_IV0] = 0x26,
>>> + [PWRAP_DEW_CIPHER_IV1] = 0x28,
>>> + [PWRAP_DEW_CIPHER_IV2] = 0x2a,
>>> + [PWRAP_DEW_CIPHER_IV3] = 0x2c,
>>> + [PWRAP_DEW_CIPHER_IV4] = 0x2e,
>>> + [PWRAP_DEW_CIPHER_IV5] = 0x30,
>>> +};
>>>
>>> enum pwrap_regs {
>>> PWRAP_MUX_SEL,
>>> @@ -347,18 +400,24 @@ enum pwrap_type {
>>>
>>> struct pmic_wrapper_type {
>>> int *regs;
>>> + int *dew_regs;
>>> + u32 dew_base;
>>> enum pwrap_type type;
>>> u32 arb_en_all;
>>> };
>>>
>>> static struct pmic_wrapper_type pwrap_mt8135 = {
>>> .regs = mt8135_regs,
>>> + .dew_regs = mt8135_dew_regs,
>>> + .dew_base = 0xbc00,
>>> .type = PWRAP_MT8135,
>>> .arb_en_all = 0x1ff,
>>> };
>>>
>>> static struct pmic_wrapper_type pwrap_mt8173 = {
>>> .regs = mt8173_regs,
>>> + .dew_regs = mt8173_dew_regs,
>>> + .dew_base = 0xbc00,
>>> .type = PWRAP_MT8173,
>>> .arb_en_all = 0x3f,
>>> };
>>> @@ -368,6 +427,8 @@ struct pmic_wrapper {
>>> void __iomem *base;
>>> struct regmap *regmap;
>>> int *regs;
>>> + int *dew_regs;
>>> + u32 dew_base;
>>> enum pwrap_type type;
>>> u32 arb_en_all;
>>> struct clk *clk_spi;
>>> @@ -475,6 +536,18 @@ static int pwrap_read(struct pmic_wrapper *wrp,
>>> u32 adr, u32 *rdata)
>>> return 0;
>>> }
>>
>> Hi John,
>>
>> Because the DEW was the address of PMIC not the address of AP. I think
>> that dew_regs/dew_base was much better to define out of pmic_wrapper,
>> maybe create another structure for it.
>>
>> struct pwrap_slv_type {
>> const u32 *dew_regs;
>> enum pmic_type type;
>> };
>>
>> and define for different PMIC, something likes
>>
>> static const struct pwrap_slv_type pmic_mt6397 = {
>> .dew_regs = mt6397_regs,
>> .type = PMIC_MT6397,
>> };
>>
>> static const struct pwrap_slv_type pmic_mt6323 = {
>> .dew_regs = mt6323_regs,
>> .type = PMIC_MT6323,
>> };
>>
>
> I would like to go one step further and actually get the DEW values
> depending on the PMIC in the device tree, which is the child of the
> pmic-wrapper.
>
> Regards,
> Matthias
not sure if that is a good idea. the code path and dew register usage
depends on the slave type. putting the dew registers into the DT will
only have the effect that we will have 1 array less in the driver but in
turn will have code to load that exact array back. also it wont be a
simple array that we store in the DT. but we need to match register
names to register offsets.
although i agree that putting static data into the DT tends to be a good
thing i believe in this case it is not really sane.
John
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary
[not found] ` <56A0D7AA.3010301-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
@ 2016-01-21 16:28 ` Matthias Brugger
[not found] ` <56A10718.1010801-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 12+ messages in thread
From: Matthias Brugger @ 2016-01-21 16:28 UTC (permalink / raw)
To: John Crispin, Henry Chen; +Cc: linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 21/01/16 14:05, John Crispin wrote:
>
>
> On 21/01/2016 12:44, Matthias Brugger wrote:
>>
>>
>> On 12/01/16 05:28, Henry Chen wrote:
>>> On Mon, 2016-01-11 at 00:04 +0800, John Crispin wrote:
>>>> The MT6323 and possible other PMICs have a different DEW base addr.
>>>> Change
>>>> the driver so that it handles the DEW registeres in the same manner
>>>> as the
>>>> rest of the registers.
>>>>
>>>> Signed-off-by: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
>>>> ---
>>>> drivers/soc/mediatek/mtk-pmic-wrap.c | 166
>>>> +++++++++++++++++++++++++---------
>>>> 1 file changed, 122 insertions(+), 44 deletions(-)
>>>>
>>>> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c
>>>> b/drivers/soc/mediatek/mtk-pmic-wrap.c
>>>> index 105597a..f3fccea 100644
>>>> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
>>>> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
>>>> @@ -61,32 +61,85 @@
>>>> #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
>>>>
>>>> /* macro for slave device wrapper registers */
>>>> -#define PWRAP_DEW_BASE 0xbc00
>>>> -#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
>>>> -#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
>>>> -#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
>>>> -#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
>>>> -#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
>>>> -#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
>>>> -#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
>>>> -#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
>>>> -#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
>>>> -#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
>>>> -#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
>>>> -#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
>>>> -#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
>>>> -#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a)
>>>> -#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
>>>> -#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
>>>> -#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
>>>> -#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
>>>> -#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
>>>> +enum pwrap_dew_regs {
>>>> + PWRAP_DEW_EVENT_OUT_EN,
>>>> + PWRAP_DEW_DIO_EN,
>>>> + PWRAP_DEW_EVENT_SRC_EN,
>>>> + PWRAP_DEW_EVENT_SRC,
>>>> + PWRAP_DEW_EVENT_FLAG,
>>>> + PWRAP_DEW_READ_TEST,
>>>> + PWRAP_DEW_WRITE_TEST,
>>>> + PWRAP_DEW_CRC_EN,
>>>> + PWRAP_DEW_CRC_VAL,
>>>> + PWRAP_DEW_MON_GRP_SEL,
>>>> + PWRAP_DEW_MON_FLAG_SEL,
>>>> + PWRAP_DEW_EVENT_TEST,
>>>> + PWRAP_DEW_CIPHER_KEY_SEL,
>>>> + PWRAP_DEW_CIPHER_IV_SEL,
>>>> + PWRAP_DEW_CIPHER_LOAD,
>>>> + PWRAP_DEW_CIPHER_START,
>>>> + PWRAP_DEW_CIPHER_RDY,
>>>> + PWRAP_DEW_CIPHER_MODE,
>>>> + PWRAP_DEW_CIPHER_SWRST,
>>>> +
>>>> + /* MT8173 only regs */
>>>> + PWRAP_DEW_CIPHER_IV0,
>>>> + PWRAP_DEW_CIPHER_IV1,
>>>> + PWRAP_DEW_CIPHER_IV2,
>>>> + PWRAP_DEW_CIPHER_IV3,
>>>> + PWRAP_DEW_CIPHER_IV4,
>>>> + PWRAP_DEW_CIPHER_IV5,
>>>> +};
>>>> +
>>>> +static int mt8135_dew_regs[] = {
>>>> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
>>>> + [PWRAP_DEW_DIO_EN] = 0x2,
>>>> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
>>>> + [PWRAP_DEW_EVENT_SRC] = 0x6,
>>>> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
>>>> + [PWRAP_DEW_READ_TEST] = 0xa,
>>>> + [PWRAP_DEW_WRITE_TEST] = 0xc,
>>>> + [PWRAP_DEW_CRC_EN] = 0xe,
>>>> + [PWRAP_DEW_CRC_VAL] = 0x10,
>>>> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
>>>> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
>>>> + [PWRAP_DEW_EVENT_TEST] = 0x16,
>>>> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
>>>> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
>>>> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
>>>> + [PWRAP_DEW_CIPHER_START] = 0x1e,
>>>> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
>>>> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
>>>> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
>>>> +};
>>>> +
>>>> +static int mt8173_dew_regs[] = {
>>>> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
>>>> + [PWRAP_DEW_DIO_EN] = 0x2,
>>>> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
>>>> + [PWRAP_DEW_EVENT_SRC] = 0x6,
>>>> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
>>>> + [PWRAP_DEW_READ_TEST] = 0xa,
>>>> + [PWRAP_DEW_WRITE_TEST] = 0xc,
>>>> + [PWRAP_DEW_CRC_EN] = 0xe,
>>>> + [PWRAP_DEW_CRC_VAL] = 0x10,
>>>> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
>>>> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
>>>> + [PWRAP_DEW_EVENT_TEST] = 0x16,
>>>> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
>>>> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
>>>> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
>>>> + [PWRAP_DEW_CIPHER_START] = 0x1e,
>>>> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
>>>> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
>>>> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
>>>> + [PWRAP_DEW_CIPHER_IV0] = 0x26,
>>>> + [PWRAP_DEW_CIPHER_IV1] = 0x28,
>>>> + [PWRAP_DEW_CIPHER_IV2] = 0x2a,
>>>> + [PWRAP_DEW_CIPHER_IV3] = 0x2c,
>>>> + [PWRAP_DEW_CIPHER_IV4] = 0x2e,
>>>> + [PWRAP_DEW_CIPHER_IV5] = 0x30,
>>>> +};
>>>>
>>>> enum pwrap_regs {
>>>> PWRAP_MUX_SEL,
>>>> @@ -347,18 +400,24 @@ enum pwrap_type {
>>>>
>>>> struct pmic_wrapper_type {
>>>> int *regs;
>>>> + int *dew_regs;
>>>> + u32 dew_base;
>>>> enum pwrap_type type;
>>>> u32 arb_en_all;
>>>> };
>>>>
>>>> static struct pmic_wrapper_type pwrap_mt8135 = {
>>>> .regs = mt8135_regs,
>>>> + .dew_regs = mt8135_dew_regs,
>>>> + .dew_base = 0xbc00,
>>>> .type = PWRAP_MT8135,
>>>> .arb_en_all = 0x1ff,
>>>> };
>>>>
>>>> static struct pmic_wrapper_type pwrap_mt8173 = {
>>>> .regs = mt8173_regs,
>>>> + .dew_regs = mt8173_dew_regs,
>>>> + .dew_base = 0xbc00,
>>>> .type = PWRAP_MT8173,
>>>> .arb_en_all = 0x3f,
>>>> };
>>>> @@ -368,6 +427,8 @@ struct pmic_wrapper {
>>>> void __iomem *base;
>>>> struct regmap *regmap;
>>>> int *regs;
>>>> + int *dew_regs;
>>>> + u32 dew_base;
>>>> enum pwrap_type type;
>>>> u32 arb_en_all;
>>>> struct clk *clk_spi;
>>>> @@ -475,6 +536,18 @@ static int pwrap_read(struct pmic_wrapper *wrp,
>>>> u32 adr, u32 *rdata)
>>>> return 0;
>>>> }
>>>
>>> Hi John,
>>>
>>> Because the DEW was the address of PMIC not the address of AP. I think
>>> that dew_regs/dew_base was much better to define out of pmic_wrapper,
>>> maybe create another structure for it.
>>>
>>> struct pwrap_slv_type {
>>> const u32 *dew_regs;
>>> enum pmic_type type;
>>> };
>>>
>>> and define for different PMIC, something likes
>>>
>>> static const struct pwrap_slv_type pmic_mt6397 = {
>>> .dew_regs = mt6397_regs,
>>> .type = PMIC_MT6397,
>>> };
>>>
>>> static const struct pwrap_slv_type pmic_mt6323 = {
>>> .dew_regs = mt6323_regs,
>>> .type = PMIC_MT6323,
>>> };
>>>
>>
>> I would like to go one step further and actually get the DEW values
>> depending on the PMIC in the device tree, which is the child of the
>> pmic-wrapper.
>>
>> Regards,
>> Matthias
>
>
> not sure if that is a good idea. the code path and dew register usage
> depends on the slave type. putting the dew registers into the DT will
> only have the effect that we will have 1 array less in the driver but in
> turn will have code to load that exact array back. also it wont be a
> simple array that we store in the DT. but we need to match register
> names to register offsets.
>
> although i agree that putting static data into the DT tends to be a good
> thing i believe in this case it is not really sane.
>
Actually I wasn't thinking of this. My idea (poor mans solution) would
be to identify the pmic dts node and use the values dependent on this,
rather then on the SoC version.
The premium class solution would be to have the registers definded in
the pmic driver and get them accessed through the pmic-wrapper driver.
Regards,
Matthias
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary
[not found] ` <56A10718.1010801-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2016-01-21 16:51 ` John Crispin
[not found] ` <56A10C7A.5080809-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
0 siblings, 1 reply; 12+ messages in thread
From: John Crispin @ 2016-01-21 16:51 UTC (permalink / raw)
To: Matthias Brugger, Henry Chen
Cc: linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 21/01/2016 17:28, Matthias Brugger wrote:
>
>
> On 21/01/16 14:05, John Crispin wrote:
>>
>>
>> On 21/01/2016 12:44, Matthias Brugger wrote:
>>>
>>>
>>> On 12/01/16 05:28, Henry Chen wrote:
>>>> On Mon, 2016-01-11 at 00:04 +0800, John Crispin wrote:
>>>>> The MT6323 and possible other PMICs have a different DEW base addr.
>>>>> Change
>>>>> the driver so that it handles the DEW registeres in the same manner
>>>>> as the
>>>>> rest of the registers.
>>>>>
>>>>> Signed-off-by: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
>>>>> ---
>>>>> drivers/soc/mediatek/mtk-pmic-wrap.c | 166
>>>>> +++++++++++++++++++++++++---------
>>>>> 1 file changed, 122 insertions(+), 44 deletions(-)
>>>>>
>>>>> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c
>>>>> b/drivers/soc/mediatek/mtk-pmic-wrap.c
>>>>> index 105597a..f3fccea 100644
>>>>> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
>>>>> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
>>>>> @@ -61,32 +61,85 @@
>>>>> #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
>>>>>
>>>>> /* macro for slave device wrapper registers */
>>>>> -#define PWRAP_DEW_BASE 0xbc00
>>>>> -#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
>>>>> -#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
>>>>> -#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
>>>>> -#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
>>>>> -#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
>>>>> -#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
>>>>> -#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
>>>>> -#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
>>>>> -#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
>>>>> -#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
>>>>> -#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
>>>>> -#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
>>>>> -#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
>>>>> -#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE +
>>>>> 0x1a)
>>>>> -#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
>>>>> -#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
>>>>> -#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
>>>>> -#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
>>>>> -#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
>>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
>>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
>>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
>>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
>>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
>>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
>>>>> +enum pwrap_dew_regs {
>>>>> + PWRAP_DEW_EVENT_OUT_EN,
>>>>> + PWRAP_DEW_DIO_EN,
>>>>> + PWRAP_DEW_EVENT_SRC_EN,
>>>>> + PWRAP_DEW_EVENT_SRC,
>>>>> + PWRAP_DEW_EVENT_FLAG,
>>>>> + PWRAP_DEW_READ_TEST,
>>>>> + PWRAP_DEW_WRITE_TEST,
>>>>> + PWRAP_DEW_CRC_EN,
>>>>> + PWRAP_DEW_CRC_VAL,
>>>>> + PWRAP_DEW_MON_GRP_SEL,
>>>>> + PWRAP_DEW_MON_FLAG_SEL,
>>>>> + PWRAP_DEW_EVENT_TEST,
>>>>> + PWRAP_DEW_CIPHER_KEY_SEL,
>>>>> + PWRAP_DEW_CIPHER_IV_SEL,
>>>>> + PWRAP_DEW_CIPHER_LOAD,
>>>>> + PWRAP_DEW_CIPHER_START,
>>>>> + PWRAP_DEW_CIPHER_RDY,
>>>>> + PWRAP_DEW_CIPHER_MODE,
>>>>> + PWRAP_DEW_CIPHER_SWRST,
>>>>> +
>>>>> + /* MT8173 only regs */
>>>>> + PWRAP_DEW_CIPHER_IV0,
>>>>> + PWRAP_DEW_CIPHER_IV1,
>>>>> + PWRAP_DEW_CIPHER_IV2,
>>>>> + PWRAP_DEW_CIPHER_IV3,
>>>>> + PWRAP_DEW_CIPHER_IV4,
>>>>> + PWRAP_DEW_CIPHER_IV5,
>>>>> +};
>>>>> +
>>>>> +static int mt8135_dew_regs[] = {
>>>>> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
>>>>> + [PWRAP_DEW_DIO_EN] = 0x2,
>>>>> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
>>>>> + [PWRAP_DEW_EVENT_SRC] = 0x6,
>>>>> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
>>>>> + [PWRAP_DEW_READ_TEST] = 0xa,
>>>>> + [PWRAP_DEW_WRITE_TEST] = 0xc,
>>>>> + [PWRAP_DEW_CRC_EN] = 0xe,
>>>>> + [PWRAP_DEW_CRC_VAL] = 0x10,
>>>>> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
>>>>> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
>>>>> + [PWRAP_DEW_EVENT_TEST] = 0x16,
>>>>> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
>>>>> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
>>>>> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
>>>>> + [PWRAP_DEW_CIPHER_START] = 0x1e,
>>>>> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
>>>>> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
>>>>> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
>>>>> +};
>>>>> +
>>>>> +static int mt8173_dew_regs[] = {
>>>>> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
>>>>> + [PWRAP_DEW_DIO_EN] = 0x2,
>>>>> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
>>>>> + [PWRAP_DEW_EVENT_SRC] = 0x6,
>>>>> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
>>>>> + [PWRAP_DEW_READ_TEST] = 0xa,
>>>>> + [PWRAP_DEW_WRITE_TEST] = 0xc,
>>>>> + [PWRAP_DEW_CRC_EN] = 0xe,
>>>>> + [PWRAP_DEW_CRC_VAL] = 0x10,
>>>>> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
>>>>> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
>>>>> + [PWRAP_DEW_EVENT_TEST] = 0x16,
>>>>> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
>>>>> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
>>>>> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
>>>>> + [PWRAP_DEW_CIPHER_START] = 0x1e,
>>>>> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
>>>>> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
>>>>> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
>>>>> + [PWRAP_DEW_CIPHER_IV0] = 0x26,
>>>>> + [PWRAP_DEW_CIPHER_IV1] = 0x28,
>>>>> + [PWRAP_DEW_CIPHER_IV2] = 0x2a,
>>>>> + [PWRAP_DEW_CIPHER_IV3] = 0x2c,
>>>>> + [PWRAP_DEW_CIPHER_IV4] = 0x2e,
>>>>> + [PWRAP_DEW_CIPHER_IV5] = 0x30,
>>>>> +};
>>>>>
>>>>> enum pwrap_regs {
>>>>> PWRAP_MUX_SEL,
>>>>> @@ -347,18 +400,24 @@ enum pwrap_type {
>>>>>
>>>>> struct pmic_wrapper_type {
>>>>> int *regs;
>>>>> + int *dew_regs;
>>>>> + u32 dew_base;
>>>>> enum pwrap_type type;
>>>>> u32 arb_en_all;
>>>>> };
>>>>>
>>>>> static struct pmic_wrapper_type pwrap_mt8135 = {
>>>>> .regs = mt8135_regs,
>>>>> + .dew_regs = mt8135_dew_regs,
>>>>> + .dew_base = 0xbc00,
>>>>> .type = PWRAP_MT8135,
>>>>> .arb_en_all = 0x1ff,
>>>>> };
>>>>>
>>>>> static struct pmic_wrapper_type pwrap_mt8173 = {
>>>>> .regs = mt8173_regs,
>>>>> + .dew_regs = mt8173_dew_regs,
>>>>> + .dew_base = 0xbc00,
>>>>> .type = PWRAP_MT8173,
>>>>> .arb_en_all = 0x3f,
>>>>> };
>>>>> @@ -368,6 +427,8 @@ struct pmic_wrapper {
>>>>> void __iomem *base;
>>>>> struct regmap *regmap;
>>>>> int *regs;
>>>>> + int *dew_regs;
>>>>> + u32 dew_base;
>>>>> enum pwrap_type type;
>>>>> u32 arb_en_all;
>>>>> struct clk *clk_spi;
>>>>> @@ -475,6 +536,18 @@ static int pwrap_read(struct pmic_wrapper *wrp,
>>>>> u32 adr, u32 *rdata)
>>>>> return 0;
>>>>> }
>>>>
>>>> Hi John,
>>>>
>>>> Because the DEW was the address of PMIC not the address of AP. I think
>>>> that dew_regs/dew_base was much better to define out of pmic_wrapper,
>>>> maybe create another structure for it.
>>>>
>>>> struct pwrap_slv_type {
>>>> const u32 *dew_regs;
>>>> enum pmic_type type;
>>>> };
>>>>
>>>> and define for different PMIC, something likes
>>>>
>>>> static const struct pwrap_slv_type pmic_mt6397 = {
>>>> .dew_regs = mt6397_regs,
>>>> .type = PMIC_MT6397,
>>>> };
>>>>
>>>> static const struct pwrap_slv_type pmic_mt6323 = {
>>>> .dew_regs = mt6323_regs,
>>>> .type = PMIC_MT6323,
>>>> };
>>>>
>>>
>>> I would like to go one step further and actually get the DEW values
>>> depending on the PMIC in the device tree, which is the child of the
>>> pmic-wrapper.
>>>
>>> Regards,
>>> Matthias
>>
>>
>> not sure if that is a good idea. the code path and dew register usage
>> depends on the slave type. putting the dew registers into the DT will
>> only have the effect that we will have 1 array less in the driver but in
>> turn will have code to load that exact array back. also it wont be a
>> simple array that we store in the DT. but we need to match register
>> names to register offsets.
>>
>> although i agree that putting static data into the DT tends to be a good
>> thing i believe in this case it is not really sane.
>>
>
> Actually I wasn't thinking of this. My idea (poor mans solution) would
> be to identify the pmic dts node and use the values dependent on this,
> rather then on the SoC version.
i have that bit already in my series based on code i got from mtk.
however even cooler might be to just read the CID register and make an
educated decision based on that.
i'll try to cleanup the patches tomorrow and then post them.
>
> The premium class solution would be to have the registers definded in
> the pmic driver and get them accessed through the pmic-wrapper driver.
indeed that would be an option.
another thing that we might want to replace the pwrap_is_mtxyz()
functions and use switch (pwrap->type) { case PWRAP_MTXYZ: ... }
constructs instead.
John
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary
[not found] ` <56A10C7A.5080809-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
@ 2016-01-21 17:23 ` Matthias Brugger
2016-01-22 5:04 ` Henry Chen
1 sibling, 0 replies; 12+ messages in thread
From: Matthias Brugger @ 2016-01-21 17:23 UTC (permalink / raw)
To: John Crispin, Henry Chen; +Cc: linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On 21/01/16 17:51, John Crispin wrote:
>
>
> On 21/01/2016 17:28, Matthias Brugger wrote:
>>
>>
>> On 21/01/16 14:05, John Crispin wrote:
>>>
>>>
>>> On 21/01/2016 12:44, Matthias Brugger wrote:
>>>>
>>>>
>>>> On 12/01/16 05:28, Henry Chen wrote:
>>>>> On Mon, 2016-01-11 at 00:04 +0800, John Crispin wrote:
>>>>>> The MT6323 and possible other PMICs have a different DEW base addr.
>>>>>> Change
>>>>>> the driver so that it handles the DEW registeres in the same manner
>>>>>> as the
>>>>>> rest of the registers.
>>>>>>
>>>>>> Signed-off-by: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
>>>>>> ---
>>>>>> drivers/soc/mediatek/mtk-pmic-wrap.c | 166
>>>>>> +++++++++++++++++++++++++---------
>>>>>> 1 file changed, 122 insertions(+), 44 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c
>>>>>> b/drivers/soc/mediatek/mtk-pmic-wrap.c
>>>>>> index 105597a..f3fccea 100644
>>>>>> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
>>>>>> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
>>>>>> @@ -61,32 +61,85 @@
>>>>>> #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
>>>>>>
>>>>>> /* macro for slave device wrapper registers */
>>>>>> -#define PWRAP_DEW_BASE 0xbc00
>>>>>> -#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
>>>>>> -#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
>>>>>> -#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
>>>>>> -#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
>>>>>> -#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
>>>>>> -#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
>>>>>> -#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
>>>>>> -#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
>>>>>> -#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
>>>>>> -#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
>>>>>> -#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
>>>>>> -#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
>>>>>> -#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
>>>>>> -#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE +
>>>>>> 0x1a)
>>>>>> -#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
>>>>>> -#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
>>>>>> -#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
>>>>>> -#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
>>>>>> -#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
>>>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
>>>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
>>>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
>>>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
>>>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
>>>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
>>>>>> +enum pwrap_dew_regs {
>>>>>> + PWRAP_DEW_EVENT_OUT_EN,
>>>>>> + PWRAP_DEW_DIO_EN,
>>>>>> + PWRAP_DEW_EVENT_SRC_EN,
>>>>>> + PWRAP_DEW_EVENT_SRC,
>>>>>> + PWRAP_DEW_EVENT_FLAG,
>>>>>> + PWRAP_DEW_READ_TEST,
>>>>>> + PWRAP_DEW_WRITE_TEST,
>>>>>> + PWRAP_DEW_CRC_EN,
>>>>>> + PWRAP_DEW_CRC_VAL,
>>>>>> + PWRAP_DEW_MON_GRP_SEL,
>>>>>> + PWRAP_DEW_MON_FLAG_SEL,
>>>>>> + PWRAP_DEW_EVENT_TEST,
>>>>>> + PWRAP_DEW_CIPHER_KEY_SEL,
>>>>>> + PWRAP_DEW_CIPHER_IV_SEL,
>>>>>> + PWRAP_DEW_CIPHER_LOAD,
>>>>>> + PWRAP_DEW_CIPHER_START,
>>>>>> + PWRAP_DEW_CIPHER_RDY,
>>>>>> + PWRAP_DEW_CIPHER_MODE,
>>>>>> + PWRAP_DEW_CIPHER_SWRST,
>>>>>> +
>>>>>> + /* MT8173 only regs */
>>>>>> + PWRAP_DEW_CIPHER_IV0,
>>>>>> + PWRAP_DEW_CIPHER_IV1,
>>>>>> + PWRAP_DEW_CIPHER_IV2,
>>>>>> + PWRAP_DEW_CIPHER_IV3,
>>>>>> + PWRAP_DEW_CIPHER_IV4,
>>>>>> + PWRAP_DEW_CIPHER_IV5,
>>>>>> +};
>>>>>> +
>>>>>> +static int mt8135_dew_regs[] = {
>>>>>> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
>>>>>> + [PWRAP_DEW_DIO_EN] = 0x2,
>>>>>> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
>>>>>> + [PWRAP_DEW_EVENT_SRC] = 0x6,
>>>>>> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
>>>>>> + [PWRAP_DEW_READ_TEST] = 0xa,
>>>>>> + [PWRAP_DEW_WRITE_TEST] = 0xc,
>>>>>> + [PWRAP_DEW_CRC_EN] = 0xe,
>>>>>> + [PWRAP_DEW_CRC_VAL] = 0x10,
>>>>>> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
>>>>>> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
>>>>>> + [PWRAP_DEW_EVENT_TEST] = 0x16,
>>>>>> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
>>>>>> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
>>>>>> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
>>>>>> + [PWRAP_DEW_CIPHER_START] = 0x1e,
>>>>>> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
>>>>>> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
>>>>>> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
>>>>>> +};
>>>>>> +
>>>>>> +static int mt8173_dew_regs[] = {
>>>>>> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
>>>>>> + [PWRAP_DEW_DIO_EN] = 0x2,
>>>>>> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
>>>>>> + [PWRAP_DEW_EVENT_SRC] = 0x6,
>>>>>> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
>>>>>> + [PWRAP_DEW_READ_TEST] = 0xa,
>>>>>> + [PWRAP_DEW_WRITE_TEST] = 0xc,
>>>>>> + [PWRAP_DEW_CRC_EN] = 0xe,
>>>>>> + [PWRAP_DEW_CRC_VAL] = 0x10,
>>>>>> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
>>>>>> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
>>>>>> + [PWRAP_DEW_EVENT_TEST] = 0x16,
>>>>>> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
>>>>>> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
>>>>>> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
>>>>>> + [PWRAP_DEW_CIPHER_START] = 0x1e,
>>>>>> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
>>>>>> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
>>>>>> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
>>>>>> + [PWRAP_DEW_CIPHER_IV0] = 0x26,
>>>>>> + [PWRAP_DEW_CIPHER_IV1] = 0x28,
>>>>>> + [PWRAP_DEW_CIPHER_IV2] = 0x2a,
>>>>>> + [PWRAP_DEW_CIPHER_IV3] = 0x2c,
>>>>>> + [PWRAP_DEW_CIPHER_IV4] = 0x2e,
>>>>>> + [PWRAP_DEW_CIPHER_IV5] = 0x30,
>>>>>> +};
>>>>>>
>>>>>> enum pwrap_regs {
>>>>>> PWRAP_MUX_SEL,
>>>>>> @@ -347,18 +400,24 @@ enum pwrap_type {
>>>>>>
>>>>>> struct pmic_wrapper_type {
>>>>>> int *regs;
>>>>>> + int *dew_regs;
>>>>>> + u32 dew_base;
>>>>>> enum pwrap_type type;
>>>>>> u32 arb_en_all;
>>>>>> };
>>>>>>
>>>>>> static struct pmic_wrapper_type pwrap_mt8135 = {
>>>>>> .regs = mt8135_regs,
>>>>>> + .dew_regs = mt8135_dew_regs,
>>>>>> + .dew_base = 0xbc00,
>>>>>> .type = PWRAP_MT8135,
>>>>>> .arb_en_all = 0x1ff,
>>>>>> };
>>>>>>
>>>>>> static struct pmic_wrapper_type pwrap_mt8173 = {
>>>>>> .regs = mt8173_regs,
>>>>>> + .dew_regs = mt8173_dew_regs,
>>>>>> + .dew_base = 0xbc00,
>>>>>> .type = PWRAP_MT8173,
>>>>>> .arb_en_all = 0x3f,
>>>>>> };
>>>>>> @@ -368,6 +427,8 @@ struct pmic_wrapper {
>>>>>> void __iomem *base;
>>>>>> struct regmap *regmap;
>>>>>> int *regs;
>>>>>> + int *dew_regs;
>>>>>> + u32 dew_base;
>>>>>> enum pwrap_type type;
>>>>>> u32 arb_en_all;
>>>>>> struct clk *clk_spi;
>>>>>> @@ -475,6 +536,18 @@ static int pwrap_read(struct pmic_wrapper *wrp,
>>>>>> u32 adr, u32 *rdata)
>>>>>> return 0;
>>>>>> }
>>>>>
>>>>> Hi John,
>>>>>
>>>>> Because the DEW was the address of PMIC not the address of AP. I think
>>>>> that dew_regs/dew_base was much better to define out of pmic_wrapper,
>>>>> maybe create another structure for it.
>>>>>
>>>>> struct pwrap_slv_type {
>>>>> const u32 *dew_regs;
>>>>> enum pmic_type type;
>>>>> };
>>>>>
>>>>> and define for different PMIC, something likes
>>>>>
>>>>> static const struct pwrap_slv_type pmic_mt6397 = {
>>>>> .dew_regs = mt6397_regs,
>>>>> .type = PMIC_MT6397,
>>>>> };
>>>>>
>>>>> static const struct pwrap_slv_type pmic_mt6323 = {
>>>>> .dew_regs = mt6323_regs,
>>>>> .type = PMIC_MT6323,
>>>>> };
>>>>>
>>>>
>>>> I would like to go one step further and actually get the DEW values
>>>> depending on the PMIC in the device tree, which is the child of the
>>>> pmic-wrapper.
>>>>
>>>> Regards,
>>>> Matthias
>>>
>>>
>>> not sure if that is a good idea. the code path and dew register usage
>>> depends on the slave type. putting the dew registers into the DT will
>>> only have the effect that we will have 1 array less in the driver but in
>>> turn will have code to load that exact array back. also it wont be a
>>> simple array that we store in the DT. but we need to match register
>>> names to register offsets.
>>>
>>> although i agree that putting static data into the DT tends to be a good
>>> thing i believe in this case it is not really sane.
>>>
>>
>> Actually I wasn't thinking of this. My idea (poor mans solution) would
>> be to identify the pmic dts node and use the values dependent on this,
>> rather then on the SoC version.
>
> i have that bit already in my series based on code i got from mtk.
>
> however even cooler might be to just read the CID register and make an
> educated decision based on that.
>
> i'll try to cleanup the patches tomorrow and then post them.
>
>>
>> The premium class solution would be to have the registers definded in
>> the pmic driver and get them accessed through the pmic-wrapper driver.
>
> indeed that would be an option.
>
> another thing that we might want to replace the pwrap_is_mtxyz()
> functions and use switch (pwrap->type) { case PWRAP_MTXYZ: ... }
> constructs instead.
>
Yeah, that would be good. Would you mind doing this?
If yes, it would be great if you base your work on the v4.5-next/soc [1]
branch.
Cheers,
Matthias
[1] https://github.com/mbgg/linux-mediatek/tree/v4.5-next/soc
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary
[not found] ` <56A10C7A.5080809-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
2016-01-21 17:23 ` Matthias Brugger
@ 2016-01-22 5:04 ` Henry Chen
2016-01-22 9:03 ` John Crispin
1 sibling, 1 reply; 12+ messages in thread
From: Henry Chen @ 2016-01-22 5:04 UTC (permalink / raw)
To: John Crispin
Cc: Matthias Brugger, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Thu, 2016-01-21 at 17:51 +0100, John Crispin wrote:
>
> On 21/01/2016 17:28, Matthias Brugger wrote:
> >
> >
> > On 21/01/16 14:05, John Crispin wrote:
> >>
> >>
> >> On 21/01/2016 12:44, Matthias Brugger wrote:
> >>>
> >>>
> >>> On 12/01/16 05:28, Henry Chen wrote:
> >>>> On Mon, 2016-01-11 at 00:04 +0800, John Crispin wrote:
> >>>>> The MT6323 and possible other PMICs have a different DEW base addr.
> >>>>> Change
> >>>>> the driver so that it handles the DEW registeres in the same manner
> >>>>> as the
> >>>>> rest of the registers.
> >>>>>
> >>>>> Signed-off-by: John Crispin <blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
> >>>>> ---
> >>>>> drivers/soc/mediatek/mtk-pmic-wrap.c | 166
> >>>>> +++++++++++++++++++++++++---------
> >>>>> 1 file changed, 122 insertions(+), 44 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c
> >>>>> b/drivers/soc/mediatek/mtk-pmic-wrap.c
> >>>>> index 105597a..f3fccea 100644
> >>>>> --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> >>>>> +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> >>>>> @@ -61,32 +61,85 @@
> >>>>> #define PWRAP_MAN_CMD_OP_OUTQ (0xa << 8)
> >>>>>
> >>>>> /* macro for slave device wrapper registers */
> >>>>> -#define PWRAP_DEW_BASE 0xbc00
> >>>>> -#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0)
> >>>>> -#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2)
> >>>>> -#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4)
> >>>>> -#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6)
> >>>>> -#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8)
> >>>>> -#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa)
> >>>>> -#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc)
> >>>>> -#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe)
> >>>>> -#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10)
> >>>>> -#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12)
> >>>>> -#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14)
> >>>>> -#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16)
> >>>>> -#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18)
> >>>>> -#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE +
> >>>>> 0x1a)
> >>>>> -#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c)
> >>>>> -#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e)
> >>>>> -#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20)
> >>>>> -#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22)
> >>>>> -#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24)
> >>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26)
> >>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28)
> >>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a)
> >>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c)
> >>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e)
> >>>>> -#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30)
> >>>>> +enum pwrap_dew_regs {
> >>>>> + PWRAP_DEW_EVENT_OUT_EN,
> >>>>> + PWRAP_DEW_DIO_EN,
> >>>>> + PWRAP_DEW_EVENT_SRC_EN,
> >>>>> + PWRAP_DEW_EVENT_SRC,
> >>>>> + PWRAP_DEW_EVENT_FLAG,
> >>>>> + PWRAP_DEW_READ_TEST,
> >>>>> + PWRAP_DEW_WRITE_TEST,
> >>>>> + PWRAP_DEW_CRC_EN,
> >>>>> + PWRAP_DEW_CRC_VAL,
> >>>>> + PWRAP_DEW_MON_GRP_SEL,
> >>>>> + PWRAP_DEW_MON_FLAG_SEL,
> >>>>> + PWRAP_DEW_EVENT_TEST,
> >>>>> + PWRAP_DEW_CIPHER_KEY_SEL,
> >>>>> + PWRAP_DEW_CIPHER_IV_SEL,
> >>>>> + PWRAP_DEW_CIPHER_LOAD,
> >>>>> + PWRAP_DEW_CIPHER_START,
> >>>>> + PWRAP_DEW_CIPHER_RDY,
> >>>>> + PWRAP_DEW_CIPHER_MODE,
> >>>>> + PWRAP_DEW_CIPHER_SWRST,
> >>>>> +
> >>>>> + /* MT8173 only regs */
> >>>>> + PWRAP_DEW_CIPHER_IV0,
> >>>>> + PWRAP_DEW_CIPHER_IV1,
> >>>>> + PWRAP_DEW_CIPHER_IV2,
> >>>>> + PWRAP_DEW_CIPHER_IV3,
> >>>>> + PWRAP_DEW_CIPHER_IV4,
> >>>>> + PWRAP_DEW_CIPHER_IV5,
> >>>>> +};
> >>>>> +
> >>>>> +static int mt8135_dew_regs[] = {
> >>>>> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
> >>>>> + [PWRAP_DEW_DIO_EN] = 0x2,
> >>>>> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
> >>>>> + [PWRAP_DEW_EVENT_SRC] = 0x6,
> >>>>> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
> >>>>> + [PWRAP_DEW_READ_TEST] = 0xa,
> >>>>> + [PWRAP_DEW_WRITE_TEST] = 0xc,
> >>>>> + [PWRAP_DEW_CRC_EN] = 0xe,
> >>>>> + [PWRAP_DEW_CRC_VAL] = 0x10,
> >>>>> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
> >>>>> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
> >>>>> + [PWRAP_DEW_EVENT_TEST] = 0x16,
> >>>>> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
> >>>>> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
> >>>>> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
> >>>>> + [PWRAP_DEW_CIPHER_START] = 0x1e,
> >>>>> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
> >>>>> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
> >>>>> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
> >>>>> +};
> >>>>> +
> >>>>> +static int mt8173_dew_regs[] = {
> >>>>> + [PWRAP_DEW_EVENT_OUT_EN] = 0x0,
> >>>>> + [PWRAP_DEW_DIO_EN] = 0x2,
> >>>>> + [PWRAP_DEW_EVENT_SRC_EN] = 0x4,
> >>>>> + [PWRAP_DEW_EVENT_SRC] = 0x6,
> >>>>> + [PWRAP_DEW_EVENT_FLAG] = 0x8,
> >>>>> + [PWRAP_DEW_READ_TEST] = 0xa,
> >>>>> + [PWRAP_DEW_WRITE_TEST] = 0xc,
> >>>>> + [PWRAP_DEW_CRC_EN] = 0xe,
> >>>>> + [PWRAP_DEW_CRC_VAL] = 0x10,
> >>>>> + [PWRAP_DEW_MON_GRP_SEL] = 0x12,
> >>>>> + [PWRAP_DEW_MON_FLAG_SEL] = 0x14,
> >>>>> + [PWRAP_DEW_EVENT_TEST] = 0x16,
> >>>>> + [PWRAP_DEW_CIPHER_KEY_SEL] = 0x18,
> >>>>> + [PWRAP_DEW_CIPHER_IV_SEL] = 0x1a,
> >>>>> + [PWRAP_DEW_CIPHER_LOAD] = 0x1c,
> >>>>> + [PWRAP_DEW_CIPHER_START] = 0x1e,
> >>>>> + [PWRAP_DEW_CIPHER_RDY] = 0x20,
> >>>>> + [PWRAP_DEW_CIPHER_MODE] = 0x22,
> >>>>> + [PWRAP_DEW_CIPHER_SWRST] = 0x24,
> >>>>> + [PWRAP_DEW_CIPHER_IV0] = 0x26,
> >>>>> + [PWRAP_DEW_CIPHER_IV1] = 0x28,
> >>>>> + [PWRAP_DEW_CIPHER_IV2] = 0x2a,
> >>>>> + [PWRAP_DEW_CIPHER_IV3] = 0x2c,
> >>>>> + [PWRAP_DEW_CIPHER_IV4] = 0x2e,
> >>>>> + [PWRAP_DEW_CIPHER_IV5] = 0x30,
> >>>>> +};
> >>>>>
> >>>>> enum pwrap_regs {
> >>>>> PWRAP_MUX_SEL,
> >>>>> @@ -347,18 +400,24 @@ enum pwrap_type {
> >>>>>
> >>>>> struct pmic_wrapper_type {
> >>>>> int *regs;
> >>>>> + int *dew_regs;
> >>>>> + u32 dew_base;
> >>>>> enum pwrap_type type;
> >>>>> u32 arb_en_all;
> >>>>> };
> >>>>>
> >>>>> static struct pmic_wrapper_type pwrap_mt8135 = {
> >>>>> .regs = mt8135_regs,
> >>>>> + .dew_regs = mt8135_dew_regs,
> >>>>> + .dew_base = 0xbc00,
> >>>>> .type = PWRAP_MT8135,
> >>>>> .arb_en_all = 0x1ff,
> >>>>> };
> >>>>>
> >>>>> static struct pmic_wrapper_type pwrap_mt8173 = {
> >>>>> .regs = mt8173_regs,
> >>>>> + .dew_regs = mt8173_dew_regs,
> >>>>> + .dew_base = 0xbc00,
> >>>>> .type = PWRAP_MT8173,
> >>>>> .arb_en_all = 0x3f,
> >>>>> };
> >>>>> @@ -368,6 +427,8 @@ struct pmic_wrapper {
> >>>>> void __iomem *base;
> >>>>> struct regmap *regmap;
> >>>>> int *regs;
> >>>>> + int *dew_regs;
> >>>>> + u32 dew_base;
> >>>>> enum pwrap_type type;
> >>>>> u32 arb_en_all;
> >>>>> struct clk *clk_spi;
> >>>>> @@ -475,6 +536,18 @@ static int pwrap_read(struct pmic_wrapper *wrp,
> >>>>> u32 adr, u32 *rdata)
> >>>>> return 0;
> >>>>> }
> >>>>
> >>>> Hi John,
> >>>>
> >>>> Because the DEW was the address of PMIC not the address of AP. I think
> >>>> that dew_regs/dew_base was much better to define out of pmic_wrapper,
> >>>> maybe create another structure for it.
> >>>>
> >>>> struct pwrap_slv_type {
> >>>> const u32 *dew_regs;
> >>>> enum pmic_type type;
> >>>> };
> >>>>
> >>>> and define for different PMIC, something likes
> >>>>
> >>>> static const struct pwrap_slv_type pmic_mt6397 = {
> >>>> .dew_regs = mt6397_regs,
> >>>> .type = PMIC_MT6397,
> >>>> };
> >>>>
> >>>> static const struct pwrap_slv_type pmic_mt6323 = {
> >>>> .dew_regs = mt6323_regs,
> >>>> .type = PMIC_MT6323,
> >>>> };
> >>>>
> >>>
> >>> I would like to go one step further and actually get the DEW values
> >>> depending on the PMIC in the device tree, which is the child of the
> >>> pmic-wrapper.
> >>>
> >>> Regards,
> >>> Matthias
> >>
> >>
> >> not sure if that is a good idea. the code path and dew register usage
> >> depends on the slave type. putting the dew registers into the DT will
> >> only have the effect that we will have 1 array less in the driver but in
> >> turn will have code to load that exact array back. also it wont be a
> >> simple array that we store in the DT. but we need to match register
> >> names to register offsets.
> >>
> >> although i agree that putting static data into the DT tends to be a good
> >> thing i believe in this case it is not really sane.
> >>
> >
> > Actually I wasn't thinking of this. My idea (poor mans solution) would
> > be to identify the pmic dts node and use the values dependent on this,
> > rather then on the SoC version.
>
> i have that bit already in my series based on code i got from mtk.
>
> however even cooler might be to just read the CID register and make an
> educated decision based on that.
>
CID of mt6397/mt6391/mt6323 was 0x0100 => bit[7:0]
> i'll try to cleanup the patches tomorrow and then post them.
>
> >
> > The premium class solution would be to have the registers definded in
> > the pmic driver and get them accessed through the pmic-wrapper driver.
>
> indeed that would be an option.
There was a problem, pmic-wrapper driver was needed to probe before pmic
driver, if DEW address was definded in the pmic driver or stored in pmic
device tree, how could pmic-wrap driver to get them because pmic driver
was not initialize yet?
Henry
>
> another thing that we might want to replace the pwrap_is_mtxyz()
> functions and use switch (pwrap->type) { case PWRAP_MTXYZ: ... }
> constructs instead.
>
> John
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary
2016-01-22 5:04 ` Henry Chen
@ 2016-01-22 9:03 ` John Crispin
0 siblings, 0 replies; 12+ messages in thread
From: John Crispin @ 2016-01-22 9:03 UTC (permalink / raw)
To: Henry Chen
Cc: Matthias Brugger, linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Hi Henry
>>>> not sure if that is a good idea. the code path and dew register usage
>>>> depends on the slave type. putting the dew registers into the DT will
>>>> only have the effect that we will have 1 array less in the driver but in
>>>> turn will have code to load that exact array back. also it wont be a
>>>> simple array that we store in the DT. but we need to match register
>>>> names to register offsets.
>>>>
>>>> although i agree that putting static data into the DT tends to be a good
>>>> thing i believe in this case it is not really sane.
>>>>
>>>
>>> Actually I wasn't thinking of this. My idea (poor mans solution) would
>>> be to identify the pmic dts node and use the values dependent on this,
>>> rather then on the SoC version.
>>
>> i have that bit already in my series based on code i got from mtk.
>>
>> however even cooler might be to just read the CID register and make an
>> educated decision based on that.
>>
> CID of mt6397/mt6391/mt6323 was 0x0100 => bit[7:0]
>
Yep, i have a patch here that i will test today that utilizes the CID
register.
>> i'll try to cleanup the patches tomorrow and then post them.
>>
>>>
>>> The premium class solution would be to have the registers definded in
>>> the pmic driver and get them accessed through the pmic-wrapper driver.
>>
>> indeed that would be an option.
> There was a problem, pmic-wrapper driver was needed to probe before pmic
> driver, if DEW address was definded in the pmic driver or stored in pmic
> device tree, how could pmic-wrap driver to get them because pmic driver
> was not initialize yet?
>
That is exactly what i was wondering about. i can only think of
solutions that would
i have respun the series and will resend it today once i tested it on a
device.
John
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2016-01-22 9:03 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-01-10 16:04 [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary John Crispin
[not found] ` <1452441884-25882-1-git-send-email-blogic-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
2016-01-10 16:04 ` [PATCH V2 2/4] soc: mediatek: PMIC wrap: INT_EN mask " John Crispin
2016-01-10 16:04 ` [PATCH V2 3/4] soc: mediatek: PMIC wrap the SPI_W bit in PWRAP_MAN_CMD " John Crispin
2016-01-10 16:04 ` [PATCH V2 4/4] soc: mediatek: PMIC wrap: add support for MT7623/6323 John Crispin
2016-01-12 4:28 ` [PATCH V2 1/4] soc: mediatek: PMIC wrap: DEW base addr may vary Henry Chen
2016-01-21 11:44 ` Matthias Brugger
[not found] ` <56A0C4B4.8090807-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-01-21 13:05 ` John Crispin
[not found] ` <56A0D7AA.3010301-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
2016-01-21 16:28 ` Matthias Brugger
[not found] ` <56A10718.1010801-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2016-01-21 16:51 ` John Crispin
[not found] ` <56A10C7A.5080809-p3rKhJxN3npAfugRpC6u6w@public.gmane.org>
2016-01-21 17:23 ` Matthias Brugger
2016-01-22 5:04 ` Henry Chen
2016-01-22 9:03 ` John Crispin
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