From: Alexander Graf <agraf@suse.de>
To: David Gibson <david@gibson.dropbear.id.au>, benh@kernel.crashing.org
Cc: aik@ozlabs.ru, lvivier@redhat.com, thuth@redhat.com,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 00/10] Clean up page size handling for ppc 64-bit hash MMUs with TCG
Date: Mon, 25 Jan 2016 21:36:40 +0100 [thread overview]
Message-ID: <56A68758.8090805@suse.de> (raw)
In-Reply-To: <20160125111040.GH32205@voom.redhat.com>
On 01/25/2016 12:10 PM, David Gibson wrote:
> On Mon, Jan 25, 2016 at 04:15:42PM +1100, David Gibson wrote:
>> Encoding of page sizes on 64-bit hash MMUs for Power is rather arcane,
>> involving control bits in both the SLB and HPTE. At present we
>> support a few of the options, but far fewer than real hardware.
>>
>> We're able to get away with that in practice, because guests use a
>> device tree property to determine which page sizes are available and
>> we are setting that to match. However, the fact that the actual code
>> doesn't necessarily what we put into the table of available page sizes
>> is another ugliness.
>>
>> This series makes a number of cleanups to the page size handling. The
>> upshot is that afterwards the softmmu code operates off the same page
>> size encoding table that is advertised to the guests, ensuring that
>> they will be in sync.
>>
>> Finally, we extend the table of allowed sizes for POWER7 and POWER8 to
>> include the options allowed in hardware (including MPSS). We can fix
>> other hash MMU based CPUs in future if anyone cares enough.
>>
>> Please review, and I'll fold into ppc-for-2.6 for my next pull.
> Bother, somehow missed a serious bug in here that's causing
> oops-on-boot. Sorry, still tracking it down.
I still have no idea where your bug is (bisect probably should get you
there pretty quick), but the overall concept sounds very reasonable to
me. Please benchmark performance before and after in the next cover
letter also :)
Reviewed-by: Alexander Graf <agraf@suse.de>
Alex
next prev parent reply other threads:[~2016-01-25 20:36 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-25 5:15 [Qemu-devel] [PATCH 00/10] Clean up page size handling for ppc 64-bit hash MMUs with TCG David Gibson
2016-01-25 5:15 ` [Qemu-devel] [PATCH 01/10] target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub David Gibson
2016-01-25 5:15 ` [Qemu-devel] [PATCH 02/10] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU David Gibson
2016-01-25 5:15 ` [Qemu-devel] [PATCH 03/10] target-ppc: Rework ppc_store_slb David Gibson
2016-01-25 19:22 ` Alexander Graf
2016-01-27 0:04 ` David Gibson
2016-01-27 7:32 ` Thomas Huth
2016-01-27 10:07 ` David Gibson
2016-01-25 5:15 ` [Qemu-devel] [PATCH 04/10] target-ppc: Rework SLB page size lookup David Gibson
2016-01-25 19:38 ` Alexander Graf
2016-01-27 0:59 ` David Gibson
2016-01-25 5:15 ` [Qemu-devel] [PATCH 05/10] target-ppc: Use actual page size encodings from HPTE David Gibson
2016-01-25 13:26 ` David Gibson
2016-01-25 20:18 ` Alexander Graf
2016-01-27 0:40 ` David Gibson
2016-01-25 5:15 ` [Qemu-devel] [PATCH 06/10] target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one David Gibson
2016-01-25 5:15 ` [Qemu-devel] [PATCH 07/10] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one() David Gibson
2016-01-25 5:15 ` [Qemu-devel] [PATCH 08/10] target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs David Gibson
2016-01-25 5:15 ` [Qemu-devel] [PATCH 09/10] target-ppc: Helper to determine page size information from hpte alone David Gibson
2016-01-25 5:15 ` [Qemu-devel] [PATCH 10/10] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG David Gibson
2016-01-25 11:10 ` [Qemu-devel] [PATCH 00/10] Clean up page size handling for ppc 64-bit hash MMUs with TCG David Gibson
2016-01-25 20:36 ` Alexander Graf [this message]
2016-01-26 5:41 ` David Gibson
2016-01-26 7:09 ` Alexander Graf
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