* [U-Boot] [PATCH 1/2] video: Add support for Armada XP LCD controller
@ 2016-01-20 7:13 Stefan Roese
2016-01-20 7:13 ` [U-Boot] [PATCH 2/2] arm: mvebu: Add support for the Armada XP theadorable board Stefan Roese
2016-01-23 22:18 ` [U-Boot] [PATCH 1/2] video: Add support for Armada XP LCD controller Anatolij Gustschin
0 siblings, 2 replies; 4+ messages in thread
From: Stefan Roese @ 2016-01-20 7:13 UTC (permalink / raw)
To: u-boot
This patch adds basic support for the LCD controller of the Marvell
Armada XP SoC.
An AXP based custom board port will be added later, to use this
driver to display a splash screen via the bmp command later.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
arch/arm/mach-mvebu/include/mach/cpu.h | 13 +
arch/arm/mach-mvebu/include/mach/soc.h | 1 +
drivers/video/Kconfig | 7 +
drivers/video/Makefile | 1 +
drivers/video/mvebu_lcd.c | 532 +++++++++++++++++++++++++++++++++
5 files changed, 554 insertions(+)
create mode 100644 drivers/video/mvebu_lcd.c
diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h
index 47f45c1..017d55f 100644
--- a/arch/arm/mach-mvebu/include/mach/cpu.h
+++ b/arch/arm/mach-mvebu/include/mach/cpu.h
@@ -145,5 +145,18 @@ int serdes_phy_config(void);
* drivers/ddr/marvell
*/
int ddr3_init(void);
+
+struct mvebu_lcd_info {
+ u32 fb_base;
+ int x_res;
+ int y_res;
+ int x_fp; /* frontporch */
+ int y_fp;
+ int x_bp; /* backporch */
+ int y_bp;
+};
+
+int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info);
+
#endif /* __ASSEMBLY__ */
#endif /* _MVEBU_CPU_H */
diff --git a/arch/arm/mach-mvebu/include/mach/soc.h b/arch/arm/mach-mvebu/include/mach/soc.h
index cb216bc..b317940 100644
--- a/arch/arm/mach-mvebu/include/mach/soc.h
+++ b/arch/arm/mach-mvebu/include/mach/soc.h
@@ -67,6 +67,7 @@
#define MVEBU_SATA0_BASE (MVEBU_REGISTER(0xa8000))
#define MVEBU_NAND_BASE (MVEBU_REGISTER(0xd0000))
#define MVEBU_SDIO_BASE (MVEBU_REGISTER(0xd8000))
+#define MVEBU_LCD_BASE (MVEBU_REGISTER(0xe0000))
#define SOC_COHERENCY_FABRIC_CTRL_REG (MVEBU_REGISTER(0x20200))
#define MBUS_ERR_PROP_EN (1 << 8)
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index caf1efc..64dbf1f 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -247,6 +247,13 @@ config DISPLAY_PORT
to drive LCD panels. This framework provides support for enabling
these displays where supported by the video hardware.
+config VIDEO_MVEBU
+ bool "Armada XP LCD controller"
+ default n
+ ---help---
+ Support for the LCD controller integrated in the Marvell
+ Armada XP SoC.
+
config VIDEO_TEGRA124
bool "Enable video support on Tegra124"
help
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index e85fd8a..64cb61c 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
+obj-$(CONFIG_VIDEO_MVEBU) += mvebu_lcd.o
obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o
obj-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o
obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o
diff --git a/drivers/video/mvebu_lcd.c b/drivers/video/mvebu_lcd.c
new file mode 100644
index 0000000..86dae52
--- /dev/null
+++ b/drivers/video/mvebu_lcd.c
@@ -0,0 +1,532 @@
+/*
+ * Video driver for Marvell Armada XP SoC
+ *
+ * Initialization of LCD interface and setup of SPLASH screen image
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <video_fb.h>
+#include <linux/mbus.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+
+#define MVEBU_LCD_WIN_CONTROL(w) (MVEBU_LCD_BASE + 0xf000 + ((w) << 4))
+#define MVEBU_LCD_WIN_BASE(w) (MVEBU_LCD_BASE + 0xf004 + ((w) << 4))
+#define MVEBU_LCD_WIN_REMAP(w) (MVEBU_LCD_BASE + 0xf00c + ((w) << 4))
+
+#define MVEBU_LCD_CFG_DMA_START_ADDR_0 (MVEBU_LCD_BASE + 0x00cc)
+#define MVEBU_LCD_CFG_DMA_START_ADDR_1 (MVEBU_LCD_BASE + 0x00dc)
+
+#define MVEBU_LCD_CFG_GRA_START_ADDR0 (MVEBU_LCD_BASE + 0x00f4)
+#define MVEBU_LCD_CFG_GRA_START_ADDR1 (MVEBU_LCD_BASE + 0x00f8)
+#define MVEBU_LCD_CFG_GRA_PITCH (MVEBU_LCD_BASE + 0x00fc)
+#define MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN (MVEBU_LCD_BASE + 0x0100)
+#define MVEBU_LCD_SPU_GRA_HPXL_VLN (MVEBU_LCD_BASE + 0x0104)
+#define MVEBU_LCD_SPU_GZM_HPXL_VLN (MVEBU_LCD_BASE + 0x0108)
+#define MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN (MVEBU_LCD_BASE + 0x010c)
+#define MVEBU_LCD_SPU_HWC_HPXL_VLN (MVEBU_LCD_BASE + 0x0110)
+#define MVEBU_LCD_SPUT_V_H_TOTAL (MVEBU_LCD_BASE + 0x0114)
+#define MVEBU_LCD_SPU_V_H_ACTIVE (MVEBU_LCD_BASE + 0x0118)
+#define MVEBU_LCD_SPU_H_PORCH (MVEBU_LCD_BASE + 0x011c)
+#define MVEBU_LCD_SPU_V_PORCH (MVEBU_LCD_BASE + 0x0120)
+#define MVEBU_LCD_SPU_BLANKCOLOR (MVEBU_LCD_BASE + 0x0124)
+#define MVEBU_LCD_SPU_ALPHA_COLOR1 (MVEBU_LCD_BASE + 0x0128)
+#define MVEBU_LCD_SPU_ALPHA_COLOR2 (MVEBU_LCD_BASE + 0x012c)
+#define MVEBU_LCD_SPU_COLORKEY_Y (MVEBU_LCD_BASE + 0x0130)
+#define MVEBU_LCD_SPU_COLORKEY_U (MVEBU_LCD_BASE + 0x0134)
+#define MVEBU_LCD_SPU_COLORKEY_V (MVEBU_LCD_BASE + 0x0138)
+#define MVEBU_LCD_CFG_RDREG4F (MVEBU_LCD_BASE + 0x013c)
+#define MVEBU_LCD_SPU_SPI_RXDATA (MVEBU_LCD_BASE + 0x0140)
+#define MVEBU_LCD_SPU_ISA_RXDATA (MVEBU_LCD_BASE + 0x0144)
+#define MVEBU_LCD_SPU_DBG_ISA (MVEBU_LCD_BASE + 0x0148)
+
+#define MVEBU_LCD_SPU_HWC_RDDAT (MVEBU_LCD_BASE + 0x0158)
+#define MVEBU_LCD_SPU_GAMMA_RDDAT (MVEBU_LCD_BASE + 0x015c)
+#define MVEBU_LCD_SPU_PALETTE_RDDAT (MVEBU_LCD_BASE + 0x0160)
+#define MVEBU_LCD_SPU_IOPAD_IN (MVEBU_LCD_BASE + 0x0178)
+#define MVEBU_LCD_FRAME_COUNT (MVEBU_LCD_BASE + 0x017c)
+#define MVEBU_LCD_SPU_DMA_CTRL0 (MVEBU_LCD_BASE + 0x0190)
+#define MVEBU_LCD_SPU_DMA_CTRL1 (MVEBU_LCD_BASE + 0x0194)
+#define MVEBU_LCD_SPU_SRAM_CTRL (MVEBU_LCD_BASE + 0x0198)
+#define MVEBU_LCD_SPU_SRAM_WRDAT (MVEBU_LCD_BASE + 0x019c)
+#define MVEBU_LCD_SPU_SRAM_PARA0 (MVEBU_LCD_BASE + 0x01a0)
+#define MVEBU_LCD_SPU_SRAM_PARA1 (MVEBU_LCD_BASE + 0x01a4)
+#define MVEBU_LCD_CFG_SCLK_DIV (MVEBU_LCD_BASE + 0x01a8)
+#define MVEBU_LCD_SPU_CONTRAST (MVEBU_LCD_BASE + 0x01ac)
+#define MVEBU_LCD_SPU_SATURATION (MVEBU_LCD_BASE + 0x01b0)
+#define MVEBU_LCD_SPU_CBSH_HUE (MVEBU_LCD_BASE + 0x01b4)
+#define MVEBU_LCD_SPU_DUMB_CTRL (MVEBU_LCD_BASE + 0x01b8)
+#define MVEBU_LCD_SPU_IOPAD_CONTROL (MVEBU_LCD_BASE + 0x01bc)
+#define MVEBU_LCD_SPU_IRQ_ENA_2 (MVEBU_LCD_BASE + 0x01d8)
+#define MVEBU_LCD_SPU_IRQ_ISR_2 (MVEBU_LCD_BASE + 0x01dc)
+#define MVEBU_LCD_SPU_IRQ_ENA (MVEBU_LCD_BASE + 0x01c0)
+#define MVEBU_LCD_SPU_IRQ_ISR (MVEBU_LCD_BASE + 0x01c4)
+#define MVEBU_LCD_ADLL_CTRL (MVEBU_LCD_BASE + 0x01c8)
+#define MVEBU_LCD_CLK_DIS (MVEBU_LCD_BASE + 0x01cc)
+#define MVEBU_LCD_VGA_HVSYNC_DELAY (MVEBU_LCD_BASE + 0x01d4)
+#define MVEBU_LCD_CLK_CFG_0 (MVEBU_LCD_BASE + 0xf0a0)
+#define MVEBU_LCD_CLK_CFG_1 (MVEBU_LCD_BASE + 0xf0a4)
+#define MVEBU_LCD_LVDS_CLK_CFG (MVEBU_LCD_BASE + 0xf0ac)
+
+#define MVEBU_LVDS_PADS_REG (MVEBU_SYSTEM_REG_BASE + 0xf0)
+
+/* Setup Mbus Bridge Windows for LCD */
+static void mvebu_lcd_conf_mbus_registers(void)
+{
+ const struct mbus_dram_target_info *dram;
+ int i;
+
+ dram = mvebu_mbus_dram_info();
+
+ /* Disable windows, set size/base/remap to 0 */
+ for (i = 0; i < 6; i++) {
+ writel(0, MVEBU_LCD_WIN_CONTROL(i));
+ writel(0, MVEBU_LCD_WIN_BASE(i));
+ writel(0, MVEBU_LCD_WIN_REMAP(i));
+ }
+
+ /* Write LCD bridge window registers */
+ for (i = 0; i < dram->num_cs; i++) {
+ const struct mbus_dram_window *cs = dram->cs + i;
+ writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
+ (dram->mbus_dram_target_id << 4) | 1,
+ MVEBU_LCD_WIN_CONTROL(i));
+
+ writel(cs->base & 0xffff0000, MVEBU_LCD_WIN_BASE(i));
+ }
+}
+
+/* Initialize LCD registers */
+int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info)
+{
+ /* Local variable for easier handling */
+ int x = lcd_info->x_res;
+ int y = lcd_info->y_res;
+ u32 val;
+
+ /* Setup Mbus Bridge Windows */
+ mvebu_lcd_conf_mbus_registers();
+
+ /*
+ * Set LVDS Pads Control Register
+ * wr 0 182F0 FFE00000
+ */
+ clrbits_le32(MVEBU_LVDS_PADS_REG, 0x1f << 16);
+
+ /*
+ * Set the LCD_CFG_GRA_START_ADDR0/1 Registers
+ * This is supposed to point to the "physical" memory@memory
+ * end (currently 1GB-64MB but also may be 2GB-64MB).
+ * See also the Window 0 settings!
+ */
+ writel(lcd_info->fb_base, MVEBU_LCD_CFG_GRA_START_ADDR0);
+ writel(lcd_info->fb_base, MVEBU_LCD_CFG_GRA_START_ADDR1);
+
+ /*
+ * Set the LCD_CFG_GRA_PITCH Register
+ * Bits 31-28: Duty Cycle of Backlight. value/16=High (0x8=Mid Setting)
+ * Bits 25-16: Backlight divider from 32kHz Clock
+ * (here 16=0x10 for 1kHz)
+ * Bits 15-00: Line Length in Bytes
+ * 240*2 (for RGB1555)=480=0x1E0
+ */
+ writel(0x80100000 + 2 * x, MVEBU_LCD_CFG_GRA_PITCH);
+
+ /*
+ * Set the LCD_SPU_GRA_OVSA_HPXL_VLN Register
+ * Bits 31-16: Vertical start of graphical overlay on screen
+ * Bits 15-00: Horizontal start of graphical overlay on screen
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_GRA_OVSA_HPXL_VLN);
+
+ /*
+ * Set the LCD_SPU_GRA_HPXL_VLN Register
+ * Bits 31-16: Vertical size of graphical overlay 320=0x140
+ * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
+ * Values before zooming
+ */
+ writel((y << 16) | x, MVEBU_LCD_SPU_GRA_HPXL_VLN);
+
+ /*
+ * Set the LCD_SPU_GZM_HPXL_VLN Register
+ * Bits 31-16: Vertical size of graphical overlay 320=0x140
+ * Bits 15-00: Horizontal size of graphical overlay 240=0xF0
+ * Values after zooming
+ */
+ writel((y << 16) | x, MVEBU_LCD_SPU_GZM_HPXL_VLN);
+
+ /*
+ * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
+ * Bits 31-16: Vertical position of HW Cursor 320=0x140
+ * Bits 15-00: Horizontal position of HW Cursor 240=0xF0
+ */
+ writel((y << 16) | x, MVEBU_LCD_SPU_HWC_OVSA_HPXL_VLN);
+
+ /*
+ * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
+ * Bits 31-16: Vertical size of HW Cursor
+ * Bits 15-00: Horizontal size of HW Cursor
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_HWC_HPXL_VLN);
+
+ /*
+ * Set the LCD_SPU_HWC_OVSA_HPXL_VLN Register
+ * Bits 31-16: Screen total vertical lines:
+ * VSYNC = 1
+ * Vertical Front Porch = 2
+ * Vertical Lines = 320
+ * Vertical Back Porch = 2
+ * SUM = 325 = 0x0145
+ * Bits 15-00: Screen total horizontal pixels:
+ * HSYNC = 1
+ * Horizontal Front Porch = 44
+ * Horizontal Lines = 240
+ * Horizontal Back Porch = 2
+ * SUM = 287 = 0x011F
+ * Note: For the display the backporch is between SYNC and
+ * the start of the pixels.
+ * This is not certain for the Marvell (!?)
+ */
+ val = ((y + lcd_info->y_fp + lcd_info->y_bp + 1) << 16) |
+ (x + lcd_info->x_fp + lcd_info->x_bp + 1);
+ writel(val, MVEBU_LCD_SPUT_V_H_TOTAL);
+
+ /*
+ * Set the LCD_SPU_V_H_ACTIVE Register
+ * Bits 31-16: Screen active vertical lines 320=0x140
+ * Bits 15-00: Screen active horizontakl pixels 240=0x00F0
+ */
+ writel((y << 16) | x, MVEBU_LCD_SPU_V_H_ACTIVE);
+
+ /*
+ * Set the LCD_SPU_H_PORCH Register
+ * Bits 31-16: Screen horizontal backporch 44=0x2c
+ * Bits 15-00: Screen horizontal frontporch 2=0x02
+ * Note: The terms "front" and "back" for the Marvell seem to be
+ * exactly opposite to the display.
+ */
+ writel((lcd_info->x_fp << 16) | lcd_info->x_bp, MVEBU_LCD_SPU_H_PORCH);
+
+ /*
+ * Set the LCD_SPU_V_PORCH Register
+ * Bits 31-16: Screen vertical backporch 2=0x02
+ * Bits 15-00: Screen vertical frontporch 2=0x02
+ * Note: The terms "front" and "back" for the Marvell seem to be exactly
+ * opposite to the display.
+ */
+ writel((lcd_info->y_fp << 16) | lcd_info->y_bp, MVEBU_LCD_SPU_V_PORCH);
+
+ /*
+ * Set the LCD_SPU_BLANKCOLOR Register
+ * This should be black = 0
+ * For tests this is magenta=00FF00FF
+ */
+ writel(0x00FF00FF, MVEBU_LCD_SPU_BLANKCOLOR);
+
+ /*
+ * Registers in the range of 0x0128 to 0x012C are colors for the cursor
+ * Registers in the range of 0x0130 to 0x0138 are colors for video
+ * color keying
+ */
+
+ /*
+ * Set the LCD_SPU_RDREG4F Register
+ * Bits 31-12: Reservd
+ * Bit 11: SRAM Wait
+ * Bit 10: Smart display fast TX (must be 1)
+ * Bit 9: DMA Arbitration Video/Graphics overlay: 0=interleaved
+ * Bit 8: FIFO watermark for DMA: 0=disable
+ * Bits 07-00: Empty 8B FIFO entries to trigger DMA, default=0x80
+ */
+ writel(0x00000780, MVEBU_LCD_CFG_RDREG4F);
+
+ /*
+ * Set the LCD_SPU_DMACTRL 0 Register
+ * Bit 31: Disable overlay blending 1=disable
+ * Bit 30: Gamma correction enable, 0=disable
+ * Bit 29: Video Contrast/Saturation/Hue Adjust enable, 0=disable
+ * Bit 28: Color palette enable, 0=disable
+ * Bit 27: DMA AXI Arbiter, 1=default
+ * Bit 26: HW Cursor 1-bit mode
+ * Bit 25: HW Cursor or 1- or 2-bit mode
+ * Bit 24: HW Cursor enabled, 0=disable
+ * Bits 23-20: Graphics Memory Color Format: 0x1=RGB1555
+ * Bits 19-16: Video Memory Color Format: 0x1=RGB1555
+ * Bit 15: Memory Toggle between frame 0 and 1: 0=disable
+ * Bit 14: Graphics horizontal scaling enable: 0=disable
+ * Bit 13: Graphics test mode: 0=disable
+ * Bit 12: Graphics SWAP R and B: 0=disable
+ * Bit 11: Graphics SWAP U and V: 0=disable
+ * Bit 10: Graphics SWAP Y and U/V: 0=disable
+ * Bit 09: Graphic YUV to RGB Conversion: 0=disable
+ * Bit 08: Graphic Transfer: 1=enable
+ * Bit 07: Memory Toggle: 0=disable
+ * Bit 06: Video horizontal scaling enable: 0=disable
+ * Bit 05: Video test mode: 0=disable
+ * Bit 04: Video SWAP R and B: 0=disable
+ * Bit 03: Video SWAP U and V: 0=disable
+ * Bit 02: Video SWAP Y and U/V: 0=disable
+ * Bit 01: Video YUV to RGB Conversion: 0=disable
+ * Bit 00: Video Transfer: 0=disable
+ */
+ writel(0x88111100, MVEBU_LCD_SPU_DMA_CTRL0);
+
+ /*
+ * Set the LCD_SPU_DMA_CTRL1 Register
+ * Bit 31: Manual DMA Trigger = 0
+ * Bits 30-28: DMA Trigger Source: 0x2 VSYNC
+ * Bit 28: VSYNC_INV: 0=Rising Edge, 1=Falling Edge
+ * Bits 26-24: Color Key Mode: 0=disable
+ * Bit 23: Fill low bits: 0=fill with zeroes
+ * Bit 22: Reserved
+ * Bit 21: Gated Clock: 0=disable
+ * Bit 20: Power Save enable: 0=disable
+ * Bits 19-18: Reserved
+ * Bits 17-16: Configure Video/Graphic Path: 0x1: Graphic path alpha.
+ * Bits 15-08: Configure Alpha: 0x00.
+ * Bits 07-00: Reserved.
+ */
+ writel(0x20010000, MVEBU_LCD_SPU_DMA_CTRL1);
+
+ /*
+ * Set the LCD_SPU_SRAM_CTRL Register
+ * Reset to default = 0000C000
+ * Bits 15-14: SRAM control: init=0x3, Read=0, Write=2
+ * Bits 11-08: SRAM address ID: 0=gamma_yr, 1=gammy_ug, 2=gamma_vb,
+ * 3=palette, 15=cursor
+ */
+ writel(0x0000C000, MVEBU_LCD_SPU_SRAM_CTRL);
+
+ /*
+ * LCD_SPU_SRAM_WRDAT register: 019C
+ * LCD_SPU_SRAM_PARA0 register: 01A0
+ * LCD_SPU_SRAM_PARA1 register: 01A4 - Cursor control/Power settings
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_SRAM_PARA1);
+
+
+ /* Clock settings in the at 01A8 and in the range F0A0 see below */
+
+ /*
+ * Set LCD_SPU_CONTRAST
+ * Bits 31-16: Brightness sign ext. 8-bit value +255 to -255: default=0
+ * Bits 15-00: Contrast sign ext. 8-bit value +255 to -255: default=0
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_CONTRAST);
+
+ /*
+ * Set LCD_SPU_SATURATION
+ * Bits 31-16: Multiplier signed 4.12 fixed point value
+ * Bits 15-00: Saturation signed 4.12 fixed point value
+ */
+ writel(0x10001000, MVEBU_LCD_SPU_SATURATION);
+
+ /*
+ * Set LCD_SPU_HUE
+ * Bits 31-16: Sine signed 2.14 fixed point value
+ * Bits 15-00: Cosine signed 2.14 fixed point value
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_CBSH_HUE);
+
+ /*
+ * Set LCD_SPU_DUMB_CTRL
+ * Bits 31-28: LCD Type: 3=18 bit RGB | 6=24 bit RGB888
+ * Bits 27-12: Reserved
+ * Bit 11: LCD DMA Pipeline Enable: 1=Enable
+ * Bits 10-09: Reserved
+ * Bit 8: LCD GPIO pin (??)
+ * Bit 7: Reverse RGB
+ * Bit 6: Invert composite blank signal DE/EN (??)
+ * Bit 5: Invert composite sync signal
+ * Bit 4: Invert Pixel Valid Enable DE/EN (??)
+ * Bit 3: Invert VSYNC
+ * Bit 2: Invert HSYNC
+ * Bit 1: Invert Pixel Clock
+ * Bit 0: Enable LCD Panel: 1=Enable
+ * Question: Do we have to disable Smart and Dumb LCD
+ * and separately enable LVDS?
+ */
+ writel(0x6000080F, MVEBU_LCD_SPU_DUMB_CTRL);
+
+ /*
+ * Set LCD_SPU_IOPAD_CTRL
+ * Bits 31-20: Reserved
+ * Bits 19-18: Vertical Interpolation: 0=Disable
+ * Bits 17-16: Reserved
+ * Bit 15: Graphics Vertical Mirror enable: 0=disable
+ * Bit 14: Reserved
+ * Bit 13: Video Vertical Mirror enable: 0=disable
+ * Bit 12: Reserved
+ * Bit 11: Command Vertical Mirror enable: 0=disable
+ * Bit 10: Reserved
+ * Bits 09-08: YUV to RGB Color space conversion: 0 (Not used)
+ * Bits 07-04: AXI Bus Master: 0x4: no crossing of 4k boundary,
+ * 128 Bytes burst
+ * Bits 03-00: LCD pins: ??? 0=24-bit Dump panel ??
+ */
+ writel(0x000000C0, MVEBU_LCD_SPU_IOPAD_CONTROL);
+
+ /*
+ * Set SUP_IRQ_ENA_2: Disable all interrupts
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_IRQ_ENA_2);
+
+ /*
+ * Set SUP_IRQ_ENA: Disable all interrupts.
+ */
+ writel(0x00000000, MVEBU_LCD_SPU_IRQ_ENA);
+
+ /*
+ * Set up ADDL Control Register
+ * Bits 31-29: 0x0 = Fastest Delay Line (default)
+ * 0x3 = Slowest Delay Line (default)
+ * Bit 28: Calibration done status.
+ * Bit 27: Reserved
+ * Bit 26: Set Pixel Clock to ADDL output
+ * Bit 25: Reduce CAL Enable
+ * Bits 24-22: Manual calibration value.
+ * Bit 21: Manual calibration enable.
+ * Bit 20: Restart Auto Cal
+ * Bits 19-16: Calibration Threshold voltage, default= 0x2
+ * Bite 15-14: Reserved
+ * Bits 13-11: Divisor for ADDL Clock: 0x1=/2, 0x3=/8, 0x5=/16
+ * Bit 10: Power Down ADDL module, default = 1!
+ * Bits 09-08: Test point configuration: 0x2=Bias, 0x3=High-z
+ * Bit 07: Reset ADDL
+ * Bit 06: Invert ADLL Clock
+ * Bits 05-00: Delay taps, 0x3F=Half Cycle, 0x00=No delay
+ * Note: ADLL is used for a VGA interface with DAC - not used here
+ */
+ writel(0x00000000, MVEBU_LCD_ADLL_CTRL);
+
+ /*
+ * Set the LCD_CLK_DIS Register:
+ * Bits 3 and 4 must be 1
+ */
+ writel(0x00000018, MVEBU_LCD_CLK_DIS);
+
+ /*
+ * Set the LCD_VGA_HSYNC/VSYNC Delay Register:
+ * Bits 03-00: Sets the delay for the HSYNC and VSYNC signals
+ */
+ writel(0x00000000, MVEBU_LCD_VGA_HVSYNC_DELAY);
+
+ /*
+ * Clock registers
+ * See page 475 in the functional spec.
+ */
+
+ /* Step 1 and 2: Disable the PLL */
+
+ /*
+ * Disable PLL, see "LCD Clock Configuration 1 Register" below
+ */
+ writel(0x8FF40007, MVEBU_LCD_CLK_CFG_1);
+
+ /*
+ * Powerdown, see "LCD Clock Configuration 0 Register" below
+ */
+ writel(0x94000174, MVEBU_LCD_CLK_CFG_0);
+
+ /*
+ * Set the LCD_CFG_SCLK_DIV Register
+ * This is set fix to 0x40000001 for the LVDS output:
+ * Bits 31-30: SCLCK Source: 0=AXIBus, 1=AHBus, 2=PLLDivider0
+ * Bits 15-01: Clock Divider: Bypass for LVDS=0x0001
+ * See page 475 in section 28.5.
+ */
+ writel(0x80000001, MVEBU_LCD_CFG_SCLK_DIV);
+
+ /*
+ * Set the LCD Clock Configuration 0 Register:
+ * Bit 31: Powerdown: 0=Power up
+ * Bits 30-29: Reserved
+ * Bits 28-26: PLL_KDIV: This encodes K
+ * K=16 => 0x5
+ * Bits 25-17: PLL_MDIV: This is M-1:
+ * M=1 => 0x0
+ * Bits 16-13: VCO band: 0x1 for 700-920MHz
+ * Bits 12-04: PLL_NDIV: This is N-1 and corresponds to R1_CTRL!
+ * N=28=0x1C => 0x1B
+ * Bits 03-00: R1_CTRL (for N=28 => 0x4)
+ */
+ writel(0x940021B4, MVEBU_LCD_CLK_CFG_0);
+
+ /*
+ * Set the LCD Clock Configuration 1 Register:
+ * Bits 31-19: Reserved
+ * Bit 18: Select PLL: Core PLL, 1=Dedicated PPL
+ * Bit 17: Clock Output Enable: 0=disable, 1=enable
+ * Bit 16: Select RefClk: 0=RefClk (25MHz), 1=External
+ * Bit 15: Half-Div, Device Clock by DIV+0.5*Half-Dev
+ * Bits 14-13: Reserved
+ * Bits 12-00: PLL Full Divider [Note: Assumed to be the Post-Divider
+ * M' for LVDS=7!]
+ */
+ writel(0x8FF40007, MVEBU_LCD_CLK_CFG_1);
+
+ /*
+ * Set the LVDS Clock Configuration Register:
+ * Bit 31: Clock Gating for the input clock to the LVDS
+ * Bit 30: LVDS Serializer enable: 1=Enabled
+ * Bits 29-11: Reserved
+ * Bit 11-08: LVDS Clock delay: 0x02 (default): by 2 pixel clock/7
+ * Bits 07-02: Reserved
+ * Bit 01: 24bbp Option: 0=Option_1,1=Option2
+ * Bit 00: 1=24bbp Panel: 0=18bpp Panel
+ * Note: Bits 0 and must be verified with the help of the
+ * Interface/display
+ */
+ writel(0xC0000201, MVEBU_LCD_LVDS_CLK_CFG);
+
+ /*
+ * Power up PLL (Clock Config 0)
+ */
+ writel(0x140021B4, MVEBU_LCD_CLK_CFG_0);
+
+ /* wait 10 ms */
+ mdelay(10);
+
+ /*
+ * Enable PLL (Clock Config 1)
+ */
+ writel(0x8FF60007, MVEBU_LCD_CLK_CFG_1);
+
+ return 0;
+}
+
+int __weak board_video_init(void)
+{
+ return -1;
+}
+
+void *video_hw_init(void)
+{
+ static GraphicDevice mvebufb;
+ GraphicDevice *pGD = &mvebufb;
+ u32 val;
+
+ /*
+ * The board code needs to call mvebu_lcd_register_init()
+ * in its board_video_init() implementation, with the board
+ * specific parameters for its LCD.
+ */
+ if (board_video_init() || !readl(MVEBU_LCD_CFG_GRA_START_ADDR0))
+ return NULL;
+
+ /* Provide the necessary values for the U-Boot video IF */
+ val = readl(MVEBU_LCD_SPU_V_H_ACTIVE);
+ pGD->winSizeY = val >> 16;
+ pGD->winSizeX = val & 0x0000ffff;
+ pGD->gdfBytesPP = 2;
+ pGD->gdfIndex = GDF_15BIT_555RGB;
+ pGD->frameAdrs = readl(MVEBU_LCD_CFG_GRA_START_ADDR0);
+
+ debug("LCD: buffer at 0x%08x resolution %dx%d\n", pGD->frameAdrs,
+ pGD->winSizeX, pGD->winSizeY);
+
+ return pGD;
+}
--
2.6.5
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH 2/2] arm: mvebu: Add support for the Armada XP theadorable board
2016-01-20 7:13 [U-Boot] [PATCH 1/2] video: Add support for Armada XP LCD controller Stefan Roese
@ 2016-01-20 7:13 ` Stefan Roese
2016-01-27 6:55 ` Stefan Roese
2016-01-23 22:18 ` [U-Boot] [PATCH 1/2] video: Add support for Armada XP LCD controller Anatolij Gustschin
1 sibling, 1 reply; 4+ messages in thread
From: Stefan Roese @ 2016-01-20 7:13 UTC (permalink / raw)
To: u-boot
This patch adds support for the Armada XP (MV78260) based theadorable
board. Its equipped with onboard DDR3, UART, ethernet, I2C, SPI NOR,
LCD and SATA (SSD) interfaces / devices.
Two defconfigs are added:
theadorable_defconfig:
The production U-Boot version with a stripped down drivers and feature
list. This removes networking, USB and PCI support.
theadorable_debug_defconfig:
The debugging / testing U-Boot version with full support for all drivers.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/armada-xp-theadorable.dts | 143 +++++++++++++++++++++++++++
arch/arm/mach-mvebu/Kconfig | 6 ++
board/theadorable/MAINTAINERS | 7 ++
board/theadorable/Makefile | 7 ++
board/theadorable/kwbimage.cfg | 12 +++
board/theadorable/theadorable.c | 171 +++++++++++++++++++++++++++++++++
configs/theadorable_debug_defconfig | 28 ++++++
configs/theadorable_defconfig | 26 +++++
include/configs/theadorable.h | 170 ++++++++++++++++++++++++++++++++
10 files changed, 572 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/armada-xp-theadorable.dts
create mode 100644 board/theadorable/MAINTAINERS
create mode 100644 board/theadorable/Makefile
create mode 100644 board/theadorable/kwbimage.cfg
create mode 100644 board/theadorable/theadorable.c
create mode 100644 configs/theadorable_debug_defconfig
create mode 100644 configs/theadorable_defconfig
create mode 100644 include/configs/theadorable.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e4f8aae..9b933ac 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -52,7 +52,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
armada-388-gp.dtb \
armada-xp-gp.dtb \
armada-xp-maxbcm.dtb \
- armada-xp-synology-ds414.dtb
+ armada-xp-synology-ds414.dtb \
+ armada-xp-theadorable.dtb
dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ph1-ld4-ref.dtb \
diff --git a/arch/arm/dts/armada-xp-theadorable.dts b/arch/arm/dts/armada-xp-theadorable.dts
new file mode 100644
index 0000000..cf1be2a
--- /dev/null
+++ b/arch/arm/dts/armada-xp-theadorable.dts
@@ -0,0 +1,143 @@
+/*
+ * Device Tree file for Marvell Armada XP theadorable board
+ *
+ * Copyright (C) 2013-2014 Marvell
+ *
+ * Lior Amsalem <alior@marvell.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Note: this Device Tree assumes that the bootloader has remapped the
+ * internal registers to 0xf1000000 (instead of the default
+ * 0xd0000000). The 0xf1000000 is the default used by the recent,
+ * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
+ * boards were delivered with an older version of the bootloader that
+ * left internal registers mapped at 0xd0000000. If you are in this
+ * situation, you should either update your bootloader (preferred
+ * solution) or the below Device Tree should be adjusted.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "armada-xp-mv78260.dtsi"
+
+/ {
+ model = "Marvell Armada XP theadorable";
+ compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ spi0 = &spi0;
+ ethernet0 = ð0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x00000000 0x00000000 0x80000000>;
+ };
+
+ soc {
+ ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
+ MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
+ MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
+
+ internal-regs {
+ serial at 12000 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+ };
+
+ serial at 12100 {
+ status = "okay";
+ };
+
+ serial at 12200 {
+ status = "okay";
+ };
+
+ serial at 12300 {
+ status = "okay";
+ };
+
+ sata at a0000 {
+ nr-ports = <2>;
+ status = "okay";
+ };
+
+ mdio {
+ phy0: ethernet-phy at 0 {
+ reg = <0>;
+ };
+ };
+
+ ethernet at 70000 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "sgmii";
+ };
+
+ usb at 50000 {
+ status = "okay";
+ };
+
+ usb at 51000 {
+ status = "okay";
+ };
+
+ spi0: spi at 10600 {
+ status = "okay";
+ u-boot,dm-pre-reloc;
+
+ spi-flash at 0 {
+ u-boot,dm-pre-reloc;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a13", "jedec,spi-nor";
+ reg = <0>; /* Chip select 0 */
+ spi-max-frequency = <27777777>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index b962846..96a3313 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -46,6 +46,10 @@ config TARGET_MAXBCM
bool "Support maxbcm"
select MV78460
+config TARGET_THEADORABLE
+ bool "Support theadorable Armada XP"
+ select MV78260
+
endchoice
config SYS_BOARD
@@ -54,6 +58,7 @@ config SYS_BOARD
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
+ default "theadorable" if TARGET_THEADORABLE
config SYS_CONFIG_NAME
default "clearfog" if TARGET_CLEARFOG
@@ -61,6 +66,7 @@ config SYS_CONFIG_NAME
default "db-mv784mp-gp" if TARGET_DB_MV784MP_GP
default "ds414" if TARGET_DS414
default "maxbcm" if TARGET_MAXBCM
+ default "theadorable" if TARGET_THEADORABLE
config SYS_VENDOR
default "Marvell" if TARGET_DB_MV784MP_GP
diff --git a/board/theadorable/MAINTAINERS b/board/theadorable/MAINTAINERS
new file mode 100644
index 0000000..5ae6b64
--- /dev/null
+++ b/board/theadorable/MAINTAINERS
@@ -0,0 +1,7 @@
+THEADORABLE BOARD
+M: Stefan Roese <sr@denx.de>
+S: Maintained
+F: board/theadorable/
+F: include/configs/theadorable.h
+F: configs/theadorable_debug_defconfig
+F: configs/theadorable_defconfig
diff --git a/board/theadorable/Makefile b/board/theadorable/Makefile
new file mode 100644
index 0000000..9d5b39e
--- /dev/null
+++ b/board/theadorable/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := theadorable.o
diff --git a/board/theadorable/kwbimage.cfg b/board/theadorable/kwbimage.cfg
new file mode 100644
index 0000000..4f3b7b2
--- /dev/null
+++ b/board/theadorable/kwbimage.cfg
@@ -0,0 +1,12 @@
+#
+# Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+#
+
+# Armada XP uses version 1 image format
+VERSION 1
+
+# Boot Media configurations
+BOOT_FROM spi
+
+# Binary Header (bin_hdr) with DDR3 training code
+BINARY spl/u-boot-spl-dtb.bin 0000005b 00000068
diff --git a/board/theadorable/theadorable.c b/board/theadorable/theadorable.c
new file mode 100644
index 0000000..0e23265
--- /dev/null
+++ b/board/theadorable/theadorable.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/soc.h>
+#ifdef CONFIG_NET
+#include <netdev.h>
+#endif
+
+#include "../drivers/ddr/marvell/axp/ddr3_hw_training.h"
+#include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define THEADORABLE_GPP_OUT_ENA_LOW 0x00336780
+#define THEADORABLE_GPP_OUT_ENA_MID 0x00003cf0
+#define THEADORABLE_GPP_OUT_ENA_HIGH (~(0x0))
+
+#define THEADORABLE_GPP_OUT_VAL_LOW 0x2c0c983f
+#define THEADORABLE_GPP_OUT_VAL_MID 0x0007000c
+#define THEADORABLE_GPP_OUT_VAL_HIGH 0x00000000
+
+/* DDR3 static configuration */
+static MV_DRAM_MC_INIT ddr3_theadorable[MV_MAX_DDR3_STATIC_SIZE] = {
+ {0x00001400, 0x7301ca28}, /* DDR SDRAM Configuration Register */
+ {0x00001404, 0x30000800}, /* Dunit Control Low Register */
+ {0x00001408, 0x44149887}, /* DDR SDRAM Timing (Low) Register */
+ {0x0000140C, 0x38d93fc7}, /* DDR SDRAM Timing (High) Register */
+ {0x00001410, 0x1b100001}, /* DDR SDRAM Address Control Register */
+ {0x00001424, 0x0000f3ff}, /* Dunit Control High Register */
+ {0x00001428, 0x000f8830}, /* ODT Timing (Low) Register */
+ {0x0000142C, 0x014c50f4}, /* DDR3 Timing Register */
+ {0x0000147C, 0x0000c671}, /* ODT Timing (High) Register */
+
+ {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */
+ {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */
+ {0x000014A0, 0x00000001}, /* DRAM FIFO Control Register */
+ {0x000014A8, 0x00000101}, /* AXI Control Register */
+
+ /*
+ * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the
+ * training sequence
+ */
+ {0x000200e8, 0x3fff0e01},
+ {0x00020184, 0x3fffffe0}, /* Close fast path Window to - 2G */
+
+ {0x0001504, 0x7fffffe1}, /* CS0 Size */
+ {0x000150C, 0x00000000}, /* CS1 Size */
+ {0x0001514, 0x00000000}, /* CS2 Size */
+ {0x000151C, 0x00000000}, /* CS3 Size */
+
+ {0x00020220, 0x00000007}, /* Reserved */
+
+ {0x00001538, 0x00000009}, /* Read Data Sample Delays Register */
+ {0x0000153C, 0x00000009}, /* Read Data Ready Delay Register */
+
+ {0x000015D0, 0x00000650}, /* MR0 */
+ {0x000015D4, 0x00000044}, /* MR1 */
+ {0x000015D8, 0x00000010}, /* MR2 */
+ {0x000015DC, 0x00000000}, /* MR3 */
+ {0x000015E0, 0x00000001},
+ {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */
+ {0x000015EC, 0xf800a225}, /* DDR PHY */
+
+ /* Recommended Settings from Marvell for 4 x 16 bit devices: */
+ {0x000014C0, 0x192424c9}, /* DRAM addr and Ctrl Driving Strenght*/
+ {0x000014C4, 0x0aaa24c9}, /* DRAM Data and DQS Driving Strenght */
+
+ {0x0, 0x0}
+};
+
+static MV_DRAM_MODES board_ddr_modes[MV_DDR3_MODES_NUMBER] = {
+ {"theadorable_1333-667", 0x3, 0x5, 0x0, A0, ddr3_theadorable, NULL},
+};
+
+extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[];
+
+/*
+ * Lane0 - PCIE0.0 X1 (to WIFI Module)
+ * Lane5 - SATA0
+ * Lane6 - SATA1
+ * Lane7 - SGMII0 (to Ethernet Phy)
+ * Lane8-11 - PCIE2.0 X4 (to PEX Switch)
+ * all other lanes are disabled
+ */
+MV_BIN_SERDES_CFG theadorable_serdes_cfg[] = {
+ { MV_PEX_ROOT_COMPLEX, 0x22200001, 0x00001111,
+ { PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4,
+ PEX_BUS_DISABLED },
+ 0x0060, serdes_change_m_phy
+ },
+};
+
+MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
+{
+ /* Only one mode supported for this board */
+ return &board_ddr_modes[0];
+}
+
+MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode)
+{
+ return &theadorable_serdes_cfg[0];
+}
+
+int board_early_init_f(void)
+{
+ /* Configure MPP */
+ writel(0x00000000, MVEBU_MPP_BASE + 0x00);
+ writel(0x03300000, MVEBU_MPP_BASE + 0x04);
+ writel(0x00000033, MVEBU_MPP_BASE + 0x08);
+ writel(0x00000000, MVEBU_MPP_BASE + 0x0c);
+ writel(0x11110000, MVEBU_MPP_BASE + 0x10);
+ writel(0x00221100, MVEBU_MPP_BASE + 0x14);
+ writel(0x00000000, MVEBU_MPP_BASE + 0x18);
+ writel(0x00000000, MVEBU_MPP_BASE + 0x1c);
+ writel(0x00000000, MVEBU_MPP_BASE + 0x20);
+
+ /* Configure GPIO */
+ writel(THEADORABLE_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
+ writel(THEADORABLE_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
+ writel(THEADORABLE_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
+ writel(THEADORABLE_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
+ writel(THEADORABLE_GPP_OUT_VAL_HIGH, MVEBU_GPIO2_BASE + 0x00);
+ writel(THEADORABLE_GPP_OUT_ENA_HIGH, MVEBU_GPIO2_BASE + 0x04);
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: theadorable\n");
+
+ return 0;
+}
+
+#ifdef CONFIG_NET
+int board_eth_init(bd_t *bis)
+{
+ cpu_eth_init(bis); /* Built in controller(s) come first */
+ return pci_eth_init(bis);
+}
+#endif
+
+int board_video_init(void)
+{
+ struct mvebu_lcd_info lcd_info;
+
+ /* Reserved memory area via CONFIG_SYS_MEM_TOP_HIDE */
+ lcd_info.fb_base = gd->ram_size;
+ lcd_info.x_res = 240;
+ lcd_info.x_fp = 1;
+ lcd_info.x_bp = 45;
+ lcd_info.y_res = 320;
+ lcd_info.y_fp = 1;
+ lcd_info.y_bp = 3;
+
+ return mvebu_lcd_register_init(&lcd_info);
+}
diff --git a/configs/theadorable_debug_defconfig b/configs/theadorable_debug_defconfig
new file mode 100644
index 0000000..fbed23c
--- /dev/null
+++ b/configs/theadorable_debug_defconfig
@@ -0,0 +1,28 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_THEADORABLE=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_VIDEO_MVEBU=y
diff --git a/configs/theadorable_defconfig b/configs/theadorable_defconfig
new file mode 100644
index 0000000..cce4669
--- /dev/null
+++ b/configs/theadorable_defconfig
@@ -0,0 +1,26 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_THEADORABLE=y
+CONFIG_DEFAULT_DEVICE_TREE="armada-xp-theadorable"
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_SPL=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_SF=y
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0xd0012000
+CONFIG_DEBUG_UART_CLOCK=250000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550=y
+CONFIG_VIDEO_MVEBU=y
+CONFIG_REGEX=y
+CONFIG_LIB_RAND=y
diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h
new file mode 100644
index 0000000..cd9d6b6
--- /dev/null
+++ b/include/configs/theadorable.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_THEADORABLE_H
+#define _CONFIG_THEADORABLE_H
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+/*
+ * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
+ * for DDR ECC byte filling in the SPL before loading the main
+ * U-Boot into it.
+ */
+#define CONFIG_SYS_TEXT_BASE 0x00800000
+#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_ENV
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_FS_GENERIC
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_SATA
+#define CONFIG_CMD_TIME
+
+/*
+ * The debugging version enables USB support via defconfig.
+ * This version should also enable all other non-production
+ * interfaces / features.
+ */
+#ifdef CONFIG_USB
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_TFTPPUT
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MVTWSI
+#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
+#define CONFIG_SYS_I2C_SLAVE 0x0
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* USB/EHCI configuration */
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
+
+#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
+
+/* SPI NOR flash default params, used by sf commands */
+#define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
+
+/* Environment in SPI NOR flash */
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
+#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
+#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_PHY_MARVELL /* there is a marvell phy */
+#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
+
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PREBOOT
+#define CONFIG_FIT
+
+#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* Keep device tree and initrd in lower memory so the kernel can access them */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x10000000\0" \
+ "initrd_high=0x10000000\0"
+
+/* SATA support */
+#define CONFIG_SYS_SATA_MAX_DEVICE 1
+#define CONFIG_SATA_MV
+#define CONFIG_LIBATA
+#define CONFIG_LBA48
+#define CONFIG_EFI_PARTITION
+#define CONFIG_DOS_PARTITION
+
+/* Additional FS support/configuration */
+#define CONFIG_SUPPORT_VFAT
+
+/* PCIe support */
+#ifdef CONFIG_CMD_PCI
+#ifndef CONFIG_SPL_BUILD
+#define CONFIG_PCI
+#define CONFIG_PCI_MVEBU
+#define CONFIG_PCI_PNP
+#endif
+#endif
+
+/* Enable LCD and reserve 512KB from top of memory*/
+#define CONFIG_SYS_MEM_TOP_HIDE 0x80000
+
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_CMD_BMP
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+/*
+ * Memory layout while starting into the bin_hdr via the
+ * BootROM:
+ *
+ * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
+ * 0x4000.4030 bin_hdr start address
+ * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
+ * 0x4007.fffc BootROM stack top
+ *
+ * The address space between 0x4007.fffc and 0x400f.fff is not locked in
+ * L2 cache thus cannot be used.
+ */
+
+/* SPL */
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x40004030
+#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
+
+#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
+#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
+#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+
+/* SPL related SPI defines */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SPL_SPI_BUS 0
+#define CONFIG_SPL_SPI_CS 0
+#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
+#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
+
+/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
+#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
+
+#endif /* _CONFIG_THEADORABLE_H */
--
2.6.5
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH 1/2] video: Add support for Armada XP LCD controller
2016-01-20 7:13 [U-Boot] [PATCH 1/2] video: Add support for Armada XP LCD controller Stefan Roese
2016-01-20 7:13 ` [U-Boot] [PATCH 2/2] arm: mvebu: Add support for the Armada XP theadorable board Stefan Roese
@ 2016-01-23 22:18 ` Anatolij Gustschin
1 sibling, 0 replies; 4+ messages in thread
From: Anatolij Gustschin @ 2016-01-23 22:18 UTC (permalink / raw)
To: u-boot
Hi Stefan,
On Wed, 20 Jan 2016 08:13:28 +0100
Stefan Roese <sr@denx.de> wrote:
> This patch adds basic support for the LCD controller of the Marvell
> Armada XP SoC.
>
> An AXP based custom board port will be added later, to use this
> driver to display a splash screen via the bmp command later.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Anatolij Gustschin <agust@denx.de>
> Cc: Luka Perkov <luka.perkov@sartura.hr>
> ---
> arch/arm/mach-mvebu/include/mach/cpu.h | 13 +
> arch/arm/mach-mvebu/include/mach/soc.h | 1 +
> drivers/video/Kconfig | 7 +
> drivers/video/Makefile | 1 +
> drivers/video/mvebu_lcd.c | 532 +++++++++++++++++++++++++++++++++
> 5 files changed, 554 insertions(+)
> create mode 100644 drivers/video/mvebu_lcd.c
applied to u-boot-video/master, thanks!
--
Anatolij
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH 2/2] arm: mvebu: Add support for the Armada XP theadorable board
2016-01-20 7:13 ` [U-Boot] [PATCH 2/2] arm: mvebu: Add support for the Armada XP theadorable board Stefan Roese
@ 2016-01-27 6:55 ` Stefan Roese
0 siblings, 0 replies; 4+ messages in thread
From: Stefan Roese @ 2016-01-27 6:55 UTC (permalink / raw)
To: u-boot
On 20.01.2016 08:13, Stefan Roese wrote:
> This patch adds support for the Armada XP (MV78260) based theadorable
> board. Its equipped with onboard DDR3, UART, ethernet, I2C, SPI NOR,
> LCD and SATA (SSD) interfaces / devices.
>
> Two defconfigs are added:
>
> theadorable_defconfig:
> The production U-Boot version with a stripped down drivers and feature
> list. This removes networking, USB and PCI support.
>
> theadorable_debug_defconfig:
> The debugging / testing U-Boot version with full support for all drivers.
>
> Signed-off-by: Stefan Roese <sr@denx.de>
> Cc: Luka Perkov <luka.perkov@sartura.hr>
Applied to u-boot-marvell/master.
Thanks,
Stefan
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2016-01-27 6:55 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-01-20 7:13 [U-Boot] [PATCH 1/2] video: Add support for Armada XP LCD controller Stefan Roese
2016-01-20 7:13 ` [U-Boot] [PATCH 2/2] arm: mvebu: Add support for the Armada XP theadorable board Stefan Roese
2016-01-27 6:55 ` Stefan Roese
2016-01-23 22:18 ` [U-Boot] [PATCH 1/2] video: Add support for Armada XP LCD controller Anatolij Gustschin
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