* [PATCH v6 0/7] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
0 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This patch series adds generic cpufreq-dt driver support for
Exynos542x/5800 (using the new CPU clock type which allows it).
It has been tested on Exynos5422 based ODROID-XU3 Lite board.
Depends on:
- next-20151211 branch of linux-next kernel tree
- "[PATCH] ARM: dts: Make CPU configuration more readable for
exynos542x/5800" patch (https://lkml.org/lkml/2015/12/11/107)
Changes since v5:
- rebased over next-20151211 branch (something is broken in
newer branches, namely next-2015121[45])
- rebased on top of "ARM: dts: Make CPU configuration more
readable for exynos542x/5800" patch
- renamed cpu0_opp_table to cluster_a15_opp_table and
cpu1_opp_table to cluster_a7_opp_table
- added Reviewed-by from Krzysztof
Changes since v4:
- renamed oppXX at hz to opp at hz
- put Odroid changes in exynos5422-odroidxu3-common.dtsi
- override CPU OPP properties for Exynos5422/5800 instead of
duplicating them
- merged "ARM: dts: Exynos5422: fix OPP tables" patch with
"ARM: dts: Exynos5420: add CPU OPP properties" one
- added missing Thomas' SoB line to "ARM: dts: Exynos5420:
add CPU OPP properties" patch
- updated authorship of "ARM: Exynos: use generic cpufreq
driver for Exynos5420" and "ARM: Exynos: use generic
cpufreq driver for Exynos5422/5800" patches
- updated Javier's and Mike's e-mail adresses
- removed non-working e-mail address of Sachin Kamat
Changes since v3:
- switched to using cpufreq-dt driver
- updated patch descriptions to cover Exynos5422 support
- added Acked-by from Sylwester to clock driver patches
Changes since v2:
- ported over next-20151124 branch
- integrated missing CLK_RECALC_NEW_RATES flags fix to patch #3
(from Anand Moon)
- added regulator supply properties for ODROID-XU3 Lite and
ODROID-XU4 in patch #2
- ported CPU OPPs to operating-points-v2 (from Ben Gamari)
- added "ARM: dts: Exynos5422: fix OPP tables" patch (from Ben
Gamari)
- added "cpufreq: arm-big-little: accept operating-points-v2
nodes" patch (from Ben Gamari)
- renamed OPP nodes as opp@<opp-hz>
Changes since v1:
- added CPU cluster regulator supply properties to
exynos5420-arndale-octa.dts, exynos5420-peach-pit.dts,
exynos5420-smdk5420.dts and exynos5800-peach-pi.dts
Changes over Thomas' original v12 code:
- split Exynos5420 and Exynos5800 support
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
- disabled cpufreq if big.LITTLE switcher support is enabled
- enhanced arm_big_little[_dt] driver with CPU cluster regulator
support
- fixed CPU clock configuration data for Exynos5800
- fixed CPU operating points setup for Exynos5800
- added CPU cluster regulator supplies for ODROID-XU3 board
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
Bartlomiej Zolnierkiewicz (5):
ARM: dts: Exynos542x/5800: add cluster regulator supply properties
ARM: Exynos: use generic cpufreq driver for Exynos5420
clk: samsung: exynos5422/5800: fix cpu clock configuration data
ARM: dts: Exynos5800: fix CPU OPP
ARM: Exynos: use generic cpufreq driver for Exynos5422/5800
Thomas Abraham (2):
clk: samsung: exynos5420: add cpu clock configuration data and
instantiate cpu clock
ARM: dts: Exynos542x/5800: add CPU OPP properties
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 8 ++
arch/arm/boot/dts/exynos5420-cpus.dtsi | 10 ++
arch/arm/boot/dts/exynos5420-peach-pit.dts | 8 ++
arch/arm/boot/dts/exynos5420-smdk5420.dts | 8 ++
arch/arm/boot/dts/exynos5420.dtsi | 110 +++++++++++++++++++++
arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 ++
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 ++
arch/arm/boot/dts/exynos5800-peach-pi.dts | 8 ++
arch/arm/boot/dts/exynos5800.dtsi | 108 ++++++++++++++++++++
arch/arm/mach-exynos/exynos.c | 4 +
drivers/clk/samsung/clk-exynos5420.c | 88 ++++++++++++++++-
include/dt-bindings/clock/exynos5420.h | 2 +
12 files changed, 370 insertions(+), 2 deletions(-)
--
1.9.1
^ permalink raw reply [flat|nested] 25+ messages in thread* [PATCH v6 1/7] ARM: dts: Exynos542x/5800: add cluster regulator supply properties
2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
-1 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: Thomas Abraham, Sylwester Nawrocki, Mike Turquette, Kukjin Kim,
Kukjin Kim, Viresh Kumar, Krzysztof Kozlowski, Ben Gamari
Cc: Tomasz Figa, Lukasz Majewski, Heiko Stuebner, Chanwoo Choi,
Kevin Hilman, Javier Martinez Canillas, Tobias Jakobi,
Anand Moon, linux-samsung-soc, linux-pm, linux-arm-kernel,
linux-kernel, b.zolnierkie, Doug Anderson, Andreas Faerber
Add cluster regulator supply properties as a preparation to
adding generic cpufreq-dt driver support for Exynos542x and
Exynos5800 based boards.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 8 ++++++++
arch/arm/boot/dts/exynos5420-peach-pit.dts | 8 ++++++++
arch/arm/boot/dts/exynos5420-smdk5420.dts | 8 ++++++++
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 ++++++++
arch/arm/boot/dts/exynos5800-peach-pi.dts | 8 ++++++++
5 files changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 365eec6..762f6ff 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -53,6 +53,14 @@
};
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&usbdrd_dwc3_1 {
dr_mode = "host";
};
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 61a0c0d..f7b31e1 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -144,6 +144,14 @@
vdd-supply = <&ldo9_reg>;
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&dp {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 1935a0b..0785fed 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -90,6 +90,14 @@
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&dp {
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 9134217..1bd507b 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -67,6 +67,14 @@
<19200000>;
};
+&cpu0 {
+ cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck2_reg>;
+};
+
&hdmi {
status = "okay";
hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 279322b..4731dbb 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -144,6 +144,14 @@
vdd-supply = <&ldo9_reg>;
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&dp {
status = "okay";
pinctrl-names = "default";
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v6 1/7] ARM: dts: Exynos542x/5800: add cluster regulator supply properties
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
0 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: linux-arm-kernel
Add cluster regulator supply properties as a preparation to
adding generic cpufreq-dt driver support for Exynos542x and
Exynos5800 based boards.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 8 ++++++++
arch/arm/boot/dts/exynos5420-peach-pit.dts | 8 ++++++++
arch/arm/boot/dts/exynos5420-smdk5420.dts | 8 ++++++++
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 8 ++++++++
arch/arm/boot/dts/exynos5800-peach-pi.dts | 8 ++++++++
5 files changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 365eec6..762f6ff 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -53,6 +53,14 @@
};
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&usbdrd_dwc3_1 {
dr_mode = "host";
};
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 61a0c0d..f7b31e1 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -144,6 +144,14 @@
vdd-supply = <&ldo9_reg>;
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&dp {
status = "okay";
pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 1935a0b..0785fed 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -90,6 +90,14 @@
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&dp {
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 9134217..1bd507b 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -67,6 +67,14 @@
<19200000>;
};
+&cpu0 {
+ cpu-supply = <&buck6_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck2_reg>;
+};
+
&hdmi {
status = "okay";
hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 279322b..4731dbb 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -144,6 +144,14 @@
vdd-supply = <&ldo9_reg>;
};
+&cpu0 {
+ cpu-supply = <&buck2_reg>;
+};
+
+&cpu4 {
+ cpu-supply = <&buck6_reg>;
+};
+
&dp {
status = "okay";
pinctrl-names = "default";
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v6 2/7] clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock
2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
-1 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: Thomas Abraham, Sylwester Nawrocki, Mike Turquette, Kukjin Kim,
Kukjin Kim, Viresh Kumar, Krzysztof Kozlowski, Ben Gamari
Cc: Tomasz Figa, Lukasz Majewski, Heiko Stuebner, Chanwoo Choi,
Kevin Hilman, Javier Martinez Canillas, Tobias Jakobi,
Anand Moon, linux-samsung-soc, linux-pm, linux-arm-kernel,
linux-kernel, b.zolnierkie
From: Thomas Abraham <thomas.ab@samsung.com>
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@baylibre.com>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 58 ++++++++++++++++++++++++++++++++--
include/dt-bindings/clock/exynos5420.h | 2 ++
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 389af3c..2a92546 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -18,6 +18,7 @@
#include <linux/syscore_ops.h>
#include "clk.h"
+#include "clk-cpu.h"
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
@@ -616,9 +617,11 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
- MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+ MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
- MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
+ MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
@@ -1246,6 +1249,50 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
KPLL_CON0, NULL),
};
+#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
+ ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
+ ((cpud) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
+ { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 900000, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 800000, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 700000, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 600000, E5420_EGL_DIV0(3, 4, 4, 2), },
+ { 500000, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 400000, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 300000, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 200000, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 0 },
+};
+
+#define E5420_KFC_DIV(kpll, pclk, aclk) \
+ ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
+ { 1300000, E5420_KFC_DIV(3, 5, 2), },
+ { 1200000, E5420_KFC_DIV(3, 5, 2), },
+ { 1100000, E5420_KFC_DIV(3, 5, 2), },
+ { 1000000, E5420_KFC_DIV(3, 5, 2), },
+ { 900000, E5420_KFC_DIV(3, 5, 2), },
+ { 800000, E5420_KFC_DIV(3, 5, 2), },
+ { 700000, E5420_KFC_DIV(3, 4, 2), },
+ { 600000, E5420_KFC_DIV(3, 4, 2), },
+ { 500000, E5420_KFC_DIV(3, 4, 2), },
+ { 400000, E5420_KFC_DIV(3, 3, 2), },
+ { 300000, E5420_KFC_DIV(3, 3, 2), },
+ { 200000, E5420_KFC_DIV(3, 3, 2), },
+ { 0 },
+};
+
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
{ },
@@ -1310,6 +1357,13 @@ static void __init exynos5x_clk_init(struct device_node *np,
ARRAY_SIZE(exynos5800_gate_clks));
}
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
+ mout_kfc_p[0], mout_kfc_p[1], 0x28200,
+ exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
+
exynos5420_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 99da0d1..dde9664 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -25,6 +25,8 @@
#define CLK_FOUT_MPLL 10
#define CLK_FOUT_BPLL 11
#define CLK_FOUT_KPLL 12
+#define CLK_ARM_CLK 13
+#define CLK_KFC_CLK 14
/* gate for special clocks (sclk) */
#define CLK_SCLK_UART0 128
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v6 2/7] clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
0 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Abraham <thomas.ab@samsung.com>
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@baylibre.com>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 58 ++++++++++++++++++++++++++++++++--
include/dt-bindings/clock/exynos5420.h | 2 ++
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 389af3c..2a92546 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -18,6 +18,7 @@
#include <linux/syscore_ops.h>
#include "clk.h"
+#include "clk-cpu.h"
#define APLL_LOCK 0x0
#define APLL_CON0 0x100
@@ -616,9 +617,11 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
- MUX(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1),
+ MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
- MUX(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1),
+ MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
+ CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
@@ -1246,6 +1249,50 @@ static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
KPLL_CON0, NULL),
};
+#define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
+ ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
+ ((cpud) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
+ { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 900000, E5420_EGL_DIV0(3, 6, 6, 2), },
+ { 800000, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 700000, E5420_EGL_DIV0(3, 5, 5, 2), },
+ { 600000, E5420_EGL_DIV0(3, 4, 4, 2), },
+ { 500000, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 400000, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 300000, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 200000, E5420_EGL_DIV0(3, 3, 3, 2), },
+ { 0 },
+};
+
+#define E5420_KFC_DIV(kpll, pclk, aclk) \
+ ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
+
+static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
+ { 1300000, E5420_KFC_DIV(3, 5, 2), },
+ { 1200000, E5420_KFC_DIV(3, 5, 2), },
+ { 1100000, E5420_KFC_DIV(3, 5, 2), },
+ { 1000000, E5420_KFC_DIV(3, 5, 2), },
+ { 900000, E5420_KFC_DIV(3, 5, 2), },
+ { 800000, E5420_KFC_DIV(3, 5, 2), },
+ { 700000, E5420_KFC_DIV(3, 4, 2), },
+ { 600000, E5420_KFC_DIV(3, 4, 2), },
+ { 500000, E5420_KFC_DIV(3, 4, 2), },
+ { 400000, E5420_KFC_DIV(3, 3, 2), },
+ { 300000, E5420_KFC_DIV(3, 3, 2), },
+ { 200000, E5420_KFC_DIV(3, 3, 2), },
+ { 0 },
+};
+
static const struct of_device_id ext_clk_match[] __initconst = {
{ .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
{ },
@@ -1310,6 +1357,13 @@ static void __init exynos5x_clk_init(struct device_node *np,
ARRAY_SIZE(exynos5800_gate_clks));
}
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
+ mout_kfc_p[0], mout_kfc_p[1], 0x28200,
+ exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
+
exynos5420_clk_sleep_init();
samsung_clk_of_add_provider(np, ctx);
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 99da0d1..dde9664 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -25,6 +25,8 @@
#define CLK_FOUT_MPLL 10
#define CLK_FOUT_BPLL 11
#define CLK_FOUT_KPLL 12
+#define CLK_ARM_CLK 13
+#define CLK_KFC_CLK 14
/* gate for special clocks (sclk) */
#define CLK_SCLK_UART0 128
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v6 3/7] ARM: dts: Exynos542x/5800: add CPU OPP properties
2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
-1 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: Thomas Abraham, Sylwester Nawrocki, Mike Turquette, Kukjin Kim,
Kukjin Kim, Viresh Kumar, Krzysztof Kozlowski, Ben Gamari
Cc: Tomasz Figa, Lukasz Majewski, Heiko Stuebner, Chanwoo Choi,
Kevin Hilman, Javier Martinez Canillas, Tobias Jakobi,
Anand Moon, linux-samsung-soc, linux-pm, linux-arm-kernel,
linux-kernel, b.zolnierkie, Doug Anderson, Andreas Faerber
From: Thomas Abraham <thomas.ab@samsung.com>
For Exynos542x/5800 platforms, add CPU operating points
for migrating from Exynos specific cpufreq driver to using
generic cpufreq driver.
Changes by Bartlomiej:
- split Exynos5420 support from the original patch
- merged Exynos5422 fixes from Ben
Changes by Ben Gamari:
- Port to operating-points-v2
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Andreas Faerber <afaerber@suse.de>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Ben Gamari <ben@smart-cactus.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
arch/arm/boot/dts/exynos5420-cpus.dtsi | 10 +++
arch/arm/boot/dts/exynos5420.dtsi | 110 +++++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 +++
3 files changed, 130 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 7aaf031..261d251 100644
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -29,8 +29,10 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
+ clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu1: cpu@1 {
@@ -39,6 +41,7 @@
reg = <0x1>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu2: cpu@2 {
@@ -47,6 +50,7 @@
reg = <0x2>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu3: cpu@3 {
@@ -55,14 +59,17 @@
reg = <0x3>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu5: cpu@101 {
@@ -71,6 +78,7 @@
reg = <0x101>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu6: cpu@102 {
@@ -79,6 +87,7 @@
reg = <0x102>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu7: cpu@103 {
@@ -87,6 +96,7 @@
reg = <0x103>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
};
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 29b7cba..2458bdf 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -50,6 +50,116 @@
usbdrdphy1 = &usbdrd_phy1;
};
+ cluster_a15_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp@1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1250000>;
+ clock-latency-ns = <140000>;
+ };
+ opp@1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <1212500>;
+ clock-latency-ns = <140000>;
+ };
+ opp@1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <1175000>;
+ clock-latency-ns = <140000>;
+ };
+ opp@1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <1137500>;
+ clock-latency-ns = <140000>;
+ };
+ opp@1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <1112500>;
+ clock-latency-ns = <140000>;
+ };
+ opp@1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <1062500>;
+ clock-latency-ns = <140000>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1037500>;
+ clock-latency-ns = <140000>;
+ };
+ opp@1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <1012500>;
+ clock-latency-ns = <140000>;
+ };
+ opp@1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = < 987500>;
+ clock-latency-ns = <140000>;
+ };
+ opp@900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = < 962500>;
+ clock-latency-ns = <140000>;
+ };
+ opp@800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = < 937500>;
+ clock-latency-ns = <140000>;
+ };
+ opp@700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = < 912500>;
+ clock-latency-ns = <140000>;
+ };
+ };
+
+ cluster_a7_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp@1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <1275000>;
+ clock-latency-ns = <140000>;
+ };
+ opp@1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1212500>;
+ clock-latency-ns = <140000>;
+ };
+ opp@1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <1162500>;
+ clock-latency-ns = <140000>;
+ };
+ opp@1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1112500>;
+ clock-latency-ns = <140000>;
+ };
+ opp@900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <1062500>;
+ clock-latency-ns = <140000>;
+ };
+ opp@800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1025000>;
+ clock-latency-ns = <140000>;
+ };
+ opp@700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <975000>;
+ clock-latency-ns = <140000>;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <937500>;
+ clock-latency-ns = <140000>;
+ };
+ };
+
/*
* The 'cpus' node is not present here but instead it is provided
* by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index 33028ac..9b46b9f 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -28,8 +28,10 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu1: cpu@101 {
@@ -38,6 +40,7 @@
reg = <0x101>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu2: cpu@102 {
@@ -46,6 +49,7 @@
reg = <0x102>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu3: cpu@103 {
@@ -54,14 +58,17 @@
reg = <0x103>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu4: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
+ clocks = <&clock CLK_ARM_CLK>;
reg = <0x0>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu5: cpu@1 {
@@ -70,6 +77,7 @@
reg = <0x1>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu6: cpu@2 {
@@ -78,6 +86,7 @@
reg = <0x2>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu7: cpu@3 {
@@ -86,6 +95,7 @@
reg = <0x3>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v6 3/7] ARM: dts: Exynos542x/5800: add CPU OPP properties
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
0 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: linux-arm-kernel
From: Thomas Abraham <thomas.ab@samsung.com>
For Exynos542x/5800 platforms, add CPU operating points
for migrating from Exynos specific cpufreq driver to using
generic cpufreq driver.
Changes by Bartlomiej:
- split Exynos5420 support from the original patch
- merged Exynos5422 fixes from Ben
Changes by Ben Gamari:
- Port to operating-points-v2
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Andreas Faerber <afaerber@suse.de>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Ben Gamari <ben@smart-cactus.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
arch/arm/boot/dts/exynos5420-cpus.dtsi | 10 +++
arch/arm/boot/dts/exynos5420.dtsi | 110 +++++++++++++++++++++++++++++++++
arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 +++
3 files changed, 130 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 7aaf031..261d251 100644
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -29,8 +29,10 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
+ clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu1: cpu at 1 {
@@ -39,6 +41,7 @@
reg = <0x1>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu2: cpu at 2 {
@@ -47,6 +50,7 @@
reg = <0x2>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu3: cpu at 3 {
@@ -55,14 +59,17 @@
reg = <0x3>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu4: cpu at 100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu5: cpu at 101 {
@@ -71,6 +78,7 @@
reg = <0x101>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu6: cpu at 102 {
@@ -79,6 +87,7 @@
reg = <0x102>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu7: cpu at 103 {
@@ -87,6 +96,7 @@
reg = <0x103>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
};
};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 29b7cba..2458bdf 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -50,6 +50,116 @@
usbdrdphy1 = &usbdrd_phy1;
};
+ cluster_a15_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp at 1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1250000>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 1700000000 {
+ opp-hz = /bits/ 64 <1700000000>;
+ opp-microvolt = <1212500>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 1600000000 {
+ opp-hz = /bits/ 64 <1600000000>;
+ opp-microvolt = <1175000>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <1137500>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <1112500>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <1062500>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1037500>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <1012500>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = < 987500>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = < 962500>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = < 937500>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = < 912500>;
+ clock-latency-ns = <140000>;
+ };
+ };
+
+ cluster_a7_opp_table: opp_table1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp at 1300000000 {
+ opp-hz = /bits/ 64 <1300000000>;
+ opp-microvolt = <1275000>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <1212500>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-microvolt = <1162500>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1112500>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ opp-microvolt = <1062500>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <1025000>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <975000>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <937500>;
+ clock-latency-ns = <140000>;
+ };
+ };
+
/*
* The 'cpus' node is not present here but instead it is provided
* by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index 33028ac..9b46b9f 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -28,8 +28,10 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu1: cpu at 101 {
@@ -38,6 +40,7 @@
reg = <0x101>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu2: cpu at 102 {
@@ -46,6 +49,7 @@
reg = <0x102>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu3: cpu at 103 {
@@ -54,14 +58,17 @@
reg = <0x103>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
+ operating-points-v2 = <&cluster_a7_opp_table>;
};
cpu4: cpu at 0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
+ clocks = <&clock CLK_ARM_CLK>;
reg = <0x0>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu5: cpu at 1 {
@@ -70,6 +77,7 @@
reg = <0x1>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu6: cpu at 2 {
@@ -78,6 +86,7 @@
reg = <0x2>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
cpu7: cpu at 3 {
@@ -86,6 +95,7 @@
reg = <0x3>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
+ operating-points-v2 = <&cluster_a15_opp_table>;
};
};
};
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* Re: [PATCH v6 3/7] ARM: dts: Exynos542x/5800: add CPU OPP properties
2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
@ 2015-12-16 0:43 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 25+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-16 0:43 UTC (permalink / raw)
To: Bartlomiej Zolnierkiewicz, Thomas Abraham, Sylwester Nawrocki,
Mike Turquette, Kukjin Kim, Kukjin Kim, Viresh Kumar, Ben Gamari
Cc: Tomasz Figa, Lukasz Majewski, Heiko Stuebner, Chanwoo Choi,
Kevin Hilman, Javier Martinez Canillas, Tobias Jakobi,
Anand Moon, linux-samsung-soc, linux-pm, linux-arm-kernel,
linux-kernel, Doug Anderson, Andreas Faerber
On 16.12.2015 02:33, Bartlomiej Zolnierkiewicz wrote:
> From: Thomas Abraham <thomas.ab@samsung.com>
>
> For Exynos542x/5800 platforms, add CPU operating points
> for migrating from Exynos specific cpufreq driver to using
> generic cpufreq driver.
>
> Changes by Bartlomiej:
> - split Exynos5420 support from the original patch
> - merged Exynos5422 fixes from Ben
>
> Changes by Ben Gamari:
> - Port to operating-points-v2
>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Javier Martinez Canillas <javier@osg.samsung.com>
> Cc: Andreas Faerber <afaerber@suse.de>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> Signed-off-by: Ben Gamari <ben@smart-cactus.org>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
> arch/arm/boot/dts/exynos5420-cpus.dtsi | 10 +++
> arch/arm/boot/dts/exynos5420.dtsi | 110 +++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 +++
> 3 files changed, 130 insertions(+)
>
Thanks for rebasing on "exynos5422-cpus.dtsi" patch, I appreciate this.
Looks good:
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v6 3/7] ARM: dts: Exynos542x/5800: add CPU OPP properties
@ 2015-12-16 0:43 ` Krzysztof Kozlowski
0 siblings, 0 replies; 25+ messages in thread
From: Krzysztof Kozlowski @ 2015-12-16 0:43 UTC (permalink / raw)
To: linux-arm-kernel
On 16.12.2015 02:33, Bartlomiej Zolnierkiewicz wrote:
> From: Thomas Abraham <thomas.ab@samsung.com>
>
> For Exynos542x/5800 platforms, add CPU operating points
> for migrating from Exynos specific cpufreq driver to using
> generic cpufreq driver.
>
> Changes by Bartlomiej:
> - split Exynos5420 support from the original patch
> - merged Exynos5422 fixes from Ben
>
> Changes by Ben Gamari:
> - Port to operating-points-v2
>
> Cc: Kukjin Kim <kgene.kim@samsung.com>
> Cc: Doug Anderson <dianders@chromium.org>
> Cc: Javier Martinez Canillas <javier@osg.samsung.com>
> Cc: Andreas Faerber <afaerber@suse.de>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> Signed-off-by: Ben Gamari <ben@smart-cactus.org>
> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
> arch/arm/boot/dts/exynos5420-cpus.dtsi | 10 +++
> arch/arm/boot/dts/exynos5420.dtsi | 110 +++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/exynos5422-cpus.dtsi | 10 +++
> 3 files changed, 130 insertions(+)
>
Thanks for rebasing on "exynos5422-cpus.dtsi" patch, I appreciate this.
Looks good:
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v6 4/7] ARM: Exynos: use generic cpufreq driver for Exynos5420
2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
-1 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: Thomas Abraham, Sylwester Nawrocki, Mike Turquette, Kukjin Kim,
Kukjin Kim, Viresh Kumar, Krzysztof Kozlowski, Ben Gamari
Cc: Tomasz Figa, Lukasz Majewski, Heiko Stuebner, Chanwoo Choi,
Kevin Hilman, Javier Martinez Canillas, Tobias Jakobi,
Anand Moon, linux-samsung-soc, linux-pm, linux-arm-kernel,
linux-kernel, b.zolnierkie
The new CPU clock type allows the use of cpufreq-dt driver
for Exynos5420.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
arch/arm/mach-exynos/exynos.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 1c47aee..7a89c9d 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
+#ifndef CONFIG_BL_SWITCHER
+ { .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+#endif
{ /* sentinel */ }
};
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v6 4/7] ARM: Exynos: use generic cpufreq driver for Exynos5420
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
0 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: linux-arm-kernel
The new CPU clock type allows the use of cpufreq-dt driver
for Exynos5420.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
arch/arm/mach-exynos/exynos.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 1c47aee..7a89c9d 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -230,6 +230,9 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
{ .compatible = "samsung,exynos4212", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos4412", .data = "cpufreq-dt" },
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
+#ifndef CONFIG_BL_SWITCHER
+ { .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+#endif
{ /* sentinel */ }
};
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v6 5/7] clk: samsung: exynos5422/5800: fix cpu clock configuration data
2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
(?)
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
-1 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: Thomas Abraham, Sylwester Nawrocki, Mike Turquette, Kukjin Kim,
Kukjin Kim, Viresh Kumar, Krzysztof Kozlowski, Ben Gamari
Cc: Tomasz Figa, Lukasz Majewski, Heiko Stuebner, Chanwoo Choi,
Kevin Hilman, Javier Martinez Canillas, Tobias Jakobi,
Anand Moon, linux-samsung-soc, linux-pm, linux-arm-kernel,
linux-kernel, b.zolnierkie
Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).
Based on Hardkernel's kernel for ODROID-XU3 board.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@baylibre.com>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 36 +++++++++++++++++++++++++++++++++---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 2a92546..837329d 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
{ 0 },
};
+static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
+ { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 900000, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 800000, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 700000, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 600000, E5420_EGL_DIV0(3, 7, 4, 2), },
+ { 500000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 400000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 300000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 200000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 0 },
+};
+
#define E5420_KFC_DIV(kpll, pclk, aclk) \
((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
+ { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
{ 1300000, E5420_KFC_DIV(3, 5, 2), },
{ 1200000, E5420_KFC_DIV(3, 5, 2), },
{ 1100000, E5420_KFC_DIV(3, 5, 2), },
@@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node *np,
ARRAY_SIZE(exynos5800_gate_clks));
}
- exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
- mout_cpu_p[0], mout_cpu_p[1], 0x200,
- exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ if (soc == EXYNOS5420) {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ } else {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
+ }
exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
mout_kfc_p[0], mout_kfc_p[1], 0x28200,
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v6 5/7] clk: samsung: exynos5422/5800: fix cpu clock configuration data
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
0 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: linux-arm-kernel
Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).
Based on Hardkernel's kernel for ODROID-XU3 board.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@baylibre.com>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 36 +++++++++++++++++++++++++++++++++---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 2a92546..837329d 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
{ 0 },
};
+static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
+ { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 900000, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 800000, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 700000, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 600000, E5420_EGL_DIV0(3, 7, 4, 2), },
+ { 500000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 400000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 300000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 200000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 0 },
+};
+
#define E5420_KFC_DIV(kpll, pclk, aclk) \
((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
+ { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
{ 1300000, E5420_KFC_DIV(3, 5, 2), },
{ 1200000, E5420_KFC_DIV(3, 5, 2), },
{ 1100000, E5420_KFC_DIV(3, 5, 2), },
@@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node *np,
ARRAY_SIZE(exynos5800_gate_clks));
}
- exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
- mout_cpu_p[0], mout_cpu_p[1], 0x200,
- exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ if (soc == EXYNOS5420) {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ } else {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
+ }
exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
mout_kfc_p[0], mout_kfc_p[1], 0x28200,
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v6 5/7] clk: samsung: exynos5422/5800: fix cpu clock configuration data
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
0 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: Thomas Abraham, Sylwester Nawrocki, Mike Turquette, Kukjin Kim,
Kukjin Kim, Viresh Kumar, Krzysztof Kozlowski, Ben Gamari
Cc: Lukasz Majewski, Kevin Hilman, Heiko Stuebner,
Javier Martinez Canillas, Anand Moon, linux-pm, Tomasz Figa,
linux-kernel, Chanwoo Choi, b.zolnierkie, Tobias Jakobi,
linux-arm-kernel, linux-samsung-soc
Fix cpu clock configuration data for Exynos5422/5800 SoCs
(they use higher PCLK_DBG divider values than Exynos5420 and
support additional frequencies).
Based on Hardkernel's kernel for ODROID-XU3 board.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@baylibre.com>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 36 +++++++++++++++++++++++++++++++++---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 2a92546..837329d 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1274,10 +1274,34 @@ static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
{ 0 },
};
+static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
+ { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
+ { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
+ { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
+ { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 900000, E5420_EGL_DIV0(3, 7, 6, 2), },
+ { 800000, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 700000, E5420_EGL_DIV0(3, 7, 5, 2), },
+ { 600000, E5420_EGL_DIV0(3, 7, 4, 2), },
+ { 500000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 400000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 300000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 200000, E5420_EGL_DIV0(3, 7, 3, 2), },
+ { 0 },
+};
+
#define E5420_KFC_DIV(kpll, pclk, aclk) \
((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
+ { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
{ 1300000, E5420_KFC_DIV(3, 5, 2), },
{ 1200000, E5420_KFC_DIV(3, 5, 2), },
{ 1100000, E5420_KFC_DIV(3, 5, 2), },
@@ -1357,9 +1381,15 @@ static void __init exynos5x_clk_init(struct device_node *np,
ARRAY_SIZE(exynos5800_gate_clks));
}
- exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
- mout_cpu_p[0], mout_cpu_p[1], 0x200,
- exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ if (soc == EXYNOS5420) {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
+ } else {
+ exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
+ mout_cpu_p[0], mout_cpu_p[1], 0x200,
+ exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
+ }
exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
mout_kfc_p[0], mout_kfc_p[1], 0x28200,
exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v6 6/7] ARM: dts: Exynos5800: fix CPU OPP
2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
-1 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: Thomas Abraham, Sylwester Nawrocki, Mike Turquette, Kukjin Kim,
Kukjin Kim, Viresh Kumar, Krzysztof Kozlowski, Ben Gamari
Cc: Tomasz Figa, Lukasz Majewski, Heiko Stuebner, Chanwoo Choi,
Kevin Hilman, Javier Martinez Canillas, Tobias Jakobi,
Anand Moon, linux-samsung-soc, linux-pm, linux-arm-kernel,
linux-kernel, b.zolnierkie, Doug Anderson, Andreas Faerber
Fix CPU operating points for Exynos5800 (it use different
voltages than Exynos5420 and supports additional frequencies).
However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
1400MHz OPP (for A7 cores) for now as they are not available
on all boards.
Based on Hardkernel's kernel for ODROID-XU3 board.
Changes by Ben Gamari:
- Port to operating-points-v2
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Ben Gamari <ben@smart-cactus.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
arch/arm/boot/dts/exynos5800.dtsi | 108 ++++++++++++++++++++++++++++++++++++++
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index c0bb356..8213016 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -23,6 +23,114 @@
compatible = "samsung,exynos5800-clock";
};
+&cluster_a15_opp_table {
+ opp@1700000000 {
+ opp-microvolt = <1250000>;
+ };
+ opp@1600000000 {
+ opp-microvolt = <1250000>;
+ };
+ opp@1500000000 {
+ opp-microvolt = <1100000>;
+ };
+ opp@1400000000 {
+ opp-microvolt = <1100000>;
+ };
+ opp@1300000000 {
+ opp-microvolt = <1100000>;
+ };
+ opp@1200000000 {
+ opp-microvolt = <1000000>;
+ };
+ opp@1100000000 {
+ opp-microvolt = <1000000>;
+ };
+ opp@1000000000 {
+ opp-microvolt = <1000000>;
+ };
+ opp@900000000 {
+ opp-microvolt = <1000000>;
+ };
+ opp@800000000 {
+ opp-microvolt = <900000>;
+ };
+ opp@700000000 {
+ opp-microvolt = <900000>;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+ opp@500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+ opp@300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+};
+
+&cluster_a7_opp_table {
+ opp@1300000000 {
+ opp-microvolt = <1250000>;
+ };
+ opp@1200000000 {
+ opp-microvolt = <1250000>;
+ };
+ opp@1100000000 {
+ opp-microvolt = <1250000>;
+ };
+ opp@1000000000 {
+ opp-microvolt = <1100000>;
+ };
+ opp@900000000 {
+ opp-microvolt = <1100000>;
+ };
+ opp@800000000 {
+ opp-microvolt = <1100000>;
+ };
+ opp@700000000 {
+ opp-microvolt = <1000000>;
+ };
+ opp@600000000 {
+ opp-microvolt = <1000000>;
+ };
+ opp@500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <140000>;
+ };
+ opp@400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <140000>;
+ };
+ opp@300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+ opp@200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+};
+
&mfc {
compatible = "samsung,mfc-v8";
};
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v6 6/7] ARM: dts: Exynos5800: fix CPU OPP
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
0 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: linux-arm-kernel
Fix CPU operating points for Exynos5800 (it use different
voltages than Exynos5420 and supports additional frequencies).
However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
1400MHz OPP (for A7 cores) for now as they are not available
on all boards.
Based on Hardkernel's kernel for ODROID-XU3 board.
Changes by Ben Gamari:
- Port to operating-points-v2
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Ben Gamari <ben@smart-cactus.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
arch/arm/boot/dts/exynos5800.dtsi | 108 ++++++++++++++++++++++++++++++++++++++
1 file changed, 108 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index c0bb356..8213016 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -23,6 +23,114 @@
compatible = "samsung,exynos5800-clock";
};
+&cluster_a15_opp_table {
+ opp at 1700000000 {
+ opp-microvolt = <1250000>;
+ };
+ opp at 1600000000 {
+ opp-microvolt = <1250000>;
+ };
+ opp at 1500000000 {
+ opp-microvolt = <1100000>;
+ };
+ opp at 1400000000 {
+ opp-microvolt = <1100000>;
+ };
+ opp at 1300000000 {
+ opp-microvolt = <1100000>;
+ };
+ opp at 1200000000 {
+ opp-microvolt = <1000000>;
+ };
+ opp at 1100000000 {
+ opp-microvolt = <1000000>;
+ };
+ opp at 1000000000 {
+ opp-microvolt = <1000000>;
+ };
+ opp at 900000000 {
+ opp-microvolt = <1000000>;
+ };
+ opp at 800000000 {
+ opp-microvolt = <900000>;
+ };
+ opp at 700000000 {
+ opp-microvolt = <900000>;
+ };
+ opp at 600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+};
+
+&cluster_a7_opp_table {
+ opp at 1300000000 {
+ opp-microvolt = <1250000>;
+ };
+ opp at 1200000000 {
+ opp-microvolt = <1250000>;
+ };
+ opp at 1100000000 {
+ opp-microvolt = <1250000>;
+ };
+ opp at 1000000000 {
+ opp-microvolt = <1100000>;
+ };
+ opp at 900000000 {
+ opp-microvolt = <1100000>;
+ };
+ opp at 800000000 {
+ opp-microvolt = <1100000>;
+ };
+ opp at 700000000 {
+ opp-microvolt = <1000000>;
+ };
+ opp at 600000000 {
+ opp-microvolt = <1000000>;
+ };
+ opp at 500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+ opp at 200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ opp-microvolt = <900000>;
+ clock-latency-ns = <140000>;
+ };
+};
+
&mfc {
compatible = "samsung,mfc-v8";
};
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v6 7/7] ARM: Exynos: use generic cpufreq driver for Exynos5422/5800
2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
-1 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: Thomas Abraham, Sylwester Nawrocki, Mike Turquette, Kukjin Kim,
Kukjin Kim, Viresh Kumar, Krzysztof Kozlowski, Ben Gamari
Cc: Tomasz Figa, Lukasz Majewski, Heiko Stuebner, Chanwoo Choi,
Kevin Hilman, Javier Martinez Canillas, Tobias Jakobi,
Anand Moon, linux-samsung-soc, linux-pm, linux-arm-kernel,
linux-kernel, b.zolnierkie
The new CPU clock type allows the use of generic cpufreq-dt driver
for Exynos5422/5800.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
arch/arm/mach-exynos/exynos.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 7a89c9d..cec8aeb 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -232,6 +232,7 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
#ifndef CONFIG_BL_SWITCHER
{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+ { .compatible = "samsung,exynos5800", .data = "cpufreq-dt" },
#endif
{ /* sentinel */ }
};
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread* [PATCH v6 7/7] ARM: Exynos: use generic cpufreq driver for Exynos5422/5800
@ 2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
0 siblings, 0 replies; 25+ messages in thread
From: Bartlomiej Zolnierkiewicz @ 2015-12-15 17:33 UTC (permalink / raw)
To: linux-arm-kernel
The new CPU clock type allows the use of generic cpufreq-dt driver
for Exynos5422/5800.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
arch/arm/mach-exynos/exynos.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index 7a89c9d..cec8aeb 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -232,6 +232,7 @@ static const struct of_device_id exynos_cpufreq_matches[] = {
{ .compatible = "samsung,exynos5250", .data = "cpufreq-dt" },
#ifndef CONFIG_BL_SWITCHER
{ .compatible = "samsung,exynos5420", .data = "cpufreq-dt" },
+ { .compatible = "samsung,exynos5800", .data = "cpufreq-dt" },
#endif
{ /* sentinel */ }
};
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH v6 0/7] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms
2015-12-15 17:33 ` Bartlomiej Zolnierkiewicz
@ 2015-12-16 2:14 ` Viresh Kumar
-1 siblings, 0 replies; 25+ messages in thread
From: Viresh Kumar @ 2015-12-16 2:14 UTC (permalink / raw)
To: Bartlomiej Zolnierkiewicz
Cc: Thomas Abraham, Sylwester Nawrocki, Mike Turquette, Kukjin Kim,
Kukjin Kim, Krzysztof Kozlowski, Ben Gamari, Tomasz Figa,
Lukasz Majewski, Heiko Stuebner, Chanwoo Choi, Kevin Hilman,
Javier Martinez Canillas, Tobias Jakobi, Anand Moon,
linux-samsung-soc, linux-pm, linux-arm-kernel, linux-kernel
On 15-12-15, 18:33, Bartlomiej Zolnierkiewicz wrote:
> Hi,
>
> This patch series adds generic cpufreq-dt driver support for
> Exynos542x/5800 (using the new CPU clock type which allows it).
>
> It has been tested on Exynos5422 based ODROID-XU3 Lite board.
>
> Depends on:
> - next-20151211 branch of linux-next kernel tree
> - "[PATCH] ARM: dts: Make CPU configuration more readable for
> exynos542x/5800" patch (https://lkml.org/lkml/2015/12/11/107)
>
> Changes since v5:
> - rebased over next-20151211 branch (something is broken in
> newer branches, namely next-2015121[45])
> - rebased on top of "ARM: dts: Make CPU configuration more
> readable for exynos542x/5800" patch
> - renamed cpu0_opp_table to cluster_a15_opp_table and
> cpu1_opp_table to cluster_a7_opp_table
> - added Reviewed-by from Krzysztof
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v6 0/7] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms
@ 2015-12-16 2:14 ` Viresh Kumar
0 siblings, 0 replies; 25+ messages in thread
From: Viresh Kumar @ 2015-12-16 2:14 UTC (permalink / raw)
To: linux-arm-kernel
On 15-12-15, 18:33, Bartlomiej Zolnierkiewicz wrote:
> Hi,
>
> This patch series adds generic cpufreq-dt driver support for
> Exynos542x/5800 (using the new CPU clock type which allows it).
>
> It has been tested on Exynos5422 based ODROID-XU3 Lite board.
>
> Depends on:
> - next-20151211 branch of linux-next kernel tree
> - "[PATCH] ARM: dts: Make CPU configuration more readable for
> exynos542x/5800" patch (https://lkml.org/lkml/2015/12/11/107)
>
> Changes since v5:
> - rebased over next-20151211 branch (something is broken in
> newer branches, namely next-2015121[45])
> - rebased on top of "ARM: dts: Make CPU configuration more
> readable for exynos542x/5800" patch
> - renamed cpu0_opp_table to cluster_a15_opp_table and
> cpu1_opp_table to cluster_a7_opp_table
> - added Reviewed-by from Krzysztof
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v6 0/7] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms
2015-12-16 2:14 ` Viresh Kumar
@ 2016-01-28 10:48 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 25+ messages in thread
From: Krzysztof Kozlowski @ 2016-01-28 10:48 UTC (permalink / raw)
To: Viresh Kumar, Bartlomiej Zolnierkiewicz
Cc: Thomas Abraham, Sylwester Nawrocki, Mike Turquette, Kukjin Kim,
Kukjin Kim, Ben Gamari, Tomasz Figa, Lukasz Majewski,
Heiko Stuebner, Chanwoo Choi, Kevin Hilman,
Javier Martinez Canillas, Tobias Jakobi, Anand Moon,
linux-samsung-soc, linux-pm, linux-arm-kernel, linux-kernel
On 16.12.2015 11:14, Viresh Kumar wrote:
> On 15-12-15, 18:33, Bartlomiej Zolnierkiewicz wrote:
>> Hi,
>>
>> This patch series adds generic cpufreq-dt driver support for
>> Exynos542x/5800 (using the new CPU clock type which allows it).
>>
>> It has been tested on Exynos5422 based ODROID-XU3 Lite board.
>>
>> Depends on:
>> - next-20151211 branch of linux-next kernel tree
>> - "[PATCH] ARM: dts: Make CPU configuration more readable for
>> exynos542x/5800" patch (https://lkml.org/lkml/2015/12/11/107)
>>
>> Changes since v5:
>> - rebased over next-20151211 branch (something is broken in
>> newer branches, namely next-2015121[45])
>> - rebased on top of "ARM: dts: Make CPU configuration more
>> readable for exynos542x/5800" patch
>> - renamed cpu0_opp_table to cluster_a15_opp_table and
>> cpu1_opp_table to cluster_a7_opp_table
>> - added Reviewed-by from Krzysztof
>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Applied entire patchset to my krzk repo.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v6 0/7] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms
@ 2016-01-28 10:48 ` Krzysztof Kozlowski
0 siblings, 0 replies; 25+ messages in thread
From: Krzysztof Kozlowski @ 2016-01-28 10:48 UTC (permalink / raw)
To: linux-arm-kernel
On 16.12.2015 11:14, Viresh Kumar wrote:
> On 15-12-15, 18:33, Bartlomiej Zolnierkiewicz wrote:
>> Hi,
>>
>> This patch series adds generic cpufreq-dt driver support for
>> Exynos542x/5800 (using the new CPU clock type which allows it).
>>
>> It has been tested on Exynos5422 based ODROID-XU3 Lite board.
>>
>> Depends on:
>> - next-20151211 branch of linux-next kernel tree
>> - "[PATCH] ARM: dts: Make CPU configuration more readable for
>> exynos542x/5800" patch (https://lkml.org/lkml/2015/12/11/107)
>>
>> Changes since v5:
>> - rebased over next-20151211 branch (something is broken in
>> newer branches, namely next-2015121[45])
>> - rebased on top of "ARM: dts: Make CPU configuration more
>> readable for exynos542x/5800" patch
>> - renamed cpu0_opp_table to cluster_a15_opp_table and
>> cpu1_opp_table to cluster_a7_opp_table
>> - added Reviewed-by from Krzysztof
>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Applied entire patchset to my krzk repo.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v6 0/7] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms
2016-01-28 10:48 ` Krzysztof Kozlowski
@ 2016-01-28 10:50 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 25+ messages in thread
From: Krzysztof Kozlowski @ 2016-01-28 10:50 UTC (permalink / raw)
To: Viresh Kumar, Bartlomiej Zolnierkiewicz
Cc: Thomas Abraham, Sylwester Nawrocki, Mike Turquette, Kukjin Kim,
Kukjin Kim, Ben Gamari, Tomasz Figa, Lukasz Majewski,
Heiko Stuebner, Chanwoo Choi, Kevin Hilman,
Javier Martinez Canillas, Tobias Jakobi, Anand Moon,
linux-samsung-soc, linux-pm, linux-arm-kernel, linux-kernel
On 28.01.2016 19:48, Krzysztof Kozlowski wrote:
> On 16.12.2015 11:14, Viresh Kumar wrote:
>> On 15-12-15, 18:33, Bartlomiej Zolnierkiewicz wrote:
>>> Hi,
>>>
>>> This patch series adds generic cpufreq-dt driver support for
>>> Exynos542x/5800 (using the new CPU clock type which allows it).
>>>
>>> It has been tested on Exynos5422 based ODROID-XU3 Lite board.
>>>
>>> Depends on:
>>> - next-20151211 branch of linux-next kernel tree
>>> - "[PATCH] ARM: dts: Make CPU configuration more readable for
>>> exynos542x/5800" patch (https://lkml.org/lkml/2015/12/11/107)
>>>
>>> Changes since v5:
>>> - rebased over next-20151211 branch (something is broken in
>>> newer branches, namely next-2015121[45])
>>> - rebased on top of "ARM: dts: Make CPU configuration more
>>> readable for exynos542x/5800" patch
>>> - renamed cpu0_opp_table to cluster_a15_opp_table and
>>> cpu1_opp_table to cluster_a7_opp_table
>>> - added Reviewed-by from Krzysztof
>>
>> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
>
> Applied entire patchset to my krzk repo.
Wrong. Applied only Exynos part, which is DTS + mach-exynos. The clock
stuff was already in v4.5-rc1.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH v6 0/7] cpufreq: add generic cpufreq driver support for Exynos542x/5800 platforms
@ 2016-01-28 10:50 ` Krzysztof Kozlowski
0 siblings, 0 replies; 25+ messages in thread
From: Krzysztof Kozlowski @ 2016-01-28 10:50 UTC (permalink / raw)
To: linux-arm-kernel
On 28.01.2016 19:48, Krzysztof Kozlowski wrote:
> On 16.12.2015 11:14, Viresh Kumar wrote:
>> On 15-12-15, 18:33, Bartlomiej Zolnierkiewicz wrote:
>>> Hi,
>>>
>>> This patch series adds generic cpufreq-dt driver support for
>>> Exynos542x/5800 (using the new CPU clock type which allows it).
>>>
>>> It has been tested on Exynos5422 based ODROID-XU3 Lite board.
>>>
>>> Depends on:
>>> - next-20151211 branch of linux-next kernel tree
>>> - "[PATCH] ARM: dts: Make CPU configuration more readable for
>>> exynos542x/5800" patch (https://lkml.org/lkml/2015/12/11/107)
>>>
>>> Changes since v5:
>>> - rebased over next-20151211 branch (something is broken in
>>> newer branches, namely next-2015121[45])
>>> - rebased on top of "ARM: dts: Make CPU configuration more
>>> readable for exynos542x/5800" patch
>>> - renamed cpu0_opp_table to cluster_a15_opp_table and
>>> cpu1_opp_table to cluster_a7_opp_table
>>> - added Reviewed-by from Krzysztof
>>
>> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
>
> Applied entire patchset to my krzk repo.
Wrong. Applied only Exynos part, which is DTS + mach-exynos. The clock
stuff was already in v4.5-rc1.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 25+ messages in thread