* [PATCH v2 0/7] irqchip: introduce the Alpine MSIX driver
@ 2016-02-10 13:22 ` Antoine Tenart
0 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:22 UTC (permalink / raw)
To: tglx, jason, marc.zyngier, tsahee
Cc: Antoine Tenart, rshitrit, thomas.petazzoni, linux-arm-kernel,
linux-kernel
Hi all,
This series introduce the Alpine MSIX driver, and enables it in both
the Alpine v1 and Alpine v2 device trees.
This series depends on "[PATCH v2 0/3] arm64: introduce the Alpine support":
https://lkml.org/lkml/2016/2/10/83
You can find the series at:
https://github.com/atenart/linux.git 4.5-rc1/alpinev2-msix
Antoine
Since v1:
- Added an interrupt-parent property in the documentation example.
- Updated to use bitmap_*() instead of *_bit().
- Removed the static irq_set_affinity to use irq_chip_set_affinity_parent().
- Updated the address field to use phys_addr_t.
- Added a comment on why we're setting bit 16 in the address.
- Patched the gic_set_affinity() function in irqchip/gic-v3.
Antoine Tenart (7):
irqchip/gic-v3: always return IRQ_SET_MASK_OK_DONE in gic_set_affinity
irqchip: add the Alpine MSIX interrupt controller
Documentation: bindings: document the Alpine MSIX driver
arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi
ARM: dts: alpine: add the MSIX node
arm64: alpine: select the Alpine MSI controller driver
arm: alpine: select the Alpine MSI controller driver
.../interrupt-controller/al,alpine-msix.txt | 24 ++
arch/arm/boot/dts/alpine.dtsi | 10 +
arch/arm/mach-alpine/Kconfig | 1 +
arch/arm64/Kconfig.platforms | 1 +
arch/arm64/boot/dts/al/alpine-v2.dtsi | 10 +
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-alpine-msi.c | 293 +++++++++++++++++++++
drivers/irqchip/irq-gic-v3.c | 2 +-
9 files changed, 347 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
create mode 100644 drivers/irqchip/irq-alpine-msi.c
--
2.7.0
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 0/7] irqchip: introduce the Alpine MSIX driver
@ 2016-02-10 13:22 ` Antoine Tenart
0 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:22 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
This series introduce the Alpine MSIX driver, and enables it in both
the Alpine v1 and Alpine v2 device trees.
This series depends on "[PATCH v2 0/3] arm64: introduce the Alpine support":
https://lkml.org/lkml/2016/2/10/83
You can find the series at:
https://github.com/atenart/linux.git 4.5-rc1/alpinev2-msix
Antoine
Since v1:
- Added an interrupt-parent property in the documentation example.
- Updated to use bitmap_*() instead of *_bit().
- Removed the static irq_set_affinity to use irq_chip_set_affinity_parent().
- Updated the address field to use phys_addr_t.
- Added a comment on why we're setting bit 16 in the address.
- Patched the gic_set_affinity() function in irqchip/gic-v3.
Antoine Tenart (7):
irqchip/gic-v3: always return IRQ_SET_MASK_OK_DONE in gic_set_affinity
irqchip: add the Alpine MSIX interrupt controller
Documentation: bindings: document the Alpine MSIX driver
arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi
ARM: dts: alpine: add the MSIX node
arm64: alpine: select the Alpine MSI controller driver
arm: alpine: select the Alpine MSI controller driver
.../interrupt-controller/al,alpine-msix.txt | 24 ++
arch/arm/boot/dts/alpine.dtsi | 10 +
arch/arm/mach-alpine/Kconfig | 1 +
arch/arm64/Kconfig.platforms | 1 +
arch/arm64/boot/dts/al/alpine-v2.dtsi | 10 +
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-alpine-msi.c | 293 +++++++++++++++++++++
drivers/irqchip/irq-gic-v3.c | 2 +-
9 files changed, 347 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
create mode 100644 drivers/irqchip/irq-alpine-msi.c
--
2.7.0
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 1/7] irqchip/gic-v3: always return IRQ_SET_MASK_OK_DONE in gic_set_affinity
2016-02-10 13:22 ` Antoine Tenart
@ 2016-02-10 13:22 ` Antoine Tenart
-1 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:22 UTC (permalink / raw)
To: tglx, jason, marc.zyngier, tsahee
Cc: Antoine Tenart, rshitrit, thomas.petazzoni, linux-arm-kernel,
linux-kernel
Always return IRQ_SET_MASK_OK_DONE instead of IRQ_SET_MASK_OK when the
affinity has been updated. When using stacked irqchips, returning
IRQ_SET_MASK_OK_DONE means skipping all descendant irqchips.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
drivers/irqchip/irq-gic-v3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index d7be6ddc34f6..ca120a99bd5a 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -634,7 +634,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
else
gic_dist_wait_for_rwp();
- return IRQ_SET_MASK_OK;
+ return IRQ_SET_MASK_OK_DONE;
}
#else
#define gic_set_affinity NULL
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 1/7] irqchip/gic-v3: always return IRQ_SET_MASK_OK_DONE in gic_set_affinity
@ 2016-02-10 13:22 ` Antoine Tenart
0 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:22 UTC (permalink / raw)
To: linux-arm-kernel
Always return IRQ_SET_MASK_OK_DONE instead of IRQ_SET_MASK_OK when the
affinity has been updated. When using stacked irqchips, returning
IRQ_SET_MASK_OK_DONE means skipping all descendant irqchips.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
drivers/irqchip/irq-gic-v3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index d7be6ddc34f6..ca120a99bd5a 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -634,7 +634,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
else
gic_dist_wait_for_rwp();
- return IRQ_SET_MASK_OK;
+ return IRQ_SET_MASK_OK_DONE;
}
#else
#define gic_set_affinity NULL
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 2/7] irqchip: add the Alpine MSIX interrupt controller
2016-02-10 13:22 ` Antoine Tenart
@ 2016-02-10 13:22 ` Antoine Tenart
-1 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:22 UTC (permalink / raw)
To: tglx, jason, marc.zyngier, tsahee
Cc: Antoine Tenart, rshitrit, thomas.petazzoni, linux-arm-kernel,
linux-kernel
This patch adds the Alpine MSIX interrupt controller driver.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
---
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-alpine-msi.c | 293 +++++++++++++++++++++++++++++++++++++++
3 files changed, 300 insertions(+)
create mode 100644 drivers/irqchip/irq-alpine-msi.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 715923d5236c..f20e5b28eb5f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -60,6 +60,12 @@ config ARM_VIC_NR
The maximum number of VICs available in the system, for
power management.
+config ALPINE_MSI
+ bool
+ depends on PCI && PCI_MSI
+ select GENERIC_IRQ_CHIP
+ select PCI_MSI_IRQ_DOMAIN
+
config ATMEL_AIC_IRQ
bool
select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 18caacb60d58..57f68e0eea74 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_IRQCHIP) += irqchip.o
+obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
diff --git a/drivers/irqchip/irq-alpine-msi.c b/drivers/irqchip/irq-alpine-msi.c
new file mode 100644
index 000000000000..f8712722a606
--- /dev/null
+++ b/drivers/irqchip/irq-alpine-msi.c
@@ -0,0 +1,293 @@
+/*
+ * Annapurna Labs MSIX support services
+ *
+ * Copyright (C) 2016, Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Antoine Tenart <antoine.tenart@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/msi.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+
+#include <asm/irq.h>
+#include <asm-generic/msi.h>
+
+/* MSIX message address format: local GIC target */
+#define ALPINE_MSIX_SPI_TARGET_CLUSTER0 BIT(16)
+
+struct alpine_msix_data {
+ spinlock_t msi_map_lock;
+ phys_addr_t addr;
+ u32 spi_first; /* The SGI number that MSIs start */
+ u32 num_spis; /* The number of SGIs for MSIs */
+ unsigned long *msi_map;
+};
+
+static void alpine_msix_mask_msi_irq(struct irq_data *d)
+{
+ pci_msi_mask_irq(d);
+ irq_chip_mask_parent(d);
+}
+
+static void alpine_msix_unmask_msi_irq(struct irq_data *d)
+{
+ pci_msi_unmask_irq(d);
+ irq_chip_unmask_parent(d);
+}
+
+static struct irq_chip alpine_msix_irq_chip = {
+ .name = "MSIx",
+ .irq_mask = alpine_msix_mask_msi_irq,
+ .irq_unmask = alpine_msix_unmask_msi_irq,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+};
+
+static int alpine_msix_allocate_sgi(struct alpine_msix_data *priv, int num_req)
+{
+ int first;
+
+ spin_lock(&priv->msi_map_lock);
+
+ first = bitmap_find_next_zero_area(priv->msi_map, priv->num_spis, 0,
+ num_req, 0);
+ if (first >= priv->num_spis) {
+ spin_unlock(&priv->msi_map_lock);
+ return -ENOSPC;
+ }
+
+ bitmap_set(priv->msi_map, first, num_req);
+
+ spin_unlock(&priv->msi_map_lock);
+
+ return priv->spi_first + first;
+}
+
+static void alpine_msix_free_sgi(struct alpine_msix_data *priv, unsigned sgi,
+ int num_req)
+{
+ int first = sgi - priv->spi_first;
+
+ spin_lock(&priv->msi_map_lock);
+
+ bitmap_clear(priv->msi_map, first, num_req);
+
+ spin_unlock(&priv->msi_map_lock);
+}
+
+static void alpine_msix_compose_msi_msg(struct irq_data *data,
+ struct msi_msg *msg)
+{
+ struct alpine_msix_data *priv = irq_data_get_irq_chip_data(data);
+ phys_addr_t msg_addr = priv->addr;
+
+ msg_addr |= (data->hwirq << 3);
+
+ msg->address_hi = upper_32_bits(msg_addr);
+ msg->address_lo = lower_32_bits(msg_addr);
+ msg->data = 0;
+}
+
+static struct msi_domain_info alpine_msix_domain_info = {
+ .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+ MSI_FLAG_PCI_MSIX,
+ .chip = &alpine_msix_irq_chip,
+};
+
+static struct irq_chip middle_irq_chip = {
+ .name = "alpine_msix_middle",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .irq_compose_msi_msg = alpine_msix_compose_msi_msg,
+};
+
+static int alpine_msix_gic_domain_alloc(struct irq_domain *domain,
+ unsigned int virq, int sgi)
+{
+ struct irq_fwspec fwspec;
+ struct irq_data *d;
+ int ret;
+
+ if (!is_of_node(domain->parent->fwnode))
+ return -EINVAL;
+
+ fwspec.fwnode = domain->parent->fwnode;
+ fwspec.param_count = 3;
+ fwspec.param[0] = 0;
+ fwspec.param[1] = sgi;
+ fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
+
+ ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
+ if (ret)
+ return ret;
+
+ d = irq_domain_get_irq_data(domain->parent, virq);
+ d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
+
+ return 0;
+}
+
+static int alpine_msix_middle_domain_alloc(struct irq_domain *domain,
+ unsigned int virq,
+ unsigned int nr_irqs, void *args)
+{
+ struct alpine_msix_data *priv = domain->host_data;
+ int sgi, err, i;
+
+ sgi = alpine_msix_allocate_sgi(priv, nr_irqs);
+ if (sgi < 0)
+ return sgi;
+
+ for (i = 0; i < nr_irqs; i++) {
+ err = alpine_msix_gic_domain_alloc(domain, virq + i, sgi + i);
+ if (err)
+ goto err_sgi;
+
+ irq_domain_set_hwirq_and_chip(domain, virq + i, sgi + i,
+ &middle_irq_chip, priv);
+ }
+
+ return 0;
+
+err_sgi:
+ while (--i >= 0)
+ irq_domain_free_irqs_parent(domain, virq, i);
+ alpine_msix_free_sgi(priv, sgi, nr_irqs);
+ return err;
+}
+
+static void alpine_msix_middle_domain_free(struct irq_domain *domain,
+ unsigned int virq,
+ unsigned int nr_irqs)
+{
+ struct irq_data *d = irq_domain_get_irq_data(domain, virq);
+ struct alpine_msix_data *priv = irq_data_get_irq_chip_data(d);
+
+ irq_domain_free_irqs_parent(domain, virq, nr_irqs);
+ alpine_msix_free_sgi(priv, d->hwirq, nr_irqs);
+}
+
+static const struct irq_domain_ops alpine_msix_middle_domain_ops = {
+ .alloc = alpine_msix_middle_domain_alloc,
+ .free = alpine_msix_middle_domain_free,
+};
+
+static int alpine_msix_init_domains(struct alpine_msix_data *priv,
+ struct device_node *node)
+{
+ struct irq_domain *middle_domain, *msi_domain, *gic_domain;
+ struct device_node *gic_node;
+
+ gic_node = of_irq_find_parent(node);
+ if (!gic_node) {
+ pr_err("Failed to find the GIC node\n");
+ return -ENODEV;
+ }
+
+ gic_domain = irq_find_host(gic_node);
+ if (!gic_domain) {
+ pr_err("Failed to find the GIC domain\n");
+ return -ENXIO;
+ }
+
+ middle_domain = irq_domain_add_tree(NULL,
+ &alpine_msix_middle_domain_ops,
+ priv);
+ if (!middle_domain) {
+ pr_err("Failed to create the MSIX middle domain\n");
+ return -ENOMEM;
+ }
+
+ middle_domain->parent = gic_domain;
+
+ msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
+ &alpine_msix_domain_info,
+ middle_domain);
+ if (!msi_domain) {
+ pr_err("Failed to create MSI domain\n");
+ irq_domain_remove(msi_domain);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static int alpine_msix_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct alpine_msix_data *priv;
+ struct resource res;
+ int ret;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->msi_map_lock);
+
+ ret = of_address_to_resource(node, 0, &res);
+ if (ret) {
+ pr_err("Failed to allocate resource\n");
+ goto err_priv;
+ }
+
+ /*
+ * The 20 least significant bits of addr provide direct information
+ * regarding the interrupt destination.
+ *
+ * To select the primary GIC as the target GIC, bits [18:17] must be set
+ * to 0x0. In this case, bit 16 (SPI_TARGET_CLUSTER0) must be set.
+ */
+ priv->addr = res.start & GENMASK_ULL(63,20);
+ priv->addr |= ALPINE_MSIX_SPI_TARGET_CLUSTER0;
+
+ if (of_property_read_u32(node, "al,msi-base-spi", &priv->spi_first)) {
+ pr_err("Unable to parse MSI base\n");
+ ret = -EINVAL;
+ goto err_priv;
+ }
+
+ if (of_property_read_u32(node, "al,msi-num-spis", &priv->num_spis)) {
+ pr_err("Unable to parse MSI numbers\n");
+ ret = -EINVAL;
+ goto err_priv;
+ }
+
+ priv->msi_map = kzalloc(sizeof(*priv->msi_map) * BITS_TO_LONGS(priv->num_spis),
+ GFP_KERNEL);
+ if (!priv->msi_map) {
+ ret = -ENOMEM;
+ goto err_priv;
+ }
+
+ pr_debug("Registering %d msixs, starting at %d\n",
+ priv->num_spis, priv->spi_first);
+
+ ret = alpine_msix_init_domains(priv, node);
+ if (ret)
+ goto err_map;
+
+ return 0;
+
+err_map:
+ kfree(priv->msi_map);
+err_priv:
+ kfree(priv);
+ return ret;
+}
+IRQCHIP_DECLARE(alpine_msix, "al,alpine-msix", alpine_msix_init);
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 2/7] irqchip: add the Alpine MSIX interrupt controller
@ 2016-02-10 13:22 ` Antoine Tenart
0 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:22 UTC (permalink / raw)
To: linux-arm-kernel
This patch adds the Alpine MSIX interrupt controller driver.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
---
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-alpine-msi.c | 293 +++++++++++++++++++++++++++++++++++++++
3 files changed, 300 insertions(+)
create mode 100644 drivers/irqchip/irq-alpine-msi.c
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 715923d5236c..f20e5b28eb5f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -60,6 +60,12 @@ config ARM_VIC_NR
The maximum number of VICs available in the system, for
power management.
+config ALPINE_MSI
+ bool
+ depends on PCI && PCI_MSI
+ select GENERIC_IRQ_CHIP
+ select PCI_MSI_IRQ_DOMAIN
+
config ATMEL_AIC_IRQ
bool
select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 18caacb60d58..57f68e0eea74 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -1,5 +1,6 @@
obj-$(CONFIG_IRQCHIP) += irqchip.o
+obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
diff --git a/drivers/irqchip/irq-alpine-msi.c b/drivers/irqchip/irq-alpine-msi.c
new file mode 100644
index 000000000000..f8712722a606
--- /dev/null
+++ b/drivers/irqchip/irq-alpine-msi.c
@@ -0,0 +1,293 @@
+/*
+ * Annapurna Labs MSIX support services
+ *
+ * Copyright (C) 2016, Amazon.com, Inc. or its affiliates. All Rights Reserved.
+ *
+ * Antoine Tenart <antoine.tenart@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
+#include <linux/irqchip.h>
+#include <linux/irqchip/arm-gic.h>
+#include <linux/msi.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_pci.h>
+#include <linux/pci.h>
+#include <linux/slab.h>
+
+#include <asm/irq.h>
+#include <asm-generic/msi.h>
+
+/* MSIX message address format: local GIC target */
+#define ALPINE_MSIX_SPI_TARGET_CLUSTER0 BIT(16)
+
+struct alpine_msix_data {
+ spinlock_t msi_map_lock;
+ phys_addr_t addr;
+ u32 spi_first; /* The SGI number that MSIs start */
+ u32 num_spis; /* The number of SGIs for MSIs */
+ unsigned long *msi_map;
+};
+
+static void alpine_msix_mask_msi_irq(struct irq_data *d)
+{
+ pci_msi_mask_irq(d);
+ irq_chip_mask_parent(d);
+}
+
+static void alpine_msix_unmask_msi_irq(struct irq_data *d)
+{
+ pci_msi_unmask_irq(d);
+ irq_chip_unmask_parent(d);
+}
+
+static struct irq_chip alpine_msix_irq_chip = {
+ .name = "MSIx",
+ .irq_mask = alpine_msix_mask_msi_irq,
+ .irq_unmask = alpine_msix_unmask_msi_irq,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+};
+
+static int alpine_msix_allocate_sgi(struct alpine_msix_data *priv, int num_req)
+{
+ int first;
+
+ spin_lock(&priv->msi_map_lock);
+
+ first = bitmap_find_next_zero_area(priv->msi_map, priv->num_spis, 0,
+ num_req, 0);
+ if (first >= priv->num_spis) {
+ spin_unlock(&priv->msi_map_lock);
+ return -ENOSPC;
+ }
+
+ bitmap_set(priv->msi_map, first, num_req);
+
+ spin_unlock(&priv->msi_map_lock);
+
+ return priv->spi_first + first;
+}
+
+static void alpine_msix_free_sgi(struct alpine_msix_data *priv, unsigned sgi,
+ int num_req)
+{
+ int first = sgi - priv->spi_first;
+
+ spin_lock(&priv->msi_map_lock);
+
+ bitmap_clear(priv->msi_map, first, num_req);
+
+ spin_unlock(&priv->msi_map_lock);
+}
+
+static void alpine_msix_compose_msi_msg(struct irq_data *data,
+ struct msi_msg *msg)
+{
+ struct alpine_msix_data *priv = irq_data_get_irq_chip_data(data);
+ phys_addr_t msg_addr = priv->addr;
+
+ msg_addr |= (data->hwirq << 3);
+
+ msg->address_hi = upper_32_bits(msg_addr);
+ msg->address_lo = lower_32_bits(msg_addr);
+ msg->data = 0;
+}
+
+static struct msi_domain_info alpine_msix_domain_info = {
+ .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+ MSI_FLAG_PCI_MSIX,
+ .chip = &alpine_msix_irq_chip,
+};
+
+static struct irq_chip middle_irq_chip = {
+ .name = "alpine_msix_middle",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .irq_compose_msi_msg = alpine_msix_compose_msi_msg,
+};
+
+static int alpine_msix_gic_domain_alloc(struct irq_domain *domain,
+ unsigned int virq, int sgi)
+{
+ struct irq_fwspec fwspec;
+ struct irq_data *d;
+ int ret;
+
+ if (!is_of_node(domain->parent->fwnode))
+ return -EINVAL;
+
+ fwspec.fwnode = domain->parent->fwnode;
+ fwspec.param_count = 3;
+ fwspec.param[0] = 0;
+ fwspec.param[1] = sgi;
+ fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
+
+ ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
+ if (ret)
+ return ret;
+
+ d = irq_domain_get_irq_data(domain->parent, virq);
+ d->chip->irq_set_type(d, IRQ_TYPE_EDGE_RISING);
+
+ return 0;
+}
+
+static int alpine_msix_middle_domain_alloc(struct irq_domain *domain,
+ unsigned int virq,
+ unsigned int nr_irqs, void *args)
+{
+ struct alpine_msix_data *priv = domain->host_data;
+ int sgi, err, i;
+
+ sgi = alpine_msix_allocate_sgi(priv, nr_irqs);
+ if (sgi < 0)
+ return sgi;
+
+ for (i = 0; i < nr_irqs; i++) {
+ err = alpine_msix_gic_domain_alloc(domain, virq + i, sgi + i);
+ if (err)
+ goto err_sgi;
+
+ irq_domain_set_hwirq_and_chip(domain, virq + i, sgi + i,
+ &middle_irq_chip, priv);
+ }
+
+ return 0;
+
+err_sgi:
+ while (--i >= 0)
+ irq_domain_free_irqs_parent(domain, virq, i);
+ alpine_msix_free_sgi(priv, sgi, nr_irqs);
+ return err;
+}
+
+static void alpine_msix_middle_domain_free(struct irq_domain *domain,
+ unsigned int virq,
+ unsigned int nr_irqs)
+{
+ struct irq_data *d = irq_domain_get_irq_data(domain, virq);
+ struct alpine_msix_data *priv = irq_data_get_irq_chip_data(d);
+
+ irq_domain_free_irqs_parent(domain, virq, nr_irqs);
+ alpine_msix_free_sgi(priv, d->hwirq, nr_irqs);
+}
+
+static const struct irq_domain_ops alpine_msix_middle_domain_ops = {
+ .alloc = alpine_msix_middle_domain_alloc,
+ .free = alpine_msix_middle_domain_free,
+};
+
+static int alpine_msix_init_domains(struct alpine_msix_data *priv,
+ struct device_node *node)
+{
+ struct irq_domain *middle_domain, *msi_domain, *gic_domain;
+ struct device_node *gic_node;
+
+ gic_node = of_irq_find_parent(node);
+ if (!gic_node) {
+ pr_err("Failed to find the GIC node\n");
+ return -ENODEV;
+ }
+
+ gic_domain = irq_find_host(gic_node);
+ if (!gic_domain) {
+ pr_err("Failed to find the GIC domain\n");
+ return -ENXIO;
+ }
+
+ middle_domain = irq_domain_add_tree(NULL,
+ &alpine_msix_middle_domain_ops,
+ priv);
+ if (!middle_domain) {
+ pr_err("Failed to create the MSIX middle domain\n");
+ return -ENOMEM;
+ }
+
+ middle_domain->parent = gic_domain;
+
+ msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
+ &alpine_msix_domain_info,
+ middle_domain);
+ if (!msi_domain) {
+ pr_err("Failed to create MSI domain\n");
+ irq_domain_remove(msi_domain);
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static int alpine_msix_init(struct device_node *node,
+ struct device_node *parent)
+{
+ struct alpine_msix_data *priv;
+ struct resource res;
+ int ret;
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->msi_map_lock);
+
+ ret = of_address_to_resource(node, 0, &res);
+ if (ret) {
+ pr_err("Failed to allocate resource\n");
+ goto err_priv;
+ }
+
+ /*
+ * The 20 least significant bits of addr provide direct information
+ * regarding the interrupt destination.
+ *
+ * To select the primary GIC as the target GIC, bits [18:17] must be set
+ * to 0x0. In this case, bit 16 (SPI_TARGET_CLUSTER0) must be set.
+ */
+ priv->addr = res.start & GENMASK_ULL(63,20);
+ priv->addr |= ALPINE_MSIX_SPI_TARGET_CLUSTER0;
+
+ if (of_property_read_u32(node, "al,msi-base-spi", &priv->spi_first)) {
+ pr_err("Unable to parse MSI base\n");
+ ret = -EINVAL;
+ goto err_priv;
+ }
+
+ if (of_property_read_u32(node, "al,msi-num-spis", &priv->num_spis)) {
+ pr_err("Unable to parse MSI numbers\n");
+ ret = -EINVAL;
+ goto err_priv;
+ }
+
+ priv->msi_map = kzalloc(sizeof(*priv->msi_map) * BITS_TO_LONGS(priv->num_spis),
+ GFP_KERNEL);
+ if (!priv->msi_map) {
+ ret = -ENOMEM;
+ goto err_priv;
+ }
+
+ pr_debug("Registering %d msixs, starting at %d\n",
+ priv->num_spis, priv->spi_first);
+
+ ret = alpine_msix_init_domains(priv, node);
+ if (ret)
+ goto err_map;
+
+ return 0;
+
+err_map:
+ kfree(priv->msi_map);
+err_priv:
+ kfree(priv);
+ return ret;
+}
+IRQCHIP_DECLARE(alpine_msix, "al,alpine-msix", alpine_msix_init);
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 3/7] Documentation: bindings: document the Alpine MSIX driver
2016-02-10 13:22 ` Antoine Tenart
@ 2016-02-10 13:22 ` Antoine Tenart
-1 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:22 UTC (permalink / raw)
To: tglx, jason, marc.zyngier, tsahee
Cc: Antoine Tenart, rshitrit, thomas.petazzoni, linux-arm-kernel,
linux-kernel
Following the addition of the Alpine MSIX driver, this patch adds the
corresponding bindings documentation.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
---
.../interrupt-controller/al,alpine-msix.txt | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
new file mode 100644
index 000000000000..c7d3d0192f5d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
@@ -0,0 +1,24 @@
+Alpine MSIX controller
+
+Required properties:
+
+- compatible: should be "al,alpine-msix"
+- reg: physical base address and size of the registers
+- interrupt-parent: specifies the parent interrupt controller.
+- interrupt-controller: identifies the node as an interrupt controller
+- msi-controller: identifies the node as an PCI Message Signaled Interrupt
+ controller
+- al,msi-base-spi: SPI base of the MSI frame
+- al,msi-num-spis: number of SPIs assigned to the MSI frame
+
+Example:
+
+msix: msix {
+ compatible = "al,alpine-msix";
+ reg = <0x0 0xfbe00000 0x0 0x100000>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ msi-controller;
+ al,msi-base-spi = <160>;
+ al,msi-num-spis = <160>;
+};
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 3/7] Documentation: bindings: document the Alpine MSIX driver
@ 2016-02-10 13:22 ` Antoine Tenart
0 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:22 UTC (permalink / raw)
To: linux-arm-kernel
Following the addition of the Alpine MSIX driver, this patch adds the
corresponding bindings documentation.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
---
.../interrupt-controller/al,alpine-msix.txt | 24 ++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
new file mode 100644
index 000000000000..c7d3d0192f5d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
@@ -0,0 +1,24 @@
+Alpine MSIX controller
+
+Required properties:
+
+- compatible: should be "al,alpine-msix"
+- reg: physical base address and size of the registers
+- interrupt-parent: specifies the parent interrupt controller.
+- interrupt-controller: identifies the node as an interrupt controller
+- msi-controller: identifies the node as an PCI Message Signaled Interrupt
+ controller
+- al,msi-base-spi: SPI base of the MSI frame
+- al,msi-num-spis: number of SPIs assigned to the MSI frame
+
+Example:
+
+msix: msix {
+ compatible = "al,alpine-msix";
+ reg = <0x0 0xfbe00000 0x0 0x100000>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ msi-controller;
+ al,msi-base-spi = <160>;
+ al,msi-num-spis = <160>;
+};
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 4/7] arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi
2016-02-10 13:22 ` Antoine Tenart
@ 2016-02-10 13:23 ` Antoine Tenart
-1 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:23 UTC (permalink / raw)
To: tglx, jason, marc.zyngier, tsahee
Cc: Antoine Tenart, rshitrit, thomas.petazzoni, linux-arm-kernel,
linux-kernel
Following the addition of the Alpine MSIX controller driver, add the
corresponding node in the Alpine v2 device tree.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
---
arch/arm64/boot/dts/al/alpine-v2.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/al/alpine-v2.dtsi b/arch/arm64/boot/dts/al/alpine-v2.dtsi
index c021e077343b..5b7bef684256 100644
--- a/arch/arm64/boot/dts/al/alpine-v2.dtsi
+++ b/arch/arm64/boot/dts/al/alpine-v2.dtsi
@@ -139,6 +139,16 @@
/* 32 bit non prefetchable memory space */
ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
bus-range = <0x00 0x00>;
+ msi-parent = <&msix>;
+ };
+
+ msix: msix@fbe00000 {
+ compatible = "al,alpine-msix";
+ reg = <0x0 0xfbe00000 0x0 0x100000>;
+ interrupt-controller;
+ msi-controller;
+ al,msi-base-spi = <160>;
+ al,msi-num-spis = <160>;
};
io-fabric {
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 4/7] arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi
@ 2016-02-10 13:23 ` Antoine Tenart
0 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:23 UTC (permalink / raw)
To: linux-arm-kernel
Following the addition of the Alpine MSIX controller driver, add the
corresponding node in the Alpine v2 device tree.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
---
arch/arm64/boot/dts/al/alpine-v2.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/al/alpine-v2.dtsi b/arch/arm64/boot/dts/al/alpine-v2.dtsi
index c021e077343b..5b7bef684256 100644
--- a/arch/arm64/boot/dts/al/alpine-v2.dtsi
+++ b/arch/arm64/boot/dts/al/alpine-v2.dtsi
@@ -139,6 +139,16 @@
/* 32 bit non prefetchable memory space */
ranges = <0x2000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
bus-range = <0x00 0x00>;
+ msi-parent = <&msix>;
+ };
+
+ msix: msix at fbe00000 {
+ compatible = "al,alpine-msix";
+ reg = <0x0 0xfbe00000 0x0 0x100000>;
+ interrupt-controller;
+ msi-controller;
+ al,msi-base-spi = <160>;
+ al,msi-num-spis = <160>;
};
io-fabric {
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 5/7] ARM: dts: alpine: add the MSIX node
2016-02-10 13:22 ` Antoine Tenart
@ 2016-02-10 13:23 ` Antoine Tenart
-1 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:23 UTC (permalink / raw)
To: tglx, jason, marc.zyngier, tsahee
Cc: Antoine Tenart, rshitrit, thomas.petazzoni, linux-arm-kernel,
linux-kernel
With the newly available MSIX driver for Alpine, add the corresponding
node in the Alpine device tree.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
arch/arm/boot/dts/alpine.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
index 9af2d60e9a7f..db8752fc480e 100644
--- a/arch/arm/boot/dts/alpine.dtsi
+++ b/arch/arm/boot/dts/alpine.dtsi
@@ -155,6 +155,16 @@
ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
bus-range = <0x00 0x00>;
+ msi-parent = <&msix>;
+ };
+
+ msix: msix@fbe00000 {
+ compatible = "al,alpine-msix";
+ reg = <0x0 0xfbe00000 0x0 0x100000>;
+ interrupt-controller;
+ msi-controller;
+ al,msi-base-spi = <96>;
+ al,msi-num-spis = <64>;
};
};
};
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 5/7] ARM: dts: alpine: add the MSIX node
@ 2016-02-10 13:23 ` Antoine Tenart
0 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:23 UTC (permalink / raw)
To: linux-arm-kernel
With the newly available MSIX driver for Alpine, add the corresponding
node in the Alpine device tree.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
arch/arm/boot/dts/alpine.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
index 9af2d60e9a7f..db8752fc480e 100644
--- a/arch/arm/boot/dts/alpine.dtsi
+++ b/arch/arm/boot/dts/alpine.dtsi
@@ -155,6 +155,16 @@
ranges = <0x02000000 0x0 0xfe000000 0x0 0xfe000000 0x0 0x1000000>;
bus-range = <0x00 0x00>;
+ msi-parent = <&msix>;
+ };
+
+ msix: msix at fbe00000 {
+ compatible = "al,alpine-msix";
+ reg = <0x0 0xfbe00000 0x0 0x100000>;
+ interrupt-controller;
+ msi-controller;
+ al,msi-base-spi = <96>;
+ al,msi-num-spis = <64>;
};
};
};
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 6/7] arm64: alpine: select the Alpine MSI controller driver
2016-02-10 13:22 ` Antoine Tenart
@ 2016-02-10 13:23 ` Antoine Tenart
-1 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:23 UTC (permalink / raw)
To: tglx, jason, marc.zyngier, tsahee
Cc: Antoine Tenart, rshitrit, thomas.petazzoni, linux-arm-kernel,
linux-kernel
Select the Alpine MSI controller driver when using an Alpine platform.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
---
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index bfbefa3e0dbe..6761e12e5e13 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -2,6 +2,7 @@ menu "Platform selection"
config ARCH_ALPINE
bool "Annapurna Labs Alpine platform"
+ select ALPINE_MSI
help
This enables support for the Annapurna Labs Alpine
Soc family.
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 6/7] arm64: alpine: select the Alpine MSI controller driver
@ 2016-02-10 13:23 ` Antoine Tenart
0 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:23 UTC (permalink / raw)
To: linux-arm-kernel
Select the Alpine MSI controller driver when using an Alpine platform.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
---
arch/arm64/Kconfig.platforms | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index bfbefa3e0dbe..6761e12e5e13 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -2,6 +2,7 @@ menu "Platform selection"
config ARCH_ALPINE
bool "Annapurna Labs Alpine platform"
+ select ALPINE_MSI
help
This enables support for the Annapurna Labs Alpine
Soc family.
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 7/7] arm: alpine: select the Alpine MSI controller driver
2016-02-10 13:22 ` Antoine Tenart
@ 2016-02-10 13:23 ` Antoine Tenart
-1 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:23 UTC (permalink / raw)
To: tglx, jason, marc.zyngier, tsahee
Cc: Antoine Tenart, rshitrit, thomas.petazzoni, linux-arm-kernel,
linux-kernel
Select the Alpine MSI controller driver when using an Alpine platform.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
---
arch/arm/mach-alpine/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-alpine/Kconfig b/arch/arm/mach-alpine/Kconfig
index 5c2d54f59f53..b41838a58ae4 100644
--- a/arch/arm/mach-alpine/Kconfig
+++ b/arch/arm/mach-alpine/Kconfig
@@ -1,6 +1,7 @@
config ARCH_ALPINE
bool "Annapurna Labs Alpine platform"
depends on ARCH_MULTI_V7
+ select ALPINE_MSI
select ARM_AMBA
select ARM_GIC
select GENERIC_IRQ_CHIP
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 7/7] arm: alpine: select the Alpine MSI controller driver
@ 2016-02-10 13:23 ` Antoine Tenart
0 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-10 13:23 UTC (permalink / raw)
To: linux-arm-kernel
Select the Alpine MSI controller driver when using an Alpine platform.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
---
arch/arm/mach-alpine/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-alpine/Kconfig b/arch/arm/mach-alpine/Kconfig
index 5c2d54f59f53..b41838a58ae4 100644
--- a/arch/arm/mach-alpine/Kconfig
+++ b/arch/arm/mach-alpine/Kconfig
@@ -1,6 +1,7 @@
config ARCH_ALPINE
bool "Annapurna Labs Alpine platform"
depends on ARCH_MULTI_V7
+ select ALPINE_MSI
select ARM_AMBA
select ARM_GIC
select GENERIC_IRQ_CHIP
--
2.7.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v2 1/7] irqchip/gic-v3: always return IRQ_SET_MASK_OK_DONE in gic_set_affinity
2016-02-10 13:22 ` Antoine Tenart
@ 2016-02-10 17:19 ` Marc Zyngier
-1 siblings, 0 replies; 28+ messages in thread
From: Marc Zyngier @ 2016-02-10 17:19 UTC (permalink / raw)
To: Antoine Tenart, tglx, jason, tsahee
Cc: rshitrit, thomas.petazzoni, linux-arm-kernel, linux-kernel
On 10/02/16 13:22, Antoine Tenart wrote:
> Always return IRQ_SET_MASK_OK_DONE instead of IRQ_SET_MASK_OK when the
> affinity has been updated. When using stacked irqchips, returning
> IRQ_SET_MASK_OK_DONE means skipping all descendant irqchips.
>
> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 1/7] irqchip/gic-v3: always return IRQ_SET_MASK_OK_DONE in gic_set_affinity
@ 2016-02-10 17:19 ` Marc Zyngier
0 siblings, 0 replies; 28+ messages in thread
From: Marc Zyngier @ 2016-02-10 17:19 UTC (permalink / raw)
To: linux-arm-kernel
On 10/02/16 13:22, Antoine Tenart wrote:
> Always return IRQ_SET_MASK_OK_DONE instead of IRQ_SET_MASK_OK when the
> affinity has been updated. When using stacked irqchips, returning
> IRQ_SET_MASK_OK_DONE means skipping all descendant irqchips.
>
> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 2/7] irqchip: add the Alpine MSIX interrupt controller
2016-02-10 13:22 ` Antoine Tenart
@ 2016-02-11 13:27 ` Marc Zyngier
-1 siblings, 0 replies; 28+ messages in thread
From: Marc Zyngier @ 2016-02-11 13:27 UTC (permalink / raw)
To: Antoine Tenart, tglx, jason, tsahee
Cc: rshitrit, thomas.petazzoni, linux-arm-kernel, linux-kernel
On 10/02/16 13:22, Antoine Tenart wrote:
> This patch adds the Alpine MSIX interrupt controller driver.
>
> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
> Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 2/7] irqchip: add the Alpine MSIX interrupt controller
@ 2016-02-11 13:27 ` Marc Zyngier
0 siblings, 0 replies; 28+ messages in thread
From: Marc Zyngier @ 2016-02-11 13:27 UTC (permalink / raw)
To: linux-arm-kernel
On 10/02/16 13:22, Antoine Tenart wrote:
> This patch adds the Alpine MSIX interrupt controller driver.
>
> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
> Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 3/7] Documentation: bindings: document the Alpine MSIX driver
2016-02-10 13:22 ` Antoine Tenart
@ 2016-02-11 13:32 ` Marc Zyngier
-1 siblings, 0 replies; 28+ messages in thread
From: Marc Zyngier @ 2016-02-11 13:32 UTC (permalink / raw)
To: Antoine Tenart, tglx, jason, tsahee
Cc: rshitrit, thomas.petazzoni, linux-arm-kernel, linux-kernel
On 10/02/16 13:22, Antoine Tenart wrote:
> Following the addition of the Alpine MSIX driver, this patch adds the
> corresponding bindings documentation.
>
> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
> Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
> ---
> .../interrupt-controller/al,alpine-msix.txt | 24 ++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
> new file mode 100644
> index 000000000000..c7d3d0192f5d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
> @@ -0,0 +1,24 @@
> +Alpine MSIX controller
> +
> +Required properties:
> +
> +- compatible: should be "al,alpine-msix"
> +- reg: physical base address and size of the registers
> +- interrupt-parent: specifies the parent interrupt controller.
> +- interrupt-controller: identifies the node as an interrupt controller
> +- msi-controller: identifies the node as an PCI Message Signaled Interrupt
> + controller
> +- al,msi-base-spi: SPI base of the MSI frame
> +- al,msi-num-spis: number of SPIs assigned to the MSI frame
It would probably be good to reference the GIC bindings so that the
"SPI" acronym makes actual sense. It will also disambiguate the "base"
aspect (is this number relative to IRQ0? or SPI0? - I assume the latter,
but that's by looking at the code).
> +
> +Example:
> +
> +msix: msix {
> + compatible = "al,alpine-msix";
> + reg = <0x0 0xfbe00000 0x0 0x100000>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + msi-controller;
> + al,msi-base-spi = <160>;
> + al,msi-num-spis = <160>;
> +};
>
Otherwise looks good to me.
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 3/7] Documentation: bindings: document the Alpine MSIX driver
@ 2016-02-11 13:32 ` Marc Zyngier
0 siblings, 0 replies; 28+ messages in thread
From: Marc Zyngier @ 2016-02-11 13:32 UTC (permalink / raw)
To: linux-arm-kernel
On 10/02/16 13:22, Antoine Tenart wrote:
> Following the addition of the Alpine MSIX driver, this patch adds the
> corresponding bindings documentation.
>
> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
> Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
> ---
> .../interrupt-controller/al,alpine-msix.txt | 24 ++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
> new file mode 100644
> index 000000000000..c7d3d0192f5d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/al,alpine-msix.txt
> @@ -0,0 +1,24 @@
> +Alpine MSIX controller
> +
> +Required properties:
> +
> +- compatible: should be "al,alpine-msix"
> +- reg: physical base address and size of the registers
> +- interrupt-parent: specifies the parent interrupt controller.
> +- interrupt-controller: identifies the node as an interrupt controller
> +- msi-controller: identifies the node as an PCI Message Signaled Interrupt
> + controller
> +- al,msi-base-spi: SPI base of the MSI frame
> +- al,msi-num-spis: number of SPIs assigned to the MSI frame
It would probably be good to reference the GIC bindings so that the
"SPI" acronym makes actual sense. It will also disambiguate the "base"
aspect (is this number relative to IRQ0? or SPI0? - I assume the latter,
but that's by looking at the code).
> +
> +Example:
> +
> +msix: msix {
> + compatible = "al,alpine-msix";
> + reg = <0x0 0xfbe00000 0x0 0x100000>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + msi-controller;
> + al,msi-base-spi = <160>;
> + al,msi-num-spis = <160>;
> +};
>
Otherwise looks good to me.
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/7] irqchip: introduce the Alpine MSIX driver
2016-02-10 13:22 ` Antoine Tenart
@ 2016-02-11 13:41 ` Marc Zyngier
-1 siblings, 0 replies; 28+ messages in thread
From: Marc Zyngier @ 2016-02-11 13:41 UTC (permalink / raw)
To: Antoine Tenart, tglx, jason, tsahee
Cc: rshitrit, thomas.petazzoni, linux-arm-kernel, linux-kernel
Antoine,
On 10/02/16 13:22, Antoine Tenart wrote:
> Hi all,
>
> This series introduce the Alpine MSIX driver, and enables it in both
> the Alpine v1 and Alpine v2 device trees.
>
> This series depends on "[PATCH v2 0/3] arm64: introduce the Alpine support":
> https://lkml.org/lkml/2016/2/10/83
>
> You can find the series at:
> https://github.com/atenart/linux.git 4.5-rc1/alpinev2-msix
So I'm quite happy with this as it is (modulo the documentation fix on
patch 3). I can take the first 3 patches through my GIC tree, but the
last 4 patches depend on your other series.
Would it be a problem to get these 4 patches merged after 4.6-rc1, so
that all the code can be merged before?
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 0/7] irqchip: introduce the Alpine MSIX driver
@ 2016-02-11 13:41 ` Marc Zyngier
0 siblings, 0 replies; 28+ messages in thread
From: Marc Zyngier @ 2016-02-11 13:41 UTC (permalink / raw)
To: linux-arm-kernel
Antoine,
On 10/02/16 13:22, Antoine Tenart wrote:
> Hi all,
>
> This series introduce the Alpine MSIX driver, and enables it in both
> the Alpine v1 and Alpine v2 device trees.
>
> This series depends on "[PATCH v2 0/3] arm64: introduce the Alpine support":
> https://lkml.org/lkml/2016/2/10/83
>
> You can find the series at:
> https://github.com/atenart/linux.git 4.5-rc1/alpinev2-msix
So I'm quite happy with this as it is (modulo the documentation fix on
patch 3). I can take the first 3 patches through my GIC tree, but the
last 4 patches depend on your other series.
Would it be a problem to get these 4 patches merged after 4.6-rc1, so
that all the code can be merged before?
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/7] irqchip: introduce the Alpine MSIX driver
2016-02-11 13:41 ` Marc Zyngier
@ 2016-02-11 14:45 ` Antoine Tenart
-1 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-11 14:45 UTC (permalink / raw)
To: Marc Zyngier
Cc: Antoine Tenart, tglx, jason, tsahee, rshitrit, thomas.petazzoni,
linux-arm-kernel, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 999 bytes --]
Hello Marc,
On Thu, Feb 11, 2016 at 01:41:48PM +0000, Marc Zyngier wrote:
> On 10/02/16 13:22, Antoine Tenart wrote:
> >
> > This series introduce the Alpine MSIX driver, and enables it in both
> > the Alpine v1 and Alpine v2 device trees.
> >
> > This series depends on "[PATCH v2 0/3] arm64: introduce the Alpine support":
> > https://lkml.org/lkml/2016/2/10/83
> >
> > You can find the series at:
> > https://github.com/atenart/linux.git 4.5-rc1/alpinev2-msix
>
> So I'm quite happy with this as it is (modulo the documentation fix on
> patch 3). I can take the first 3 patches through my GIC tree, but the
> last 4 patches depend on your other series.
I'll fix the documentation.
> Would it be a problem to get these 4 patches merged after 4.6-rc1, so
> that all the code can be merged before?
I think we can live with that :)
Thanks,
Antoine
--
Antoine Ténart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 0/7] irqchip: introduce the Alpine MSIX driver
@ 2016-02-11 14:45 ` Antoine Tenart
0 siblings, 0 replies; 28+ messages in thread
From: Antoine Tenart @ 2016-02-11 14:45 UTC (permalink / raw)
To: linux-arm-kernel
Hello Marc,
On Thu, Feb 11, 2016 at 01:41:48PM +0000, Marc Zyngier wrote:
> On 10/02/16 13:22, Antoine Tenart wrote:
> >
> > This series introduce the Alpine MSIX driver, and enables it in both
> > the Alpine v1 and Alpine v2 device trees.
> >
> > This series depends on "[PATCH v2 0/3] arm64: introduce the Alpine support":
> > https://lkml.org/lkml/2016/2/10/83
> >
> > You can find the series at:
> > https://github.com/atenart/linux.git 4.5-rc1/alpinev2-msix
>
> So I'm quite happy with this as it is (modulo the documentation fix on
> patch 3). I can take the first 3 patches through my GIC tree, but the
> last 4 patches depend on your other series.
I'll fix the documentation.
> Would it be a problem to get these 4 patches merged after 4.6-rc1, so
> that all the code can be merged before?
I think we can live with that :)
Thanks,
Antoine
--
Antoine T?nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v2 0/7] irqchip: introduce the Alpine MSIX driver
2016-02-11 14:45 ` Antoine Tenart
@ 2016-02-11 14:59 ` Thomas Petazzoni
-1 siblings, 0 replies; 28+ messages in thread
From: Thomas Petazzoni @ 2016-02-11 14:59 UTC (permalink / raw)
To: Antoine Tenart
Cc: Marc Zyngier, tglx, jason, tsahee, rshitrit, linux-arm-kernel,
linux-kernel
Hello,
On Thu, 11 Feb 2016 15:45:44 +0100, Antoine Tenart wrote:
> On Thu, Feb 11, 2016 at 01:41:48PM +0000, Marc Zyngier wrote:
> > On 10/02/16 13:22, Antoine Tenart wrote:
> > >
> > > This series introduce the Alpine MSIX driver, and enables it in both
> > > the Alpine v1 and Alpine v2 device trees.
> > >
> > > This series depends on "[PATCH v2 0/3] arm64: introduce the Alpine support":
> > > https://lkml.org/lkml/2016/2/10/83
> > >
> > > You can find the series at:
> > > https://github.com/atenart/linux.git 4.5-rc1/alpinev2-msix
> >
> > So I'm quite happy with this as it is (modulo the documentation fix on
> > patch 3). I can take the first 3 patches through my GIC tree, but the
> > last 4 patches depend on your other series.
>
> I'll fix the documentation.
>
> > Would it be a problem to get these 4 patches merged after 4.6-rc1, so
> > that all the code can be merged before?
>
> I think we can live with that :)
Practically speaking, patches 4-7 have no build dependency on patches
1-3, so they can be merged independently. As long as the DT binding
introduced in patches 1-3 is validated, then patches 4-7 can be merged
in parallel.
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 0/7] irqchip: introduce the Alpine MSIX driver
@ 2016-02-11 14:59 ` Thomas Petazzoni
0 siblings, 0 replies; 28+ messages in thread
From: Thomas Petazzoni @ 2016-02-11 14:59 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
On Thu, 11 Feb 2016 15:45:44 +0100, Antoine Tenart wrote:
> On Thu, Feb 11, 2016 at 01:41:48PM +0000, Marc Zyngier wrote:
> > On 10/02/16 13:22, Antoine Tenart wrote:
> > >
> > > This series introduce the Alpine MSIX driver, and enables it in both
> > > the Alpine v1 and Alpine v2 device trees.
> > >
> > > This series depends on "[PATCH v2 0/3] arm64: introduce the Alpine support":
> > > https://lkml.org/lkml/2016/2/10/83
> > >
> > > You can find the series at:
> > > https://github.com/atenart/linux.git 4.5-rc1/alpinev2-msix
> >
> > So I'm quite happy with this as it is (modulo the documentation fix on
> > patch 3). I can take the first 3 patches through my GIC tree, but the
> > last 4 patches depend on your other series.
>
> I'll fix the documentation.
>
> > Would it be a problem to get these 4 patches merged after 4.6-rc1, so
> > that all the code can be merged before?
>
> I think we can live with that :)
Practically speaking, patches 4-7 have no build dependency on patches
1-3, so they can be merged independently. As long as the DT binding
introduced in patches 1-3 is validated, then patches 4-7 can be merged
in parallel.
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2016-02-11 15:10 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-02-10 13:22 [PATCH v2 0/7] irqchip: introduce the Alpine MSIX driver Antoine Tenart
2016-02-10 13:22 ` Antoine Tenart
2016-02-10 13:22 ` [PATCH v2 1/7] irqchip/gic-v3: always return IRQ_SET_MASK_OK_DONE in gic_set_affinity Antoine Tenart
2016-02-10 13:22 ` Antoine Tenart
2016-02-10 17:19 ` Marc Zyngier
2016-02-10 17:19 ` Marc Zyngier
2016-02-10 13:22 ` [PATCH v2 2/7] irqchip: add the Alpine MSIX interrupt controller Antoine Tenart
2016-02-10 13:22 ` Antoine Tenart
2016-02-11 13:27 ` Marc Zyngier
2016-02-11 13:27 ` Marc Zyngier
2016-02-10 13:22 ` [PATCH v2 3/7] Documentation: bindings: document the Alpine MSIX driver Antoine Tenart
2016-02-10 13:22 ` Antoine Tenart
2016-02-11 13:32 ` Marc Zyngier
2016-02-11 13:32 ` Marc Zyngier
2016-02-10 13:23 ` [PATCH v2 4/7] arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi Antoine Tenart
2016-02-10 13:23 ` Antoine Tenart
2016-02-10 13:23 ` [PATCH v2 5/7] ARM: dts: alpine: add the MSIX node Antoine Tenart
2016-02-10 13:23 ` Antoine Tenart
2016-02-10 13:23 ` [PATCH v2 6/7] arm64: alpine: select the Alpine MSI controller driver Antoine Tenart
2016-02-10 13:23 ` Antoine Tenart
2016-02-10 13:23 ` [PATCH v2 7/7] arm: " Antoine Tenart
2016-02-10 13:23 ` Antoine Tenart
2016-02-11 13:41 ` [PATCH v2 0/7] irqchip: introduce the Alpine MSIX driver Marc Zyngier
2016-02-11 13:41 ` Marc Zyngier
2016-02-11 14:45 ` Antoine Tenart
2016-02-11 14:45 ` Antoine Tenart
2016-02-11 14:59 ` Thomas Petazzoni
2016-02-11 14:59 ` Thomas Petazzoni
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