* [PATCH V7 00/12] Add T210 support in Tegra soctherm
@ 2016-03-11 3:09 ` Wei Ni
0 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-11 3:09 UTC (permalink / raw)
To: rui.zhang, edubezval, thierry.reding
Cc: MLongnecker, swarren, mikko.perttunen, linux-tegra, linux-pm,
linux-kernel, Wei Ni
This patchset adds following functions for tegra_soctherm driver:
1. add T210 support.
2. export debugfs to show some registers.
3. add thermtrip funciton.
4. add suspend/resume function.
The v6 series is in:
https://lkml.org/lkml/2016/2/22/66
The v5 series is in:
http://www.spinics.net/lists/linux-tegra/msg25079.html
The v4 series is in:
http://www.spinics.net/lists/linux-tegra/msg24972.html
The V3 series is in:
http://www.spinics.net/lists/linux-tegra/msg24911.html
The V2 series is in:
http://www.spinics.net/lists/linux-tegra/msg24901.html
The V1 series is in:
http://www.spinics.net/lists/linux-tegra/msg24808.html
Main changes from V6:
1. rebased patches on Eduardo's
[PATCH 00/13] thermal: convert users of thermal_zone_of_sensor_register to devm_
Main changes from V5:
1. Change to use linux thermal framework to implement
thermtrip funciton, per Rob's comment.
2. Add .set_trip_temp() in of-thermal driver, so that
we can set trips on hardware.
Main changes from V4:
1. Change description of devicetree binding per Rob's comment.
2. Call of_node_put to decrement refcount of the node.
Main changes from V3:
1. Change structures to "const" in chip specific files.
2. Minor changes per Thieery's comments.
Main changes from V2:
1. Fix build error in patch [1/11].
2. Use of_get_child_by_name instead of of_find_node_by_name in patch [8/11].
3. Use debugfs_remove_recursive to remove debugfs in patch [6/11].
Main changes from V1:
1. Use the new type to handl different Tegra chips in one driver, which suggested by Thierry.
2. Changes per Thieery's other comments.
Wei Ni (12):
thermal: tegra: move tegra thermal files into tegra directory
thermal: tegra: combine sensor group-related data
thermal: tegra: get rid of PDIV/HOTSPOT hack
thermal: tegra: split tegra_soctherm driver
thermal: tegra: add Tegra210 specific SOC_THERM driver
thermal: tegra: add a debugfs to show registers
thermal: of-thermal: allow setting trip_temp on hardware
of: add notes of critical trips for soctherm
thermal: tegra: add thermtrip function
thermal: tegra: add PM support
arm64: tegra: add soctherm node for Tegra210
arm: tegra: set critical trips for Tegra124
.../devicetree/bindings/thermal/tegra-soctherm.txt | 12 +
arch/arm/boot/dts/tegra124.dtsi | 16 +
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 60 ++
drivers/thermal/Kconfig | 12 +-
drivers/thermal/Makefile | 2 +-
drivers/thermal/of-thermal.c | 8 +
drivers/thermal/tegra/Kconfig | 13 +
drivers/thermal/tegra/Makefile | 5 +
drivers/thermal/tegra/soctherm-fuse.c | 169 +++++
drivers/thermal/tegra/soctherm.c | 681 +++++++++++++++++++++
drivers/thermal/tegra/soctherm.h | 123 ++++
drivers/thermal/tegra/tegra124-soctherm.c | 196 ++++++
drivers/thermal/tegra/tegra210-soctherm.c | 197 ++++++
drivers/thermal/tegra_soctherm.c | 463 --------------
include/dt-bindings/thermal/tegra124-soctherm.h | 1 +
include/linux/thermal.h | 1 +
16 files changed, 1485 insertions(+), 474 deletions(-)
create mode 100644 drivers/thermal/tegra/Kconfig
create mode 100644 drivers/thermal/tegra/Makefile
create mode 100644 drivers/thermal/tegra/soctherm-fuse.c
create mode 100644 drivers/thermal/tegra/soctherm.c
create mode 100644 drivers/thermal/tegra/soctherm.h
create mode 100644 drivers/thermal/tegra/tegra124-soctherm.c
create mode 100644 drivers/thermal/tegra/tegra210-soctherm.c
delete mode 100644 drivers/thermal/tegra_soctherm.c
--
1.9.1
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH V7 00/12] Add T210 support in Tegra soctherm
@ 2016-03-11 3:09 ` Wei Ni
0 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-11 3:09 UTC (permalink / raw)
To: rui.zhang, edubezval, thierry.reding
Cc: MLongnecker, swarren, mikko.perttunen, linux-tegra, linux-pm,
linux-kernel, Wei Ni
This patchset adds following functions for tegra_soctherm driver:
1. add T210 support.
2. export debugfs to show some registers.
3. add thermtrip funciton.
4. add suspend/resume function.
The v6 series is in:
https://lkml.org/lkml/2016/2/22/66
The v5 series is in:
http://www.spinics.net/lists/linux-tegra/msg25079.html
The v4 series is in:
http://www.spinics.net/lists/linux-tegra/msg24972.html
The V3 series is in:
http://www.spinics.net/lists/linux-tegra/msg24911.html
The V2 series is in:
http://www.spinics.net/lists/linux-tegra/msg24901.html
The V1 series is in:
http://www.spinics.net/lists/linux-tegra/msg24808.html
Main changes from V6:
1. rebased patches on Eduardo's
[PATCH 00/13] thermal: convert users of thermal_zone_of_sensor_register to devm_
Main changes from V5:
1. Change to use linux thermal framework to implement
thermtrip funciton, per Rob's comment.
2. Add .set_trip_temp() in of-thermal driver, so that
we can set trips on hardware.
Main changes from V4:
1. Change description of devicetree binding per Rob's comment.
2. Call of_node_put to decrement refcount of the node.
Main changes from V3:
1. Change structures to "const" in chip specific files.
2. Minor changes per Thieery's comments.
Main changes from V2:
1. Fix build error in patch [1/11].
2. Use of_get_child_by_name instead of of_find_node_by_name in patch [8/11].
3. Use debugfs_remove_recursive to remove debugfs in patch [6/11].
Main changes from V1:
1. Use the new type to handl different Tegra chips in one driver, which suggested by Thierry.
2. Changes per Thieery's other comments.
Wei Ni (12):
thermal: tegra: move tegra thermal files into tegra directory
thermal: tegra: combine sensor group-related data
thermal: tegra: get rid of PDIV/HOTSPOT hack
thermal: tegra: split tegra_soctherm driver
thermal: tegra: add Tegra210 specific SOC_THERM driver
thermal: tegra: add a debugfs to show registers
thermal: of-thermal: allow setting trip_temp on hardware
of: add notes of critical trips for soctherm
thermal: tegra: add thermtrip function
thermal: tegra: add PM support
arm64: tegra: add soctherm node for Tegra210
arm: tegra: set critical trips for Tegra124
.../devicetree/bindings/thermal/tegra-soctherm.txt | 12 +
arch/arm/boot/dts/tegra124.dtsi | 16 +
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 60 ++
drivers/thermal/Kconfig | 12 +-
drivers/thermal/Makefile | 2 +-
drivers/thermal/of-thermal.c | 8 +
drivers/thermal/tegra/Kconfig | 13 +
drivers/thermal/tegra/Makefile | 5 +
drivers/thermal/tegra/soctherm-fuse.c | 169 +++++
drivers/thermal/tegra/soctherm.c | 681 +++++++++++++++++++++
drivers/thermal/tegra/soctherm.h | 123 ++++
drivers/thermal/tegra/tegra124-soctherm.c | 196 ++++++
drivers/thermal/tegra/tegra210-soctherm.c | 197 ++++++
drivers/thermal/tegra_soctherm.c | 463 --------------
include/dt-bindings/thermal/tegra124-soctherm.h | 1 +
include/linux/thermal.h | 1 +
16 files changed, 1485 insertions(+), 474 deletions(-)
create mode 100644 drivers/thermal/tegra/Kconfig
create mode 100644 drivers/thermal/tegra/Makefile
create mode 100644 drivers/thermal/tegra/soctherm-fuse.c
create mode 100644 drivers/thermal/tegra/soctherm.c
create mode 100644 drivers/thermal/tegra/soctherm.h
create mode 100644 drivers/thermal/tegra/tegra124-soctherm.c
create mode 100644 drivers/thermal/tegra/tegra210-soctherm.c
delete mode 100644 drivers/thermal/tegra_soctherm.c
--
1.9.1
^ permalink raw reply [flat|nested] 25+ messages in thread
* [PATCH V7 01/12] thermal: tegra: move tegra thermal files into tegra directory
2016-03-11 3:09 ` Wei Ni
@ 2016-03-11 3:09 ` Wei Ni
-1 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-11 3:09 UTC (permalink / raw)
To: rui.zhang, edubezval, thierry.reding
Cc: MLongnecker, swarren, mikko.perttunen, linux-tegra, linux-pm,
linux-kernel, Wei Ni
Move Tegra soctherm driver to tegra directory, it's easy to maintain
and add more new function support for Tegra platforms.
This will also help to split soctherm driver into common parts and
chip specific data related parts.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
drivers/thermal/Kconfig | 12 ++----------
drivers/thermal/Makefile | 2 +-
drivers/thermal/tegra/Kconfig | 13 +++++++++++++
drivers/thermal/tegra/Makefile | 1 +
.../thermal/{tegra_soctherm.c => tegra/tegra-soctherm.c} | 0
5 files changed, 17 insertions(+), 11 deletions(-)
create mode 100644 drivers/thermal/tegra/Kconfig
create mode 100644 drivers/thermal/tegra/Makefile
rename drivers/thermal/{tegra_soctherm.c => tegra/tegra-soctherm.c} (100%)
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 8cc4ac64a91c..1802629f5051 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -254,16 +254,6 @@ config ARMADA_THERMAL
Enable this option if you want to have support for thermal management
controller present in Armada 370 and Armada XP SoC.
-config TEGRA_SOCTHERM
- tristate "Tegra SOCTHERM thermal management"
- depends on ARCH_TEGRA
- help
- Enable this option for integrated thermal management support on NVIDIA
- Tegra124 systems-on-chip. The driver supports four thermal zones
- (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
- zones to manage temperatures. This option is also required for the
- emergency thermal reset (thermtrip) feature to function.
-
config DB8500_CPUFREQ_COOLING
tristate "DB8500 cpufreq cooling"
depends on ARCH_U8500
@@ -380,6 +370,8 @@ depends on ARCH_STI && OF
source "drivers/thermal/st/Kconfig"
endmenu
+source "drivers/thermal/tegra/Kconfig"
+
config QCOM_SPMI_TEMP_ALARM
tristate "Qualcomm SPMI PMIC Temperature Alarm"
depends on OF && SPMI && IIO
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index cfae6a654793..119e25cdcc66 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -46,5 +46,5 @@ obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/
obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/
obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o
obj-$(CONFIG_ST_THERMAL) += st/
-obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o
+obj-$(CONFIG_TEGRA_SOCTHERM) += tegra/
obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
diff --git a/drivers/thermal/tegra/Kconfig b/drivers/thermal/tegra/Kconfig
new file mode 100644
index 000000000000..0b719d8b629b
--- /dev/null
+++ b/drivers/thermal/tegra/Kconfig
@@ -0,0 +1,13 @@
+menu "NVIDIA Tegra thermal drivers"
+
+config TEGRA_SOCTHERM
+ tristate "Tegra SOCTHERM thermal management"
+ depends on ARCH_TEGRA
+ help
+ Enable this option for integrated thermal management support on NVIDIA
+ Tegra124 systems-on-chip. The driver supports four thermal zones
+ (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
+ zones to manage temperatures. This option is also required for the
+ emergency thermal reset (thermtrip) feature to function.
+
+endmenu
diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile
new file mode 100644
index 000000000000..d4dc4e7f279e
--- /dev/null
+++ b/drivers/thermal/tegra/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_TEGRA_SOCTHERM) += tegra-soctherm.o
diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
similarity index 100%
rename from drivers/thermal/tegra_soctherm.c
rename to drivers/thermal/tegra/tegra-soctherm.c
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH V7 01/12] thermal: tegra: move tegra thermal files into tegra directory
@ 2016-03-11 3:09 ` Wei Ni
0 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-11 3:09 UTC (permalink / raw)
To: rui.zhang, edubezval, thierry.reding
Cc: MLongnecker, swarren, mikko.perttunen, linux-tegra, linux-pm,
linux-kernel, Wei Ni
Move Tegra soctherm driver to tegra directory, it's easy to maintain
and add more new function support for Tegra platforms.
This will also help to split soctherm driver into common parts and
chip specific data related parts.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
drivers/thermal/Kconfig | 12 ++----------
drivers/thermal/Makefile | 2 +-
drivers/thermal/tegra/Kconfig | 13 +++++++++++++
drivers/thermal/tegra/Makefile | 1 +
.../thermal/{tegra_soctherm.c => tegra/tegra-soctherm.c} | 0
5 files changed, 17 insertions(+), 11 deletions(-)
create mode 100644 drivers/thermal/tegra/Kconfig
create mode 100644 drivers/thermal/tegra/Makefile
rename drivers/thermal/{tegra_soctherm.c => tegra/tegra-soctherm.c} (100%)
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 8cc4ac64a91c..1802629f5051 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -254,16 +254,6 @@ config ARMADA_THERMAL
Enable this option if you want to have support for thermal management
controller present in Armada 370 and Armada XP SoC.
-config TEGRA_SOCTHERM
- tristate "Tegra SOCTHERM thermal management"
- depends on ARCH_TEGRA
- help
- Enable this option for integrated thermal management support on NVIDIA
- Tegra124 systems-on-chip. The driver supports four thermal zones
- (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
- zones to manage temperatures. This option is also required for the
- emergency thermal reset (thermtrip) feature to function.
-
config DB8500_CPUFREQ_COOLING
tristate "DB8500 cpufreq cooling"
depends on ARCH_U8500
@@ -380,6 +370,8 @@ depends on ARCH_STI && OF
source "drivers/thermal/st/Kconfig"
endmenu
+source "drivers/thermal/tegra/Kconfig"
+
config QCOM_SPMI_TEMP_ALARM
tristate "Qualcomm SPMI PMIC Temperature Alarm"
depends on OF && SPMI && IIO
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
index cfae6a654793..119e25cdcc66 100644
--- a/drivers/thermal/Makefile
+++ b/drivers/thermal/Makefile
@@ -46,5 +46,5 @@ obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/
obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/
obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o
obj-$(CONFIG_ST_THERMAL) += st/
-obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o
+obj-$(CONFIG_TEGRA_SOCTHERM) += tegra/
obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
diff --git a/drivers/thermal/tegra/Kconfig b/drivers/thermal/tegra/Kconfig
new file mode 100644
index 000000000000..0b719d8b629b
--- /dev/null
+++ b/drivers/thermal/tegra/Kconfig
@@ -0,0 +1,13 @@
+menu "NVIDIA Tegra thermal drivers"
+
+config TEGRA_SOCTHERM
+ tristate "Tegra SOCTHERM thermal management"
+ depends on ARCH_TEGRA
+ help
+ Enable this option for integrated thermal management support on NVIDIA
+ Tegra124 systems-on-chip. The driver supports four thermal zones
+ (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
+ zones to manage temperatures. This option is also required for the
+ emergency thermal reset (thermtrip) feature to function.
+
+endmenu
diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile
new file mode 100644
index 000000000000..d4dc4e7f279e
--- /dev/null
+++ b/drivers/thermal/tegra/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_TEGRA_SOCTHERM) += tegra-soctherm.o
diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
similarity index 100%
rename from drivers/thermal/tegra_soctherm.c
rename to drivers/thermal/tegra/tegra-soctherm.c
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH V7 02/12] thermal: tegra: combine sensor group-related data
2016-03-11 3:09 ` Wei Ni
@ 2016-03-11 3:09 ` Wei Ni
-1 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-11 3:09 UTC (permalink / raw)
To: rui.zhang, edubezval, thierry.reding
Cc: MLongnecker, swarren, mikko.perttunen, linux-tegra, linux-pm,
linux-kernel, Wei Ni
Combine sensor group-related data structures into struct
tegra_tsensor_group. This provides a single location for
sensor group data storage.
More sensor group data will be added in subsequent patches.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
drivers/thermal/tegra/tegra-soctherm.c | 145 +++++++++++++++++++-----
include/dt-bindings/thermal/tegra124-soctherm.h | 1 +
2 files changed, 119 insertions(+), 27 deletions(-)
diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
index 0018ccd51de4..b3ec0faa2bee 100644
--- a/drivers/thermal/tegra/tegra-soctherm.c
+++ b/drivers/thermal/tegra/tegra-soctherm.c
@@ -28,6 +28,7 @@
#include <linux/thermal.h>
#include <soc/tegra/fuse.h>
+#include <dt-bindings/thermal/tegra124-soctherm.h>
#define SENSOR_CONFIG0 0
#define SENSOR_CONFIG0_STOP BIT(0)
@@ -48,12 +49,24 @@
#define SENSOR_PDIV 0x1c0
#define SENSOR_PDIV_T124 0x8888
+#define SENSOR_PDIV_CPU_MASK (0xf << 12)
+#define SENSOR_PDIV_GPU_MASK (0xf << 8)
+#define SENSOR_PDIV_MEM_MASK (0xf << 4)
+#define SENSOR_PDIV_PLLX_MASK (0xf << 0)
+
#define SENSOR_HOTSPOT_OFF 0x1c4
#define SENSOR_HOTSPOT_OFF_T124 0x00060600
+#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
+#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
+#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
+
#define SENSOR_TEMP1 0x1c8
+#define SENSOR_TEMP1_CPU_TEMP_MASK (0xffff << 16)
+#define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff
#define SENSOR_TEMP2 0x1cc
+#define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16)
+#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
-#define SENSOR_TEMP_MASK 0xffff
#define READBACK_VALUE_MASK 0xff00
#define READBACK_VALUE_SHIFT 8
#define READBACK_ADD_HALF BIT(7)
@@ -77,8 +90,36 @@
#define NOMINAL_CALIB_FT_T124 105
#define NOMINAL_CALIB_CP_T124 25
+/* get val from register(r) mask bits(m) */
+#define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
+/* set val(v) to mask bits(m) of register(r) */
+#define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
+ (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
+
+/**
+ * struct tegra_tsensor_group - SOC_THERM sensor group data
+ * @name: short name of the temperature sensor group
+ * @id: numeric ID of the temperature sensor group
+ * @sensor_temp_offset: offset of the SENSOR_TEMP* register
+ * @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register
+ * @pdiv: the sensor count post-divider to use during runtime
+ * @pdiv_ate: the sensor count post-divider used during automated test
+ * @pdiv_mask: register bitfield mask for the PDIV field for this sensor
+ * @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for
+ PLLX sensor group
+ * @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field
+ */
+struct tegra_tsensor_group {
+ const char *name;
+ u8 id;
+ u16 sensor_temp_offset;
+ u32 sensor_temp_mask;
+ u32 pdiv, pdiv_ate, pdiv_mask;
+ u32 pllx_hotspot_diff, pllx_hotspot_mask;
+};
+
struct tegra_tsensor_configuration {
- u32 tall, tsample, tiddq_en, ten_count, pdiv, tsample_ate, pdiv_ate;
+ u32 tall, tiddq_en, ten_count, tsample, tsample_ate;
};
struct tegra_tsensor {
@@ -86,21 +127,74 @@ struct tegra_tsensor {
u32 base, calib_fuse_offset;
/* Correction values used to modify values read from calibration fuses */
s32 fuse_corr_alpha, fuse_corr_beta;
+ const struct tegra_tsensor_group *group;
};
struct tegra_thermctl_zone {
void __iomem *reg;
- unsigned int shift;
+ u32 mask;
};
static const struct tegra_tsensor_configuration t124_tsensor_config = {
.tall = 16300,
- .tsample = 120,
.tiddq_en = 1,
.ten_count = 1,
- .pdiv = 8,
+ .tsample = 120,
.tsample_ate = 480,
- .pdiv_ate = 8
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = {
+ .id = TEGRA124_SOCTHERM_SENSOR_CPU,
+ .name = "cpu",
+ .sensor_temp_offset = SENSOR_TEMP1,
+ .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_CPU_MASK,
+ .pllx_hotspot_diff = 10,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
+ .id = TEGRA124_SOCTHERM_SENSOR_GPU,
+ .name = "gpu",
+ .sensor_temp_offset = SENSOR_TEMP1,
+ .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_GPU_MASK,
+ .pllx_hotspot_diff = 5,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
+ .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
+ .name = "pll",
+ .sensor_temp_offset = SENSOR_TEMP2,
+ .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
+ .pllx_hotspot_diff = 0,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
+ .id = TEGRA124_SOCTHERM_SENSOR_MEM,
+ .name = "mem",
+ .sensor_temp_offset = SENSOR_TEMP2,
+ .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_MEM_MASK,
+};
+
+static const struct tegra_tsensor_group *
+tegra124_tsensor_groups[TEGRA124_SOCTHERM_SENSOR_NUM] = {
+ &tegra124_tsensor_group_cpu,
+ &tegra124_tsensor_group_gpu,
+ &tegra124_tsensor_group_pll,
+ &tegra124_tsensor_group_mem,
};
static const struct tegra_tsensor t124_tsensors[] = {
@@ -110,6 +204,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x098,
.fuse_corr_alpha = 1135400,
.fuse_corr_beta = -6266900,
+ .group = &tegra124_tsensor_group_cpu,
},
{
.config = &t124_tsensor_config,
@@ -117,6 +212,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x084,
.fuse_corr_alpha = 1122220,
.fuse_corr_beta = -5700700,
+ .group = &tegra124_tsensor_group_cpu,
},
{
.config = &t124_tsensor_config,
@@ -124,6 +220,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x088,
.fuse_corr_alpha = 1127000,
.fuse_corr_beta = -6768200,
+ .group = &tegra124_tsensor_group_cpu,
},
{
.config = &t124_tsensor_config,
@@ -131,6 +228,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x12c,
.fuse_corr_alpha = 1110900,
.fuse_corr_beta = -6232000,
+ .group = &tegra124_tsensor_group_cpu,
},
{
.config = &t124_tsensor_config,
@@ -138,6 +236,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x158,
.fuse_corr_alpha = 1122300,
.fuse_corr_beta = -5936400,
+ .group = &tegra124_tsensor_group_mem,
},
{
.config = &t124_tsensor_config,
@@ -145,6 +244,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x15c,
.fuse_corr_alpha = 1145700,
.fuse_corr_beta = -7124600,
+ .group = &tegra124_tsensor_group_mem,
},
{
.config = &t124_tsensor_config,
@@ -152,6 +252,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x154,
.fuse_corr_alpha = 1120100,
.fuse_corr_beta = -6000500,
+ .group = &tegra124_tsensor_group_gpu,
},
{
.config = &t124_tsensor_config,
@@ -159,6 +260,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x160,
.fuse_corr_alpha = 1106500,
.fuse_corr_beta = -6729300,
+ .group = &tegra124_tsensor_group_pll,
},
};
@@ -167,8 +269,6 @@ struct tegra_soctherm {
struct clk *clock_tsensor;
struct clk *clock_soctherm;
void __iomem *regs;
-
-#define ZONE_NUMBER 4
};
struct tsensor_shared_calibration {
@@ -237,8 +337,8 @@ calculate_tsensor_calibration(const struct tegra_tsensor *sensor,
delta_sens = actual_tsensor_ft - actual_tsensor_cp;
delta_temp = shared->actual_temp_ft - shared->actual_temp_cp;
- mult = sensor->config->pdiv * sensor->config->tsample_ate;
- div = sensor->config->tsample * sensor->config->pdiv_ate;
+ mult = sensor->group->pdiv * sensor->config->tsample_ate;
+ div = sensor->config->tsample * sensor->group->pdiv_ate;
therma = div64_s64_precise((s64) delta_temp * (1LL << 13) * mult,
(s64) delta_sens * div);
@@ -311,7 +411,8 @@ static int tegra_thermctl_get_temp(void *data, int *out_temp)
struct tegra_thermctl_zone *zone = data;
u32 val;
- val = (readl(zone->reg) >> zone->shift) & SENSOR_TEMP_MASK;
+ val = readl(zone->reg);
+ val = REG_GET_MASK(val, zone->mask);
*out_temp = translate_temp(val);
return 0;
@@ -327,18 +428,6 @@ static const struct of_device_id tegra_soctherm_of_match[] = {
};
MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
-struct thermctl_zone_desc {
- unsigned int offset;
- unsigned int shift;
-};
-
-static const struct thermctl_zone_desc t124_thermctl_temp_zones[] = {
- { SENSOR_TEMP1, 16 },
- { SENSOR_TEMP2, 16 },
- { SENSOR_TEMP1, 0 },
- { SENSOR_TEMP2, 0 }
-};
-
static int tegra_soctherm_probe(struct platform_device *pdev)
{
struct tegra_soctherm *tegra;
@@ -349,6 +438,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
int err;
const struct tegra_tsensor *tsensors = t124_tsensors;
+ const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
if (!tegra)
@@ -408,7 +498,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
/* Initialize thermctl sensors */
- for (i = 0; i < ZONE_NUMBER; ++i) {
+ for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
struct tegra_thermctl_zone *zone =
devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
if (!zone) {
@@ -416,10 +506,11 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
goto disable_clocks;
}
- zone->reg = tegra->regs + t124_thermctl_temp_zones[i].offset;
- zone->shift = t124_thermctl_temp_zones[i].shift;
+ zone->reg = tegra->regs + ttgs[i]->sensor_temp_offset;
+ zone->mask = ttgs[i]->sensor_temp_mask;
- z = devm_thermal_zone_of_sensor_register(&pdev->dev, i, zone,
+ z = devm_thermal_zone_of_sensor_register(&pdev->dev,
+ ttgs[i]->id, zone,
&tegra_of_thermal_ops);
if (IS_ERR(z)) {
err = PTR_ERR(z);
diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
index 85aaf66690f9..729ab9fc325e 100644
--- a/include/dt-bindings/thermal/tegra124-soctherm.h
+++ b/include/dt-bindings/thermal/tegra124-soctherm.h
@@ -9,5 +9,6 @@
#define TEGRA124_SOCTHERM_SENSOR_MEM 1
#define TEGRA124_SOCTHERM_SENSOR_GPU 2
#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
+#define TEGRA124_SOCTHERM_SENSOR_NUM 4
#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH V7 02/12] thermal: tegra: combine sensor group-related data
@ 2016-03-11 3:09 ` Wei Ni
0 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-11 3:09 UTC (permalink / raw)
To: rui.zhang, edubezval, thierry.reding
Cc: MLongnecker, swarren, mikko.perttunen, linux-tegra, linux-pm,
linux-kernel, Wei Ni
Combine sensor group-related data structures into struct
tegra_tsensor_group. This provides a single location for
sensor group data storage.
More sensor group data will be added in subsequent patches.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
drivers/thermal/tegra/tegra-soctherm.c | 145 +++++++++++++++++++-----
include/dt-bindings/thermal/tegra124-soctherm.h | 1 +
2 files changed, 119 insertions(+), 27 deletions(-)
diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
index 0018ccd51de4..b3ec0faa2bee 100644
--- a/drivers/thermal/tegra/tegra-soctherm.c
+++ b/drivers/thermal/tegra/tegra-soctherm.c
@@ -28,6 +28,7 @@
#include <linux/thermal.h>
#include <soc/tegra/fuse.h>
+#include <dt-bindings/thermal/tegra124-soctherm.h>
#define SENSOR_CONFIG0 0
#define SENSOR_CONFIG0_STOP BIT(0)
@@ -48,12 +49,24 @@
#define SENSOR_PDIV 0x1c0
#define SENSOR_PDIV_T124 0x8888
+#define SENSOR_PDIV_CPU_MASK (0xf << 12)
+#define SENSOR_PDIV_GPU_MASK (0xf << 8)
+#define SENSOR_PDIV_MEM_MASK (0xf << 4)
+#define SENSOR_PDIV_PLLX_MASK (0xf << 0)
+
#define SENSOR_HOTSPOT_OFF 0x1c4
#define SENSOR_HOTSPOT_OFF_T124 0x00060600
+#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
+#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
+#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
+
#define SENSOR_TEMP1 0x1c8
+#define SENSOR_TEMP1_CPU_TEMP_MASK (0xffff << 16)
+#define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff
#define SENSOR_TEMP2 0x1cc
+#define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16)
+#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
-#define SENSOR_TEMP_MASK 0xffff
#define READBACK_VALUE_MASK 0xff00
#define READBACK_VALUE_SHIFT 8
#define READBACK_ADD_HALF BIT(7)
@@ -77,8 +90,36 @@
#define NOMINAL_CALIB_FT_T124 105
#define NOMINAL_CALIB_CP_T124 25
+/* get val from register(r) mask bits(m) */
+#define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
+/* set val(v) to mask bits(m) of register(r) */
+#define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
+ (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
+
+/**
+ * struct tegra_tsensor_group - SOC_THERM sensor group data
+ * @name: short name of the temperature sensor group
+ * @id: numeric ID of the temperature sensor group
+ * @sensor_temp_offset: offset of the SENSOR_TEMP* register
+ * @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register
+ * @pdiv: the sensor count post-divider to use during runtime
+ * @pdiv_ate: the sensor count post-divider used during automated test
+ * @pdiv_mask: register bitfield mask for the PDIV field for this sensor
+ * @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for
+ PLLX sensor group
+ * @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field
+ */
+struct tegra_tsensor_group {
+ const char *name;
+ u8 id;
+ u16 sensor_temp_offset;
+ u32 sensor_temp_mask;
+ u32 pdiv, pdiv_ate, pdiv_mask;
+ u32 pllx_hotspot_diff, pllx_hotspot_mask;
+};
+
struct tegra_tsensor_configuration {
- u32 tall, tsample, tiddq_en, ten_count, pdiv, tsample_ate, pdiv_ate;
+ u32 tall, tiddq_en, ten_count, tsample, tsample_ate;
};
struct tegra_tsensor {
@@ -86,21 +127,74 @@ struct tegra_tsensor {
u32 base, calib_fuse_offset;
/* Correction values used to modify values read from calibration fuses */
s32 fuse_corr_alpha, fuse_corr_beta;
+ const struct tegra_tsensor_group *group;
};
struct tegra_thermctl_zone {
void __iomem *reg;
- unsigned int shift;
+ u32 mask;
};
static const struct tegra_tsensor_configuration t124_tsensor_config = {
.tall = 16300,
- .tsample = 120,
.tiddq_en = 1,
.ten_count = 1,
- .pdiv = 8,
+ .tsample = 120,
.tsample_ate = 480,
- .pdiv_ate = 8
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = {
+ .id = TEGRA124_SOCTHERM_SENSOR_CPU,
+ .name = "cpu",
+ .sensor_temp_offset = SENSOR_TEMP1,
+ .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_CPU_MASK,
+ .pllx_hotspot_diff = 10,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
+ .id = TEGRA124_SOCTHERM_SENSOR_GPU,
+ .name = "gpu",
+ .sensor_temp_offset = SENSOR_TEMP1,
+ .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_GPU_MASK,
+ .pllx_hotspot_diff = 5,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
+ .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
+ .name = "pll",
+ .sensor_temp_offset = SENSOR_TEMP2,
+ .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
+ .pllx_hotspot_diff = 0,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
+ .id = TEGRA124_SOCTHERM_SENSOR_MEM,
+ .name = "mem",
+ .sensor_temp_offset = SENSOR_TEMP2,
+ .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_MEM_MASK,
+};
+
+static const struct tegra_tsensor_group *
+tegra124_tsensor_groups[TEGRA124_SOCTHERM_SENSOR_NUM] = {
+ &tegra124_tsensor_group_cpu,
+ &tegra124_tsensor_group_gpu,
+ &tegra124_tsensor_group_pll,
+ &tegra124_tsensor_group_mem,
};
static const struct tegra_tsensor t124_tsensors[] = {
@@ -110,6 +204,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x098,
.fuse_corr_alpha = 1135400,
.fuse_corr_beta = -6266900,
+ .group = &tegra124_tsensor_group_cpu,
},
{
.config = &t124_tsensor_config,
@@ -117,6 +212,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x084,
.fuse_corr_alpha = 1122220,
.fuse_corr_beta = -5700700,
+ .group = &tegra124_tsensor_group_cpu,
},
{
.config = &t124_tsensor_config,
@@ -124,6 +220,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x088,
.fuse_corr_alpha = 1127000,
.fuse_corr_beta = -6768200,
+ .group = &tegra124_tsensor_group_cpu,
},
{
.config = &t124_tsensor_config,
@@ -131,6 +228,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x12c,
.fuse_corr_alpha = 1110900,
.fuse_corr_beta = -6232000,
+ .group = &tegra124_tsensor_group_cpu,
},
{
.config = &t124_tsensor_config,
@@ -138,6 +236,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x158,
.fuse_corr_alpha = 1122300,
.fuse_corr_beta = -5936400,
+ .group = &tegra124_tsensor_group_mem,
},
{
.config = &t124_tsensor_config,
@@ -145,6 +244,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x15c,
.fuse_corr_alpha = 1145700,
.fuse_corr_beta = -7124600,
+ .group = &tegra124_tsensor_group_mem,
},
{
.config = &t124_tsensor_config,
@@ -152,6 +252,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x154,
.fuse_corr_alpha = 1120100,
.fuse_corr_beta = -6000500,
+ .group = &tegra124_tsensor_group_gpu,
},
{
.config = &t124_tsensor_config,
@@ -159,6 +260,7 @@ static const struct tegra_tsensor t124_tsensors[] = {
.calib_fuse_offset = 0x160,
.fuse_corr_alpha = 1106500,
.fuse_corr_beta = -6729300,
+ .group = &tegra124_tsensor_group_pll,
},
};
@@ -167,8 +269,6 @@ struct tegra_soctherm {
struct clk *clock_tsensor;
struct clk *clock_soctherm;
void __iomem *regs;
-
-#define ZONE_NUMBER 4
};
struct tsensor_shared_calibration {
@@ -237,8 +337,8 @@ calculate_tsensor_calibration(const struct tegra_tsensor *sensor,
delta_sens = actual_tsensor_ft - actual_tsensor_cp;
delta_temp = shared->actual_temp_ft - shared->actual_temp_cp;
- mult = sensor->config->pdiv * sensor->config->tsample_ate;
- div = sensor->config->tsample * sensor->config->pdiv_ate;
+ mult = sensor->group->pdiv * sensor->config->tsample_ate;
+ div = sensor->config->tsample * sensor->group->pdiv_ate;
therma = div64_s64_precise((s64) delta_temp * (1LL << 13) * mult,
(s64) delta_sens * div);
@@ -311,7 +411,8 @@ static int tegra_thermctl_get_temp(void *data, int *out_temp)
struct tegra_thermctl_zone *zone = data;
u32 val;
- val = (readl(zone->reg) >> zone->shift) & SENSOR_TEMP_MASK;
+ val = readl(zone->reg);
+ val = REG_GET_MASK(val, zone->mask);
*out_temp = translate_temp(val);
return 0;
@@ -327,18 +428,6 @@ static const struct of_device_id tegra_soctherm_of_match[] = {
};
MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
-struct thermctl_zone_desc {
- unsigned int offset;
- unsigned int shift;
-};
-
-static const struct thermctl_zone_desc t124_thermctl_temp_zones[] = {
- { SENSOR_TEMP1, 16 },
- { SENSOR_TEMP2, 16 },
- { SENSOR_TEMP1, 0 },
- { SENSOR_TEMP2, 0 }
-};
-
static int tegra_soctherm_probe(struct platform_device *pdev)
{
struct tegra_soctherm *tegra;
@@ -349,6 +438,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
int err;
const struct tegra_tsensor *tsensors = t124_tsensors;
+ const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
if (!tegra)
@@ -408,7 +498,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
/* Initialize thermctl sensors */
- for (i = 0; i < ZONE_NUMBER; ++i) {
+ for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
struct tegra_thermctl_zone *zone =
devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
if (!zone) {
@@ -416,10 +506,11 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
goto disable_clocks;
}
- zone->reg = tegra->regs + t124_thermctl_temp_zones[i].offset;
- zone->shift = t124_thermctl_temp_zones[i].shift;
+ zone->reg = tegra->regs + ttgs[i]->sensor_temp_offset;
+ zone->mask = ttgs[i]->sensor_temp_mask;
- z = devm_thermal_zone_of_sensor_register(&pdev->dev, i, zone,
+ z = devm_thermal_zone_of_sensor_register(&pdev->dev,
+ ttgs[i]->id, zone,
&tegra_of_thermal_ops);
if (IS_ERR(z)) {
err = PTR_ERR(z);
diff --git a/include/dt-bindings/thermal/tegra124-soctherm.h b/include/dt-bindings/thermal/tegra124-soctherm.h
index 85aaf66690f9..729ab9fc325e 100644
--- a/include/dt-bindings/thermal/tegra124-soctherm.h
+++ b/include/dt-bindings/thermal/tegra124-soctherm.h
@@ -9,5 +9,6 @@
#define TEGRA124_SOCTHERM_SENSOR_MEM 1
#define TEGRA124_SOCTHERM_SENSOR_GPU 2
#define TEGRA124_SOCTHERM_SENSOR_PLLX 3
+#define TEGRA124_SOCTHERM_SENSOR_NUM 4
#endif
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH V7 03/12] thermal: tegra: get rid of PDIV/HOTSPOT hack
2016-03-11 3:09 ` Wei Ni
@ 2016-03-11 3:09 ` Wei Ni
-1 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-11 3:09 UTC (permalink / raw)
To: rui.zhang, edubezval, thierry.reding
Cc: MLongnecker, swarren, mikko.perttunen, linux-tegra, linux-pm,
linux-kernel, Wei Ni
Get rid of T124-specific PDIV/HOTSPOT hack.
tegra-soctherm.c contained a hack to set the SENSOR_PDIV and
SENSOR_HOTSPOT_OFFSET registers - it just did two writes of
T124-specific opaque values. Convert these into a form that can be
substituted on a per-chip basis, and into structure fields that have
at least some independent meaning.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
drivers/thermal/tegra/tegra-soctherm.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
index b3ec0faa2bee..b4b791ebfbb6 100644
--- a/drivers/thermal/tegra/tegra-soctherm.c
+++ b/drivers/thermal/tegra/tegra-soctherm.c
@@ -48,14 +48,12 @@
#define SENSOR_CONFIG2_THERMB_SHIFT 0
#define SENSOR_PDIV 0x1c0
-#define SENSOR_PDIV_T124 0x8888
#define SENSOR_PDIV_CPU_MASK (0xf << 12)
#define SENSOR_PDIV_GPU_MASK (0xf << 8)
#define SENSOR_PDIV_MEM_MASK (0xf << 4)
#define SENSOR_PDIV_PLLX_MASK (0xf << 0)
#define SENSOR_HOTSPOT_OFF 0x1c4
-#define SENSOR_HOTSPOT_OFF_T124 0x00060600
#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
@@ -436,6 +434,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
struct resource *res;
unsigned int i;
int err;
+ u32 pdiv, hotspot;
const struct tegra_tsensor *tsensors = t124_tsensors;
const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
@@ -493,8 +492,19 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
goto disable_clocks;
}
- writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
- writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
+ /* Program pdiv and hotspot offsets per THERM */
+ pdiv = readl(tegra->regs + SENSOR_PDIV);
+ hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
+ for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
+ pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
+ ttgs[i]->pdiv);
+ if (ttgs[i]->id != TEGRA124_SOCTHERM_SENSOR_PLLX)
+ hotspot = REG_SET_MASK(hotspot,
+ ttgs[i]->pllx_hotspot_mask,
+ ttgs[i]->pllx_hotspot_diff);
+ }
+ writel(pdiv, tegra->regs + SENSOR_PDIV);
+ writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
/* Initialize thermctl sensors */
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH V7 03/12] thermal: tegra: get rid of PDIV/HOTSPOT hack
@ 2016-03-11 3:09 ` Wei Ni
0 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-11 3:09 UTC (permalink / raw)
To: rui.zhang, edubezval, thierry.reding
Cc: MLongnecker, swarren, mikko.perttunen, linux-tegra, linux-pm,
linux-kernel, Wei Ni
Get rid of T124-specific PDIV/HOTSPOT hack.
tegra-soctherm.c contained a hack to set the SENSOR_PDIV and
SENSOR_HOTSPOT_OFFSET registers - it just did two writes of
T124-specific opaque values. Convert these into a form that can be
substituted on a per-chip basis, and into structure fields that have
at least some independent meaning.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
drivers/thermal/tegra/tegra-soctherm.c | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
index b3ec0faa2bee..b4b791ebfbb6 100644
--- a/drivers/thermal/tegra/tegra-soctherm.c
+++ b/drivers/thermal/tegra/tegra-soctherm.c
@@ -48,14 +48,12 @@
#define SENSOR_CONFIG2_THERMB_SHIFT 0
#define SENSOR_PDIV 0x1c0
-#define SENSOR_PDIV_T124 0x8888
#define SENSOR_PDIV_CPU_MASK (0xf << 12)
#define SENSOR_PDIV_GPU_MASK (0xf << 8)
#define SENSOR_PDIV_MEM_MASK (0xf << 4)
#define SENSOR_PDIV_PLLX_MASK (0xf << 0)
#define SENSOR_HOTSPOT_OFF 0x1c4
-#define SENSOR_HOTSPOT_OFF_T124 0x00060600
#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
@@ -436,6 +434,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
struct resource *res;
unsigned int i;
int err;
+ u32 pdiv, hotspot;
const struct tegra_tsensor *tsensors = t124_tsensors;
const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
@@ -493,8 +492,19 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
goto disable_clocks;
}
- writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
- writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
+ /* Program pdiv and hotspot offsets per THERM */
+ pdiv = readl(tegra->regs + SENSOR_PDIV);
+ hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
+ for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
+ pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
+ ttgs[i]->pdiv);
+ if (ttgs[i]->id != TEGRA124_SOCTHERM_SENSOR_PLLX)
+ hotspot = REG_SET_MASK(hotspot,
+ ttgs[i]->pllx_hotspot_mask,
+ ttgs[i]->pllx_hotspot_diff);
+ }
+ writel(pdiv, tegra->regs + SENSOR_PDIV);
+ writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
/* Initialize thermctl sensors */
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH V7 04/12] thermal: tegra: split tegra_soctherm driver
2016-03-11 3:09 ` Wei Ni
@ 2016-03-11 3:09 ` Wei Ni
-1 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-11 3:09 UTC (permalink / raw)
To: rui.zhang-ral2JQCrhuEAvxtiuMwx3w,
edubezval-Re5JQEeQqe8AvxtiuMwx3w,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w
Cc: MLongnecker-DDmLM1+adcrQT0dZR+AlfA,
swarren-3lzwWm7+Weoh9ZMKESR00Q, mikko.perttunen-/1wQRMveznE,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Wei Ni
Split most of the Tegra124 data and code into a Tegra124-specific
file.
Split most of the fuse-related code into a fuse-related source file.
This is in preparation for adding a Tegra210-specific driver in a
future patch.
Beyond the maintainability improvements, this is intended to separate
chip-specific ATE and characterization-related hacks into chip-specific
files, in the hopes that they won't pollute code for other chips.
Signed-off-by: Wei Ni <wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
drivers/thermal/tegra/Kconfig | 2 +-
drivers/thermal/tegra/Makefile | 3 +
drivers/thermal/tegra/soctherm-fuse.c | 158 +++++++++
drivers/thermal/tegra/soctherm.c | 307 ++++++++++++++++
drivers/thermal/tegra/soctherm.h | 110 ++++++
drivers/thermal/tegra/tegra-soctherm.c | 564 ------------------------------
drivers/thermal/tegra/tegra124-soctherm.c | 172 +++++++++
7 files changed, 751 insertions(+), 565 deletions(-)
create mode 100644 drivers/thermal/tegra/soctherm-fuse.c
create mode 100644 drivers/thermal/tegra/soctherm.c
create mode 100644 drivers/thermal/tegra/soctherm.h
delete mode 100644 drivers/thermal/tegra/tegra-soctherm.c
create mode 100644 drivers/thermal/tegra/tegra124-soctherm.c
diff --git a/drivers/thermal/tegra/Kconfig b/drivers/thermal/tegra/Kconfig
index 0b719d8b629b..fc8a6769b70d 100644
--- a/drivers/thermal/tegra/Kconfig
+++ b/drivers/thermal/tegra/Kconfig
@@ -5,7 +5,7 @@ config TEGRA_SOCTHERM
depends on ARCH_TEGRA
help
Enable this option for integrated thermal management support on NVIDIA
- Tegra124 systems-on-chip. The driver supports four thermal zones
+ Tegra systems-on-chip. The driver supports four thermal zones
(CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
zones to manage temperatures. This option is also required for the
emergency thermal reset (thermtrip) feature to function.
diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile
index d4dc4e7f279e..d5fb15377b97 100644
--- a/drivers/thermal/tegra/Makefile
+++ b/drivers/thermal/tegra/Makefile
@@ -1 +1,4 @@
obj-$(CONFIG_TEGRA_SOCTHERM) += tegra-soctherm.o
+
+tegra-soctherm-y := soctherm.o soctherm-fuse.o
+tegra-soctherm-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124-soctherm.o
diff --git a/drivers/thermal/tegra/soctherm-fuse.c b/drivers/thermal/tegra/soctherm-fuse.c
new file mode 100644
index 000000000000..931c299ab0e8
--- /dev/null
+++ b/drivers/thermal/tegra/soctherm-fuse.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <soc/tegra/fuse.h>
+
+#include "soctherm.h"
+
+#define NOMINAL_CALIB_FT 105
+#define NOMINAL_CALIB_CP 25
+
+#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
+#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13)
+#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13
+
+#define FUSE_TSENSOR_COMMON 0x180
+
+/*
+ * Tegra12x, etc:
+ * FUSE_TSENSOR_COMMON:
+ * 3 2 1 0
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |-----------| SHFT_FT | BASE_FT | BASE_CP |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *
+ * FUSE_SPARE_REALIGNMENT_REG:
+ * 3 2 1 0
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |---------------------------------------------------| SHIFT_CP |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define CALIB_COEFFICIENT 1000000LL
+
+/**
+ * div64_s64_precise() - wrapper for div64_s64()
+ * @a: the dividend
+ * @b: the divisor
+ *
+ * Implements division with fairly accurate rounding instead of truncation by
+ * shifting the dividend to the left by 16 so that the quotient has a
+ * much higher precision.
+ *
+ * Return: the quotient of a / b.
+ */
+static s64 div64_s64_precise(s64 a, s32 b)
+{
+ s64 r, al;
+
+ /* Scale up for increased precision division */
+ al = a << 16;
+
+ r = div64_s64(al * 2 + 1, 2 * b);
+ return r >> 16;
+}
+
+int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
+ struct tsensor_shared_calib *shared)
+{
+ u32 val;
+ s32 shifted_cp, shifted_ft;
+ int err;
+
+ err = tegra_fuse_readl(FUSE_TSENSOR_COMMON, &val);
+ if (err)
+ return err;
+
+ shared->base_cp = (val & tfuse->fuse_base_cp_mask) >>
+ tfuse->fuse_base_cp_shift;
+ shared->base_ft = (val & tfuse->fuse_base_ft_mask) >>
+ tfuse->fuse_base_ft_shift;
+
+ shifted_ft = (val & tfuse->fuse_shift_ft_mask) >>
+ tfuse->fuse_shift_ft_shift;
+ shifted_ft = sign_extend32(shifted_ft, 4);
+
+ if (tfuse->fuse_spare_realignment) {
+ err = tegra_fuse_readl(tfuse->fuse_spare_realignment, &val);
+ if (err)
+ return err;
+ }
+
+ shifted_cp = sign_extend32(val, 5);
+
+ shared->actual_temp_cp = 2 * NOMINAL_CALIB_CP + shifted_cp;
+ shared->actual_temp_ft = 2 * NOMINAL_CALIB_FT + shifted_ft;
+
+ return 0;
+}
+
+int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
+ const struct tsensor_shared_calib *shared,
+ u32 *calibration)
+{
+ const struct tegra_tsensor_group *sensor_group;
+ u32 val, calib;
+ s32 actual_tsensor_ft, actual_tsensor_cp;
+ s32 delta_sens, delta_temp;
+ s32 mult, div;
+ s16 therma, thermb;
+ s64 temp;
+ int err;
+
+ sensor_group = sensor->group;
+
+ err = tegra_fuse_readl(sensor->calib_fuse_offset, &val);
+ if (err)
+ return err;
+
+ actual_tsensor_cp = (shared->base_cp * 64) + sign_extend32(val, 12);
+ val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK) >>
+ FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT;
+ actual_tsensor_ft = (shared->base_ft * 32) + sign_extend32(val, 12);
+
+ delta_sens = actual_tsensor_ft - actual_tsensor_cp;
+ delta_temp = shared->actual_temp_ft - shared->actual_temp_cp;
+
+ mult = sensor_group->pdiv * sensor->config->tsample_ate;
+ div = sensor->config->tsample * sensor_group->pdiv_ate;
+
+ temp = (s64)delta_temp * (1LL << 13) * mult;
+ therma = div64_s64_precise(temp, (s64)delta_sens * div);
+
+ temp = ((s64)actual_tsensor_ft * shared->actual_temp_cp) -
+ ((s64)actual_tsensor_cp * shared->actual_temp_ft);
+ thermb = div64_s64_precise(temp, delta_sens);
+
+ temp = (s64)therma * sensor->fuse_corr_alpha;
+ therma = div64_s64_precise(temp, CALIB_COEFFICIENT);
+
+ temp = (s64)thermb * sensor->fuse_corr_alpha + sensor->fuse_corr_beta;
+ thermb = div64_s64_precise(temp, CALIB_COEFFICIENT);
+
+ calib = ((u16)therma << SENSOR_CONFIG2_THERMA_SHIFT) |
+ ((u16)thermb << SENSOR_CONFIG2_THERMB_SHIFT);
+
+ *calibration = calib;
+
+ return 0;
+}
+
+MODULE_AUTHOR("Wei Ni <wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>");
+MODULE_DESCRIPTION("Tegra SOCTHERM fuse management");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
new file mode 100644
index 000000000000..f56e5a11384e
--- /dev/null
+++ b/drivers/thermal/tegra/soctherm.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author:
+ * Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/thermal.h>
+
+#include <dt-bindings/thermal/tegra124-soctherm.h>
+
+#include "soctherm.h"
+
+#define SENSOR_CONFIG0 0
+#define SENSOR_CONFIG0_STOP BIT(0)
+#define SENSOR_CONFIG0_TALL_SHIFT 8
+#define SENSOR_CONFIG0_TCALC_OVER BIT(4)
+#define SENSOR_CONFIG0_OVER BIT(3)
+#define SENSOR_CONFIG0_CPTR_OVER BIT(2)
+
+#define SENSOR_CONFIG1 4
+#define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
+#define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
+#define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
+#define SENSOR_CONFIG1_TEMP_ENABLE BIT(31)
+
+/*
+ * SENSOR_CONFIG2 is defined in soctherm.h
+ * because, it will be used by tegra_soctherm_fuse.c
+ */
+
+#define READBACK_VALUE_MASK 0xff00
+#define READBACK_VALUE_SHIFT 8
+#define READBACK_ADD_HALF BIT(7)
+#define READBACK_NEGATE BIT(1)
+
+/* get val from register(r) mask bits(m) */
+#define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
+/* set val(v) to mask bits(m) of register(r) */
+#define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
+ (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
+
+struct tegra_thermctl_zone {
+ void __iomem *reg;
+ u32 mask;
+};
+
+struct tegra_soctherm {
+ struct reset_control *reset;
+ struct clk *clock_tsensor;
+ struct clk *clock_soctherm;
+ void __iomem *regs;
+
+ u32 *calib;
+ struct tegra_soctherm_soc *soc;
+};
+
+static int enable_tsensor(struct tegra_soctherm *tegra,
+ unsigned int i,
+ const struct tsensor_shared_calib *shared)
+{
+ const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i];
+ void __iomem *base = tegra->regs + sensor->base;
+ u32 *calib = &tegra->calib[i];
+ unsigned int val;
+ int err;
+
+ err = tegra_calc_tsensor_calib(sensor, shared, calib);
+ if (err)
+ return err;
+
+ val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
+ writel(val, base + SENSOR_CONFIG0);
+
+ val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
+ val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
+ val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
+ val |= SENSOR_CONFIG1_TEMP_ENABLE;
+ writel(val, base + SENSOR_CONFIG1);
+
+ writel(*calib, base + SENSOR_CONFIG2);
+
+ return 0;
+}
+
+/*
+ * Translate from soctherm readback format to millicelsius.
+ * The soctherm readback format in bits is as follows:
+ * TTTTTTTT H______N
+ * where T's contain the temperature in Celsius,
+ * H denotes an addition of 0.5 Celsius and N denotes negation
+ * of the final value.
+ */
+static int translate_temp(u16 val)
+{
+ int t;
+
+ t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
+ if (val & READBACK_ADD_HALF)
+ t += 500;
+ if (val & READBACK_NEGATE)
+ t *= -1;
+
+ return t;
+}
+
+static int tegra_thermctl_get_temp(void *data, int *out_temp)
+{
+ struct tegra_thermctl_zone *zone = data;
+ u32 val;
+
+ val = readl(zone->reg);
+ val = REG_GET_MASK(val, zone->mask);
+ *out_temp = translate_temp(val);
+
+ return 0;
+}
+
+static const struct thermal_zone_of_device_ops tegra_of_thermal_ops = {
+ .get_temp = tegra_thermctl_get_temp,
+};
+
+static const struct of_device_id tegra_soctherm_of_match[] = {
+#ifdef CONFIG_ARCH_TEGRA_124_SOC
+ {
+ .compatible = "nvidia,tegra124-soctherm",
+ .data = &tegra124_soctherm,
+ },
+#endif
+ { },
+};
+MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
+
+static int tegra_soctherm_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ struct tegra_soctherm *tegra;
+ struct thermal_zone_device *z;
+ struct tsensor_shared_calib shared_calib;
+ struct resource *res;
+ struct tegra_soctherm_soc *soc;
+ unsigned int i;
+ int err;
+ u32 pdiv, hotspot;
+
+ match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node);
+ if (!match)
+ return -ENODEV;
+
+ soc = (struct tegra_soctherm_soc *)match->data;
+ if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM)
+ return -EINVAL;
+
+ tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
+ if (!tegra)
+ return -ENOMEM;
+
+ dev_set_drvdata(&pdev->dev, tegra);
+
+ tegra->soc = soc;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ tegra->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(tegra->regs))
+ return PTR_ERR(tegra->regs);
+
+ tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
+ if (IS_ERR(tegra->reset)) {
+ dev_err(&pdev->dev, "can't get soctherm reset\n");
+ return PTR_ERR(tegra->reset);
+ }
+
+ tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
+ if (IS_ERR(tegra->clock_tsensor)) {
+ dev_err(&pdev->dev, "can't get tsensor clock\n");
+ return PTR_ERR(tegra->clock_tsensor);
+ }
+
+ tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
+ if (IS_ERR(tegra->clock_soctherm)) {
+ dev_err(&pdev->dev, "can't get soctherm clock\n");
+ return PTR_ERR(tegra->clock_soctherm);
+ }
+
+ reset_control_assert(tegra->reset);
+
+ err = clk_prepare_enable(tegra->clock_soctherm);
+ if (err)
+ return err;
+
+ err = clk_prepare_enable(tegra->clock_tsensor);
+ if (err) {
+ clk_disable_unprepare(tegra->clock_soctherm);
+ return err;
+ }
+
+ reset_control_deassert(tegra->reset);
+
+ /* Initialize raw sensors */
+
+ tegra->calib = devm_kzalloc(&pdev->dev,
+ sizeof(u32) * soc->num_tsensors,
+ GFP_KERNEL);
+ if (!tegra->calib)
+ return -ENOMEM;
+
+ err = tegra_calc_shared_calib(soc->tfuse, &shared_calib);
+ if (err)
+ goto disable_clocks;
+
+ for (i = 0; i < soc->num_tsensors; ++i) {
+ err = enable_tsensor(tegra, i, &shared_calib);
+ if (err)
+ goto disable_clocks;
+ }
+
+ /* Program pdiv and hotspot offsets per THERM */
+ pdiv = readl(tegra->regs + SENSOR_PDIV);
+ hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
+ for (i = 0; i < soc->num_ttgs; ++i) {
+ pdiv = REG_SET_MASK(pdiv, soc->ttgs[i]->pdiv_mask,
+ soc->ttgs[i]->pdiv);
+ if (soc->ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX)
+ continue;
+ hotspot = REG_SET_MASK(hotspot,
+ soc->ttgs[i]->pllx_hotspot_mask,
+ soc->ttgs[i]->pllx_hotspot_diff);
+ }
+ writel(pdiv, tegra->regs + SENSOR_PDIV);
+ writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
+
+ /* Initialize thermctl sensors */
+
+ for (i = 0; i < soc->num_ttgs; ++i) {
+ struct tegra_thermctl_zone *zone =
+ devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
+ if (!zone) {
+ err = -ENOMEM;
+ goto disable_clocks;
+ }
+
+ zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset;
+ zone->mask = soc->ttgs[i]->sensor_temp_mask;
+
+ z = devm_thermal_zone_of_sensor_register(&pdev->dev,
+ soc->ttgs[i]->id, zone,
+ &tegra_of_thermal_ops);
+ if (IS_ERR(z)) {
+ err = PTR_ERR(z);
+ dev_err(&pdev->dev, "failed to register sensor: %d\n",
+ err);
+ goto disable_clocks;
+ }
+ }
+
+ return 0;
+
+disable_clocks:
+ clk_disable_unprepare(tegra->clock_tsensor);
+ clk_disable_unprepare(tegra->clock_soctherm);
+
+ return err;
+}
+
+static int tegra_soctherm_remove(struct platform_device *pdev)
+{
+ struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(tegra->clock_tsensor);
+ clk_disable_unprepare(tegra->clock_soctherm);
+
+ return 0;
+}
+
+static struct platform_driver tegra_soctherm_driver = {
+ .probe = tegra_soctherm_probe,
+ .remove = tegra_soctherm_remove,
+ .driver = {
+ .name = "tegra_soctherm",
+ .of_match_table = tegra_soctherm_of_match,
+ },
+};
+module_platform_driver(tegra_soctherm_driver);
+
+MODULE_AUTHOR("Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>");
+MODULE_DESCRIPTION("NVIDIA Tegra SOCTHERM thermal management driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/soctherm.h
new file mode 100644
index 000000000000..f80ee1492ddb
--- /dev/null
+++ b/drivers/thermal/tegra/soctherm.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __DRIVERS_THERMAL_TEGRA_SOCTHERM_H
+#define __DRIVERS_THERMAL_TEGRA_SOCTHERM_H
+
+#define SENSOR_CONFIG2 8
+#define SENSOR_CONFIG2_THERMA_SHIFT 16
+#define SENSOR_CONFIG2_THERMB_SHIFT 0
+
+#define SENSOR_PDIV 0x1c0
+#define SENSOR_PDIV_CPU_MASK (0xf << 12)
+#define SENSOR_PDIV_GPU_MASK (0xf << 8)
+#define SENSOR_PDIV_MEM_MASK (0xf << 4)
+#define SENSOR_PDIV_PLLX_MASK (0xf << 0)
+
+#define SENSOR_HOTSPOT_OFF 0x1c4
+#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
+#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
+#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
+
+#define SENSOR_TEMP1 0x1c8
+#define SENSOR_TEMP1_CPU_TEMP_MASK (0xffff << 16)
+#define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff
+#define SENSOR_TEMP2 0x1cc
+#define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16)
+#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
+
+/**
+ * struct tegra_tsensor_group - SOC_THERM sensor group data
+ * @name: short name of the temperature sensor group
+ * @id: numeric ID of the temperature sensor group
+ * @sensor_temp_offset: offset of the SENSOR_TEMP* register
+ * @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register
+ * @pdiv: the sensor count post-divider to use during runtime
+ * @pdiv_ate: the sensor count post-divider used during automated test
+ * @pdiv_mask: register bitfield mask for the PDIV field for this sensor
+ * @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for
+ PLLX sensor group
+ * @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field
+ */
+struct tegra_tsensor_group {
+ const char *name;
+ u8 id;
+ u16 sensor_temp_offset;
+ u32 sensor_temp_mask;
+ u32 pdiv, pdiv_ate, pdiv_mask;
+ u32 pllx_hotspot_diff, pllx_hotspot_mask;
+};
+
+struct tegra_tsensor_configuration {
+ u32 tall, tiddq_en, ten_count, pdiv, pdiv_ate, tsample, tsample_ate;
+};
+
+struct tegra_tsensor {
+ const char *name;
+ const u32 base;
+ const struct tegra_tsensor_configuration *config;
+ const u32 calib_fuse_offset;
+ /*
+ * Correction values used to modify values read from
+ * calibration fuses
+ */
+ const s32 fuse_corr_alpha, fuse_corr_beta;
+ const struct tegra_tsensor_group *group;
+};
+
+struct tegra_soctherm_fuse {
+ u32 fuse_base_cp_mask, fuse_base_cp_shift;
+ u32 fuse_base_ft_mask, fuse_base_ft_shift;
+ u32 fuse_shift_ft_mask, fuse_shift_ft_shift;
+ u32 fuse_spare_realignment;
+};
+
+struct tsensor_shared_calib {
+ u32 base_cp, base_ft;
+ u32 actual_temp_cp, actual_temp_ft;
+};
+
+struct tegra_soctherm_soc {
+ const struct tegra_tsensor *tsensors;
+ const unsigned int num_tsensors;
+ const struct tegra_tsensor_group **ttgs;
+ const unsigned int num_ttgs;
+ const struct tegra_soctherm_fuse *tfuse;
+};
+
+int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
+ struct tsensor_shared_calib *shared);
+int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
+ const struct tsensor_shared_calib *shared,
+ u32 *calib);
+
+#ifdef CONFIG_ARCH_TEGRA_124_SOC
+extern const struct tegra_soctherm_soc tegra124_soctherm;
+#endif
+
+#endif
+
diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
deleted file mode 100644
index b4b791ebfbb6..000000000000
--- a/drivers/thermal/tegra/tegra-soctherm.c
+++ /dev/null
@@ -1,564 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Author:
- * Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/bitops.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/reset.h>
-#include <linux/thermal.h>
-
-#include <soc/tegra/fuse.h>
-#include <dt-bindings/thermal/tegra124-soctherm.h>
-
-#define SENSOR_CONFIG0 0
-#define SENSOR_CONFIG0_STOP BIT(0)
-#define SENSOR_CONFIG0_TALL_SHIFT 8
-#define SENSOR_CONFIG0_TCALC_OVER BIT(4)
-#define SENSOR_CONFIG0_OVER BIT(3)
-#define SENSOR_CONFIG0_CPTR_OVER BIT(2)
-
-#define SENSOR_CONFIG1 4
-#define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
-#define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
-#define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
-#define SENSOR_CONFIG1_TEMP_ENABLE BIT(31)
-
-#define SENSOR_CONFIG2 8
-#define SENSOR_CONFIG2_THERMA_SHIFT 16
-#define SENSOR_CONFIG2_THERMB_SHIFT 0
-
-#define SENSOR_PDIV 0x1c0
-#define SENSOR_PDIV_CPU_MASK (0xf << 12)
-#define SENSOR_PDIV_GPU_MASK (0xf << 8)
-#define SENSOR_PDIV_MEM_MASK (0xf << 4)
-#define SENSOR_PDIV_PLLX_MASK (0xf << 0)
-
-#define SENSOR_HOTSPOT_OFF 0x1c4
-#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
-#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
-#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
-
-#define SENSOR_TEMP1 0x1c8
-#define SENSOR_TEMP1_CPU_TEMP_MASK (0xffff << 16)
-#define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff
-#define SENSOR_TEMP2 0x1cc
-#define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16)
-#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
-
-#define READBACK_VALUE_MASK 0xff00
-#define READBACK_VALUE_SHIFT 8
-#define READBACK_ADD_HALF BIT(7)
-#define READBACK_NEGATE BIT(1)
-
-#define FUSE_TSENSOR8_CALIB 0x180
-#define FUSE_SPARE_REALIGNMENT_REG_0 0x1fc
-
-#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
-#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13)
-#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13
-
-#define FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK 0x3ff
-#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK (0x7ff << 10)
-#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT 10
-
-#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP_MASK 0x3f
-#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK (0x1f << 21)
-#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT 21
-
-#define NOMINAL_CALIB_FT_T124 105
-#define NOMINAL_CALIB_CP_T124 25
-
-/* get val from register(r) mask bits(m) */
-#define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
-/* set val(v) to mask bits(m) of register(r) */
-#define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
- (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
-
-/**
- * struct tegra_tsensor_group - SOC_THERM sensor group data
- * @name: short name of the temperature sensor group
- * @id: numeric ID of the temperature sensor group
- * @sensor_temp_offset: offset of the SENSOR_TEMP* register
- * @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register
- * @pdiv: the sensor count post-divider to use during runtime
- * @pdiv_ate: the sensor count post-divider used during automated test
- * @pdiv_mask: register bitfield mask for the PDIV field for this sensor
- * @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for
- PLLX sensor group
- * @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field
- */
-struct tegra_tsensor_group {
- const char *name;
- u8 id;
- u16 sensor_temp_offset;
- u32 sensor_temp_mask;
- u32 pdiv, pdiv_ate, pdiv_mask;
- u32 pllx_hotspot_diff, pllx_hotspot_mask;
-};
-
-struct tegra_tsensor_configuration {
- u32 tall, tiddq_en, ten_count, tsample, tsample_ate;
-};
-
-struct tegra_tsensor {
- const struct tegra_tsensor_configuration *config;
- u32 base, calib_fuse_offset;
- /* Correction values used to modify values read from calibration fuses */
- s32 fuse_corr_alpha, fuse_corr_beta;
- const struct tegra_tsensor_group *group;
-};
-
-struct tegra_thermctl_zone {
- void __iomem *reg;
- u32 mask;
-};
-
-static const struct tegra_tsensor_configuration t124_tsensor_config = {
- .tall = 16300,
- .tiddq_en = 1,
- .ten_count = 1,
- .tsample = 120,
- .tsample_ate = 480,
-};
-
-static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = {
- .id = TEGRA124_SOCTHERM_SENSOR_CPU,
- .name = "cpu",
- .sensor_temp_offset = SENSOR_TEMP1,
- .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
- .pdiv = 8,
- .pdiv_ate = 8,
- .pdiv_mask = SENSOR_PDIV_CPU_MASK,
- .pllx_hotspot_diff = 10,
- .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
-};
-
-static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
- .id = TEGRA124_SOCTHERM_SENSOR_GPU,
- .name = "gpu",
- .sensor_temp_offset = SENSOR_TEMP1,
- .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
- .pdiv = 8,
- .pdiv_ate = 8,
- .pdiv_mask = SENSOR_PDIV_GPU_MASK,
- .pllx_hotspot_diff = 5,
- .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
-};
-
-static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
- .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
- .name = "pll",
- .sensor_temp_offset = SENSOR_TEMP2,
- .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
- .pdiv = 8,
- .pdiv_ate = 8,
- .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
- .pllx_hotspot_diff = 0,
- .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
-};
-
-static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
- .id = TEGRA124_SOCTHERM_SENSOR_MEM,
- .name = "mem",
- .sensor_temp_offset = SENSOR_TEMP2,
- .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
- .pdiv = 8,
- .pdiv_ate = 8,
- .pdiv_mask = SENSOR_PDIV_MEM_MASK,
-};
-
-static const struct tegra_tsensor_group *
-tegra124_tsensor_groups[TEGRA124_SOCTHERM_SENSOR_NUM] = {
- &tegra124_tsensor_group_cpu,
- &tegra124_tsensor_group_gpu,
- &tegra124_tsensor_group_pll,
- &tegra124_tsensor_group_mem,
-};
-
-static const struct tegra_tsensor t124_tsensors[] = {
- {
- .config = &t124_tsensor_config,
- .base = 0xc0,
- .calib_fuse_offset = 0x098,
- .fuse_corr_alpha = 1135400,
- .fuse_corr_beta = -6266900,
- .group = &tegra124_tsensor_group_cpu,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0xe0,
- .calib_fuse_offset = 0x084,
- .fuse_corr_alpha = 1122220,
- .fuse_corr_beta = -5700700,
- .group = &tegra124_tsensor_group_cpu,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0x100,
- .calib_fuse_offset = 0x088,
- .fuse_corr_alpha = 1127000,
- .fuse_corr_beta = -6768200,
- .group = &tegra124_tsensor_group_cpu,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0x120,
- .calib_fuse_offset = 0x12c,
- .fuse_corr_alpha = 1110900,
- .fuse_corr_beta = -6232000,
- .group = &tegra124_tsensor_group_cpu,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0x140,
- .calib_fuse_offset = 0x158,
- .fuse_corr_alpha = 1122300,
- .fuse_corr_beta = -5936400,
- .group = &tegra124_tsensor_group_mem,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0x160,
- .calib_fuse_offset = 0x15c,
- .fuse_corr_alpha = 1145700,
- .fuse_corr_beta = -7124600,
- .group = &tegra124_tsensor_group_mem,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0x180,
- .calib_fuse_offset = 0x154,
- .fuse_corr_alpha = 1120100,
- .fuse_corr_beta = -6000500,
- .group = &tegra124_tsensor_group_gpu,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0x1a0,
- .calib_fuse_offset = 0x160,
- .fuse_corr_alpha = 1106500,
- .fuse_corr_beta = -6729300,
- .group = &tegra124_tsensor_group_pll,
- },
-};
-
-struct tegra_soctherm {
- struct reset_control *reset;
- struct clk *clock_tsensor;
- struct clk *clock_soctherm;
- void __iomem *regs;
-};
-
-struct tsensor_shared_calibration {
- u32 base_cp, base_ft;
- u32 actual_temp_cp, actual_temp_ft;
-};
-
-static int calculate_shared_calibration(struct tsensor_shared_calibration *r)
-{
- u32 val, shifted_cp, shifted_ft;
- int err;
-
- err = tegra_fuse_readl(FUSE_TSENSOR8_CALIB, &val);
- if (err)
- return err;
- r->base_cp = val & FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK;
- r->base_ft = (val & FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK)
- >> FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT;
- val = ((val & FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK)
- >> FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT);
- shifted_ft = sign_extend32(val, 4);
-
- err = tegra_fuse_readl(FUSE_SPARE_REALIGNMENT_REG_0, &val);
- if (err)
- return err;
- shifted_cp = sign_extend32(val, 5);
-
- r->actual_temp_cp = 2 * NOMINAL_CALIB_CP_T124 + shifted_cp;
- r->actual_temp_ft = 2 * NOMINAL_CALIB_FT_T124 + shifted_ft;
-
- return 0;
-}
-
-static s64 div64_s64_precise(s64 a, s64 b)
-{
- s64 r, al;
-
- /* Scale up for increased precision division */
- al = a << 16;
-
- r = div64_s64(al * 2 + 1, 2 * b);
- return r >> 16;
-}
-
-static int
-calculate_tsensor_calibration(const struct tegra_tsensor *sensor,
- const struct tsensor_shared_calibration *shared,
- u32 *calib)
-{
- u32 val;
- s32 actual_tsensor_ft, actual_tsensor_cp, delta_sens, delta_temp,
- mult, div;
- s16 therma, thermb;
- s64 tmp;
- int err;
-
- err = tegra_fuse_readl(sensor->calib_fuse_offset, &val);
- if (err)
- return err;
-
- actual_tsensor_cp = (shared->base_cp * 64) + sign_extend32(val, 12);
- val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK)
- >> FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT;
- actual_tsensor_ft = (shared->base_ft * 32) + sign_extend32(val, 12);
-
- delta_sens = actual_tsensor_ft - actual_tsensor_cp;
- delta_temp = shared->actual_temp_ft - shared->actual_temp_cp;
-
- mult = sensor->group->pdiv * sensor->config->tsample_ate;
- div = sensor->config->tsample * sensor->group->pdiv_ate;
-
- therma = div64_s64_precise((s64) delta_temp * (1LL << 13) * mult,
- (s64) delta_sens * div);
-
- tmp = (s64)actual_tsensor_ft * shared->actual_temp_cp -
- (s64)actual_tsensor_cp * shared->actual_temp_ft;
- thermb = div64_s64_precise(tmp, (s64)delta_sens);
-
- therma = div64_s64_precise((s64)therma * sensor->fuse_corr_alpha,
- (s64)1000000LL);
- thermb = div64_s64_precise((s64)thermb * sensor->fuse_corr_alpha +
- sensor->fuse_corr_beta, (s64)1000000LL);
-
- *calib = ((u16)therma << SENSOR_CONFIG2_THERMA_SHIFT) |
- ((u16)thermb << SENSOR_CONFIG2_THERMB_SHIFT);
-
- return 0;
-}
-
-static int enable_tsensor(struct tegra_soctherm *tegra,
- const struct tegra_tsensor *sensor,
- const struct tsensor_shared_calibration *shared)
-{
- void __iomem *base = tegra->regs + sensor->base;
- unsigned int val;
- u32 calib;
- int err;
-
- err = calculate_tsensor_calibration(sensor, shared, &calib);
- if (err)
- return err;
-
- val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
- writel(val, base + SENSOR_CONFIG0);
-
- val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
- val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
- val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
- val |= SENSOR_CONFIG1_TEMP_ENABLE;
- writel(val, base + SENSOR_CONFIG1);
-
- writel(calib, base + SENSOR_CONFIG2);
-
- return 0;
-}
-
-/*
- * Translate from soctherm readback format to millicelsius.
- * The soctherm readback format in bits is as follows:
- * TTTTTTTT H______N
- * where T's contain the temperature in Celsius,
- * H denotes an addition of 0.5 Celsius and N denotes negation
- * of the final value.
- */
-static int translate_temp(u16 val)
-{
- long t;
-
- t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
- if (val & READBACK_ADD_HALF)
- t += 500;
- if (val & READBACK_NEGATE)
- t *= -1;
-
- return t;
-}
-
-static int tegra_thermctl_get_temp(void *data, int *out_temp)
-{
- struct tegra_thermctl_zone *zone = data;
- u32 val;
-
- val = readl(zone->reg);
- val = REG_GET_MASK(val, zone->mask);
- *out_temp = translate_temp(val);
-
- return 0;
-}
-
-static const struct thermal_zone_of_device_ops tegra_of_thermal_ops = {
- .get_temp = tegra_thermctl_get_temp,
-};
-
-static const struct of_device_id tegra_soctherm_of_match[] = {
- { .compatible = "nvidia,tegra124-soctherm" },
- { },
-};
-MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
-
-static int tegra_soctherm_probe(struct platform_device *pdev)
-{
- struct tegra_soctherm *tegra;
- struct thermal_zone_device *z;
- struct tsensor_shared_calibration shared_calib;
- struct resource *res;
- unsigned int i;
- int err;
- u32 pdiv, hotspot;
-
- const struct tegra_tsensor *tsensors = t124_tsensors;
- const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
-
- tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
- if (!tegra)
- return -ENOMEM;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- tegra->regs = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(tegra->regs))
- return PTR_ERR(tegra->regs);
-
- tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
- if (IS_ERR(tegra->reset)) {
- dev_err(&pdev->dev, "can't get soctherm reset\n");
- return PTR_ERR(tegra->reset);
- }
-
- tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
- if (IS_ERR(tegra->clock_tsensor)) {
- dev_err(&pdev->dev, "can't get tsensor clock\n");
- return PTR_ERR(tegra->clock_tsensor);
- }
-
- tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
- if (IS_ERR(tegra->clock_soctherm)) {
- dev_err(&pdev->dev, "can't get soctherm clock\n");
- return PTR_ERR(tegra->clock_soctherm);
- }
-
- reset_control_assert(tegra->reset);
-
- err = clk_prepare_enable(tegra->clock_soctherm);
- if (err)
- return err;
-
- err = clk_prepare_enable(tegra->clock_tsensor);
- if (err) {
- clk_disable_unprepare(tegra->clock_soctherm);
- return err;
- }
-
- reset_control_deassert(tegra->reset);
-
- /* Initialize raw sensors */
-
- err = calculate_shared_calibration(&shared_calib);
- if (err)
- goto disable_clocks;
-
- for (i = 0; i < ARRAY_SIZE(t124_tsensors); ++i) {
- err = enable_tsensor(tegra, tsensors + i, &shared_calib);
- if (err)
- goto disable_clocks;
- }
-
- /* Program pdiv and hotspot offsets per THERM */
- pdiv = readl(tegra->regs + SENSOR_PDIV);
- hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
- for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
- pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
- ttgs[i]->pdiv);
- if (ttgs[i]->id != TEGRA124_SOCTHERM_SENSOR_PLLX)
- hotspot = REG_SET_MASK(hotspot,
- ttgs[i]->pllx_hotspot_mask,
- ttgs[i]->pllx_hotspot_diff);
- }
- writel(pdiv, tegra->regs + SENSOR_PDIV);
- writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
-
- /* Initialize thermctl sensors */
-
- for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
- struct tegra_thermctl_zone *zone =
- devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
- if (!zone) {
- err = -ENOMEM;
- goto disable_clocks;
- }
-
- zone->reg = tegra->regs + ttgs[i]->sensor_temp_offset;
- zone->mask = ttgs[i]->sensor_temp_mask;
-
- z = devm_thermal_zone_of_sensor_register(&pdev->dev,
- ttgs[i]->id, zone,
- &tegra_of_thermal_ops);
- if (IS_ERR(z)) {
- err = PTR_ERR(z);
- dev_err(&pdev->dev, "failed to register sensor: %d\n",
- err);
- goto disable_clocks;
- }
- }
-
- return 0;
-
-disable_clocks:
- clk_disable_unprepare(tegra->clock_tsensor);
- clk_disable_unprepare(tegra->clock_soctherm);
-
- return err;
-}
-
-static int tegra_soctherm_remove(struct platform_device *pdev)
-{
- struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
-
- clk_disable_unprepare(tegra->clock_tsensor);
- clk_disable_unprepare(tegra->clock_soctherm);
-
- return 0;
-}
-
-static struct platform_driver tegra_soctherm_driver = {
- .probe = tegra_soctherm_probe,
- .remove = tegra_soctherm_remove,
- .driver = {
- .name = "tegra-soctherm",
- .of_match_table = tegra_soctherm_of_match,
- },
-};
-module_platform_driver(tegra_soctherm_driver);
-
-MODULE_AUTHOR("Mikko Perttunen <mperttunen-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>");
-MODULE_DESCRIPTION("NVIDIA Tegra SOCTHERM thermal management driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/thermal/tegra/tegra124-soctherm.c b/drivers/thermal/tegra/tegra124-soctherm.c
new file mode 100644
index 000000000000..06aad13a979f
--- /dev/null
+++ b/drivers/thermal/tegra/tegra124-soctherm.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/thermal/tegra124-soctherm.h>
+
+#include "soctherm.h"
+
+static const struct tegra_tsensor_configuration tegra124_tsensor_config = {
+ .tall = 16300,
+ .tiddq_en = 1,
+ .ten_count = 1,
+ .tsample = 120,
+ .tsample_ate = 480,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = {
+ .id = TEGRA124_SOCTHERM_SENSOR_CPU,
+ .name = "cpu",
+ .sensor_temp_offset = SENSOR_TEMP1,
+ .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_CPU_MASK,
+ .pllx_hotspot_diff = 10,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
+ .id = TEGRA124_SOCTHERM_SENSOR_GPU,
+ .name = "gpu",
+ .sensor_temp_offset = SENSOR_TEMP1,
+ .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_GPU_MASK,
+ .pllx_hotspot_diff = 5,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
+ .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
+ .name = "pll",
+ .sensor_temp_offset = SENSOR_TEMP2,
+ .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
+ .id = TEGRA124_SOCTHERM_SENSOR_MEM,
+ .name = "mem",
+ .sensor_temp_offset = SENSOR_TEMP2,
+ .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_MEM_MASK,
+ .pllx_hotspot_diff = 0,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
+};
+
+static const struct tegra_tsensor_group *tegra124_tsensor_groups[] = {
+ &tegra124_tsensor_group_cpu,
+ &tegra124_tsensor_group_gpu,
+ &tegra124_tsensor_group_pll,
+ &tegra124_tsensor_group_mem,
+};
+
+static const struct tegra_tsensor tegra124_tsensors[] = {
+ {
+ .name = "cpu0",
+ .base = 0xc0,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x098,
+ .fuse_corr_alpha = 1135400,
+ .fuse_corr_beta = -6266900,
+ .group = &tegra124_tsensor_group_cpu,
+ }, {
+ .name = "cpu1",
+ .base = 0xe0,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x084,
+ .fuse_corr_alpha = 1122220,
+ .fuse_corr_beta = -5700700,
+ .group = &tegra124_tsensor_group_cpu,
+ }, {
+ .name = "cpu2",
+ .base = 0x100,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x088,
+ .fuse_corr_alpha = 1127000,
+ .fuse_corr_beta = -6768200,
+ .group = &tegra124_tsensor_group_cpu,
+ }, {
+ .name = "cpu3",
+ .base = 0x120,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x12c,
+ .fuse_corr_alpha = 1110900,
+ .fuse_corr_beta = -6232000,
+ .group = &tegra124_tsensor_group_cpu,
+ }, {
+ .name = "mem0",
+ .base = 0x140,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x158,
+ .fuse_corr_alpha = 1122300,
+ .fuse_corr_beta = -5936400,
+ .group = &tegra124_tsensor_group_mem,
+ }, {
+ .name = "mem1",
+ .base = 0x160,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x15c,
+ .fuse_corr_alpha = 1145700,
+ .fuse_corr_beta = -7124600,
+ .group = &tegra124_tsensor_group_mem,
+ }, {
+ .name = "gpu",
+ .base = 0x180,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x154,
+ .fuse_corr_alpha = 1120100,
+ .fuse_corr_beta = -6000500,
+ .group = &tegra124_tsensor_group_gpu,
+ }, {
+ .name = "pllx",
+ .base = 0x1a0,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x160,
+ .fuse_corr_alpha = 1106500,
+ .fuse_corr_beta = -6729300,
+ .group = &tegra124_tsensor_group_pll,
+ },
+};
+
+/*
+ * Mask/shift bits in FUSE_TSENSOR_COMMON and
+ * FUSE_TSENSOR_COMMON, which are described in
+ * tegra_soctherm_fuse.c
+ */
+static const struct tegra_soctherm_fuse tegra124_soctherm_fuse = {
+ .fuse_base_cp_mask = 0x3ff,
+ .fuse_base_cp_shift = 0,
+ .fuse_base_ft_mask = 0x7ff << 10,
+ .fuse_base_ft_shift = 10,
+ .fuse_shift_ft_mask = 0x1f << 21,
+ .fuse_shift_ft_shift = 21,
+ .fuse_spare_realignment = 0x1fc,
+};
+
+const struct tegra_soctherm_soc tegra124_soctherm = {
+ .tsensors = tegra124_tsensors,
+ .num_tsensors = ARRAY_SIZE(tegra124_tsensors),
+ .ttgs = tegra124_tsensor_groups,
+ .num_ttgs = ARRAY_SIZE(tegra124_tsensor_groups),
+ .tfuse = &tegra124_soctherm_fuse,
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH V7 04/12] thermal: tegra: split tegra_soctherm driver
@ 2016-03-11 3:09 ` Wei Ni
0 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-11 3:09 UTC (permalink / raw)
To: rui.zhang, edubezval, thierry.reding
Cc: MLongnecker, swarren, mikko.perttunen, linux-tegra, linux-pm,
linux-kernel, Wei Ni
Split most of the Tegra124 data and code into a Tegra124-specific
file.
Split most of the fuse-related code into a fuse-related source file.
This is in preparation for adding a Tegra210-specific driver in a
future patch.
Beyond the maintainability improvements, this is intended to separate
chip-specific ATE and characterization-related hacks into chip-specific
files, in the hopes that they won't pollute code for other chips.
Signed-off-by: Wei Ni <wni@nvidia.com>
---
drivers/thermal/tegra/Kconfig | 2 +-
drivers/thermal/tegra/Makefile | 3 +
drivers/thermal/tegra/soctherm-fuse.c | 158 +++++++++
drivers/thermal/tegra/soctherm.c | 307 ++++++++++++++++
drivers/thermal/tegra/soctherm.h | 110 ++++++
drivers/thermal/tegra/tegra-soctherm.c | 564 ------------------------------
drivers/thermal/tegra/tegra124-soctherm.c | 172 +++++++++
7 files changed, 751 insertions(+), 565 deletions(-)
create mode 100644 drivers/thermal/tegra/soctherm-fuse.c
create mode 100644 drivers/thermal/tegra/soctherm.c
create mode 100644 drivers/thermal/tegra/soctherm.h
delete mode 100644 drivers/thermal/tegra/tegra-soctherm.c
create mode 100644 drivers/thermal/tegra/tegra124-soctherm.c
diff --git a/drivers/thermal/tegra/Kconfig b/drivers/thermal/tegra/Kconfig
index 0b719d8b629b..fc8a6769b70d 100644
--- a/drivers/thermal/tegra/Kconfig
+++ b/drivers/thermal/tegra/Kconfig
@@ -5,7 +5,7 @@ config TEGRA_SOCTHERM
depends on ARCH_TEGRA
help
Enable this option for integrated thermal management support on NVIDIA
- Tegra124 systems-on-chip. The driver supports four thermal zones
+ Tegra systems-on-chip. The driver supports four thermal zones
(CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
zones to manage temperatures. This option is also required for the
emergency thermal reset (thermtrip) feature to function.
diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile
index d4dc4e7f279e..d5fb15377b97 100644
--- a/drivers/thermal/tegra/Makefile
+++ b/drivers/thermal/tegra/Makefile
@@ -1 +1,4 @@
obj-$(CONFIG_TEGRA_SOCTHERM) += tegra-soctherm.o
+
+tegra-soctherm-y := soctherm.o soctherm-fuse.o
+tegra-soctherm-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124-soctherm.o
diff --git a/drivers/thermal/tegra/soctherm-fuse.c b/drivers/thermal/tegra/soctherm-fuse.c
new file mode 100644
index 000000000000..931c299ab0e8
--- /dev/null
+++ b/drivers/thermal/tegra/soctherm-fuse.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <soc/tegra/fuse.h>
+
+#include "soctherm.h"
+
+#define NOMINAL_CALIB_FT 105
+#define NOMINAL_CALIB_CP 25
+
+#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
+#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13)
+#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13
+
+#define FUSE_TSENSOR_COMMON 0x180
+
+/*
+ * Tegra12x, etc:
+ * FUSE_TSENSOR_COMMON:
+ * 3 2 1 0
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |-----------| SHFT_FT | BASE_FT | BASE_CP |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ *
+ * FUSE_SPARE_REALIGNMENT_REG:
+ * 3 2 1 0
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ * |---------------------------------------------------| SHIFT_CP |
+ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
+ */
+
+#define CALIB_COEFFICIENT 1000000LL
+
+/**
+ * div64_s64_precise() - wrapper for div64_s64()
+ * @a: the dividend
+ * @b: the divisor
+ *
+ * Implements division with fairly accurate rounding instead of truncation by
+ * shifting the dividend to the left by 16 so that the quotient has a
+ * much higher precision.
+ *
+ * Return: the quotient of a / b.
+ */
+static s64 div64_s64_precise(s64 a, s32 b)
+{
+ s64 r, al;
+
+ /* Scale up for increased precision division */
+ al = a << 16;
+
+ r = div64_s64(al * 2 + 1, 2 * b);
+ return r >> 16;
+}
+
+int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
+ struct tsensor_shared_calib *shared)
+{
+ u32 val;
+ s32 shifted_cp, shifted_ft;
+ int err;
+
+ err = tegra_fuse_readl(FUSE_TSENSOR_COMMON, &val);
+ if (err)
+ return err;
+
+ shared->base_cp = (val & tfuse->fuse_base_cp_mask) >>
+ tfuse->fuse_base_cp_shift;
+ shared->base_ft = (val & tfuse->fuse_base_ft_mask) >>
+ tfuse->fuse_base_ft_shift;
+
+ shifted_ft = (val & tfuse->fuse_shift_ft_mask) >>
+ tfuse->fuse_shift_ft_shift;
+ shifted_ft = sign_extend32(shifted_ft, 4);
+
+ if (tfuse->fuse_spare_realignment) {
+ err = tegra_fuse_readl(tfuse->fuse_spare_realignment, &val);
+ if (err)
+ return err;
+ }
+
+ shifted_cp = sign_extend32(val, 5);
+
+ shared->actual_temp_cp = 2 * NOMINAL_CALIB_CP + shifted_cp;
+ shared->actual_temp_ft = 2 * NOMINAL_CALIB_FT + shifted_ft;
+
+ return 0;
+}
+
+int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
+ const struct tsensor_shared_calib *shared,
+ u32 *calibration)
+{
+ const struct tegra_tsensor_group *sensor_group;
+ u32 val, calib;
+ s32 actual_tsensor_ft, actual_tsensor_cp;
+ s32 delta_sens, delta_temp;
+ s32 mult, div;
+ s16 therma, thermb;
+ s64 temp;
+ int err;
+
+ sensor_group = sensor->group;
+
+ err = tegra_fuse_readl(sensor->calib_fuse_offset, &val);
+ if (err)
+ return err;
+
+ actual_tsensor_cp = (shared->base_cp * 64) + sign_extend32(val, 12);
+ val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK) >>
+ FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT;
+ actual_tsensor_ft = (shared->base_ft * 32) + sign_extend32(val, 12);
+
+ delta_sens = actual_tsensor_ft - actual_tsensor_cp;
+ delta_temp = shared->actual_temp_ft - shared->actual_temp_cp;
+
+ mult = sensor_group->pdiv * sensor->config->tsample_ate;
+ div = sensor->config->tsample * sensor_group->pdiv_ate;
+
+ temp = (s64)delta_temp * (1LL << 13) * mult;
+ therma = div64_s64_precise(temp, (s64)delta_sens * div);
+
+ temp = ((s64)actual_tsensor_ft * shared->actual_temp_cp) -
+ ((s64)actual_tsensor_cp * shared->actual_temp_ft);
+ thermb = div64_s64_precise(temp, delta_sens);
+
+ temp = (s64)therma * sensor->fuse_corr_alpha;
+ therma = div64_s64_precise(temp, CALIB_COEFFICIENT);
+
+ temp = (s64)thermb * sensor->fuse_corr_alpha + sensor->fuse_corr_beta;
+ thermb = div64_s64_precise(temp, CALIB_COEFFICIENT);
+
+ calib = ((u16)therma << SENSOR_CONFIG2_THERMA_SHIFT) |
+ ((u16)thermb << SENSOR_CONFIG2_THERMB_SHIFT);
+
+ *calibration = calib;
+
+ return 0;
+}
+
+MODULE_AUTHOR("Wei Ni <wni@nvidia.com>");
+MODULE_DESCRIPTION("Tegra SOCTHERM fuse management");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/thermal/tegra/soctherm.c b/drivers/thermal/tegra/soctherm.c
new file mode 100644
index 000000000000..f56e5a11384e
--- /dev/null
+++ b/drivers/thermal/tegra/soctherm.c
@@ -0,0 +1,307 @@
+/*
+ * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author:
+ * Mikko Perttunen <mperttunen@nvidia.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/thermal.h>
+
+#include <dt-bindings/thermal/tegra124-soctherm.h>
+
+#include "soctherm.h"
+
+#define SENSOR_CONFIG0 0
+#define SENSOR_CONFIG0_STOP BIT(0)
+#define SENSOR_CONFIG0_TALL_SHIFT 8
+#define SENSOR_CONFIG0_TCALC_OVER BIT(4)
+#define SENSOR_CONFIG0_OVER BIT(3)
+#define SENSOR_CONFIG0_CPTR_OVER BIT(2)
+
+#define SENSOR_CONFIG1 4
+#define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
+#define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
+#define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
+#define SENSOR_CONFIG1_TEMP_ENABLE BIT(31)
+
+/*
+ * SENSOR_CONFIG2 is defined in soctherm.h
+ * because, it will be used by tegra_soctherm_fuse.c
+ */
+
+#define READBACK_VALUE_MASK 0xff00
+#define READBACK_VALUE_SHIFT 8
+#define READBACK_ADD_HALF BIT(7)
+#define READBACK_NEGATE BIT(1)
+
+/* get val from register(r) mask bits(m) */
+#define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
+/* set val(v) to mask bits(m) of register(r) */
+#define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
+ (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
+
+struct tegra_thermctl_zone {
+ void __iomem *reg;
+ u32 mask;
+};
+
+struct tegra_soctherm {
+ struct reset_control *reset;
+ struct clk *clock_tsensor;
+ struct clk *clock_soctherm;
+ void __iomem *regs;
+
+ u32 *calib;
+ struct tegra_soctherm_soc *soc;
+};
+
+static int enable_tsensor(struct tegra_soctherm *tegra,
+ unsigned int i,
+ const struct tsensor_shared_calib *shared)
+{
+ const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i];
+ void __iomem *base = tegra->regs + sensor->base;
+ u32 *calib = &tegra->calib[i];
+ unsigned int val;
+ int err;
+
+ err = tegra_calc_tsensor_calib(sensor, shared, calib);
+ if (err)
+ return err;
+
+ val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
+ writel(val, base + SENSOR_CONFIG0);
+
+ val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
+ val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
+ val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
+ val |= SENSOR_CONFIG1_TEMP_ENABLE;
+ writel(val, base + SENSOR_CONFIG1);
+
+ writel(*calib, base + SENSOR_CONFIG2);
+
+ return 0;
+}
+
+/*
+ * Translate from soctherm readback format to millicelsius.
+ * The soctherm readback format in bits is as follows:
+ * TTTTTTTT H______N
+ * where T's contain the temperature in Celsius,
+ * H denotes an addition of 0.5 Celsius and N denotes negation
+ * of the final value.
+ */
+static int translate_temp(u16 val)
+{
+ int t;
+
+ t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
+ if (val & READBACK_ADD_HALF)
+ t += 500;
+ if (val & READBACK_NEGATE)
+ t *= -1;
+
+ return t;
+}
+
+static int tegra_thermctl_get_temp(void *data, int *out_temp)
+{
+ struct tegra_thermctl_zone *zone = data;
+ u32 val;
+
+ val = readl(zone->reg);
+ val = REG_GET_MASK(val, zone->mask);
+ *out_temp = translate_temp(val);
+
+ return 0;
+}
+
+static const struct thermal_zone_of_device_ops tegra_of_thermal_ops = {
+ .get_temp = tegra_thermctl_get_temp,
+};
+
+static const struct of_device_id tegra_soctherm_of_match[] = {
+#ifdef CONFIG_ARCH_TEGRA_124_SOC
+ {
+ .compatible = "nvidia,tegra124-soctherm",
+ .data = &tegra124_soctherm,
+ },
+#endif
+ { },
+};
+MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
+
+static int tegra_soctherm_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *match;
+ struct tegra_soctherm *tegra;
+ struct thermal_zone_device *z;
+ struct tsensor_shared_calib shared_calib;
+ struct resource *res;
+ struct tegra_soctherm_soc *soc;
+ unsigned int i;
+ int err;
+ u32 pdiv, hotspot;
+
+ match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node);
+ if (!match)
+ return -ENODEV;
+
+ soc = (struct tegra_soctherm_soc *)match->data;
+ if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM)
+ return -EINVAL;
+
+ tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
+ if (!tegra)
+ return -ENOMEM;
+
+ dev_set_drvdata(&pdev->dev, tegra);
+
+ tegra->soc = soc;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ tegra->regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(tegra->regs))
+ return PTR_ERR(tegra->regs);
+
+ tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
+ if (IS_ERR(tegra->reset)) {
+ dev_err(&pdev->dev, "can't get soctherm reset\n");
+ return PTR_ERR(tegra->reset);
+ }
+
+ tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
+ if (IS_ERR(tegra->clock_tsensor)) {
+ dev_err(&pdev->dev, "can't get tsensor clock\n");
+ return PTR_ERR(tegra->clock_tsensor);
+ }
+
+ tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
+ if (IS_ERR(tegra->clock_soctherm)) {
+ dev_err(&pdev->dev, "can't get soctherm clock\n");
+ return PTR_ERR(tegra->clock_soctherm);
+ }
+
+ reset_control_assert(tegra->reset);
+
+ err = clk_prepare_enable(tegra->clock_soctherm);
+ if (err)
+ return err;
+
+ err = clk_prepare_enable(tegra->clock_tsensor);
+ if (err) {
+ clk_disable_unprepare(tegra->clock_soctherm);
+ return err;
+ }
+
+ reset_control_deassert(tegra->reset);
+
+ /* Initialize raw sensors */
+
+ tegra->calib = devm_kzalloc(&pdev->dev,
+ sizeof(u32) * soc->num_tsensors,
+ GFP_KERNEL);
+ if (!tegra->calib)
+ return -ENOMEM;
+
+ err = tegra_calc_shared_calib(soc->tfuse, &shared_calib);
+ if (err)
+ goto disable_clocks;
+
+ for (i = 0; i < soc->num_tsensors; ++i) {
+ err = enable_tsensor(tegra, i, &shared_calib);
+ if (err)
+ goto disable_clocks;
+ }
+
+ /* Program pdiv and hotspot offsets per THERM */
+ pdiv = readl(tegra->regs + SENSOR_PDIV);
+ hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
+ for (i = 0; i < soc->num_ttgs; ++i) {
+ pdiv = REG_SET_MASK(pdiv, soc->ttgs[i]->pdiv_mask,
+ soc->ttgs[i]->pdiv);
+ if (soc->ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX)
+ continue;
+ hotspot = REG_SET_MASK(hotspot,
+ soc->ttgs[i]->pllx_hotspot_mask,
+ soc->ttgs[i]->pllx_hotspot_diff);
+ }
+ writel(pdiv, tegra->regs + SENSOR_PDIV);
+ writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
+
+ /* Initialize thermctl sensors */
+
+ for (i = 0; i < soc->num_ttgs; ++i) {
+ struct tegra_thermctl_zone *zone =
+ devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
+ if (!zone) {
+ err = -ENOMEM;
+ goto disable_clocks;
+ }
+
+ zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset;
+ zone->mask = soc->ttgs[i]->sensor_temp_mask;
+
+ z = devm_thermal_zone_of_sensor_register(&pdev->dev,
+ soc->ttgs[i]->id, zone,
+ &tegra_of_thermal_ops);
+ if (IS_ERR(z)) {
+ err = PTR_ERR(z);
+ dev_err(&pdev->dev, "failed to register sensor: %d\n",
+ err);
+ goto disable_clocks;
+ }
+ }
+
+ return 0;
+
+disable_clocks:
+ clk_disable_unprepare(tegra->clock_tsensor);
+ clk_disable_unprepare(tegra->clock_soctherm);
+
+ return err;
+}
+
+static int tegra_soctherm_remove(struct platform_device *pdev)
+{
+ struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
+
+ clk_disable_unprepare(tegra->clock_tsensor);
+ clk_disable_unprepare(tegra->clock_soctherm);
+
+ return 0;
+}
+
+static struct platform_driver tegra_soctherm_driver = {
+ .probe = tegra_soctherm_probe,
+ .remove = tegra_soctherm_remove,
+ .driver = {
+ .name = "tegra_soctherm",
+ .of_match_table = tegra_soctherm_of_match,
+ },
+};
+module_platform_driver(tegra_soctherm_driver);
+
+MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
+MODULE_DESCRIPTION("NVIDIA Tegra SOCTHERM thermal management driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/soctherm.h
new file mode 100644
index 000000000000..f80ee1492ddb
--- /dev/null
+++ b/drivers/thermal/tegra/soctherm.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __DRIVERS_THERMAL_TEGRA_SOCTHERM_H
+#define __DRIVERS_THERMAL_TEGRA_SOCTHERM_H
+
+#define SENSOR_CONFIG2 8
+#define SENSOR_CONFIG2_THERMA_SHIFT 16
+#define SENSOR_CONFIG2_THERMB_SHIFT 0
+
+#define SENSOR_PDIV 0x1c0
+#define SENSOR_PDIV_CPU_MASK (0xf << 12)
+#define SENSOR_PDIV_GPU_MASK (0xf << 8)
+#define SENSOR_PDIV_MEM_MASK (0xf << 4)
+#define SENSOR_PDIV_PLLX_MASK (0xf << 0)
+
+#define SENSOR_HOTSPOT_OFF 0x1c4
+#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
+#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
+#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
+
+#define SENSOR_TEMP1 0x1c8
+#define SENSOR_TEMP1_CPU_TEMP_MASK (0xffff << 16)
+#define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff
+#define SENSOR_TEMP2 0x1cc
+#define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16)
+#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
+
+/**
+ * struct tegra_tsensor_group - SOC_THERM sensor group data
+ * @name: short name of the temperature sensor group
+ * @id: numeric ID of the temperature sensor group
+ * @sensor_temp_offset: offset of the SENSOR_TEMP* register
+ * @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register
+ * @pdiv: the sensor count post-divider to use during runtime
+ * @pdiv_ate: the sensor count post-divider used during automated test
+ * @pdiv_mask: register bitfield mask for the PDIV field for this sensor
+ * @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for
+ PLLX sensor group
+ * @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field
+ */
+struct tegra_tsensor_group {
+ const char *name;
+ u8 id;
+ u16 sensor_temp_offset;
+ u32 sensor_temp_mask;
+ u32 pdiv, pdiv_ate, pdiv_mask;
+ u32 pllx_hotspot_diff, pllx_hotspot_mask;
+};
+
+struct tegra_tsensor_configuration {
+ u32 tall, tiddq_en, ten_count, pdiv, pdiv_ate, tsample, tsample_ate;
+};
+
+struct tegra_tsensor {
+ const char *name;
+ const u32 base;
+ const struct tegra_tsensor_configuration *config;
+ const u32 calib_fuse_offset;
+ /*
+ * Correction values used to modify values read from
+ * calibration fuses
+ */
+ const s32 fuse_corr_alpha, fuse_corr_beta;
+ const struct tegra_tsensor_group *group;
+};
+
+struct tegra_soctherm_fuse {
+ u32 fuse_base_cp_mask, fuse_base_cp_shift;
+ u32 fuse_base_ft_mask, fuse_base_ft_shift;
+ u32 fuse_shift_ft_mask, fuse_shift_ft_shift;
+ u32 fuse_spare_realignment;
+};
+
+struct tsensor_shared_calib {
+ u32 base_cp, base_ft;
+ u32 actual_temp_cp, actual_temp_ft;
+};
+
+struct tegra_soctherm_soc {
+ const struct tegra_tsensor *tsensors;
+ const unsigned int num_tsensors;
+ const struct tegra_tsensor_group **ttgs;
+ const unsigned int num_ttgs;
+ const struct tegra_soctherm_fuse *tfuse;
+};
+
+int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
+ struct tsensor_shared_calib *shared);
+int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
+ const struct tsensor_shared_calib *shared,
+ u32 *calib);
+
+#ifdef CONFIG_ARCH_TEGRA_124_SOC
+extern const struct tegra_soctherm_soc tegra124_soctherm;
+#endif
+
+#endif
+
diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
deleted file mode 100644
index b4b791ebfbb6..000000000000
--- a/drivers/thermal/tegra/tegra-soctherm.c
+++ /dev/null
@@ -1,564 +0,0 @@
-/*
- * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * Author:
- * Mikko Perttunen <mperttunen@nvidia.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/bitops.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/reset.h>
-#include <linux/thermal.h>
-
-#include <soc/tegra/fuse.h>
-#include <dt-bindings/thermal/tegra124-soctherm.h>
-
-#define SENSOR_CONFIG0 0
-#define SENSOR_CONFIG0_STOP BIT(0)
-#define SENSOR_CONFIG0_TALL_SHIFT 8
-#define SENSOR_CONFIG0_TCALC_OVER BIT(4)
-#define SENSOR_CONFIG0_OVER BIT(3)
-#define SENSOR_CONFIG0_CPTR_OVER BIT(2)
-
-#define SENSOR_CONFIG1 4
-#define SENSOR_CONFIG1_TSAMPLE_SHIFT 0
-#define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15
-#define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24
-#define SENSOR_CONFIG1_TEMP_ENABLE BIT(31)
-
-#define SENSOR_CONFIG2 8
-#define SENSOR_CONFIG2_THERMA_SHIFT 16
-#define SENSOR_CONFIG2_THERMB_SHIFT 0
-
-#define SENSOR_PDIV 0x1c0
-#define SENSOR_PDIV_CPU_MASK (0xf << 12)
-#define SENSOR_PDIV_GPU_MASK (0xf << 8)
-#define SENSOR_PDIV_MEM_MASK (0xf << 4)
-#define SENSOR_PDIV_PLLX_MASK (0xf << 0)
-
-#define SENSOR_HOTSPOT_OFF 0x1c4
-#define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
-#define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
-#define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
-
-#define SENSOR_TEMP1 0x1c8
-#define SENSOR_TEMP1_CPU_TEMP_MASK (0xffff << 16)
-#define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff
-#define SENSOR_TEMP2 0x1cc
-#define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16)
-#define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff
-
-#define READBACK_VALUE_MASK 0xff00
-#define READBACK_VALUE_SHIFT 8
-#define READBACK_ADD_HALF BIT(7)
-#define READBACK_NEGATE BIT(1)
-
-#define FUSE_TSENSOR8_CALIB 0x180
-#define FUSE_SPARE_REALIGNMENT_REG_0 0x1fc
-
-#define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
-#define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13)
-#define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13
-
-#define FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK 0x3ff
-#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK (0x7ff << 10)
-#define FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT 10
-
-#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_CP_MASK 0x3f
-#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK (0x1f << 21)
-#define FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT 21
-
-#define NOMINAL_CALIB_FT_T124 105
-#define NOMINAL_CALIB_CP_T124 25
-
-/* get val from register(r) mask bits(m) */
-#define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
-/* set val(v) to mask bits(m) of register(r) */
-#define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \
- (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
-
-/**
- * struct tegra_tsensor_group - SOC_THERM sensor group data
- * @name: short name of the temperature sensor group
- * @id: numeric ID of the temperature sensor group
- * @sensor_temp_offset: offset of the SENSOR_TEMP* register
- * @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register
- * @pdiv: the sensor count post-divider to use during runtime
- * @pdiv_ate: the sensor count post-divider used during automated test
- * @pdiv_mask: register bitfield mask for the PDIV field for this sensor
- * @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for
- PLLX sensor group
- * @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field
- */
-struct tegra_tsensor_group {
- const char *name;
- u8 id;
- u16 sensor_temp_offset;
- u32 sensor_temp_mask;
- u32 pdiv, pdiv_ate, pdiv_mask;
- u32 pllx_hotspot_diff, pllx_hotspot_mask;
-};
-
-struct tegra_tsensor_configuration {
- u32 tall, tiddq_en, ten_count, tsample, tsample_ate;
-};
-
-struct tegra_tsensor {
- const struct tegra_tsensor_configuration *config;
- u32 base, calib_fuse_offset;
- /* Correction values used to modify values read from calibration fuses */
- s32 fuse_corr_alpha, fuse_corr_beta;
- const struct tegra_tsensor_group *group;
-};
-
-struct tegra_thermctl_zone {
- void __iomem *reg;
- u32 mask;
-};
-
-static const struct tegra_tsensor_configuration t124_tsensor_config = {
- .tall = 16300,
- .tiddq_en = 1,
- .ten_count = 1,
- .tsample = 120,
- .tsample_ate = 480,
-};
-
-static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = {
- .id = TEGRA124_SOCTHERM_SENSOR_CPU,
- .name = "cpu",
- .sensor_temp_offset = SENSOR_TEMP1,
- .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
- .pdiv = 8,
- .pdiv_ate = 8,
- .pdiv_mask = SENSOR_PDIV_CPU_MASK,
- .pllx_hotspot_diff = 10,
- .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
-};
-
-static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
- .id = TEGRA124_SOCTHERM_SENSOR_GPU,
- .name = "gpu",
- .sensor_temp_offset = SENSOR_TEMP1,
- .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
- .pdiv = 8,
- .pdiv_ate = 8,
- .pdiv_mask = SENSOR_PDIV_GPU_MASK,
- .pllx_hotspot_diff = 5,
- .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
-};
-
-static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
- .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
- .name = "pll",
- .sensor_temp_offset = SENSOR_TEMP2,
- .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
- .pdiv = 8,
- .pdiv_ate = 8,
- .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
- .pllx_hotspot_diff = 0,
- .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
-};
-
-static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
- .id = TEGRA124_SOCTHERM_SENSOR_MEM,
- .name = "mem",
- .sensor_temp_offset = SENSOR_TEMP2,
- .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
- .pdiv = 8,
- .pdiv_ate = 8,
- .pdiv_mask = SENSOR_PDIV_MEM_MASK,
-};
-
-static const struct tegra_tsensor_group *
-tegra124_tsensor_groups[TEGRA124_SOCTHERM_SENSOR_NUM] = {
- &tegra124_tsensor_group_cpu,
- &tegra124_tsensor_group_gpu,
- &tegra124_tsensor_group_pll,
- &tegra124_tsensor_group_mem,
-};
-
-static const struct tegra_tsensor t124_tsensors[] = {
- {
- .config = &t124_tsensor_config,
- .base = 0xc0,
- .calib_fuse_offset = 0x098,
- .fuse_corr_alpha = 1135400,
- .fuse_corr_beta = -6266900,
- .group = &tegra124_tsensor_group_cpu,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0xe0,
- .calib_fuse_offset = 0x084,
- .fuse_corr_alpha = 1122220,
- .fuse_corr_beta = -5700700,
- .group = &tegra124_tsensor_group_cpu,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0x100,
- .calib_fuse_offset = 0x088,
- .fuse_corr_alpha = 1127000,
- .fuse_corr_beta = -6768200,
- .group = &tegra124_tsensor_group_cpu,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0x120,
- .calib_fuse_offset = 0x12c,
- .fuse_corr_alpha = 1110900,
- .fuse_corr_beta = -6232000,
- .group = &tegra124_tsensor_group_cpu,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0x140,
- .calib_fuse_offset = 0x158,
- .fuse_corr_alpha = 1122300,
- .fuse_corr_beta = -5936400,
- .group = &tegra124_tsensor_group_mem,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0x160,
- .calib_fuse_offset = 0x15c,
- .fuse_corr_alpha = 1145700,
- .fuse_corr_beta = -7124600,
- .group = &tegra124_tsensor_group_mem,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0x180,
- .calib_fuse_offset = 0x154,
- .fuse_corr_alpha = 1120100,
- .fuse_corr_beta = -6000500,
- .group = &tegra124_tsensor_group_gpu,
- },
- {
- .config = &t124_tsensor_config,
- .base = 0x1a0,
- .calib_fuse_offset = 0x160,
- .fuse_corr_alpha = 1106500,
- .fuse_corr_beta = -6729300,
- .group = &tegra124_tsensor_group_pll,
- },
-};
-
-struct tegra_soctherm {
- struct reset_control *reset;
- struct clk *clock_tsensor;
- struct clk *clock_soctherm;
- void __iomem *regs;
-};
-
-struct tsensor_shared_calibration {
- u32 base_cp, base_ft;
- u32 actual_temp_cp, actual_temp_ft;
-};
-
-static int calculate_shared_calibration(struct tsensor_shared_calibration *r)
-{
- u32 val, shifted_cp, shifted_ft;
- int err;
-
- err = tegra_fuse_readl(FUSE_TSENSOR8_CALIB, &val);
- if (err)
- return err;
- r->base_cp = val & FUSE_TSENSOR8_CALIB_CP_TS_BASE_MASK;
- r->base_ft = (val & FUSE_TSENSOR8_CALIB_FT_TS_BASE_MASK)
- >> FUSE_TSENSOR8_CALIB_FT_TS_BASE_SHIFT;
- val = ((val & FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_MASK)
- >> FUSE_SPARE_REALIGNMENT_REG_SHIFT_FT_SHIFT);
- shifted_ft = sign_extend32(val, 4);
-
- err = tegra_fuse_readl(FUSE_SPARE_REALIGNMENT_REG_0, &val);
- if (err)
- return err;
- shifted_cp = sign_extend32(val, 5);
-
- r->actual_temp_cp = 2 * NOMINAL_CALIB_CP_T124 + shifted_cp;
- r->actual_temp_ft = 2 * NOMINAL_CALIB_FT_T124 + shifted_ft;
-
- return 0;
-}
-
-static s64 div64_s64_precise(s64 a, s64 b)
-{
- s64 r, al;
-
- /* Scale up for increased precision division */
- al = a << 16;
-
- r = div64_s64(al * 2 + 1, 2 * b);
- return r >> 16;
-}
-
-static int
-calculate_tsensor_calibration(const struct tegra_tsensor *sensor,
- const struct tsensor_shared_calibration *shared,
- u32 *calib)
-{
- u32 val;
- s32 actual_tsensor_ft, actual_tsensor_cp, delta_sens, delta_temp,
- mult, div;
- s16 therma, thermb;
- s64 tmp;
- int err;
-
- err = tegra_fuse_readl(sensor->calib_fuse_offset, &val);
- if (err)
- return err;
-
- actual_tsensor_cp = (shared->base_cp * 64) + sign_extend32(val, 12);
- val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK)
- >> FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT;
- actual_tsensor_ft = (shared->base_ft * 32) + sign_extend32(val, 12);
-
- delta_sens = actual_tsensor_ft - actual_tsensor_cp;
- delta_temp = shared->actual_temp_ft - shared->actual_temp_cp;
-
- mult = sensor->group->pdiv * sensor->config->tsample_ate;
- div = sensor->config->tsample * sensor->group->pdiv_ate;
-
- therma = div64_s64_precise((s64) delta_temp * (1LL << 13) * mult,
- (s64) delta_sens * div);
-
- tmp = (s64)actual_tsensor_ft * shared->actual_temp_cp -
- (s64)actual_tsensor_cp * shared->actual_temp_ft;
- thermb = div64_s64_precise(tmp, (s64)delta_sens);
-
- therma = div64_s64_precise((s64)therma * sensor->fuse_corr_alpha,
- (s64)1000000LL);
- thermb = div64_s64_precise((s64)thermb * sensor->fuse_corr_alpha +
- sensor->fuse_corr_beta, (s64)1000000LL);
-
- *calib = ((u16)therma << SENSOR_CONFIG2_THERMA_SHIFT) |
- ((u16)thermb << SENSOR_CONFIG2_THERMB_SHIFT);
-
- return 0;
-}
-
-static int enable_tsensor(struct tegra_soctherm *tegra,
- const struct tegra_tsensor *sensor,
- const struct tsensor_shared_calibration *shared)
-{
- void __iomem *base = tegra->regs + sensor->base;
- unsigned int val;
- u32 calib;
- int err;
-
- err = calculate_tsensor_calibration(sensor, shared, &calib);
- if (err)
- return err;
-
- val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
- writel(val, base + SENSOR_CONFIG0);
-
- val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
- val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
- val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
- val |= SENSOR_CONFIG1_TEMP_ENABLE;
- writel(val, base + SENSOR_CONFIG1);
-
- writel(calib, base + SENSOR_CONFIG2);
-
- return 0;
-}
-
-/*
- * Translate from soctherm readback format to millicelsius.
- * The soctherm readback format in bits is as follows:
- * TTTTTTTT H______N
- * where T's contain the temperature in Celsius,
- * H denotes an addition of 0.5 Celsius and N denotes negation
- * of the final value.
- */
-static int translate_temp(u16 val)
-{
- long t;
-
- t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
- if (val & READBACK_ADD_HALF)
- t += 500;
- if (val & READBACK_NEGATE)
- t *= -1;
-
- return t;
-}
-
-static int tegra_thermctl_get_temp(void *data, int *out_temp)
-{
- struct tegra_thermctl_zone *zone = data;
- u32 val;
-
- val = readl(zone->reg);
- val = REG_GET_MASK(val, zone->mask);
- *out_temp = translate_temp(val);
-
- return 0;
-}
-
-static const struct thermal_zone_of_device_ops tegra_of_thermal_ops = {
- .get_temp = tegra_thermctl_get_temp,
-};
-
-static const struct of_device_id tegra_soctherm_of_match[] = {
- { .compatible = "nvidia,tegra124-soctherm" },
- { },
-};
-MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
-
-static int tegra_soctherm_probe(struct platform_device *pdev)
-{
- struct tegra_soctherm *tegra;
- struct thermal_zone_device *z;
- struct tsensor_shared_calibration shared_calib;
- struct resource *res;
- unsigned int i;
- int err;
- u32 pdiv, hotspot;
-
- const struct tegra_tsensor *tsensors = t124_tsensors;
- const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
-
- tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
- if (!tegra)
- return -ENOMEM;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- tegra->regs = devm_ioremap_resource(&pdev->dev, res);
- if (IS_ERR(tegra->regs))
- return PTR_ERR(tegra->regs);
-
- tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
- if (IS_ERR(tegra->reset)) {
- dev_err(&pdev->dev, "can't get soctherm reset\n");
- return PTR_ERR(tegra->reset);
- }
-
- tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
- if (IS_ERR(tegra->clock_tsensor)) {
- dev_err(&pdev->dev, "can't get tsensor clock\n");
- return PTR_ERR(tegra->clock_tsensor);
- }
-
- tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
- if (IS_ERR(tegra->clock_soctherm)) {
- dev_err(&pdev->dev, "can't get soctherm clock\n");
- return PTR_ERR(tegra->clock_soctherm);
- }
-
- reset_control_assert(tegra->reset);
-
- err = clk_prepare_enable(tegra->clock_soctherm);
- if (err)
- return err;
-
- err = clk_prepare_enable(tegra->clock_tsensor);
- if (err) {
- clk_disable_unprepare(tegra->clock_soctherm);
- return err;
- }
-
- reset_control_deassert(tegra->reset);
-
- /* Initialize raw sensors */
-
- err = calculate_shared_calibration(&shared_calib);
- if (err)
- goto disable_clocks;
-
- for (i = 0; i < ARRAY_SIZE(t124_tsensors); ++i) {
- err = enable_tsensor(tegra, tsensors + i, &shared_calib);
- if (err)
- goto disable_clocks;
- }
-
- /* Program pdiv and hotspot offsets per THERM */
- pdiv = readl(tegra->regs + SENSOR_PDIV);
- hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
- for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
- pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
- ttgs[i]->pdiv);
- if (ttgs[i]->id != TEGRA124_SOCTHERM_SENSOR_PLLX)
- hotspot = REG_SET_MASK(hotspot,
- ttgs[i]->pllx_hotspot_mask,
- ttgs[i]->pllx_hotspot_diff);
- }
- writel(pdiv, tegra->regs + SENSOR_PDIV);
- writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
-
- /* Initialize thermctl sensors */
-
- for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
- struct tegra_thermctl_zone *zone =
- devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
- if (!zone) {
- err = -ENOMEM;
- goto disable_clocks;
- }
-
- zone->reg = tegra->regs + ttgs[i]->sensor_temp_offset;
- zone->mask = ttgs[i]->sensor_temp_mask;
-
- z = devm_thermal_zone_of_sensor_register(&pdev->dev,
- ttgs[i]->id, zone,
- &tegra_of_thermal_ops);
- if (IS_ERR(z)) {
- err = PTR_ERR(z);
- dev_err(&pdev->dev, "failed to register sensor: %d\n",
- err);
- goto disable_clocks;
- }
- }
-
- return 0;
-
-disable_clocks:
- clk_disable_unprepare(tegra->clock_tsensor);
- clk_disable_unprepare(tegra->clock_soctherm);
-
- return err;
-}
-
-static int tegra_soctherm_remove(struct platform_device *pdev)
-{
- struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
-
- clk_disable_unprepare(tegra->clock_tsensor);
- clk_disable_unprepare(tegra->clock_soctherm);
-
- return 0;
-}
-
-static struct platform_driver tegra_soctherm_driver = {
- .probe = tegra_soctherm_probe,
- .remove = tegra_soctherm_remove,
- .driver = {
- .name = "tegra-soctherm",
- .of_match_table = tegra_soctherm_of_match,
- },
-};
-module_platform_driver(tegra_soctherm_driver);
-
-MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
-MODULE_DESCRIPTION("NVIDIA Tegra SOCTHERM thermal management driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/thermal/tegra/tegra124-soctherm.c b/drivers/thermal/tegra/tegra124-soctherm.c
new file mode 100644
index 000000000000..06aad13a979f
--- /dev/null
+++ b/drivers/thermal/tegra/tegra124-soctherm.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/thermal/tegra124-soctherm.h>
+
+#include "soctherm.h"
+
+static const struct tegra_tsensor_configuration tegra124_tsensor_config = {
+ .tall = 16300,
+ .tiddq_en = 1,
+ .ten_count = 1,
+ .tsample = 120,
+ .tsample_ate = 480,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = {
+ .id = TEGRA124_SOCTHERM_SENSOR_CPU,
+ .name = "cpu",
+ .sensor_temp_offset = SENSOR_TEMP1,
+ .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_CPU_MASK,
+ .pllx_hotspot_diff = 10,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = {
+ .id = TEGRA124_SOCTHERM_SENSOR_GPU,
+ .name = "gpu",
+ .sensor_temp_offset = SENSOR_TEMP1,
+ .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_GPU_MASK,
+ .pllx_hotspot_diff = 5,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_pll = {
+ .id = TEGRA124_SOCTHERM_SENSOR_PLLX,
+ .name = "pll",
+ .sensor_temp_offset = SENSOR_TEMP2,
+ .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_PLLX_MASK,
+};
+
+static const struct tegra_tsensor_group tegra124_tsensor_group_mem = {
+ .id = TEGRA124_SOCTHERM_SENSOR_MEM,
+ .name = "mem",
+ .sensor_temp_offset = SENSOR_TEMP2,
+ .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK,
+ .pdiv = 8,
+ .pdiv_ate = 8,
+ .pdiv_mask = SENSOR_PDIV_MEM_MASK,
+ .pllx_hotspot_diff = 0,
+ .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK,
+};
+
+static const struct tegra_tsensor_group *tegra124_tsensor_groups[] = {
+ &tegra124_tsensor_group_cpu,
+ &tegra124_tsensor_group_gpu,
+ &tegra124_tsensor_group_pll,
+ &tegra124_tsensor_group_mem,
+};
+
+static const struct tegra_tsensor tegra124_tsensors[] = {
+ {
+ .name = "cpu0",
+ .base = 0xc0,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x098,
+ .fuse_corr_alpha = 1135400,
+ .fuse_corr_beta = -6266900,
+ .group = &tegra124_tsensor_group_cpu,
+ }, {
+ .name = "cpu1",
+ .base = 0xe0,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x084,
+ .fuse_corr_alpha = 1122220,
+ .fuse_corr_beta = -5700700,
+ .group = &tegra124_tsensor_group_cpu,
+ }, {
+ .name = "cpu2",
+ .base = 0x100,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x088,
+ .fuse_corr_alpha = 1127000,
+ .fuse_corr_beta = -6768200,
+ .group = &tegra124_tsensor_group_cpu,
+ }, {
+ .name = "cpu3",
+ .base = 0x120,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x12c,
+ .fuse_corr_alpha = 1110900,
+ .fuse_corr_beta = -6232000,
+ .group = &tegra124_tsensor_group_cpu,
+ }, {
+ .name = "mem0",
+ .base = 0x140,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x158,
+ .fuse_corr_alpha = 1122300,
+ .fuse_corr_beta = -5936400,
+ .group = &tegra124_tsensor_group_mem,
+ }, {
+ .name = "mem1",
+ .base = 0x160,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x15c,
+ .fuse_corr_alpha = 1145700,
+ .fuse_corr_beta = -7124600,
+ .group = &tegra124_tsensor_group_mem,
+ }, {
+ .name = "gpu",
+ .base = 0x180,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x154,
+ .fuse_corr_alpha = 1120100,
+ .fuse_corr_beta = -6000500,
+ .group = &tegra124_tsensor_group_gpu,
+ }, {
+ .name = "pllx",
+ .base = 0x1a0,
+ .config = &tegra124_tsensor_config,
+ .calib_fuse_offset = 0x160,
+ .fuse_corr_alpha = 1106500,
+ .fuse_corr_beta = -6729300,
+ .group = &tegra124_tsensor_group_pll,
+ },
+};
+
+/*
+ * Mask/shift bits in FUSE_TSENSOR_COMMON and
+ * FUSE_TSENSOR_COMMON, which are described in
+ * tegra_soctherm_fuse.c
+ */
+static const struct tegra_soctherm_fuse tegra124_soctherm_fuse = {
+ .fuse_base_cp_mask = 0x3ff,
+ .fuse_base_cp_shift = 0,
+ .fuse_base_ft_mask = 0x7ff << 10,
+ .fuse_base_ft_shift = 10,
+ .fuse_shift_ft_mask = 0x1f << 21,
+ .fuse_shift_ft_shift = 21,
+ .fuse_spare_realignment = 0x1fc,
+};
+
+const struct tegra_soctherm_soc tegra124_soctherm = {
+ .tsensors = tegra124_tsensors,
+ .num_tsensors = ARRAY_SIZE(tegra124_tsensors),
+ .ttgs = tegra124_tsensor_groups,
+ .num_ttgs = ARRAY_SIZE(tegra124_tsensor_groups),
+ .tfuse = &tegra124_soctherm_fuse,
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH V7 01/12] thermal: tegra: move tegra thermal files into tegra directory
2016-03-11 3:09 ` Wei Ni
@ 2016-03-14 18:37 ` Eduardo Valentin
-1 siblings, 0 replies; 25+ messages in thread
From: Eduardo Valentin @ 2016-03-14 18:37 UTC (permalink / raw)
To: Wei Ni
Cc: rui.zhang-ral2JQCrhuEAvxtiuMwx3w,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
MLongnecker-DDmLM1+adcrQT0dZR+AlfA,
swarren-3lzwWm7+Weoh9ZMKESR00Q, mikko.perttunen-/1wQRMveznE,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 4126 bytes --]
On Fri, Mar 11, 2016 at 11:09:12AM +0800, Wei Ni wrote:
> Move Tegra soctherm driver to tegra directory, it's easy to maintain
> and add more new function support for Tegra platforms.
> This will also help to split soctherm driver into common parts and
> chip specific data related parts.
>
> Signed-off-by: Wei Ni <wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> ---
> drivers/thermal/Kconfig | 12 ++----------
> drivers/thermal/Makefile | 2 +-
> drivers/thermal/tegra/Kconfig | 13 +++++++++++++
> drivers/thermal/tegra/Makefile | 1 +
> .../thermal/{tegra_soctherm.c => tegra/tegra-soctherm.c} | 0
> 5 files changed, 17 insertions(+), 11 deletions(-)
> create mode 100644 drivers/thermal/tegra/Kconfig
> create mode 100644 drivers/thermal/tegra/Makefile
> rename drivers/thermal/{tegra_soctherm.c => tegra/tegra-soctherm.c} (100%)
>
> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> index 8cc4ac64a91c..1802629f5051 100644
> --- a/drivers/thermal/Kconfig
> +++ b/drivers/thermal/Kconfig
> @@ -254,16 +254,6 @@ config ARMADA_THERMAL
> Enable this option if you want to have support for thermal management
> controller present in Armada 370 and Armada XP SoC.
>
> -config TEGRA_SOCTHERM
> - tristate "Tegra SOCTHERM thermal management"
> - depends on ARCH_TEGRA
> - help
> - Enable this option for integrated thermal management support on NVIDIA
> - Tegra124 systems-on-chip. The driver supports four thermal zones
> - (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
> - zones to manage temperatures. This option is also required for the
> - emergency thermal reset (thermtrip) feature to function.
> -
> config DB8500_CPUFREQ_COOLING
> tristate "DB8500 cpufreq cooling"
> depends on ARCH_U8500
> @@ -380,6 +370,8 @@ depends on ARCH_STI && OF
> source "drivers/thermal/st/Kconfig"
> endmenu
>
> +source "drivers/thermal/tegra/Kconfig"
> +
> config QCOM_SPMI_TEMP_ALARM
> tristate "Qualcomm SPMI PMIC Temperature Alarm"
> depends on OF && SPMI && IIO
> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
> index cfae6a654793..119e25cdcc66 100644
> --- a/drivers/thermal/Makefile
> +++ b/drivers/thermal/Makefile
> @@ -46,5 +46,5 @@ obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/
> obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/
> obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o
> obj-$(CONFIG_ST_THERMAL) += st/
> -obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o
> +obj-$(CONFIG_TEGRA_SOCTHERM) += tegra/
> obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
> diff --git a/drivers/thermal/tegra/Kconfig b/drivers/thermal/tegra/Kconfig
> new file mode 100644
> index 000000000000..0b719d8b629b
> --- /dev/null
> +++ b/drivers/thermal/tegra/Kconfig
> @@ -0,0 +1,13 @@
> +menu "NVIDIA Tegra thermal drivers"
> +
> +config TEGRA_SOCTHERM
> + tristate "Tegra SOCTHERM thermal management"
> + depends on ARCH_TEGRA
You probably want to move the depends part to the menu section, so the
menu wont appear where it shouldnt.
> + help
> + Enable this option for integrated thermal management support on NVIDIA
> + Tegra124 systems-on-chip. The driver supports four thermal zones
> + (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
> + zones to manage temperatures. This option is also required for the
> + emergency thermal reset (thermtrip) feature to function.
> +
> +endmenu
> diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile
> new file mode 100644
> index 000000000000..d4dc4e7f279e
> --- /dev/null
> +++ b/drivers/thermal/tegra/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_TEGRA_SOCTHERM) += tegra-soctherm.o
> diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
> similarity index 100%
> rename from drivers/thermal/tegra_soctherm.c
> rename to drivers/thermal/tegra/tegra-soctherm.c
> --
> 1.9.1
>
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 473 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 01/12] thermal: tegra: move tegra thermal files into tegra directory
@ 2016-03-14 18:37 ` Eduardo Valentin
0 siblings, 0 replies; 25+ messages in thread
From: Eduardo Valentin @ 2016-03-14 18:37 UTC (permalink / raw)
To: Wei Ni
Cc: rui.zhang, thierry.reding, MLongnecker, swarren, mikko.perttunen,
linux-tegra, linux-pm, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 4097 bytes --]
On Fri, Mar 11, 2016 at 11:09:12AM +0800, Wei Ni wrote:
> Move Tegra soctherm driver to tegra directory, it's easy to maintain
> and add more new function support for Tegra platforms.
> This will also help to split soctherm driver into common parts and
> chip specific data related parts.
>
> Signed-off-by: Wei Ni <wni@nvidia.com>
> ---
> drivers/thermal/Kconfig | 12 ++----------
> drivers/thermal/Makefile | 2 +-
> drivers/thermal/tegra/Kconfig | 13 +++++++++++++
> drivers/thermal/tegra/Makefile | 1 +
> .../thermal/{tegra_soctherm.c => tegra/tegra-soctherm.c} | 0
> 5 files changed, 17 insertions(+), 11 deletions(-)
> create mode 100644 drivers/thermal/tegra/Kconfig
> create mode 100644 drivers/thermal/tegra/Makefile
> rename drivers/thermal/{tegra_soctherm.c => tegra/tegra-soctherm.c} (100%)
>
> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
> index 8cc4ac64a91c..1802629f5051 100644
> --- a/drivers/thermal/Kconfig
> +++ b/drivers/thermal/Kconfig
> @@ -254,16 +254,6 @@ config ARMADA_THERMAL
> Enable this option if you want to have support for thermal management
> controller present in Armada 370 and Armada XP SoC.
>
> -config TEGRA_SOCTHERM
> - tristate "Tegra SOCTHERM thermal management"
> - depends on ARCH_TEGRA
> - help
> - Enable this option for integrated thermal management support on NVIDIA
> - Tegra124 systems-on-chip. The driver supports four thermal zones
> - (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
> - zones to manage temperatures. This option is also required for the
> - emergency thermal reset (thermtrip) feature to function.
> -
> config DB8500_CPUFREQ_COOLING
> tristate "DB8500 cpufreq cooling"
> depends on ARCH_U8500
> @@ -380,6 +370,8 @@ depends on ARCH_STI && OF
> source "drivers/thermal/st/Kconfig"
> endmenu
>
> +source "drivers/thermal/tegra/Kconfig"
> +
> config QCOM_SPMI_TEMP_ALARM
> tristate "Qualcomm SPMI PMIC Temperature Alarm"
> depends on OF && SPMI && IIO
> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
> index cfae6a654793..119e25cdcc66 100644
> --- a/drivers/thermal/Makefile
> +++ b/drivers/thermal/Makefile
> @@ -46,5 +46,5 @@ obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/
> obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/
> obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o
> obj-$(CONFIG_ST_THERMAL) += st/
> -obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o
> +obj-$(CONFIG_TEGRA_SOCTHERM) += tegra/
> obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
> diff --git a/drivers/thermal/tegra/Kconfig b/drivers/thermal/tegra/Kconfig
> new file mode 100644
> index 000000000000..0b719d8b629b
> --- /dev/null
> +++ b/drivers/thermal/tegra/Kconfig
> @@ -0,0 +1,13 @@
> +menu "NVIDIA Tegra thermal drivers"
> +
> +config TEGRA_SOCTHERM
> + tristate "Tegra SOCTHERM thermal management"
> + depends on ARCH_TEGRA
You probably want to move the depends part to the menu section, so the
menu wont appear where it shouldnt.
> + help
> + Enable this option for integrated thermal management support on NVIDIA
> + Tegra124 systems-on-chip. The driver supports four thermal zones
> + (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
> + zones to manage temperatures. This option is also required for the
> + emergency thermal reset (thermtrip) feature to function.
> +
> +endmenu
> diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile
> new file mode 100644
> index 000000000000..d4dc4e7f279e
> --- /dev/null
> +++ b/drivers/thermal/tegra/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_TEGRA_SOCTHERM) += tegra-soctherm.o
> diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
> similarity index 100%
> rename from drivers/thermal/tegra_soctherm.c
> rename to drivers/thermal/tegra/tegra-soctherm.c
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 03/12] thermal: tegra: get rid of PDIV/HOTSPOT hack
2016-03-11 3:09 ` Wei Ni
(?)
@ 2016-03-14 20:05 ` Eduardo Valentin
[not found] ` <20160314200539.GH1872-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
-1 siblings, 1 reply; 25+ messages in thread
From: Eduardo Valentin @ 2016-03-14 20:05 UTC (permalink / raw)
To: Wei Ni
Cc: rui.zhang, thierry.reding, MLongnecker, swarren, mikko.perttunen,
linux-tegra, linux-pm, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2720 bytes --]
On Fri, Mar 11, 2016 at 11:09:14AM +0800, Wei Ni wrote:
> Get rid of T124-specific PDIV/HOTSPOT hack.
> tegra-soctherm.c contained a hack to set the SENSOR_PDIV and
> SENSOR_HOTSPOT_OFFSET registers - it just did two writes of
> T124-specific opaque values. Convert these into a form that can be
> substituted on a per-chip basis, and into structure fields that have
> at least some independent meaning.
>
> Signed-off-by: Wei Ni <wni@nvidia.com>
> ---
> drivers/thermal/tegra/tegra-soctherm.c | 18 ++++++++++++++----
> 1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
> index b3ec0faa2bee..b4b791ebfbb6 100644
> --- a/drivers/thermal/tegra/tegra-soctherm.c
> +++ b/drivers/thermal/tegra/tegra-soctherm.c
> @@ -48,14 +48,12 @@
> #define SENSOR_CONFIG2_THERMB_SHIFT 0
>
> #define SENSOR_PDIV 0x1c0
> -#define SENSOR_PDIV_T124 0x8888
> #define SENSOR_PDIV_CPU_MASK (0xf << 12)
> #define SENSOR_PDIV_GPU_MASK (0xf << 8)
> #define SENSOR_PDIV_MEM_MASK (0xf << 4)
> #define SENSOR_PDIV_PLLX_MASK (0xf << 0)
>
> #define SENSOR_HOTSPOT_OFF 0x1c4
> -#define SENSOR_HOTSPOT_OFF_T124 0x00060600
> #define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
> #define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
> #define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
> @@ -436,6 +434,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
> struct resource *res;
> unsigned int i;
> int err;
> + u32 pdiv, hotspot;
>
> const struct tegra_tsensor *tsensors = t124_tsensors;
> const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
> @@ -493,8 +492,19 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
> goto disable_clocks;
> }
>
> - writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
> - writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
> + /* Program pdiv and hotspot offsets per THERM */
> + pdiv = readl(tegra->regs + SENSOR_PDIV);
> + hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
> + for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
> + pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
> + ttgs[i]->pdiv);
> + if (ttgs[i]->id != TEGRA124_SOCTHERM_SENSOR_PLLX)
> + hotspot = REG_SET_MASK(hotspot,
> + ttgs[i]->pllx_hotspot_mask,
> + ttgs[i]->pllx_hotspot_diff);
> + }
> + writel(pdiv, tegra->regs + SENSOR_PDIV);
> + writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
Is the above logic the same for all supported chips? e.g. do we always
skip pllx for hotspot configuration?
>
> /* Initialize thermctl sensors */
>
> --
> 1.9.1
>
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 00/12] Add T210 support in Tegra soctherm
2016-03-11 3:09 ` Wei Ni
@ 2016-03-14 21:01 ` Eduardo Valentin
-1 siblings, 0 replies; 25+ messages in thread
From: Eduardo Valentin @ 2016-03-14 21:01 UTC (permalink / raw)
To: Wei Ni
Cc: rui.zhang-ral2JQCrhuEAvxtiuMwx3w,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
MLongnecker-DDmLM1+adcrQT0dZR+AlfA,
swarren-3lzwWm7+Weoh9ZMKESR00Q, mikko.perttunen-/1wQRMveznE,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 555 bytes --]
On Fri, Mar 11, 2016 at 11:09:11AM +0800, Wei Ni wrote:
> This patchset adds following functions for tegra_soctherm driver:
> 1. add T210 support.
It would be good to update the compatible string in the binding
documentation.
> 2. export debugfs to show some registers.
> 3. add thermtrip funciton.
> 4. add suspend/resume function.
Thanks for your effort in keeping up with upstream. I think overall the
series is good, I had only very few comments (in response to each
patch).
BR,
Eduardo Valentin
>
>
> --
> 1.9.1
>
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 473 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 00/12] Add T210 support in Tegra soctherm
@ 2016-03-14 21:01 ` Eduardo Valentin
0 siblings, 0 replies; 25+ messages in thread
From: Eduardo Valentin @ 2016-03-14 21:01 UTC (permalink / raw)
To: Wei Ni
Cc: rui.zhang, thierry.reding, MLongnecker, swarren, mikko.perttunen,
linux-tegra, linux-pm, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 555 bytes --]
On Fri, Mar 11, 2016 at 11:09:11AM +0800, Wei Ni wrote:
> This patchset adds following functions for tegra_soctherm driver:
> 1. add T210 support.
It would be good to update the compatible string in the binding
documentation.
> 2. export debugfs to show some registers.
> 3. add thermtrip funciton.
> 4. add suspend/resume function.
Thanks for your effort in keeping up with upstream. I think overall the
series is good, I had only very few comments (in response to each
patch).
BR,
Eduardo Valentin
>
>
> --
> 1.9.1
>
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 473 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 00/12] Add T210 support in Tegra soctherm
2016-03-14 21:01 ` Eduardo Valentin
@ 2016-03-15 5:46 ` Wei Ni
-1 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-15 5:46 UTC (permalink / raw)
To: Eduardo Valentin
Cc: rui.zhang-ral2JQCrhuEAvxtiuMwx3w,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
MLongnecker-DDmLM1+adcrQT0dZR+AlfA,
swarren-3lzwWm7+Weoh9ZMKESR00Q, mikko.perttunen-/1wQRMveznE,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 2016年03月15日 05:01, Eduardo Valentin wrote:
> * PGP Signed by an unknown key
>
> On Fri, Mar 11, 2016 at 11:09:11AM +0800, Wei Ni wrote:
>> This patchset adds following functions for tegra_soctherm driver:
>> 1. add T210 support.
>
> It would be good to update the compatible string in the binding
> documentation.
The commit "193c9d23a0f0 Documentation: DT bindings: add more Tegra chip
compatible strings" already add compatible string for Tegra210.
>
>> 2. export debugfs to show some registers.
>> 3. add thermtrip funciton.
>> 4. add suspend/resume function.
>
> Thanks for your effort in keeping up with upstream. I think overall the
> series is good, I had only very few comments (in response to each
> patch).
Thanks for your review. I will check these comments, and update my patches in
next few days.
Wei.
>
> BR,
>
> Eduardo Valentin
>
>
>>
>>
>> --
>> 1.9.1
>>
>
> * Unknown Key
> * 0x7DA4E256
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 00/12] Add T210 support in Tegra soctherm
@ 2016-03-15 5:46 ` Wei Ni
0 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-15 5:46 UTC (permalink / raw)
To: Eduardo Valentin
Cc: rui.zhang, thierry.reding, MLongnecker, swarren, mikko.perttunen,
linux-tegra, linux-pm, linux-kernel
On 2016年03月15日 05:01, Eduardo Valentin wrote:
> * PGP Signed by an unknown key
>
> On Fri, Mar 11, 2016 at 11:09:11AM +0800, Wei Ni wrote:
>> This patchset adds following functions for tegra_soctherm driver:
>> 1. add T210 support.
>
> It would be good to update the compatible string in the binding
> documentation.
The commit "193c9d23a0f0 Documentation: DT bindings: add more Tegra chip
compatible strings" already add compatible string for Tegra210.
>
>> 2. export debugfs to show some registers.
>> 3. add thermtrip funciton.
>> 4. add suspend/resume function.
>
> Thanks for your effort in keeping up with upstream. I think overall the
> series is good, I had only very few comments (in response to each
> patch).
Thanks for your review. I will check these comments, and update my patches in
next few days.
Wei.
>
> BR,
>
> Eduardo Valentin
>
>
>>
>>
>> --
>> 1.9.1
>>
>
> * Unknown Key
> * 0x7DA4E256
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 01/12] thermal: tegra: move tegra thermal files into tegra directory
2016-03-14 18:37 ` Eduardo Valentin
@ 2016-03-15 6:17 ` Wei Ni
-1 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-15 6:17 UTC (permalink / raw)
To: Eduardo Valentin
Cc: rui.zhang-ral2JQCrhuEAvxtiuMwx3w,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
MLongnecker-DDmLM1+adcrQT0dZR+AlfA,
swarren-3lzwWm7+Weoh9ZMKESR00Q, mikko.perttunen-/1wQRMveznE,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 2016年03月15日 02:37, Eduardo Valentin wrote:
> * PGP Signed by an unknown key
>
> On Fri, Mar 11, 2016 at 11:09:12AM +0800, Wei Ni wrote:
>> Move Tegra soctherm driver to tegra directory, it's easy to maintain
>> and add more new function support for Tegra platforms.
>> This will also help to split soctherm driver into common parts and
>> chip specific data related parts.
>>
>> Signed-off-by: Wei Ni <wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> drivers/thermal/Kconfig | 12 ++----------
>> drivers/thermal/Makefile | 2 +-
>> drivers/thermal/tegra/Kconfig | 13 +++++++++++++
>> drivers/thermal/tegra/Makefile | 1 +
>> .../thermal/{tegra_soctherm.c => tegra/tegra-soctherm.c} | 0
>> 5 files changed, 17 insertions(+), 11 deletions(-)
>> create mode 100644 drivers/thermal/tegra/Kconfig
>> create mode 100644 drivers/thermal/tegra/Makefile
>> rename drivers/thermal/{tegra_soctherm.c => tegra/tegra-soctherm.c} (100%)
>>
>> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
>> index 8cc4ac64a91c..1802629f5051 100644
>> --- a/drivers/thermal/Kconfig
>> +++ b/drivers/thermal/Kconfig
>> @@ -254,16 +254,6 @@ config ARMADA_THERMAL
>> Enable this option if you want to have support for thermal management
>> controller present in Armada 370 and Armada XP SoC.
>>
>> -config TEGRA_SOCTHERM
>> - tristate "Tegra SOCTHERM thermal management"
>> - depends on ARCH_TEGRA
>> - help
>> - Enable this option for integrated thermal management support on NVIDIA
>> - Tegra124 systems-on-chip. The driver supports four thermal zones
>> - (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
>> - zones to manage temperatures. This option is also required for the
>> - emergency thermal reset (thermtrip) feature to function.
>> -
>> config DB8500_CPUFREQ_COOLING
>> tristate "DB8500 cpufreq cooling"
>> depends on ARCH_U8500
>> @@ -380,6 +370,8 @@ depends on ARCH_STI && OF
>> source "drivers/thermal/st/Kconfig"
>> endmenu
>>
>> +source "drivers/thermal/tegra/Kconfig"
>> +
>> config QCOM_SPMI_TEMP_ALARM
>> tristate "Qualcomm SPMI PMIC Temperature Alarm"
>> depends on OF && SPMI && IIO
>> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
>> index cfae6a654793..119e25cdcc66 100644
>> --- a/drivers/thermal/Makefile
>> +++ b/drivers/thermal/Makefile
>> @@ -46,5 +46,5 @@ obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/
>> obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/
>> obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o
>> obj-$(CONFIG_ST_THERMAL) += st/
>> -obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o
>> +obj-$(CONFIG_TEGRA_SOCTHERM) += tegra/
>> obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
>> diff --git a/drivers/thermal/tegra/Kconfig b/drivers/thermal/tegra/Kconfig
>> new file mode 100644
>> index 000000000000..0b719d8b629b
>> --- /dev/null
>> +++ b/drivers/thermal/tegra/Kconfig
>> @@ -0,0 +1,13 @@
>> +menu "NVIDIA Tegra thermal drivers"
>> +
>> +config TEGRA_SOCTHERM
>> + tristate "Tegra SOCTHERM thermal management"
>> + depends on ARCH_TEGRA
>
> You probably want to move the depends part to the menu section, so the
> menu wont appear where it shouldnt.
Yes, will fix it.
>
>> + help
>> + Enable this option for integrated thermal management support on NVIDIA
>> + Tegra124 systems-on-chip. The driver supports four thermal zones
>> + (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
>> + zones to manage temperatures. This option is also required for the
>> + emergency thermal reset (thermtrip) feature to function.
>> +
>> +endmenu
>> diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile
>> new file mode 100644
>> index 000000000000..d4dc4e7f279e
>> --- /dev/null
>> +++ b/drivers/thermal/tegra/Makefile
>> @@ -0,0 +1 @@
>> +obj-$(CONFIG_TEGRA_SOCTHERM) += tegra-soctherm.o
>> diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
>> similarity index 100%
>> rename from drivers/thermal/tegra_soctherm.c
>> rename to drivers/thermal/tegra/tegra-soctherm.c
>> --
>> 1.9.1
>>
>
> * Unknown Key
> * 0x7DA4E256
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 01/12] thermal: tegra: move tegra thermal files into tegra directory
@ 2016-03-15 6:17 ` Wei Ni
0 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-15 6:17 UTC (permalink / raw)
To: Eduardo Valentin
Cc: rui.zhang, thierry.reding, MLongnecker, swarren, mikko.perttunen,
linux-tegra, linux-pm, linux-kernel
On 2016年03月15日 02:37, Eduardo Valentin wrote:
> * PGP Signed by an unknown key
>
> On Fri, Mar 11, 2016 at 11:09:12AM +0800, Wei Ni wrote:
>> Move Tegra soctherm driver to tegra directory, it's easy to maintain
>> and add more new function support for Tegra platforms.
>> This will also help to split soctherm driver into common parts and
>> chip specific data related parts.
>>
>> Signed-off-by: Wei Ni <wni@nvidia.com>
>> ---
>> drivers/thermal/Kconfig | 12 ++----------
>> drivers/thermal/Makefile | 2 +-
>> drivers/thermal/tegra/Kconfig | 13 +++++++++++++
>> drivers/thermal/tegra/Makefile | 1 +
>> .../thermal/{tegra_soctherm.c => tegra/tegra-soctherm.c} | 0
>> 5 files changed, 17 insertions(+), 11 deletions(-)
>> create mode 100644 drivers/thermal/tegra/Kconfig
>> create mode 100644 drivers/thermal/tegra/Makefile
>> rename drivers/thermal/{tegra_soctherm.c => tegra/tegra-soctherm.c} (100%)
>>
>> diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
>> index 8cc4ac64a91c..1802629f5051 100644
>> --- a/drivers/thermal/Kconfig
>> +++ b/drivers/thermal/Kconfig
>> @@ -254,16 +254,6 @@ config ARMADA_THERMAL
>> Enable this option if you want to have support for thermal management
>> controller present in Armada 370 and Armada XP SoC.
>>
>> -config TEGRA_SOCTHERM
>> - tristate "Tegra SOCTHERM thermal management"
>> - depends on ARCH_TEGRA
>> - help
>> - Enable this option for integrated thermal management support on NVIDIA
>> - Tegra124 systems-on-chip. The driver supports four thermal zones
>> - (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
>> - zones to manage temperatures. This option is also required for the
>> - emergency thermal reset (thermtrip) feature to function.
>> -
>> config DB8500_CPUFREQ_COOLING
>> tristate "DB8500 cpufreq cooling"
>> depends on ARCH_U8500
>> @@ -380,6 +370,8 @@ depends on ARCH_STI && OF
>> source "drivers/thermal/st/Kconfig"
>> endmenu
>>
>> +source "drivers/thermal/tegra/Kconfig"
>> +
>> config QCOM_SPMI_TEMP_ALARM
>> tristate "Qualcomm SPMI PMIC Temperature Alarm"
>> depends on OF && SPMI && IIO
>> diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
>> index cfae6a654793..119e25cdcc66 100644
>> --- a/drivers/thermal/Makefile
>> +++ b/drivers/thermal/Makefile
>> @@ -46,5 +46,5 @@ obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/
>> obj-$(CONFIG_INT340X_THERMAL) += int340x_thermal/
>> obj-$(CONFIG_INTEL_PCH_THERMAL) += intel_pch_thermal.o
>> obj-$(CONFIG_ST_THERMAL) += st/
>> -obj-$(CONFIG_TEGRA_SOCTHERM) += tegra_soctherm.o
>> +obj-$(CONFIG_TEGRA_SOCTHERM) += tegra/
>> obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o
>> diff --git a/drivers/thermal/tegra/Kconfig b/drivers/thermal/tegra/Kconfig
>> new file mode 100644
>> index 000000000000..0b719d8b629b
>> --- /dev/null
>> +++ b/drivers/thermal/tegra/Kconfig
>> @@ -0,0 +1,13 @@
>> +menu "NVIDIA Tegra thermal drivers"
>> +
>> +config TEGRA_SOCTHERM
>> + tristate "Tegra SOCTHERM thermal management"
>> + depends on ARCH_TEGRA
>
> You probably want to move the depends part to the menu section, so the
> menu wont appear where it shouldnt.
Yes, will fix it.
>
>> + help
>> + Enable this option for integrated thermal management support on NVIDIA
>> + Tegra124 systems-on-chip. The driver supports four thermal zones
>> + (CPU, GPU, MEM, PLLX). Cooling devices can be bound to the thermal
>> + zones to manage temperatures. This option is also required for the
>> + emergency thermal reset (thermtrip) feature to function.
>> +
>> +endmenu
>> diff --git a/drivers/thermal/tegra/Makefile b/drivers/thermal/tegra/Makefile
>> new file mode 100644
>> index 000000000000..d4dc4e7f279e
>> --- /dev/null
>> +++ b/drivers/thermal/tegra/Makefile
>> @@ -0,0 +1 @@
>> +obj-$(CONFIG_TEGRA_SOCTHERM) += tegra-soctherm.o
>> diff --git a/drivers/thermal/tegra_soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
>> similarity index 100%
>> rename from drivers/thermal/tegra_soctherm.c
>> rename to drivers/thermal/tegra/tegra-soctherm.c
>> --
>> 1.9.1
>>
>
> * Unknown Key
> * 0x7DA4E256
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 03/12] thermal: tegra: get rid of PDIV/HOTSPOT hack
2016-03-14 20:05 ` Eduardo Valentin
@ 2016-03-15 6:21 ` Wei Ni
0 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-15 6:21 UTC (permalink / raw)
To: Eduardo Valentin
Cc: rui.zhang-ral2JQCrhuEAvxtiuMwx3w,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
MLongnecker-DDmLM1+adcrQT0dZR+AlfA,
swarren-3lzwWm7+Weoh9ZMKESR00Q, mikko.perttunen-/1wQRMveznE,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 2016年03月15日 04:05, Eduardo Valentin wrote:
> * PGP Signed by an unknown key
>
> On Fri, Mar 11, 2016 at 11:09:14AM +0800, Wei Ni wrote:
>> Get rid of T124-specific PDIV/HOTSPOT hack.
>> tegra-soctherm.c contained a hack to set the SENSOR_PDIV and
>> SENSOR_HOTSPOT_OFFSET registers - it just did two writes of
>> T124-specific opaque values. Convert these into a form that can be
>> substituted on a per-chip basis, and into structure fields that have
>> at least some independent meaning.
>>
>> Signed-off-by: Wei Ni <wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> ---
>> drivers/thermal/tegra/tegra-soctherm.c | 18 ++++++++++++++----
>> 1 file changed, 14 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
>> index b3ec0faa2bee..b4b791ebfbb6 100644
>> --- a/drivers/thermal/tegra/tegra-soctherm.c
>> +++ b/drivers/thermal/tegra/tegra-soctherm.c
>> @@ -48,14 +48,12 @@
>> #define SENSOR_CONFIG2_THERMB_SHIFT 0
>>
>> #define SENSOR_PDIV 0x1c0
>> -#define SENSOR_PDIV_T124 0x8888
>> #define SENSOR_PDIV_CPU_MASK (0xf << 12)
>> #define SENSOR_PDIV_GPU_MASK (0xf << 8)
>> #define SENSOR_PDIV_MEM_MASK (0xf << 4)
>> #define SENSOR_PDIV_PLLX_MASK (0xf << 0)
>>
>> #define SENSOR_HOTSPOT_OFF 0x1c4
>> -#define SENSOR_HOTSPOT_OFF_T124 0x00060600
>> #define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
>> #define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
>> #define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
>> @@ -436,6 +434,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
>> struct resource *res;
>> unsigned int i;
>> int err;
>> + u32 pdiv, hotspot;
>>
>> const struct tegra_tsensor *tsensors = t124_tsensors;
>> const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
>> @@ -493,8 +492,19 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
>> goto disable_clocks;
>> }
>>
>> - writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
>> - writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
>> + /* Program pdiv and hotspot offsets per THERM */
>> + pdiv = readl(tegra->regs + SENSOR_PDIV);
>> + hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
>> + for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
>> + pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
>> + ttgs[i]->pdiv);
>> + if (ttgs[i]->id != TEGRA124_SOCTHERM_SENSOR_PLLX)
>> + hotspot = REG_SET_MASK(hotspot,
>> + ttgs[i]->pllx_hotspot_mask,
>> + ttgs[i]->pllx_hotspot_diff);
>> + }
>> + writel(pdiv, tegra->regs + SENSOR_PDIV);
>> + writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
>
> Is the above logic the same for all supported chips? e.g. do we always
> skip pllx for hotspot configuration?
Yes, this logic support Tegra124, Tegra210, and Tegra132 which I will send out
in next series.
>
>
>>
>> /* Initialize thermctl sensors */
>>
>> --
>> 1.9.1
>>
>
> * Unknown Key
> * 0x7DA4E256
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 03/12] thermal: tegra: get rid of PDIV/HOTSPOT hack
@ 2016-03-15 6:21 ` Wei Ni
0 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-15 6:21 UTC (permalink / raw)
To: Eduardo Valentin
Cc: rui.zhang, thierry.reding, MLongnecker, swarren, mikko.perttunen,
linux-tegra, linux-pm, linux-kernel
On 2016年03月15日 04:05, Eduardo Valentin wrote:
> * PGP Signed by an unknown key
>
> On Fri, Mar 11, 2016 at 11:09:14AM +0800, Wei Ni wrote:
>> Get rid of T124-specific PDIV/HOTSPOT hack.
>> tegra-soctherm.c contained a hack to set the SENSOR_PDIV and
>> SENSOR_HOTSPOT_OFFSET registers - it just did two writes of
>> T124-specific opaque values. Convert these into a form that can be
>> substituted on a per-chip basis, and into structure fields that have
>> at least some independent meaning.
>>
>> Signed-off-by: Wei Ni <wni@nvidia.com>
>> ---
>> drivers/thermal/tegra/tegra-soctherm.c | 18 ++++++++++++++----
>> 1 file changed, 14 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
>> index b3ec0faa2bee..b4b791ebfbb6 100644
>> --- a/drivers/thermal/tegra/tegra-soctherm.c
>> +++ b/drivers/thermal/tegra/tegra-soctherm.c
>> @@ -48,14 +48,12 @@
>> #define SENSOR_CONFIG2_THERMB_SHIFT 0
>>
>> #define SENSOR_PDIV 0x1c0
>> -#define SENSOR_PDIV_T124 0x8888
>> #define SENSOR_PDIV_CPU_MASK (0xf << 12)
>> #define SENSOR_PDIV_GPU_MASK (0xf << 8)
>> #define SENSOR_PDIV_MEM_MASK (0xf << 4)
>> #define SENSOR_PDIV_PLLX_MASK (0xf << 0)
>>
>> #define SENSOR_HOTSPOT_OFF 0x1c4
>> -#define SENSOR_HOTSPOT_OFF_T124 0x00060600
>> #define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
>> #define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
>> #define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
>> @@ -436,6 +434,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
>> struct resource *res;
>> unsigned int i;
>> int err;
>> + u32 pdiv, hotspot;
>>
>> const struct tegra_tsensor *tsensors = t124_tsensors;
>> const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
>> @@ -493,8 +492,19 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
>> goto disable_clocks;
>> }
>>
>> - writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
>> - writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
>> + /* Program pdiv and hotspot offsets per THERM */
>> + pdiv = readl(tegra->regs + SENSOR_PDIV);
>> + hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
>> + for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
>> + pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
>> + ttgs[i]->pdiv);
>> + if (ttgs[i]->id != TEGRA124_SOCTHERM_SENSOR_PLLX)
>> + hotspot = REG_SET_MASK(hotspot,
>> + ttgs[i]->pllx_hotspot_mask,
>> + ttgs[i]->pllx_hotspot_diff);
>> + }
>> + writel(pdiv, tegra->regs + SENSOR_PDIV);
>> + writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
>
> Is the above logic the same for all supported chips? e.g. do we always
> skip pllx for hotspot configuration?
Yes, this logic support Tegra124, Tegra210, and Tegra132 which I will send out
in next series.
>
>
>>
>> /* Initialize thermctl sensors */
>>
>> --
>> 1.9.1
>>
>
> * Unknown Key
> * 0x7DA4E256
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 03/12] thermal: tegra: get rid of PDIV/HOTSPOT hack
2016-03-15 6:21 ` Wei Ni
@ 2016-03-15 19:56 ` Eduardo Valentin
-1 siblings, 0 replies; 25+ messages in thread
From: Eduardo Valentin @ 2016-03-15 19:56 UTC (permalink / raw)
To: Wei Ni
Cc: rui.zhang-ral2JQCrhuEAvxtiuMwx3w,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
MLongnecker-DDmLM1+adcrQT0dZR+AlfA,
swarren-3lzwWm7+Weoh9ZMKESR00Q, mikko.perttunen-/1wQRMveznE,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
[-- Attachment #1: Type: text/plain, Size: 3395 bytes --]
On Tue, Mar 15, 2016 at 02:21:53PM +0800, Wei Ni wrote:
>
>
> On 2016年03月15日 04:05, Eduardo Valentin wrote:
> > * PGP Signed by an unknown key
> >
> > On Fri, Mar 11, 2016 at 11:09:14AM +0800, Wei Ni wrote:
> >> Get rid of T124-specific PDIV/HOTSPOT hack.
> >> tegra-soctherm.c contained a hack to set the SENSOR_PDIV and
> >> SENSOR_HOTSPOT_OFFSET registers - it just did two writes of
> >> T124-specific opaque values. Convert these into a form that can be
> >> substituted on a per-chip basis, and into structure fields that have
> >> at least some independent meaning.
> >>
> >> Signed-off-by: Wei Ni <wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
> >> ---
> >> drivers/thermal/tegra/tegra-soctherm.c | 18 ++++++++++++++----
> >> 1 file changed, 14 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
> >> index b3ec0faa2bee..b4b791ebfbb6 100644
> >> --- a/drivers/thermal/tegra/tegra-soctherm.c
> >> +++ b/drivers/thermal/tegra/tegra-soctherm.c
> >> @@ -48,14 +48,12 @@
> >> #define SENSOR_CONFIG2_THERMB_SHIFT 0
> >>
> >> #define SENSOR_PDIV 0x1c0
> >> -#define SENSOR_PDIV_T124 0x8888
> >> #define SENSOR_PDIV_CPU_MASK (0xf << 12)
> >> #define SENSOR_PDIV_GPU_MASK (0xf << 8)
> >> #define SENSOR_PDIV_MEM_MASK (0xf << 4)
> >> #define SENSOR_PDIV_PLLX_MASK (0xf << 0)
> >>
> >> #define SENSOR_HOTSPOT_OFF 0x1c4
> >> -#define SENSOR_HOTSPOT_OFF_T124 0x00060600
> >> #define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
> >> #define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
> >> #define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
> >> @@ -436,6 +434,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
> >> struct resource *res;
> >> unsigned int i;
> >> int err;
> >> + u32 pdiv, hotspot;
> >>
> >> const struct tegra_tsensor *tsensors = t124_tsensors;
> >> const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
> >> @@ -493,8 +492,19 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
> >> goto disable_clocks;
> >> }
> >>
> >> - writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
> >> - writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
> >> + /* Program pdiv and hotspot offsets per THERM */
> >> + pdiv = readl(tegra->regs + SENSOR_PDIV);
> >> + hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
> >> + for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
> >> + pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
> >> + ttgs[i]->pdiv);
> >> + if (ttgs[i]->id != TEGRA124_SOCTHERM_SENSOR_PLLX)
> >> + hotspot = REG_SET_MASK(hotspot,
> >> + ttgs[i]->pllx_hotspot_mask,
> >> + ttgs[i]->pllx_hotspot_diff);
> >> + }
> >> + writel(pdiv, tegra->regs + SENSOR_PDIV);
> >> + writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
> >
> > Is the above logic the same for all supported chips? e.g. do we always
> > skip pllx for hotspot configuration?
>
> Yes, this logic support Tegra124, Tegra210, and Tegra132 which I will send out
> in next series.
Ok. Could you please add a comment then explaining why pllx is not
needed for the hotspot configuration?
>
> >
> >
> >>
> >> /* Initialize thermctl sensors */
> >>
> >> --
> >> 1.9.1
> >>
> >
> > * Unknown Key
> > * 0x7DA4E256
> >
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 473 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 03/12] thermal: tegra: get rid of PDIV/HOTSPOT hack
@ 2016-03-15 19:56 ` Eduardo Valentin
0 siblings, 0 replies; 25+ messages in thread
From: Eduardo Valentin @ 2016-03-15 19:56 UTC (permalink / raw)
To: Wei Ni
Cc: rui.zhang, thierry.reding, MLongnecker, swarren, mikko.perttunen,
linux-tegra, linux-pm, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 3366 bytes --]
On Tue, Mar 15, 2016 at 02:21:53PM +0800, Wei Ni wrote:
>
>
> On 2016年03月15日 04:05, Eduardo Valentin wrote:
> > * PGP Signed by an unknown key
> >
> > On Fri, Mar 11, 2016 at 11:09:14AM +0800, Wei Ni wrote:
> >> Get rid of T124-specific PDIV/HOTSPOT hack.
> >> tegra-soctherm.c contained a hack to set the SENSOR_PDIV and
> >> SENSOR_HOTSPOT_OFFSET registers - it just did two writes of
> >> T124-specific opaque values. Convert these into a form that can be
> >> substituted on a per-chip basis, and into structure fields that have
> >> at least some independent meaning.
> >>
> >> Signed-off-by: Wei Ni <wni@nvidia.com>
> >> ---
> >> drivers/thermal/tegra/tegra-soctherm.c | 18 ++++++++++++++----
> >> 1 file changed, 14 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
> >> index b3ec0faa2bee..b4b791ebfbb6 100644
> >> --- a/drivers/thermal/tegra/tegra-soctherm.c
> >> +++ b/drivers/thermal/tegra/tegra-soctherm.c
> >> @@ -48,14 +48,12 @@
> >> #define SENSOR_CONFIG2_THERMB_SHIFT 0
> >>
> >> #define SENSOR_PDIV 0x1c0
> >> -#define SENSOR_PDIV_T124 0x8888
> >> #define SENSOR_PDIV_CPU_MASK (0xf << 12)
> >> #define SENSOR_PDIV_GPU_MASK (0xf << 8)
> >> #define SENSOR_PDIV_MEM_MASK (0xf << 4)
> >> #define SENSOR_PDIV_PLLX_MASK (0xf << 0)
> >>
> >> #define SENSOR_HOTSPOT_OFF 0x1c4
> >> -#define SENSOR_HOTSPOT_OFF_T124 0x00060600
> >> #define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
> >> #define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
> >> #define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
> >> @@ -436,6 +434,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
> >> struct resource *res;
> >> unsigned int i;
> >> int err;
> >> + u32 pdiv, hotspot;
> >>
> >> const struct tegra_tsensor *tsensors = t124_tsensors;
> >> const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
> >> @@ -493,8 +492,19 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
> >> goto disable_clocks;
> >> }
> >>
> >> - writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
> >> - writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
> >> + /* Program pdiv and hotspot offsets per THERM */
> >> + pdiv = readl(tegra->regs + SENSOR_PDIV);
> >> + hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
> >> + for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
> >> + pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
> >> + ttgs[i]->pdiv);
> >> + if (ttgs[i]->id != TEGRA124_SOCTHERM_SENSOR_PLLX)
> >> + hotspot = REG_SET_MASK(hotspot,
> >> + ttgs[i]->pllx_hotspot_mask,
> >> + ttgs[i]->pllx_hotspot_diff);
> >> + }
> >> + writel(pdiv, tegra->regs + SENSOR_PDIV);
> >> + writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
> >
> > Is the above logic the same for all supported chips? e.g. do we always
> > skip pllx for hotspot configuration?
>
> Yes, this logic support Tegra124, Tegra210, and Tegra132 which I will send out
> in next series.
Ok. Could you please add a comment then explaining why pllx is not
needed for the hotspot configuration?
>
> >
> >
> >>
> >> /* Initialize thermctl sensors */
> >>
> >> --
> >> 1.9.1
> >>
> >
> > * Unknown Key
> > * 0x7DA4E256
> >
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 473 bytes --]
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 03/12] thermal: tegra: get rid of PDIV/HOTSPOT hack
2016-03-15 19:56 ` Eduardo Valentin
@ 2016-03-16 3:48 ` Wei Ni
-1 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-16 3:48 UTC (permalink / raw)
To: Eduardo Valentin
Cc: rui.zhang, thierry.reding, MLongnecker, swarren, mikko.perttunen,
linux-tegra, linux-pm, linux-kernel
On 2016年03月16日 03:56, Eduardo Valentin wrote:
> * PGP Signed by an unknown key
>
> On Tue, Mar 15, 2016 at 02:21:53PM +0800, Wei Ni wrote:
>>
>>
>> On 2016年03月15日 04:05, Eduardo Valentin wrote:
>>>> Old Signed by an unknown key
>>>
>>> On Fri, Mar 11, 2016 at 11:09:14AM +0800, Wei Ni wrote:
>>>> Get rid of T124-specific PDIV/HOTSPOT hack.
>>>> tegra-soctherm.c contained a hack to set the SENSOR_PDIV and
>>>> SENSOR_HOTSPOT_OFFSET registers - it just did two writes of
>>>> T124-specific opaque values. Convert these into a form that can be
>>>> substituted on a per-chip basis, and into structure fields that have
>>>> at least some independent meaning.
>>>>
>>>> Signed-off-by: Wei Ni <wni@nvidia.com>
>>>> ---
>>>> drivers/thermal/tegra/tegra-soctherm.c | 18 ++++++++++++++----
>>>> 1 file changed, 14 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
>>>> index b3ec0faa2bee..b4b791ebfbb6 100644
>>>> --- a/drivers/thermal/tegra/tegra-soctherm.c
>>>> +++ b/drivers/thermal/tegra/tegra-soctherm.c
>>>> @@ -48,14 +48,12 @@
>>>> #define SENSOR_CONFIG2_THERMB_SHIFT 0
>>>>
>>>> #define SENSOR_PDIV 0x1c0
>>>> -#define SENSOR_PDIV_T124 0x8888
>>>> #define SENSOR_PDIV_CPU_MASK (0xf << 12)
>>>> #define SENSOR_PDIV_GPU_MASK (0xf << 8)
>>>> #define SENSOR_PDIV_MEM_MASK (0xf << 4)
>>>> #define SENSOR_PDIV_PLLX_MASK (0xf << 0)
>>>>
>>>> #define SENSOR_HOTSPOT_OFF 0x1c4
>>>> -#define SENSOR_HOTSPOT_OFF_T124 0x00060600
>>>> #define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
>>>> #define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
>>>> #define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
>>>> @@ -436,6 +434,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
>>>> struct resource *res;
>>>> unsigned int i;
>>>> int err;
>>>> + u32 pdiv, hotspot;
>>>>
>>>> const struct tegra_tsensor *tsensors = t124_tsensors;
>>>> const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
>>>> @@ -493,8 +492,19 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
>>>> goto disable_clocks;
>>>> }
>>>>
>>>> - writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
>>>> - writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
>>>> + /* Program pdiv and hotspot offsets per THERM */
>>>> + pdiv = readl(tegra->regs + SENSOR_PDIV);
>>>> + hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
>>>> + for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
>>>> + pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
>>>> + ttgs[i]->pdiv);
>>>> + if (ttgs[i]->id != TEGRA124_SOCTHERM_SENSOR_PLLX)
>>>> + hotspot = REG_SET_MASK(hotspot,
>>>> + ttgs[i]->pllx_hotspot_mask,
>>>> + ttgs[i]->pllx_hotspot_diff);
>>>> + }
>>>> + writel(pdiv, tegra->regs + SENSOR_PDIV);
>>>> + writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
>>>
>>> Is the above logic the same for all supported chips? e.g. do we always
>>> skip pllx for hotspot configuration?
>>
>> Yes, this logic support Tegra124, Tegra210, and Tegra132 which I will send out
>> in next series.
>
>
> Ok. Could you please add a comment then explaining why pllx is not
> needed for the hotspot configuration?
This is the hotspot offset from PLLX, so we doesn't need to configure for PLLX,
the Tegra DRM introduced it.
I will add comment for it.
>
>>
>>>
>>>
>>>>
>>>> /* Initialize thermctl sensors */
>>>>
>>>> --
>>>> 1.9.1
>>>>
>>>
>>> * Unknown Key
>>> * 0x7DA4E256
>>>
>
> * Unknown Key
> * 0x7DA4E256
>
^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH V7 03/12] thermal: tegra: get rid of PDIV/HOTSPOT hack
@ 2016-03-16 3:48 ` Wei Ni
0 siblings, 0 replies; 25+ messages in thread
From: Wei Ni @ 2016-03-16 3:48 UTC (permalink / raw)
To: Eduardo Valentin
Cc: rui.zhang, thierry.reding, MLongnecker, swarren, mikko.perttunen,
linux-tegra, linux-pm, linux-kernel
On 2016年03月16日 03:56, Eduardo Valentin wrote:
> * PGP Signed by an unknown key
>
> On Tue, Mar 15, 2016 at 02:21:53PM +0800, Wei Ni wrote:
>>
>>
>> On 2016年03月15日 04:05, Eduardo Valentin wrote:
>>>> Old Signed by an unknown key
>>>
>>> On Fri, Mar 11, 2016 at 11:09:14AM +0800, Wei Ni wrote:
>>>> Get rid of T124-specific PDIV/HOTSPOT hack.
>>>> tegra-soctherm.c contained a hack to set the SENSOR_PDIV and
>>>> SENSOR_HOTSPOT_OFFSET registers - it just did two writes of
>>>> T124-specific opaque values. Convert these into a form that can be
>>>> substituted on a per-chip basis, and into structure fields that have
>>>> at least some independent meaning.
>>>>
>>>> Signed-off-by: Wei Ni <wni@nvidia.com>
>>>> ---
>>>> drivers/thermal/tegra/tegra-soctherm.c | 18 ++++++++++++++----
>>>> 1 file changed, 14 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/thermal/tegra/tegra-soctherm.c b/drivers/thermal/tegra/tegra-soctherm.c
>>>> index b3ec0faa2bee..b4b791ebfbb6 100644
>>>> --- a/drivers/thermal/tegra/tegra-soctherm.c
>>>> +++ b/drivers/thermal/tegra/tegra-soctherm.c
>>>> @@ -48,14 +48,12 @@
>>>> #define SENSOR_CONFIG2_THERMB_SHIFT 0
>>>>
>>>> #define SENSOR_PDIV 0x1c0
>>>> -#define SENSOR_PDIV_T124 0x8888
>>>> #define SENSOR_PDIV_CPU_MASK (0xf << 12)
>>>> #define SENSOR_PDIV_GPU_MASK (0xf << 8)
>>>> #define SENSOR_PDIV_MEM_MASK (0xf << 4)
>>>> #define SENSOR_PDIV_PLLX_MASK (0xf << 0)
>>>>
>>>> #define SENSOR_HOTSPOT_OFF 0x1c4
>>>> -#define SENSOR_HOTSPOT_OFF_T124 0x00060600
>>>> #define SENSOR_HOTSPOT_CPU_MASK (0xff << 16)
>>>> #define SENSOR_HOTSPOT_GPU_MASK (0xff << 8)
>>>> #define SENSOR_HOTSPOT_MEM_MASK (0xff << 0)
>>>> @@ -436,6 +434,7 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
>>>> struct resource *res;
>>>> unsigned int i;
>>>> int err;
>>>> + u32 pdiv, hotspot;
>>>>
>>>> const struct tegra_tsensor *tsensors = t124_tsensors;
>>>> const struct tegra_tsensor_group **ttgs = tegra124_tsensor_groups;
>>>> @@ -493,8 +492,19 @@ static int tegra_soctherm_probe(struct platform_device *pdev)
>>>> goto disable_clocks;
>>>> }
>>>>
>>>> - writel(SENSOR_PDIV_T124, tegra->regs + SENSOR_PDIV);
>>>> - writel(SENSOR_HOTSPOT_OFF_T124, tegra->regs + SENSOR_HOTSPOT_OFF);
>>>> + /* Program pdiv and hotspot offsets per THERM */
>>>> + pdiv = readl(tegra->regs + SENSOR_PDIV);
>>>> + hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
>>>> + for (i = 0; i < TEGRA124_SOCTHERM_SENSOR_NUM; ++i) {
>>>> + pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
>>>> + ttgs[i]->pdiv);
>>>> + if (ttgs[i]->id != TEGRA124_SOCTHERM_SENSOR_PLLX)
>>>> + hotspot = REG_SET_MASK(hotspot,
>>>> + ttgs[i]->pllx_hotspot_mask,
>>>> + ttgs[i]->pllx_hotspot_diff);
>>>> + }
>>>> + writel(pdiv, tegra->regs + SENSOR_PDIV);
>>>> + writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
>>>
>>> Is the above logic the same for all supported chips? e.g. do we always
>>> skip pllx for hotspot configuration?
>>
>> Yes, this logic support Tegra124, Tegra210, and Tegra132 which I will send out
>> in next series.
>
>
> Ok. Could you please add a comment then explaining why pllx is not
> needed for the hotspot configuration?
This is the hotspot offset from PLLX, so we doesn't need to configure for PLLX,
the Tegra DRM introduced it.
I will add comment for it.
>
>>
>>>
>>>
>>>>
>>>> /* Initialize thermctl sensors */
>>>>
>>>> --
>>>> 1.9.1
>>>>
>>>
>>> * Unknown Key
>>> * 0x7DA4E256
>>>
>
> * Unknown Key
> * 0x7DA4E256
>
^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2016-03-16 3:48 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-03-11 3:09 [PATCH V7 00/12] Add T210 support in Tegra soctherm Wei Ni
2016-03-11 3:09 ` Wei Ni
2016-03-11 3:09 ` [PATCH V7 01/12] thermal: tegra: move tegra thermal files into tegra directory Wei Ni
2016-03-11 3:09 ` Wei Ni
[not found] ` <1457665763-29781-2-git-send-email-wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-03-14 18:37 ` Eduardo Valentin
2016-03-14 18:37 ` Eduardo Valentin
[not found] ` <20160314183736.GA5378-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
2016-03-15 6:17 ` Wei Ni
2016-03-15 6:17 ` Wei Ni
2016-03-11 3:09 ` [PATCH V7 02/12] thermal: tegra: combine sensor group-related data Wei Ni
2016-03-11 3:09 ` Wei Ni
2016-03-11 3:09 ` [PATCH V7 03/12] thermal: tegra: get rid of PDIV/HOTSPOT hack Wei Ni
2016-03-11 3:09 ` Wei Ni
2016-03-14 20:05 ` Eduardo Valentin
[not found] ` <20160314200539.GH1872-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
2016-03-15 6:21 ` Wei Ni
2016-03-15 6:21 ` Wei Ni
[not found] ` <56E7AA01.4000305-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-03-15 19:56 ` Eduardo Valentin
2016-03-15 19:56 ` Eduardo Valentin
2016-03-16 3:48 ` Wei Ni
2016-03-16 3:48 ` Wei Ni
[not found] ` <1457665763-29781-1-git-send-email-wni-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-03-11 3:09 ` [PATCH V7 04/12] thermal: tegra: split tegra_soctherm driver Wei Ni
2016-03-11 3:09 ` Wei Ni
2016-03-14 21:01 ` [PATCH V7 00/12] Add T210 support in Tegra soctherm Eduardo Valentin
2016-03-14 21:01 ` Eduardo Valentin
[not found] ` <20160314210152.GA4717-bi+AKbBUZKY6gyzm1THtWbp2dZbC/Bob@public.gmane.org>
2016-03-15 5:46 ` Wei Ni
2016-03-15 5:46 ` Wei Ni
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