* [U-Boot] [UBOOT PATCH v1 0/2] Add ACPI table support on Minnowmax
@ 2015-08-30 0:10 Saket Sinha
2015-08-30 0:10 ` [U-Boot] [UBOOT PATCH v1 1/2] x86: Add ACPI table support to Minnowmax Saket Sinha
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Saket Sinha @ 2015-08-30 0:10 UTC (permalink / raw)
To: u-boot
This series adds ACPI table support on Minnowmax.
Saket Sinha (2):
x86: Add ACPI table support to Minnowmax
x86: Add DSDT table for supporting ACPI on Minnowmax
board/intel/minnowmax/Makefile | 1 +
board/intel/minnowmax/acpi.c | 234 +++++++++++++++++++++++
board/intel/minnowmax/acpi/cpu.asl | 65 +++++++
board/intel/minnowmax/acpi/device_nvs.asl | 75 ++++++++
board/intel/minnowmax/acpi/globalnvs.asl | 88 +++++++++
board/intel/minnowmax/acpi/mainboard.asl | 13 ++
board/intel/minnowmax/acpi/platform.asl | 62 ++++++
board/intel/minnowmax/acpi/sleepstates.asl | 14 ++
board/intel/minnowmax/acpi/southcluster.asl | 286 ++++++++++++++++++++++++++++
board/intel/minnowmax/dsdt.asl | 46 +++++
10 files changed, 884 insertions(+)
create mode 100644 board/intel/minnowmax/acpi.c
create mode 100644 board/intel/minnowmax/acpi/cpu.asl
create mode 100644 board/intel/minnowmax/acpi/device_nvs.asl
create mode 100644 board/intel/minnowmax/acpi/globalnvs.asl
create mode 100644 board/intel/minnowmax/acpi/mainboard.asl
create mode 100644 board/intel/minnowmax/acpi/platform.asl
create mode 100644 board/intel/minnowmax/acpi/sleepstates.asl
create mode 100644 board/intel/minnowmax/acpi/southcluster.asl
create mode 100644 board/intel/minnowmax/dsdt.asl
--
2.1.4
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [UBOOT PATCH v1 1/2] x86: Add ACPI table support to Minnowmax
2015-08-30 0:10 [U-Boot] [UBOOT PATCH v1 0/2] Add ACPI table support on Minnowmax Saket Sinha
@ 2015-08-30 0:10 ` Saket Sinha
2015-08-31 3:26 ` Bin Meng
2015-08-30 0:10 ` [U-Boot] [UBOOT PATCH v1 2/2] x86: Add DSDT table for supporting ACPI on Minnowmax Saket Sinha
2016-03-18 12:01 ` [U-Boot] [UBOOT PATCH v1 0/2] Add ACPI table support " Stefan Roese
2 siblings, 1 reply; 8+ messages in thread
From: Saket Sinha @ 2015-08-30 0:10 UTC (permalink / raw)
To: u-boot
This patch mainly adds ACPI support to Minnowmax.
Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
---
board/intel/minnowmax/Makefile | 1 +
board/intel/minnowmax/acpi.c | 234 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 235 insertions(+)
create mode 100644 board/intel/minnowmax/acpi.c
diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile
index 1a61432..11f020a 100644
--- a/board/intel/minnowmax/Makefile
+++ b/board/intel/minnowmax/Makefile
@@ -5,3 +5,4 @@
#
obj-y += minnowmax.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
diff --git a/board/intel/minnowmax/acpi.c b/board/intel/minnowmax/acpi.c
new file mode 100644
index 0000000..206af30
--- /dev/null
+++ b/board/intel/minnowmax/acpi.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/acpi_table.h>
+#include <asm/ioapic.h>
+#include <asm/tables.h>
+
+#define ILB_BASE_ADDRESS 0xfed08000
+/* These registers live behind the ILB_BASE_ADDRESS */
+#define ACTL 0x00
+#define SCIS_MASK 0x07
+#define SCIS_IRQ9 0x00
+#define SCIS_IRQ10 0x01
+#define SCIS_IRQ11 0x02
+#define SCIS_IRQ20 0x04
+#define SCIS_IRQ21 0x05
+#define SCIS_IRQ22 0x06
+#define SCIS_IRQ23 0x07
+
+static inline uint32_t read_address(const void *addr)
+{
+ return *(volatile uint32_t *)addr;
+}
+
+int acpi_sci_irq(void)
+{
+ u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
+ int scis;
+ static int sci_irq;
+
+ if (sci_irq)
+ return sci_irq;
+
+ /* Determine how SCI is routed. */
+ scis = read_address(actl) & SCIS_MASK;
+ switch (scis) {
+ case SCIS_IRQ9:
+ case SCIS_IRQ10:
+ case SCIS_IRQ11:
+ sci_irq = scis - SCIS_IRQ9 + 9;
+ break;
+ case SCIS_IRQ20:
+ case SCIS_IRQ21:
+ case SCIS_IRQ22:
+ case SCIS_IRQ23:
+ sci_irq = scis - SCIS_IRQ20 + 20;
+ break;
+ default:
+ debug("Invalid SCI route! Defaulting to IRQ9.\n");
+ sci_irq = 9;
+ break;
+ }
+
+ debug("SCI is IRQ%d\n", sci_irq);
+ return sci_irq;
+}
+
+unsigned long acpi_madt_irq_overrides(unsigned long current)
+{
+ int sci_irq = acpi_sci_irq();
+ struct acpi_madt_irqoverride *irqovr;
+ uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL;
+
+ /* INT_SRC_OVR */
+ irqovr = (void *)current;
+ current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
+
+ if (sci_irq >= 20)
+ sci_flags |= MP_IRQ_POLARITY_LOW;
+ else
+ sci_flags |= MP_IRQ_POLARITY_HIGH;
+
+ irqovr = (void *)current;
+ current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq,
+ sci_flags);
+
+ return current;
+}
+
+void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
+ void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pm, pmbase;
+
+ pci_dev_t bdf = PCI_BDF(0, 0x1f, 0);
+ pci_read_config_word(bdf, 0x40, &pm);
+ pmbase = pm & 0xfffe;
+ memset((void *)fadt, 0, sizeof(struct acpi_fadt));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(struct acpi_fadt);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 0;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 0x00;
+ fadt->preferred_pm_profile = PM_MOBILE;
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = 0;
+ fadt->acpi_enable = 0;
+ fadt->acpi_disable = 0;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x20;
+ fadt->gpe1_blk = 0;
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 16;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl3_lat = 87;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD |
+ ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER |
+ ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE |
+ ACPI_FADT_PLATFORM_CLOCK;
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.access_size = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.access_size = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 128;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.access_size = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ table_compute_checksum((void *)fadt, header->length);
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
+ 2, IO_APIC_ADDR, 0);
+
+ current = acpi_madt_irq_overrides(current);
+
+ return current;
+}
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ return current;
+}
+
--
2.1.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [UBOOT PATCH v1 2/2] x86: Add DSDT table for supporting ACPI on Minnowmax
2015-08-30 0:10 [U-Boot] [UBOOT PATCH v1 0/2] Add ACPI table support on Minnowmax Saket Sinha
2015-08-30 0:10 ` [U-Boot] [UBOOT PATCH v1 1/2] x86: Add ACPI table support to Minnowmax Saket Sinha
@ 2015-08-30 0:10 ` Saket Sinha
2015-08-31 3:28 ` Bin Meng
2016-03-18 12:01 ` [U-Boot] [UBOOT PATCH v1 0/2] Add ACPI table support " Stefan Roese
2 siblings, 1 reply; 8+ messages in thread
From: Saket Sinha @ 2015-08-30 0:10 UTC (permalink / raw)
To: u-boot
The DSDT table contains a bytecode that is executed by a driver in the kernel.
Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
---
board/intel/minnowmax/Makefile | 2 +-
board/intel/minnowmax/acpi/cpu.asl | 65 +++++++
board/intel/minnowmax/acpi/device_nvs.asl | 75 ++++++++
board/intel/minnowmax/acpi/globalnvs.asl | 88 +++++++++
board/intel/minnowmax/acpi/mainboard.asl | 13 ++
board/intel/minnowmax/acpi/platform.asl | 62 ++++++
board/intel/minnowmax/acpi/sleepstates.asl | 14 ++
board/intel/minnowmax/acpi/southcluster.asl | 286 ++++++++++++++++++++++++++++
board/intel/minnowmax/dsdt.asl | 46 +++++
9 files changed, 650 insertions(+), 1 deletion(-)
create mode 100644 board/intel/minnowmax/acpi/cpu.asl
create mode 100644 board/intel/minnowmax/acpi/device_nvs.asl
create mode 100644 board/intel/minnowmax/acpi/globalnvs.asl
create mode 100644 board/intel/minnowmax/acpi/mainboard.asl
create mode 100644 board/intel/minnowmax/acpi/platform.asl
create mode 100644 board/intel/minnowmax/acpi/sleepstates.asl
create mode 100644 board/intel/minnowmax/acpi/southcluster.asl
create mode 100644 board/intel/minnowmax/dsdt.asl
diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile
index 11f020a..e8d77c8 100644
--- a/board/intel/minnowmax/Makefile
+++ b/board/intel/minnowmax/Makefile
@@ -5,4 +5,4 @@
#
obj-y += minnowmax.o start.o
-obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o
diff --git a/board/intel/minnowmax/acpi/cpu.asl b/board/intel/minnowmax/acpi/cpu.asl
new file mode 100644
index 0000000..13ca8b9
--- /dev/null
+++ b/board/intel/minnowmax/acpi/cpu.asl
@@ -0,0 +1,65 @@
+/*
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * From coreboot.
+ */
+
+/* These devices are created at runtime */
+External (\_PR.CP00, DeviceObj)
+External (\_PR.CP01, DeviceObj)
+External (\_PR.CP02, DeviceObj)
+External (\_PR.CP03, DeviceObj)
+
+/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
+Method (PNOT)
+{
+ If (LGreaterEqual (\PCNT, 2)) {
+ Notify (\_PR.CP00, 0x81) /* _CST */
+ Notify (\_PR.CP01, 0x81) /* _CST */
+ }
+ If (LGreaterEqual (\PCNT, 4)) {
+ Notify (\_PR.CP02, 0x81) /* _CST */
+ Notify (\_PR.CP03, 0x81) /* _CST */
+ }
+}
+
+/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
+Method (PPCN)
+{
+ If (LGreaterEqual (\PCNT, 2)) {
+ Notify (\_PR.CP00, 0x80) /* _PPC */
+ Notify (\_PR.CP01, 0x80) /* _PPC */
+ }
+ If (LGreaterEqual (\PCNT, 4)) {
+ Notify (\_PR.CP02, 0x80) /* _PPC */
+ Notify (\_PR.CP03, 0x80) /* _PPC */
+ }
+}
+
+/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
+Method (TNOT)
+{
+ If (LGreaterEqual (\PCNT, 2)) {
+ Notify (\_PR.CP00, 0x82) /* _TPC */
+ Notify (\_PR.CP01, 0x82) /* _TPC */
+ }
+ If (LGreaterEqual (\PCNT, 4)) {
+ Notify (\_PR.CP02, 0x82) /* _TPC */
+ Notify (\_PR.CP03, 0x82) /* _TPC */
+ }
+}
+
+/* Return a package containing enabled processor entries */
+Method (PPKG)
+{
+ If (LGreaterEqual (\PCNT, 4)) {
+ Return (Package() {\_PR.CP00, \_PR.CP01, \_PR.CP02, \_PR.CP03})
+ } ElseIf (LGreaterEqual (\PCNT, 2)) {
+ Return (Package() {\_PR.CP00, \_PR.CP01})
+ } Else {
+ Return (Package() {\_PR.CP00})
+ }
+}
diff --git a/board/intel/minnowmax/acpi/device_nvs.asl b/board/intel/minnowmax/acpi/device_nvs.asl
new file mode 100644
index 0000000..1fd0eb7
--- /dev/null
+++ b/board/intel/minnowmax/acpi/device_nvs.asl
@@ -0,0 +1,75 @@
+/*
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * From coreboot.
+ */
+
+/* Device Enabled in ACPI Mode */
+
+S0EN, 8, /* SDMA Enable */
+S1EN, 8, /* I2C1 Enable */
+S2EN, 8, /* I2C2 Enable */
+S3EN, 8, /* I2C3 Enable */
+S4EN, 8, /* I2C4 Enable */
+S5EN, 8, /* I2C5 Enable */
+S6EN, 8, /* I2C6 Enable */
+S7EN, 8, /* I2C7 Enable */
+S8EN, 8, /* SDMA2 Enable */
+S9EN, 8, /* SPI Enable */
+SAEN, 8, /* PWM1 Enable */
+SBEN, 8, /* PWM2 Enable */
+SCEN, 8, /* UART2 Enable */
+SDEN, 8, /* UART2 Enable */
+C0EN, 8, /* MMC Enable */
+C1EN, 8, /* SDIO Enable */
+C2EN, 8, /* SD Card Enable */
+LPEN, 8, /* LPE Enable */
+
+/* BAR 0 */
+
+S0B0, 32, /* SDMA BAR0 */
+S1B0, 32, /* I2C1 BAR0 */
+S2B0, 32, /* I2C2 BAR0 */
+S3B0, 32, /* I2C3 BAR0 */
+S4B0, 32, /* I2C4 BAR0 */
+S5B0, 32, /* I2C5 BAR0 */
+S6B0, 32, /* I2C6 BAR0 */
+S7B0, 32, /* I2C7 BAR0 */
+S8B0, 32, /* SDMA2 BAR0 */
+S9B0, 32, /* SPI BAR0 */
+SAB0, 32, /* PWM1 BAR0 */
+SBB0, 32, /* PWM2 BAR0 */
+SCB0, 32, /* UART1 BAR0 */
+SDB0, 32, /* UART2 BAR0 */
+C0B0, 32, /* MMC BAR0 */
+C1B0, 32, /* SDIO BAR0 */
+C2B0, 32, /* SD Card BAR0 */
+LPB0, 32, /* LPE BAR0 */
+
+/* BAR 1 */
+
+S0B1, 32, /* SDMA BAR1 */
+S1B1, 32, /* I2C1 BAR1 */
+S2B1, 32, /* I2C2 BAR1 */
+S3B1, 32, /* I2C3 BAR1 */
+S4B1, 32, /* I2C4 BAR1 */
+S5B1, 32, /* I2C5 BAR1 */
+S6B1, 32, /* I2C6 BAR1 */
+S7B1, 32, /* I2C7 BAR1 */
+S8B1, 32, /* SDMA2 BAR1 */
+S9B1, 32, /* SPI BAR1 */
+SAB1, 32, /* PWM1 BAR1 */
+SBB1, 32, /* PWM2 BAR1 */
+SCB1, 32, /* UART1 BAR1 */
+SDB1, 32, /* UART2 BAR1 */
+C0B1, 32, /* MMC BAR1 */
+C1B1, 32, /* SDIO BAR1 */
+C2B1, 32, /* SD Card BAR1 */
+LPB1, 32, /* LPE BAR1 */
+
+/* Extra */
+
+LPFW, 32, /* LPE BAR2 Firmware */
diff --git a/board/intel/minnowmax/acpi/globalnvs.asl b/board/intel/minnowmax/acpi/globalnvs.asl
new file mode 100644
index 0000000..5112be8
--- /dev/null
+++ b/board/intel/minnowmax/acpi/globalnvs.asl
@@ -0,0 +1,88 @@
+/*
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * From coreboot.
+ */
+
+
+/* Global Variables */
+
+Name(\PICM, 0) /* IOAPIC/8259 */
+
+/* Global ACPI memory region */
+
+External(NVSA)
+OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+ /* Miscellaneous */
+ Offset (0x00),
+ OSYS, 16, /* 0x00 - Operating System */
+ SMIF, 8, /* 0x02 - SMI function */
+ PRM0, 8, /* 0x03 - SMI function parameter */
+ PRM1, 8, /* 0x04 - SMI function parameter */
+ SCIF, 8, /* 0x05 - SCI function */
+ PRM2, 8, /* 0x06 - SCI function parameter */
+ PRM3, 8, /* 0x07 - SCI function parameter */
+ LCKF, 8, /* 0x08 - Global Lock function for EC */
+ PRM4, 8, /* 0x09 - Lock function parameter */
+ PRM5, 8, /* 0x0a - Lock function parameter */
+ P80D, 32, /* 0x0b - Debug port (IO 0x80) value */
+ LIDS, 8, /* 0x0f - LID state (open = 1) */
+ PWRS, 8, /* 0x10 - Power State (AC = 1) */
+ PCNT, 8, /* 0x11 - Processor count */
+ TPMP, 8, /* 0x12 - TPM Present and Enabled
+ TLVL, 8, /* 0x13 - Throttle Level
+ PPCM, 8, /* 0x14 - Maximum P-state usable by OS
+
+ /* Device Config */
+ Offset (0x20),
+ S5U0, 8, /* 0x20 - Enable USB0 in S5 */
+ S5U1, 8, /* 0x21 - Enable USB1 in S5 */
+ S3U0, 8, /* 0x22 - Enable USB0 in S3 */
+ S3U1, 8, /* 0x23 - Enable USB1 in S3 */
+ TACT, 8, /* 0x24 - Thermal Active trip point */
+ TPSV, 8, /* 0x25 - Thermal Passive trip point */
+ TCRT, 8, /* 0x26 - Thermal Critical trip point */
+ DPTE, 8, /* 0x27 - Enable DPTF */
+
+ /* Base addresses */
+ Offset (0x30),
+ CMEM, 32, /* 0x30 - CBMEM TOC */
+ TOLM, 32, /* 0x34 - Top of Low Memory */
+ CBMC, 32, /* 0x38 - coreboot mem console pointer */
+
+ Offset (0x1000),
+ #include "device_nvs.asl"
+}
+
+/* Set flag to enable USB charging in S3 */
+Method (S3UE)
+{
+ Store (One, \S3U0)
+ Store (One, \S3U1)
+}
+
+/* Set flag to disable USB charging in S3 */
+Method (S3UD)
+{
+ Store (Zero, \S3U0)
+ Store (Zero, \S3U1)
+}
+
+/* Set flag to enable USB charging in S5 */
+Method (S5UE)
+{
+ Store (One, \S5U0)
+ Store (One, \S5U1)
+}
+
+/* Set flag to disable USB charging in S5 */
+Method (S5UD)
+{
+ Store (Zero, \S5U0)
+ Store (Zero, \S5U1)
+}
diff --git a/board/intel/minnowmax/acpi/mainboard.asl b/board/intel/minnowmax/acpi/mainboard.asl
new file mode 100644
index 0000000..95d1a0f
--- /dev/null
+++ b/board/intel/minnowmax/acpi/mainboard.asl
@@ -0,0 +1,13 @@
+/*
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * From coreboot.
+ */
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+}
diff --git a/board/intel/minnowmax/acpi/platform.asl b/board/intel/minnowmax/acpi/platform.asl
new file mode 100644
index 0000000..cf84194
--- /dev/null
+++ b/board/intel/minnowmax/acpi/platform.asl
@@ -0,0 +1,62 @@
+/*
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * From coreboot.
+ */
+
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, /* APM command */
+ APMS, 8 /* APM status */
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) /* SMI Function */
+ Store (0, TRP0) /* Generate trap */
+ Return (SMIF) /* Return value of SMI handler */
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration
+ */
+
+Method(_PIC, 1)
+{
+ /* Remember the OS' IRQ routing choice */
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ Return(Package(){0,0})
+}
diff --git a/board/intel/minnowmax/acpi/sleepstates.asl b/board/intel/minnowmax/acpi/sleepstates.asl
new file mode 100644
index 0000000..47bdadf
--- /dev/null
+++ b/board/intel/minnowmax/acpi/sleepstates.asl
@@ -0,0 +1,14 @@
+/*
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * From coreboot.
+ */
+
+
+Name(\_S0, Package(){0x0,0x0,0x0,0x0})
+Name(\_S3, Package(){0x5,0x5,0x0,0x0})
+Name(\_S4, Package(){0x6,0x6,0x0,0x0})
+Name(\_S5, Package(){0x7,0x7,0x0,0x0})
diff --git a/board/intel/minnowmax/acpi/southcluster.asl b/board/intel/minnowmax/acpi/southcluster.asl
new file mode 100644
index 0000000..40560c7
--- /dev/null
+++ b/board/intel/minnowmax/acpi/southcluster.asl
@@ -0,0 +1,286 @@
+/*
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * From coreboot.
+ */
+
+#define ILB_BASE_ADDRESS 0xfed08000
+#define ILB_BASE_SIZE 0x400
+#define MMCONF_BASE_ADDRESS 0xe0000000
+
+#define MCFG_BASE_ADDRESS 0xe0000000
+#define MCFG_BASE_SIZE 0x10000000
+
+/* Transactions in this range will abort */
+#define ABORT_BASE_ADDRESS 0xfeb00000
+#define ABORT_BASE_SIZE 0x00100000
+
+/* Power Management Controller */
+#define PMC_BASE_ADDRESS 0xfed03000
+#define PMC_BASE_SIZE 0x400
+
+/* IO Memory */
+#define IO_BASE_ADDRESS 0xfed0c000
+#define IO_BASE_OFFSET_GPSCORE 0x0000
+#define IO_BASE_OFFSET_GPNCORE 0x1000
+#define IO_BASE_OFFSET_GPSSUS 0x2000
+#define IO_BASE_SIZE 0x4000
+
+/* Intel Legacy Block */
+#define ILB_BASE_ADDRESS 0xfed08000
+#define ILB_BASE_SIZE 0x400
+
+/* SPI Bus */
+#define SPI_BASE_ADDRESS 0xfed01000
+#define SPI_BASE_SIZE 0x400
+
+/* MODPHY */
+#define MPHY_BASE_ADDRESS 0xfef00000
+#define MPHY_BASE_SIZE 0x100000
+
+/* Power Management Unit */
+#define PUNIT_BASE_ADDRESS 0xfed05000
+#define PUNIT_BASE_SIZE 0x800
+
+/* Root Complex Base Address */
+#define RCBA_BASE_ADDRESS 0xfed1c000
+#define RCBA_BASE_SIZE 0x400
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS 0xfed00000
+#define HPET_BASE_SIZE 0x400
+
+/* Temporary Base Address */
+#define TEMP_BASE_ADDRESS 0xfd000000
+
+
+
+
+Scope(\)
+{
+ /* IO-Trap at 0x800. This is the ACPI->SMI communication interface */
+
+ OperationRegion(IO_T, SystemIO, 0x800, 0x10)
+ Field(IO_T, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0x8),
+ TRP0, 8 /* IO-Trap at 0x808 */
+ }
+
+ /* Intel Legacy Block */
+ OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+ Field (ILBS, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x8),
+ PRTA, 8,
+ PRTB, 8,
+ PRTC, 8,
+ PRTD, 8,
+ PRTE, 8,
+ PRTF, 8,
+ PRTG, 8,
+ PRTH, 8,
+ }
+}
+
+Name(_HID,EISAID("PNP0A08")) /* PCIe */
+Name(_CID,EISAID("PNP0A03")) /* PCI */
+
+Name(_ADR, 0)
+Name(_BBN, 0)
+
+Name (MCRS, ResourceTemplate()
+{
+ /* Bus Numbers */
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
+
+ /* IO Region 0 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
+
+ /* PCI Config Space */
+ Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+ /* IO Region 1 */
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
+
+ /* VGA memory (0xa0000-0xbffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+ 0x00020000,,, ASEG)
+
+ /* OPROM reserved (0xc0000-0xc3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+ 0x00004000,,, OPR0)
+
+ /* OPROM reserved (0xc4000-0xc7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+ 0x00004000,,, OPR1)
+
+ /* OPROM reserved (0xc8000-0xcbfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+ 0x00004000,,, OPR2)
+
+ /* OPROM reserved (0xcc000-0xcffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+ 0x00004000,,, OPR3)
+
+ /* OPROM reserved (0xd0000-0xd3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+ 0x00004000,,, OPR4)
+
+ /* OPROM reserved (0xd4000-0xd7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+ 0x00004000,,, OPR5)
+
+ /* OPROM reserved (0xd8000-0xdbfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+ 0x00004000,,, OPR6)
+
+ /* OPROM reserved (0xdc000-0xdffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+ 0x00004000,,, OPR7)
+
+ /* BIOS Extension (0xe0000-0xe3fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+ 0x00004000,,, ESG0)
+
+ /* BIOS Extension (0xe4000-0xe7fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+ 0x00004000,,, ESG1)
+
+ /* BIOS Extension (0xe8000-0xebfff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+ 0x00004000,,, ESG2)
+
+ /* BIOS Extension (0xec000-0xeffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+ 0x00004000,,, ESG3)
+
+ /* System BIOS (0xf0000-0xfffff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+ 0x00010000,,, FSEG)
+
+ /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000,,, PMEM)
+
+ /* TPM Area (0xfed40000-0xfed44fff) */
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+ Cacheable, ReadWrite,
+ 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
+ 0x00005000,,, TPMR)
+})
+
+
+Method (_CRS, 0, Serialized)
+{
+ /* Update PCI resource area */
+ CreateDwordField(MCRS, ^PMEM._MIN, PMIN)
+ CreateDwordField(MCRS, ^PMEM._MAX, PMAX)
+ CreateDwordField(MCRS, ^PMEM._LEN, PLEN)
+
+ /* TOLM is BMBOUND accessible from IOSF so is saved in NVS */
+ Store (\TOLM, PMIN)
+ Store (Subtract(MMCONF_BASE_ADDRESS, 1), PMAX)
+ Add (Subtract (PMAX, PMIN), 1, PLEN)
+
+ Return (MCRS)
+}
+
+/* Device Resource Consumption */
+Device (PDRC)
+{
+ Name (_HID, EISAID("PNP0C02"))
+ Name (_UID, 1)
+
+ Name (PDRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
+ Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE)
+ Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
+ Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
+ Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
+ Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE)
+ Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE)
+ Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE)
+ })
+
+ /* Current Resource Settings */
+ Method (_CRS, 0, Serialized)
+ {
+ Return(PDRS)
+ }
+}
+
+Method (_OSC, 4)
+{
+ /* Check for proper GUID */
+ If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+ {
+ /* Let OS control everything */
+ Return (Arg3)
+ }
+ Else
+ {
+ /* Unrecognized UUID */
+ CreateDWordField (Arg3, 0, CDW1)
+ Or (CDW1, 4, CDW1)
+ Return (Arg3)
+ }
+}
+
+/* IOSF MBI Interface for kernel access */
+Device (IOSF)
+{
+ Name (_HID, "INT33BD")
+ Name (_CID, "INT33BD")
+ Name (_UID, 1)
+
+ Name (RBUF, ResourceTemplate ()
+ {
+ /* MCR / MDR / MCRX */
+ Memory32Fixed (ReadWrite, 0, 12, RBAR)
+ })
+
+ Method (_CRS)
+ {
+ CreateDwordField (^RBUF, ^RBAR._BAS, RBAS)
+ Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS)
+ Return (^RBUF)
+ }
+}
+
diff --git a/board/intel/minnowmax/dsdt.asl b/board/intel/minnowmax/dsdt.asl
new file mode 100644
index 0000000..4fac14c
--- /dev/null
+++ b/board/intel/minnowmax/dsdt.asl
@@ -0,0 +1,46 @@
+/*
+ * Minnowmax ACPI DSDT ASL definition
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * Based on baytrail/dsdt.asl from coreboot
+ */
+
+#define INCLUDE_LPE 1
+#define INCLUDE_SCC 1
+#define INCLUDE_EHCI 1
+#define INCLUDE_XHCI 1
+#define INCLUDE_LPSS 1
+
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI v2.0 */
+ "COREv4", /* OEM id */
+ "UBOOT", /* OEM table id */
+ 0x20110725 /* OEM revision */
+)
+{
+ /* Some generic macros */
+ #include "acpi/platform.asl"
+
+ /* global NVS and variables */
+ #include "acpi/globalnvs.asl"
+
+ #include "acpi/cpu.asl"
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include "acpi/southcluster.asl"
+ }
+ }
+ /* Chipset specific sleep states */
+ #include "acpi/sleepstates.asl"
+
+ #include "acpi/mainboard.asl"
+}
+
--
2.1.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [U-Boot] [UBOOT PATCH v1 1/2] x86: Add ACPI table support to Minnowmax
2015-08-30 0:10 ` [U-Boot] [UBOOT PATCH v1 1/2] x86: Add ACPI table support to Minnowmax Saket Sinha
@ 2015-08-31 3:26 ` Bin Meng
0 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2015-08-31 3:26 UTC (permalink / raw)
To: u-boot
Hi Saket,
On Sun, Aug 30, 2015 at 8:10 AM, Saket Sinha <saket.sinha89@gmail.com> wrote:
> This patch mainly adds ACPI support to Minnowmax.
>
> Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
> ---
>
> board/intel/minnowmax/Makefile | 1 +
> board/intel/minnowmax/acpi.c | 234 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 235 insertions(+)
> create mode 100644 board/intel/minnowmax/acpi.c
>
> diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile
> index 1a61432..11f020a 100644
> --- a/board/intel/minnowmax/Makefile
> +++ b/board/intel/minnowmax/Makefile
> @@ -5,3 +5,4 @@
> #
>
> obj-y += minnowmax.o start.o
> +obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o
> diff --git a/board/intel/minnowmax/acpi.c b/board/intel/minnowmax/acpi.c
> new file mode 100644
> index 0000000..206af30
> --- /dev/null
> +++ b/board/intel/minnowmax/acpi.c
> @@ -0,0 +1,234 @@
> +/*
> + * Copyright (C) 2015, Saket Sinha <saket.sinha89@gmail.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/acpi_table.h>
> +#include <asm/ioapic.h>
> +#include <asm/tables.h>
> +
> +#define ILB_BASE_ADDRESS 0xfed08000
Please don't hardcode this. Instead, read its value from the
configuration space.
> +/* These registers live behind the ILB_BASE_ADDRESS */
> +#define ACTL 0x00
See arch/x86/include/asm/arch-baytrail/baytrail.h, we have struct
byt_ibase already.
> +#define SCIS_MASK 0x07
> +#define SCIS_IRQ9 0x00
> +#define SCIS_IRQ10 0x01
> +#define SCIS_IRQ11 0x02
> +#define SCIS_IRQ20 0x04
> +#define SCIS_IRQ21 0x05
> +#define SCIS_IRQ22 0x06
> +#define SCIS_IRQ23 0x07
Please move these to arch/x86/include/asm/arch-baytrail/baytrail.h
> +
> +static inline uint32_t read_address(const void *addr)
> +{
> + return *(volatile uint32_t *)addr;
> +}
> +
It looks like debug codes. Please remove.
> +int acpi_sci_irq(void)
> +{
> + u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
Please convert to use C struct to access ACTL.
> + int scis;
> + static int sci_irq;
> +
> + if (sci_irq)
> + return sci_irq;
> +
> + /* Determine how SCI is routed. */
> + scis = read_address(actl) & SCIS_MASK;
> + switch (scis) {
> + case SCIS_IRQ9:
> + case SCIS_IRQ10:
> + case SCIS_IRQ11:
> + sci_irq = scis - SCIS_IRQ9 + 9;
> + break;
> + case SCIS_IRQ20:
> + case SCIS_IRQ21:
> + case SCIS_IRQ22:
> + case SCIS_IRQ23:
> + sci_irq = scis - SCIS_IRQ20 + 20;
> + break;
> + default:
> + debug("Invalid SCI route! Defaulting to IRQ9.\n");
> + sci_irq = 9;
> + break;
> + }
> +
> + debug("SCI is IRQ%d\n", sci_irq);
> + return sci_irq;
> +}
> +
> +unsigned long acpi_madt_irq_overrides(unsigned long current)
> +{
> + int sci_irq = acpi_sci_irq();
> + struct acpi_madt_irqoverride *irqovr;
> + uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL;
> +
> + /* INT_SRC_OVR */
> + irqovr = (void *)current;
> + current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0);
> +
> + if (sci_irq >= 20)
> + sci_flags |= MP_IRQ_POLARITY_LOW;
> + else
> + sci_flags |= MP_IRQ_POLARITY_HIGH;
> +
> + irqovr = (void *)current;
> + current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq,
> + sci_flags);
> +
> + return current;
> +}
> +
> +void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
> + void *dsdt)
> +{
> + acpi_header_t *header = &(fadt->header);
> + u16 pm, pmbase;
> +
> + pci_dev_t bdf = PCI_BDF(0, 0x1f, 0);
> + pci_read_config_word(bdf, 0x40, &pm);
Please define something meaningful for 0x40.
> + pmbase = pm & 0xfffe;
> + memset((void *)fadt, 0, sizeof(struct acpi_fadt));
> + memcpy(header->signature, "FACP", 4);
> + header->length = sizeof(struct acpi_fadt);
> + header->revision = 3;
> + memcpy(header->oem_id, OEM_ID, 6);
> + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
> + memcpy(header->asl_compiler_id, ASLC, 4);
> + header->asl_compiler_revision = 0;
> +
> + fadt->firmware_ctrl = (unsigned long) facs;
> + fadt->dsdt = (unsigned long) dsdt;
> + fadt->model = 0x00;
> + fadt->preferred_pm_profile = PM_MOBILE;
> + fadt->sci_int = 0x9;
> + fadt->smi_cmd = 0;
> + fadt->acpi_enable = 0;
> + fadt->acpi_disable = 0;
> + fadt->s4bios_req = 0x0;
> + fadt->pstate_cnt = 0;
> + fadt->pm1a_evt_blk = pmbase;
> + fadt->pm1b_evt_blk = 0x0;
> + fadt->pm1a_cnt_blk = pmbase + 0x4;
> + fadt->pm1b_cnt_blk = 0x0;
> + fadt->pm2_cnt_blk = pmbase + 0x50;
> + fadt->pm_tmr_blk = pmbase + 0x8;
> + fadt->gpe0_blk = pmbase + 0x20;
> + fadt->gpe1_blk = 0;
> + fadt->pm1_evt_len = 4;
> + fadt->pm1_cnt_len = 2;
> + fadt->pm2_cnt_len = 1;
> + fadt->pm_tmr_len = 4;
> + fadt->gpe0_blk_len = 16;
> + fadt->gpe1_blk_len = 0;
> + fadt->gpe1_base = 0;
> + fadt->cst_cnt = 0;
> + fadt->p_lvl3_lat = 87;
> + fadt->flush_size = 1024;
> + fadt->flush_stride = 16;
> + fadt->duty_offset = 1;
> + fadt->day_alrm = 0xd;
> + fadt->mon_alrm = 0x00;
> + fadt->century = 0x00;
> + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
> +
> + fadt->flags = ACPI_FADT_WBINVD |
> + ACPI_FADT_C1_SUPPORTED |
> + ACPI_FADT_SLEEP_BUTTON |
> + ACPI_FADT_RESET_REGISTER |
> + ACPI_FADT_SEALED_CASE |
> + ACPI_FADT_S4_RTC_WAKE |
> + ACPI_FADT_PLATFORM_CLOCK;
> + fadt->reset_reg.space_id = 1;
> + fadt->reset_reg.bit_width = 8;
> + fadt->reset_reg.bit_offset = 0;
> + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
> + fadt->reset_reg.addrl = 0xcf9;
> + fadt->reset_reg.addrh = 0;
> + fadt->reset_value = 6;
> + fadt->x_firmware_ctl_l = (unsigned long)facs;
> + fadt->x_firmware_ctl_h = 0;
> + fadt->x_dsdt_l = (unsigned long)dsdt;
> + fadt->x_dsdt_h = 0;
> +
> + fadt->x_pm1a_evt_blk.space_id = 1;
> + fadt->x_pm1a_evt_blk.bit_width = 32;
> + fadt->x_pm1a_evt_blk.bit_offset = 0;
> + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
> + fadt->x_pm1a_evt_blk.addrl = pmbase;
> + fadt->x_pm1a_evt_blk.addrh = 0x0;
> +
> + fadt->x_pm1b_evt_blk.space_id = 1;
> + fadt->x_pm1b_evt_blk.bit_width = 0;
> + fadt->x_pm1b_evt_blk.bit_offset = 0;
> + fadt->x_pm1b_evt_blk.access_size = 0;
> + fadt->x_pm1b_evt_blk.addrl = 0x0;
> + fadt->x_pm1b_evt_blk.addrh = 0x0;
> +
> + fadt->x_pm1a_cnt_blk.space_id = 1;
> + fadt->x_pm1a_cnt_blk.bit_width = 16;
> + fadt->x_pm1a_cnt_blk.bit_offset = 0;
> + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
> + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
> + fadt->x_pm1a_cnt_blk.addrh = 0x0;
> +
> + fadt->x_pm1b_cnt_blk.space_id = 1;
> + fadt->x_pm1b_cnt_blk.bit_width = 0;
> + fadt->x_pm1b_cnt_blk.bit_offset = 0;
> + fadt->x_pm1b_cnt_blk.access_size = 0;
> + fadt->x_pm1b_cnt_blk.addrl = 0x0;
> + fadt->x_pm1b_cnt_blk.addrh = 0x0;
> +
> + fadt->x_pm2_cnt_blk.space_id = 1;
> + fadt->x_pm2_cnt_blk.bit_width = 8;
> + fadt->x_pm2_cnt_blk.bit_offset = 0;
> + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
> + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
> + fadt->x_pm2_cnt_blk.addrh = 0x0;
> +
> + fadt->x_pm_tmr_blk.space_id = 1;
> + fadt->x_pm_tmr_blk.bit_width = 32;
> + fadt->x_pm_tmr_blk.bit_offset = 0;
> + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
> + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
> + fadt->x_pm_tmr_blk.addrh = 0x0;
> +
> + fadt->x_gpe0_blk.space_id = 1;
> + fadt->x_gpe0_blk.bit_width = 128;
> + fadt->x_gpe0_blk.bit_offset = 0;
> + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
> + fadt->x_gpe0_blk.addrl = pmbase + 0x20;
> + fadt->x_gpe0_blk.addrh = 0x0;
> +
> + fadt->x_gpe1_blk.space_id = 1;
> + fadt->x_gpe1_blk.bit_width = 0;
> + fadt->x_gpe1_blk.bit_offset = 0;
> + fadt->x_gpe1_blk.access_size = 0;
> + fadt->x_gpe1_blk.addrl = 0x0;
> + fadt->x_gpe1_blk.addrh = 0x0;
> +
> + header->checksum =
> + table_compute_checksum((void *)fadt, header->length);
> +}
> +
> +unsigned long acpi_fill_madt(unsigned long current)
> +{
> + /* create all subtables for processors */
> + current = acpi_create_madt_lapics(current);
> +
> + /* IOAPIC */
> + current += acpi_create_madt_ioapic((struct acpi_madt_ioapic *)current,
> + 2, IO_APIC_ADDR, 0);
> +
> + current = acpi_madt_irq_overrides(current);
> +
> + return current;
> +}
> +
> +unsigned long acpi_fill_mcfg(unsigned long current)
> +{
> + return current;
> +}
> +
> --
Regards,
Bin
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [UBOOT PATCH v1 2/2] x86: Add DSDT table for supporting ACPI on Minnowmax
2015-08-30 0:10 ` [U-Boot] [UBOOT PATCH v1 2/2] x86: Add DSDT table for supporting ACPI on Minnowmax Saket Sinha
@ 2015-08-31 3:28 ` Bin Meng
2015-08-31 4:28 ` Saket Sinha
0 siblings, 1 reply; 8+ messages in thread
From: Bin Meng @ 2015-08-31 3:28 UTC (permalink / raw)
To: u-boot
Hi Saket,
On Sun, Aug 30, 2015 at 8:10 AM, Saket Sinha <saket.sinha89@gmail.com> wrote:
> The DSDT table contains a bytecode that is executed by a driver in the kernel.
>
> Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
> ---
>
What tests have you run with ACPI on MinnowMax? And any errors did you see?
[snip]
Regards,
Bin
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [UBOOT PATCH v1 2/2] x86: Add DSDT table for supporting ACPI on Minnowmax
2015-08-31 3:28 ` Bin Meng
@ 2015-08-31 4:28 ` Saket Sinha
0 siblings, 0 replies; 8+ messages in thread
From: Saket Sinha @ 2015-08-31 4:28 UTC (permalink / raw)
To: u-boot
Hi Bin,
On Mon, Aug 31, 2015 at 8:58 AM, Bin Meng <bmeng.cn@gmail.com> wrote:
> Hi Saket,
>
> On Sun, Aug 30, 2015 at 8:10 AM, Saket Sinha <saket.sinha89@gmail.com> wrote:
>> The DSDT table contains a bytecode that is executed by a driver in the kernel.
>>
>> Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
>> ---
>>
>And any errors did you see?
>
I am getting PCI configuration errors on Minnowmax similar to those we
have on QEMU. I am trying to solve them.
>
> What tests have you run with ACPI on MinnowMax?
I am fixing the errors first before going into testing. The first step
is to let Linux parse the ACPI table without any errors. Then we can
go into the testing aspect for different power stages.
Regards,
Saket Sinha
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [UBOOT PATCH v1 0/2] Add ACPI table support on Minnowmax
2015-08-30 0:10 [U-Boot] [UBOOT PATCH v1 0/2] Add ACPI table support on Minnowmax Saket Sinha
2015-08-30 0:10 ` [U-Boot] [UBOOT PATCH v1 1/2] x86: Add ACPI table support to Minnowmax Saket Sinha
2015-08-30 0:10 ` [U-Boot] [UBOOT PATCH v1 2/2] x86: Add DSDT table for supporting ACPI on Minnowmax Saket Sinha
@ 2016-03-18 12:01 ` Stefan Roese
2016-03-21 9:15 ` Bin Meng
2 siblings, 1 reply; 8+ messages in thread
From: Stefan Roese @ 2016-03-18 12:01 UTC (permalink / raw)
To: u-boot
Hi Saket,
On 30.08.2015 02:10, Saket Sinha wrote:
> This series adds ACPI table support on Minnowmax.
>
> Saket Sinha (2):
> x86: Add ACPI table support to Minnowmax
> x86: Add DSDT table for supporting ACPI on Minnowmax
>
> board/intel/minnowmax/Makefile | 1 +
> board/intel/minnowmax/acpi.c | 234 +++++++++++++++++++++++
> board/intel/minnowmax/acpi/cpu.asl | 65 +++++++
> board/intel/minnowmax/acpi/device_nvs.asl | 75 ++++++++
> board/intel/minnowmax/acpi/globalnvs.asl | 88 +++++++++
> board/intel/minnowmax/acpi/mainboard.asl | 13 ++
> board/intel/minnowmax/acpi/platform.asl | 62 ++++++
> board/intel/minnowmax/acpi/sleepstates.asl | 14 ++
> board/intel/minnowmax/acpi/southcluster.asl | 286 ++++++++++++++++++++++++++++
> board/intel/minnowmax/dsdt.asl | 46 +++++
> 10 files changed, 884 insertions(+)
> create mode 100644 board/intel/minnowmax/acpi.c
> create mode 100644 board/intel/minnowmax/acpi/cpu.asl
> create mode 100644 board/intel/minnowmax/acpi/device_nvs.asl
> create mode 100644 board/intel/minnowmax/acpi/globalnvs.asl
> create mode 100644 board/intel/minnowmax/acpi/mainboard.asl
> create mode 100644 board/intel/minnowmax/acpi/platform.asl
> create mode 100644 board/intel/minnowmax/acpi/sleepstates.asl
> create mode 100644 board/intel/minnowmax/acpi/southcluster.asl
> create mode 100644 board/intel/minnowmax/dsdt.asl
I'm interested in ACPI support for BayTrail (e.g. MinnowMAX). And
noticed that you didn't follow up on this MinnowMAX ACPI support
thread. In another patchset by Miao (added to Cc), ACPI support has
now been added for QEMU already:
https://www.mail-archive.com/u-boot at lists.denx.de/msg200312.html
So what is the current status of ACPI for x86 in U-Boot? Is someone
currently working on BayTrail / MinnowMAX ACPI support? If yes,
please let me know so that we can combine our efforts. If not, please
give me some hints on how to best start / continue here. Why did this
patchset from Saket not make it into mainline? What are the main
flaws / problems?
Any hints or suggestions welcome! :)
Thanks,
Stefan
^ permalink raw reply [flat|nested] 8+ messages in thread
* [U-Boot] [UBOOT PATCH v1 0/2] Add ACPI table support on Minnowmax
2016-03-18 12:01 ` [U-Boot] [UBOOT PATCH v1 0/2] Add ACPI table support " Stefan Roese
@ 2016-03-21 9:15 ` Bin Meng
0 siblings, 0 replies; 8+ messages in thread
From: Bin Meng @ 2016-03-21 9:15 UTC (permalink / raw)
To: u-boot
Hi Stefan,
On Fri, Mar 18, 2016 at 8:01 PM, Stefan Roese <sr@denx.de> wrote:
> Hi Saket,
>
>
> On 30.08.2015 02:10, Saket Sinha wrote:
>>
>> This series adds ACPI table support on Minnowmax.
>>
>> Saket Sinha (2):
>> x86: Add ACPI table support to Minnowmax
>> x86: Add DSDT table for supporting ACPI on Minnowmax
>>
>> board/intel/minnowmax/Makefile | 1 +
>> board/intel/minnowmax/acpi.c | 234
>> +++++++++++++++++++++++
>> board/intel/minnowmax/acpi/cpu.asl | 65 +++++++
>> board/intel/minnowmax/acpi/device_nvs.asl | 75 ++++++++
>> board/intel/minnowmax/acpi/globalnvs.asl | 88 +++++++++
>> board/intel/minnowmax/acpi/mainboard.asl | 13 ++
>> board/intel/minnowmax/acpi/platform.asl | 62 ++++++
>> board/intel/minnowmax/acpi/sleepstates.asl | 14 ++
>> board/intel/minnowmax/acpi/southcluster.asl | 286
>> ++++++++++++++++++++++++++++
>> board/intel/minnowmax/dsdt.asl | 46 +++++
>> 10 files changed, 884 insertions(+)
>> create mode 100644 board/intel/minnowmax/acpi.c
>> create mode 100644 board/intel/minnowmax/acpi/cpu.asl
>> create mode 100644 board/intel/minnowmax/acpi/device_nvs.asl
>> create mode 100644 board/intel/minnowmax/acpi/globalnvs.asl
>> create mode 100644 board/intel/minnowmax/acpi/mainboard.asl
>> create mode 100644 board/intel/minnowmax/acpi/platform.asl
>> create mode 100644 board/intel/minnowmax/acpi/sleepstates.asl
>> create mode 100644 board/intel/minnowmax/acpi/southcluster.asl
>> create mode 100644 board/intel/minnowmax/dsdt.asl
>
>
> I'm interested in ACPI support for BayTrail (e.g. MinnowMAX). And
> noticed that you didn't follow up on this MinnowMAX ACPI support
> thread. In another patchset by Miao (added to Cc), ACPI support has
> now been added for QEMU already:
>
> https://www.mail-archive.com/u-boot at lists.denx.de/msg200312.html
>
> So what is the current status of ACPI for x86 in U-Boot? Is someone
So far the only working ACPI support for x86 in U-Boot is QEMU, with fw_cfg.
> currently working on BayTrail / MinnowMAX ACPI support? If yes,
> please let me know so that we can combine our efforts. If not, please
> give me some hints on how to best start / continue here. Why did this
> patchset from Saket not make it into mainline? What are the main
> flaws / problems?
Saket's patch does not get ACPI fully working on MinnowMAX. And I
guess he has stopped working on this, Simon?
>
> Any hints or suggestions welcome! :)
>
To support ACPI on real boards, the main task is to write ASL files to
describe the on-board devices, using AML language. We can take most of
these from coreboot though. The other part is to program these ACPI
registers as required by the spec.
Regards,
Bin
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-03-21 9:15 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-08-30 0:10 [U-Boot] [UBOOT PATCH v1 0/2] Add ACPI table support on Minnowmax Saket Sinha
2015-08-30 0:10 ` [U-Boot] [UBOOT PATCH v1 1/2] x86: Add ACPI table support to Minnowmax Saket Sinha
2015-08-31 3:26 ` Bin Meng
2015-08-30 0:10 ` [U-Boot] [UBOOT PATCH v1 2/2] x86: Add DSDT table for supporting ACPI on Minnowmax Saket Sinha
2015-08-31 3:28 ` Bin Meng
2015-08-31 4:28 ` Saket Sinha
2016-03-18 12:01 ` [U-Boot] [UBOOT PATCH v1 0/2] Add ACPI table support " Stefan Roese
2016-03-21 9:15 ` Bin Meng
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