[PATCH v2 0/4] Xilinx AMS fixes

[PATCH v2 0/4] Xilinx AMS fixes

[Robert Hancock]

Various fixes for the Xilinx AMS driver.

Changes since v1:
-drop addition to ZynqMP device tree, will be submitted elsewhere
-add patch to fix DT binding to add missing clock entry

Robert Hancock (4):
  dt-bindings: iio: adc: zynqmp_ams: Add clock entry
  iio: adc: xilinx-ams: Fixed missing PS channels
  iio: adc: xilinx-ams: Fixed wrong sequencer register settings
  iio: adc: xilinx-ams: Fix single channel switching sequence

 .../bindings/iio/adc/xlnx,zynqmp-ams.yaml         |  8 ++++++++
 drivers/iio/adc/xilinx-ams.c                      | 15 +++++++++++----
 2 files changed, 19 insertions(+), 4 deletions(-)

-- 
2.31.1

[PATCH v2 1/4] dt-bindings: iio: adc: zynqmp_ams: Add clock entry

[Robert Hancock]

The AMS driver DT binding was missing the clock entry, which is actually
mandatory according to the driver implementation. Add this in.

Fixes: 39dd2d1e251d ("dt-bindings: iio: adc: Add Xilinx AMS binding documentation")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
 .../devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml      | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml
index 87992db389b2..3698b4b0900f 100644
--- a/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml
@@ -92,6 +92,10 @@ properties:
     description: AMS Controller register space
     maxItems: 1
 
+  clocks:
+    items:
+      - description: AMS reference clock
+
   ranges:
     description:
       Maps the child address space for PS and/or PL.
@@ -181,12 +185,15 @@ properties:
 required:
   - compatible
   - reg
+  - clocks
   - ranges
 
 additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/clock/xlnx-zynqmp-clk.h>
+
     bus {
         #address-cells = <2>;
         #size-cells = <2>;
@@ -196,6 +203,7 @@ examples:
             interrupt-parent = <&gic>;
             interrupts = <0 56 4>;
             reg = <0x0 0xffa50000 0x0 0x800>;
+            clocks = <&zynqmp_clk AMS_REF>;
             #address-cells = <1>;
             #size-cells = <1>;
             #io-channel-cells = <1>;
-- 
2.31.1

[PATCH v2 2/4] iio: adc: xilinx-ams: Fixed missing PS channels

[Robert Hancock]

The code forgot to increment num_channels for the PS channel inputs,
resulting in them not being enabled as they should.

Fixes: d5c70627a794 ("iio: adc: Add Xilinx AMS driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Reviewed-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/iio/adc/xilinx-ams.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/iio/adc/xilinx-ams.c b/drivers/iio/adc/xilinx-ams.c
index 8343c5f74121..b93864362dac 100644
--- a/drivers/iio/adc/xilinx-ams.c
+++ b/drivers/iio/adc/xilinx-ams.c
@@ -1224,6 +1224,7 @@ static int ams_init_module(struct iio_dev *indio_dev,
 
 		/* add PS channels to iio device channels */
 		memcpy(channels, ams_ps_channels, sizeof(ams_ps_channels));
+		num_channels = ARRAY_SIZE(ams_ps_channels);
 	} else if (fwnode_property_match_string(fwnode, "compatible",
 						"xlnx,zynqmp-ams-pl") == 0) {
 		ams->pl_base = fwnode_iomap(fwnode, 0);
-- 
2.31.1

[PATCH v2 3/4] iio: adc: xilinx-ams: Fixed wrong sequencer register settings

[Robert Hancock]

Register settings used for the sequencer configuration register
were incorrect, causing some inputs to not be read properly.

Fixes: d5c70627a794 ("iio: adc: Add Xilinx AMS driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
Reviewed-by: Michael Tretter <m.tretter@pengutronix.de>
---
 drivers/iio/adc/xilinx-ams.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/xilinx-ams.c b/drivers/iio/adc/xilinx-ams.c
index b93864362dac..199027c93cdc 100644
--- a/drivers/iio/adc/xilinx-ams.c
+++ b/drivers/iio/adc/xilinx-ams.c
@@ -91,8 +91,8 @@
 
 #define AMS_CONF1_SEQ_MASK		GENMASK(15, 12)
 #define AMS_CONF1_SEQ_DEFAULT		FIELD_PREP(AMS_CONF1_SEQ_MASK, 0)
-#define AMS_CONF1_SEQ_CONTINUOUS	FIELD_PREP(AMS_CONF1_SEQ_MASK, 1)
-#define AMS_CONF1_SEQ_SINGLE_CHANNEL	FIELD_PREP(AMS_CONF1_SEQ_MASK, 2)
+#define AMS_CONF1_SEQ_CONTINUOUS	FIELD_PREP(AMS_CONF1_SEQ_MASK, 2)
+#define AMS_CONF1_SEQ_SINGLE_CHANNEL	FIELD_PREP(AMS_CONF1_SEQ_MASK, 3)
 
 #define AMS_REG_SEQ0_MASK		GENMASK(15, 0)
 #define AMS_REG_SEQ2_MASK		GENMASK(21, 16)
-- 
2.31.1

[PATCH v2 4/4] iio: adc: xilinx-ams: Fix single channel switching sequence

[Robert Hancock]

Some of the AMS channels need to be read by switching into single-channel
mode from the normal polling sequence. There was a logic issue in this
switching code that could cause the first read of these channels to read
back as zero.

It appears that the sequencer should be set back to default mode before
changing the channel selection, and the channel should be set before
switching the sequencer back into single-channel mode.

Also, write 1 to the EOC bit in the status register to clear it before
waiting for it to become set, so that we actually wait for a new
conversion to complete, and don't proceed based on a previous conversion
completing.

Fixes: d5c70627a794 ("iio: adc: Add Xilinx AMS driver")
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
 drivers/iio/adc/xilinx-ams.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/xilinx-ams.c b/drivers/iio/adc/xilinx-ams.c
index 199027c93cdc..7bf097fa10cb 100644
--- a/drivers/iio/adc/xilinx-ams.c
+++ b/drivers/iio/adc/xilinx-ams.c
@@ -530,14 +530,18 @@ static int ams_enable_single_channel(struct ams *ams, unsigned int offset)
 		return -EINVAL;
 	}
 
-	/* set single channel, sequencer off mode */
+	/* put sysmon in a soft reset to change the sequence */
 	ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
-			  AMS_CONF1_SEQ_SINGLE_CHANNEL);
+			  AMS_CONF1_SEQ_DEFAULT);
 
 	/* write the channel number */
 	ams_ps_update_reg(ams, AMS_REG_CONFIG0, AMS_CONF0_CHANNEL_NUM_MASK,
 			  channel_num);
 
+	/* set single channel, sequencer off mode */
+	ams_ps_update_reg(ams, AMS_REG_CONFIG1, AMS_CONF1_SEQ_MASK,
+			  AMS_CONF1_SEQ_SINGLE_CHANNEL);
+
 	return 0;
 }
 
@@ -551,6 +555,8 @@ static int ams_read_vcc_reg(struct ams *ams, unsigned int offset, u32 *data)
 	if (ret)
 		return ret;
 
+	/* clear end-of-conversion flag, wait for next conversion to complete */
+	writel(expect, ams->base + AMS_ISR_1);
 	ret = readl_poll_timeout(ams->base + AMS_ISR_1, reg, (reg & expect),
 				 AMS_INIT_POLL_TIME_US, AMS_INIT_TIMEOUT_US);
 	if (ret)
-- 
2.31.1

Re: [PATCH v2 0/4] Xilinx AMS fixes

[Jonathan Cameron]

On Thu, 27 Jan 2022 11:34:46 -0600
Robert Hancock <robert.hancock@calian.com> wrote:

> Various fixes for the Xilinx AMS driver.
> 
> Changes since v1:
> -drop addition to ZynqMP device tree, will be submitted elsewhere
> -add patch to fix DT binding to add missing clock entry

I'm fine with these but would like to leave them all on list a tiny
bit longer so we can hopefully get some review, particularly on patches
1 and 4.

Jonathan

> 
> Robert Hancock (4):
>   dt-bindings: iio: adc: zynqmp_ams: Add clock entry
>   iio: adc: xilinx-ams: Fixed missing PS channels
>   iio: adc: xilinx-ams: Fixed wrong sequencer register settings
>   iio: adc: xilinx-ams: Fix single channel switching sequence
> 
>  .../bindings/iio/adc/xlnx,zynqmp-ams.yaml         |  8 ++++++++
>  drivers/iio/adc/xilinx-ams.c                      | 15 +++++++++++----
>  2 files changed, 19 insertions(+), 4 deletions(-)
> 

Re: [PATCH v2 0/4] Xilinx AMS fixes

[Robert Hancock]

On Sun, 2022-01-30 at 12:46 +0000, Jonathan Cameron wrote:
> On Thu, 27 Jan 2022 11:34:46 -0600
> Robert Hancock <robert.hancock@calian.com> wrote:
> 
> > Various fixes for the Xilinx AMS driver.
> > 
> > Changes since v1:
> > -drop addition to ZynqMP device tree, will be submitted elsewhere
> > -add patch to fix DT binding to add missing clock entry
> 
> I'm fine with these but would like to leave them all on list a tiny
> bit longer so we can hopefully get some review, particularly on patches
> 1 and 4.
> 
> Jonathan

Hi all,

I don't think I've gotten any feedback. Is anyone able to review/test?

> 
> > Robert Hancock (4):
> >   dt-bindings: iio: adc: zynqmp_ams: Add clock entry
> >   iio: adc: xilinx-ams: Fixed missing PS channels
> >   iio: adc: xilinx-ams: Fixed wrong sequencer register settings
> >   iio: adc: xilinx-ams: Fix single channel switching sequence
> > 
> >  .../bindings/iio/adc/xlnx,zynqmp-ams.yaml         |  8 ++++++++
> >  drivers/iio/adc/xilinx-ams.c                      | 15 +++++++++++----
> >  2 files changed, 19 insertions(+), 4 deletions(-)
> > 
-- 
Robert Hancock
Senior Hardware Designer, Calian Advanced Technologies
www.calian.com

Re: [PATCH v2 1/4] dt-bindings: iio: adc: zynqmp_ams: Add clock entry

[Rob Herring]

On Thu, 27 Jan 2022 11:34:47 -0600, Robert Hancock wrote:
> The AMS driver DT binding was missing the clock entry, which is actually
> mandatory according to the driver implementation. Add this in.
> 
> Fixes: 39dd2d1e251d ("dt-bindings: iio: adc: Add Xilinx AMS binding documentation")
> Signed-off-by: Robert Hancock <robert.hancock@calian.com>
> ---
>  .../devicetree/bindings/iio/adc/xlnx,zynqmp-ams.yaml      | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 0/4] Xilinx AMS fixes

[Jonathan Cameron]

On Wed, 9 Feb 2022 19:49:27 +0000
Robert Hancock <robert.hancock@calian.com> wrote:

> On Sun, 2022-01-30 at 12:46 +0000, Jonathan Cameron wrote:
> > On Thu, 27 Jan 2022 11:34:46 -0600
> > Robert Hancock <robert.hancock@calian.com> wrote:
> >   
> > > Various fixes for the Xilinx AMS driver.
> > > 
> > > Changes since v1:
> > > -drop addition to ZynqMP device tree, will be submitted elsewhere
> > > -add patch to fix DT binding to add missing clock entry  
> > 
> > I'm fine with these but would like to leave them all on list a tiny
> > bit longer so we can hopefully get some review, particularly on patches
> > 1 and 4.
> > 
> > Jonathan  
> 
> Hi all,
> 
> I don't think I've gotten any feedback. Is anyone able to review/test?
> 
Michal,

If you have a chance to take a quick look at this series that would
be great.

Thanks,

Jonathan


> >   
> > > Robert Hancock (4):
> > >   dt-bindings: iio: adc: zynqmp_ams: Add clock entry
> > >   iio: adc: xilinx-ams: Fixed missing PS channels
> > >   iio: adc: xilinx-ams: Fixed wrong sequencer register settings
> > >   iio: adc: xilinx-ams: Fix single channel switching sequence
> > > 
> > >  .../bindings/iio/adc/xlnx,zynqmp-ams.yaml         |  8 ++++++++
> > >  drivers/iio/adc/xilinx-ams.c                      | 15 +++++++++++----
> > >  2 files changed, 19 insertions(+), 4 deletions(-)
> > >   

Re: [PATCH v2 0/4] Xilinx AMS fixes

[Michal Simek]

On 2/26/22 17:45, Jonathan Cameron wrote:
> On Wed, 9 Feb 2022 19:49:27 +0000
> Robert Hancock <robert.hancock@calian.com> wrote:
> 
>> On Sun, 2022-01-30 at 12:46 +0000, Jonathan Cameron wrote:
>>> On Thu, 27 Jan 2022 11:34:46 -0600
>>> Robert Hancock <robert.hancock@calian.com> wrote:
>>>    
>>>> Various fixes for the Xilinx AMS driver.
>>>>
>>>> Changes since v1:
>>>> -drop addition to ZynqMP device tree, will be submitted elsewhere
>>>> -add patch to fix DT binding to add missing clock entry
>>>
>>> I'm fine with these but would like to leave them all on list a tiny
>>> bit longer so we can hopefully get some review, particularly on patches
>>> 1 and 4.
>>>
>>> Jonathan
>>
>> Hi all,
>>
>> I don't think I've gotten any feedback. Is anyone able to review/test?
>>
> Michal,
> 
> If you have a chance to take a quick look at this series that would
> be great.

That series looks good to me. Please apply and feel free to add my

Acked-by: Michal Simek <michal.simek@xilinx.com>

Thanks,
Michal

Re: [PATCH v2 0/4] Xilinx AMS fixes

[Jonathan Cameron]

On Mon, 28 Feb 2022 07:40:59 +0100
Michal Simek <michal.simek@xilinx.com> wrote:

> On 2/26/22 17:45, Jonathan Cameron wrote:
> > On Wed, 9 Feb 2022 19:49:27 +0000
> > Robert Hancock <robert.hancock@calian.com> wrote:
> >   
> >> On Sun, 2022-01-30 at 12:46 +0000, Jonathan Cameron wrote:  
> >>> On Thu, 27 Jan 2022 11:34:46 -0600
> >>> Robert Hancock <robert.hancock@calian.com> wrote:
> >>>      
> >>>> Various fixes for the Xilinx AMS driver.
> >>>>
> >>>> Changes since v1:
> >>>> -drop addition to ZynqMP device tree, will be submitted elsewhere
> >>>> -add patch to fix DT binding to add missing clock entry  
> >>>
> >>> I'm fine with these but would like to leave them all on list a tiny
> >>> bit longer so we can hopefully get some review, particularly on patches
> >>> 1 and 4.
> >>>
> >>> Jonathan  
> >>
> >> Hi all,
> >>
> >> I don't think I've gotten any feedback. Is anyone able to review/test?
> >>  
> > Michal,
> > 
> > If you have a chance to take a quick look at this series that would
> > be great.  
> 
> That series looks good to me. Please apply and feel free to add my
> 
> Acked-by: Michal Simek <michal.simek@xilinx.com>
> 
Applied to the fixes-togreg branch of iio.git.

I'm not certain I'll get a fixes pull request out in time to make this
cycle so these might get dragged across to my togreg branch and
added to a pull request for the merge window. Or, possibly Greg
will take them for the merge window even if I do a separate pull given
we are close to the end of the cycle.

Thanks,

Jonathan

> Thanks,
> Michal

Re: [PATCH v2 0/4] Xilinx AMS fixes

[Michal Simek]

On 2/28/22 19:26, Jonathan Cameron wrote:
> On Mon, 28 Feb 2022 07:40:59 +0100
> Michal Simek <michal.simek@xilinx.com> wrote:
> 
>> On 2/26/22 17:45, Jonathan Cameron wrote:
>>> On Wed, 9 Feb 2022 19:49:27 +0000
>>> Robert Hancock <robert.hancock@calian.com> wrote:
>>>    
>>>> On Sun, 2022-01-30 at 12:46 +0000, Jonathan Cameron wrote:
>>>>> On Thu, 27 Jan 2022 11:34:46 -0600
>>>>> Robert Hancock <robert.hancock@calian.com> wrote:
>>>>>       
>>>>>> Various fixes for the Xilinx AMS driver.
>>>>>>
>>>>>> Changes since v1:
>>>>>> -drop addition to ZynqMP device tree, will be submitted elsewhere
>>>>>> -add patch to fix DT binding to add missing clock entry
>>>>>
>>>>> I'm fine with these but would like to leave them all on list a tiny
>>>>> bit longer so we can hopefully get some review, particularly on patches
>>>>> 1 and 4.
>>>>>
>>>>> Jonathan
>>>>
>>>> Hi all,
>>>>
>>>> I don't think I've gotten any feedback. Is anyone able to review/test?
>>>>   
>>> Michal,
>>>
>>> If you have a chance to take a quick look at this series that would
>>> be great.
>>
>> That series looks good to me. Please apply and feel free to add my
>>
>> Acked-by: Michal Simek <michal.simek@xilinx.com>
>>
> Applied to the fixes-togreg branch of iio.git.
> 
> I'm not certain I'll get a fixes pull request out in time to make this
> cycle so these might get dragged across to my togreg branch and
> added to a pull request for the merge window. Or, possibly Greg
> will take them for the merge window even if I do a separate pull given
> we are close to the end of the cycle.

that's fine.

Thanks,
Michal