[PATCH v3] arm: Fix asynchronous aborts (SError exceptions) due to bogus PTEs

[PATCH v3] arm: Fix asynchronous aborts (SError exceptions) due to bogus PTEs

[Shanker Donthineni]

From: Vikram Sethi <vikrams@codeaurora.org>

ARMv8 architecture allows performing prefetch data/instructions
from memory locations marked as normal memory. Prefetch does not
mean that the data/instruction has to be used/executed in code
flow. All PTEs that appear to be valid to MMU must contain valid
physical address with proper attributes otherwise MMU table walk
might cause imprecise asynchronous aborts.

The way current XEN code is preparing page tables for frametable
and xenheap memory can create bogus PTEs. This patch fixes the
issue by clearing page table memory before populating EL2 L0/L1
PTEs. Without this patch XEN crashes on Qualcomm Technologies
server chips due to asynchronous aborts.

The speculative/prefetch feature explanation is scattered everywhere
in ARM specification but below two sections have useful information.

E2.8 Memory types and attributes (ver DDI0487A_h)
G4.12.6 External abort on a translation table walk (ver DDI0487A_h)

Signed-off-by: Vikram Sethi <vikrams@codeaurora.org>
Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
---
Changes since v2:
    Include ARM spec version in commit text.

Changes since v1:
    Replace memset() with clear_page()
    Edit commit description 

 xen/arch/arm/mm.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index 81f9e2e..3fda8f3 100644
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -730,6 +730,8 @@ void __init setup_xenheap_mappings(unsigned long base_mfn,
         else
         {
             unsigned long first_mfn = alloc_boot_pages(1, 1);
+
+            clear_page(mfn_to_virt(first_mfn));
             pte = mfn_to_xen_entry(first_mfn, WRITEALLOC);
             pte.pt.table = 1;
             write_pte(p, pte);
@@ -773,6 +775,7 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
     second = mfn_to_virt(second_base);
     for ( i = 0; i < nr_second; i++ )
     {
+        clear_page(mfn_to_virt(second_base + i));
         pte = mfn_to_xen_entry(second_base + i, WRITEALLOC);
         pte.pt.table = 1;
         write_pte(&xen_first[first_table_offset(FRAMETABLE_VIRT_START)+i], pte);
-- 
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc. 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
a Linux Foundation Collaborative Project


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Re: [PATCH v3] arm: Fix asynchronous aborts (SError exceptions) due to bogus PTEs

[Shanker Donthineni]

Hi Stefano/Julien,

Any other comments to be addressed? Please propose an alternative
solution to fix the problem if this patch changes are not appropriate.

On 03/28/2016 11:46 PM, Shanker Donthineni wrote:
> From: Vikram Sethi <vikrams@codeaurora.org>
>
> ARMv8 architecture allows performing prefetch data/instructions
> from memory locations marked as normal memory. Prefetch does not
> mean that the data/instruction has to be used/executed in code
> flow. All PTEs that appear to be valid to MMU must contain valid
> physical address with proper attributes otherwise MMU table walk
> might cause imprecise asynchronous aborts.
>
> The way current XEN code is preparing page tables for frametable
> and xenheap memory can create bogus PTEs. This patch fixes the
> issue by clearing page table memory before populating EL2 L0/L1
> PTEs. Without this patch XEN crashes on Qualcomm Technologies
> server chips due to asynchronous aborts.
>
> The speculative/prefetch feature explanation is scattered everywhere
> in ARM specification but below two sections have useful information.
>
> E2.8 Memory types and attributes (ver DDI0487A_h)
> G4.12.6 External abort on a translation table walk (ver DDI0487A_h)
>
> Signed-off-by: Vikram Sethi <vikrams@codeaurora.org>
> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
> ---
> Changes since v2:
>     Include ARM spec version in commit text.
>
> Changes since v1:
>     Replace memset() with clear_page()
>     Edit commit description 
>
>  xen/arch/arm/mm.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
> index 81f9e2e..3fda8f3 100644
> --- a/xen/arch/arm/mm.c
> +++ b/xen/arch/arm/mm.c
> @@ -730,6 +730,8 @@ void __init setup_xenheap_mappings(unsigned long base_mfn,
>          else
>          {
>              unsigned long first_mfn = alloc_boot_pages(1, 1);
> +
> +            clear_page(mfn_to_virt(first_mfn));
>              pte = mfn_to_xen_entry(first_mfn, WRITEALLOC);
>              pte.pt.table = 1;
>              write_pte(p, pte);
> @@ -773,6 +775,7 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
>      second = mfn_to_virt(second_base);
>      for ( i = 0; i < nr_second; i++ )
>      {
> +        clear_page(mfn_to_virt(second_base + i));
>          pte = mfn_to_xen_entry(second_base + i, WRITEALLOC);
>          pte.pt.table = 1;
>          write_pte(&xen_first[first_table_offset(FRAMETABLE_VIRT_START)+i], pte);

-- 
Shanker Donthineni
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project


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Re: [PATCH v3] arm: Fix asynchronous aborts (SError exceptions) due to bogus PTEs

[Shanker Donthineni]

Hi Julien/Stefano,

Any other comments to be addressed? Please propose an alternative
solution to fix the problem if this patch changes are not appropriate.

On 03/28/2016 11:46 PM, Shanker Donthineni wrote:
> From: Vikram Sethi <vikrams@codeaurora.org>
>
> ARMv8 architecture allows performing prefetch data/instructions
> from memory locations marked as normal memory. Prefetch does not
> mean that the data/instruction has to be used/executed in code
> flow. All PTEs that appear to be valid to MMU must contain valid
> physical address with proper attributes otherwise MMU table walk
> might cause imprecise asynchronous aborts.
>
> The way current XEN code is preparing page tables for frametable
> and xenheap memory can create bogus PTEs. This patch fixes the
> issue by clearing page table memory before populating EL2 L0/L1
> PTEs. Without this patch XEN crashes on Qualcomm Technologies
> server chips due to asynchronous aborts.
>
> The speculative/prefetch feature explanation is scattered everywhere
> in ARM specification but below two sections have useful information.
>
> E2.8 Memory types and attributes (ver DDI0487A_h)
> G4.12.6 External abort on a translation table walk (ver DDI0487A_h)
>
> Signed-off-by: Vikram Sethi <vikrams@codeaurora.org>
> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
> ---
> Changes since v2:
>     Include ARM spec version in commit text.
>
> Changes since v1:
>     Replace memset() with clear_page()
>     Edit commit description 
>
>  xen/arch/arm/mm.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
> index 81f9e2e..3fda8f3 100644
> --- a/xen/arch/arm/mm.c
> +++ b/xen/arch/arm/mm.c
> @@ -730,6 +730,8 @@ void __init setup_xenheap_mappings(unsigned long base_mfn,
>          else
>          {
>              unsigned long first_mfn = alloc_boot_pages(1, 1);
> +
> +            clear_page(mfn_to_virt(first_mfn));
>              pte = mfn_to_xen_entry(first_mfn, WRITEALLOC);
>              pte.pt.table = 1;
>              write_pte(p, pte);
> @@ -773,6 +775,7 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe)
>      second = mfn_to_virt(second_base);
>      for ( i = 0; i < nr_second; i++ )
>      {
> +        clear_page(mfn_to_virt(second_base + i));
>          pte = mfn_to_xen_entry(second_base + i, WRITEALLOC);
>          pte.pt.table = 1;
>          write_pte(&xen_first[first_table_offset(FRAMETABLE_VIRT_START)+i], pte);

-- 
Shanker Donthineni
Qualcomm Technologies, Inc. on behalf of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project


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http://lists.xen.org/xen-devel

Re: [PATCH v3] arm: Fix asynchronous aborts (SError exceptions) due to bogus PTEs

[Julien Grall]

On 06/04/16 19:57, Shanker Donthineni wrote:
> Hi Julien/Stefano,

Hi Shanker,

>
> Any other comments to be addressed? Please propose an alternative
> solution to fix the problem if this patch changes are not appropriate.

All the comments have been addressed.

>
> On 03/28/2016 11:46 PM, Shanker Donthineni wrote:
>> From: Vikram Sethi <vikrams@codeaurora.org>
>>
>> ARMv8 architecture allows performing prefetch data/instructions
>> from memory locations marked as normal memory. Prefetch does not
>> mean that the data/instruction has to be used/executed in code
>> flow. All PTEs that appear to be valid to MMU must contain valid
>> physical address with proper attributes otherwise MMU table walk
>> might cause imprecise asynchronous aborts.
>>
>> The way current XEN code is preparing page tables for frametable
>> and xenheap memory can create bogus PTEs. This patch fixes the
>> issue by clearing page table memory before populating EL2 L0/L1
>> PTEs. Without this patch XEN crashes on Qualcomm Technologies
>> server chips due to asynchronous aborts.
>>
>> The speculative/prefetch feature explanation is scattered everywhere
>> in ARM specification but below two sections have useful information.
>>
>> E2.8 Memory types and attributes (ver DDI0487A_h)
>> G4.12.6 External abort on a translation table walk (ver DDI0487A_h)
>>
>> Signed-off-by: Vikram Sethi <vikrams@codeaurora.org>
>> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>

Acked-by: Julien Grall <julien.grall@arm.com>

Regards,

-- 
Julien Grall

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Re: [PATCH v3] arm: Fix asynchronous aborts (SError exceptions) due to bogus PTEs

[Konrad Rzeszutek Wilk]

On Fri, Apr 08, 2016 at 10:42:52AM +0100, Julien Grall wrote:
> 
> 
> On 06/04/16 19:57, Shanker Donthineni wrote:
> >Hi Julien/Stefano,
> 
> Hi Shanker,
> 
> >
> >Any other comments to be addressed? Please propose an alternative
> >solution to fix the problem if this patch changes are not appropriate.
> 
> All the comments have been addressed.
> 
> >
> >On 03/28/2016 11:46 PM, Shanker Donthineni wrote:
> >>From: Vikram Sethi <vikrams@codeaurora.org>
> >>
> >>ARMv8 architecture allows performing prefetch data/instructions
> >>from memory locations marked as normal memory. Prefetch does not
> >>mean that the data/instruction has to be used/executed in code
> >>flow. All PTEs that appear to be valid to MMU must contain valid
> >>physical address with proper attributes otherwise MMU table walk
> >>might cause imprecise asynchronous aborts.
> >>
> >>The way current XEN code is preparing page tables for frametable
> >>and xenheap memory can create bogus PTEs. This patch fixes the
> >>issue by clearing page table memory before populating EL2 L0/L1
> >>PTEs. Without this patch XEN crashes on Qualcomm Technologies
> >>server chips due to asynchronous aborts.
> >>
> >>The speculative/prefetch feature explanation is scattered everywhere
> >>in ARM specification but below two sections have useful information.
> >>
> >>E2.8 Memory types and attributes (ver DDI0487A_h)
> >>G4.12.6 External abort on a translation table walk (ver DDI0487A_h)
> >>
> >>Signed-off-by: Vikram Sethi <vikrams@codeaurora.org>
> >>Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
> 
> Acked-by: Julien Grall <julien.grall@arm.com>

Applied.

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