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From: "Jan Beulich" <JBeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Xen-devel <xen-devel@lists.xen.org>
Subject: Re: [PATCH v5 03/21] xen/x86: Generate deep dependencies of features
Date: Fri, 08 Apr 2016 09:17:33 -0600	[thread overview]
Message-ID: <5707D99D02000078000E60DF@prv-mh.provo.novell.com> (raw)
In-Reply-To: <5706EF0E.8080003@citrix.com>

>>> On 08.04.16 at 01:36, <andrew.cooper3@citrix.com> wrote:
> On 08/04/2016 00:18, Jan Beulich wrote:
>>>>> On 07.04.16 at 13:57, <andrew.cooper3@citrix.com> wrote:
>>> +    deps = {
>>> +        # FPU is taken to mean support for the x87 regisers as well as the
>>> +        # instructions.  MMX is documented to alias the %MM registers over the
>>> +        # x87 %ST registers in hardware.
>>> +        FPU: [MMX],
>>> +
>>> +        # The PSE36 feature indicates that reserved bits in a PSE superpage
>>> +        # may be used as extra physical address bits.
>>> +        PSE: [PSE36],
>>> +
>>> +        # Entering Long Mode requires that %CR4.PAE is set.  The NX and PKU
>>> +        # pagetable bits are only representable in the 64bit PTE format
>>> +        # offered by PAE.
>>> +        PAE: [LM, NX, PKU],
>> PKU is explicitly documented to be available only in IA-32e paging,
>> so I think it should be listed as a dependent of LM.
> 
> I am not so sure.  Unlike PCID, it is not declared that setting CR4.PKE
> will result in a #GP fault out of Long Mode, and the description does
> say "If CR4.PKE = 0, or if IA-32e paging is not active, the processor
> does not associate linear addresses with protection keys".
> 
> This suggests that CR4.PKE can be set out of Long Mode, but all
> pagewalks will act as if key0 is in use.  PCID on the other hand goes to
> lengths declaring that you can't set CR4.PCIDE out of Long Mode, nor may
> you attempt to exit Long Mode if it is set.
> 
> I do have some Skylake hardware with PKU available in the office.  I
> will investigate what really happens in this case.  (I am also mindful
> of the fact that 32bit PV guests could in principle use PKU, at which
> point the dependency on LM would be counter-productive.)

With the goal of the series going in soon (today?), wouldn't putting
in the tighter variant be the better approach, allowing us to relax
things if we find they can be relaxed?

Jan


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  reply	other threads:[~2016-04-08 15:17 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-07 11:57 [PATCH v5 00/21] x86: Improvements to cpuid handling for guests Andrew Cooper
2016-04-07 11:57 ` [PATCH v5 01/21] xen/x86: Annotate VM applicability in featureset Andrew Cooper
2016-04-07 23:01   ` Jan Beulich
2016-04-07 11:57 ` [PATCH v5 02/21] xen/x86: Calculate maximum host and guest featuresets Andrew Cooper
2016-04-07 23:04   ` Jan Beulich
2016-04-07 11:57 ` [PATCH v5 03/21] xen/x86: Generate deep dependencies of features Andrew Cooper
2016-04-07 23:18   ` Jan Beulich
2016-04-07 23:36     ` Andrew Cooper
2016-04-08 15:17       ` Jan Beulich [this message]
2016-04-08 15:18         ` Andrew Cooper
2016-04-07 11:57 ` [PATCH v5 04/21] xen/x86: Clear dependent features when clearing a cpu cap Andrew Cooper
2016-04-08 15:36   ` Konrad Rzeszutek Wilk
2016-04-07 11:57 ` [PATCH v5 05/21] xen/x86: Improve disabling of features which have dependencies Andrew Cooper
2016-04-08 15:04   ` Konrad Rzeszutek Wilk
2016-04-07 11:57 ` [PATCH v5 06/21] xen/x86: Improvements to in-hypervisor cpuid sanity checks Andrew Cooper
2016-04-08 16:10   ` Konrad Rzeszutek Wilk
2016-04-08 18:06   ` Jan Beulich
2016-04-07 11:57 ` [PATCH v5 07/21] x86/cpu: Move set_cpumask() calls into c_early_init() Andrew Cooper
2016-04-08 18:09   ` Jan Beulich
2016-04-07 11:57 ` [PATCH v5 08/21] x86/cpu: Sysctl and common infrastructure for levelling context switching Andrew Cooper
2016-04-07 16:54   ` Daniel De Graaf
2016-04-08 16:12   ` Konrad Rzeszutek Wilk
2016-04-07 11:57 ` [PATCH v5 09/21] x86/cpu: Rework AMD masking MSR setup Andrew Cooper
2016-04-08 16:13   ` Konrad Rzeszutek Wilk
2016-04-07 11:57 ` [PATCH v5 10/21] x86/cpu: Rework Intel masking/faulting setup Andrew Cooper
2016-04-08 16:14   ` Konrad Rzeszutek Wilk
2016-04-07 11:57 ` [PATCH v5 11/21] x86/cpu: Context switch cpuid masks and faulting state in context_switch() Andrew Cooper
2016-04-08 16:15   ` Konrad Rzeszutek Wilk
2016-04-07 11:57 ` [PATCH v5 12/21] x86/pv: Provide custom cpumasks for PV domains Andrew Cooper
2016-04-08 16:17   ` Konrad Rzeszutek Wilk
2016-04-07 11:57 ` [PATCH v5 13/21] x86/domctl: Update PV domain cpumasks when setting cpuid policy Andrew Cooper
2016-04-08 16:26   ` Konrad Rzeszutek Wilk
2016-04-07 11:57 ` [PATCH v5 14/21] xen+tools: Export maximum host and guest cpu featuresets via SYSCTL Andrew Cooper
2016-04-07 16:54   ` Daniel De Graaf
2016-04-08 16:32   ` Konrad Rzeszutek Wilk
2016-04-07 11:57 ` [PATCH v5 15/21] tools/libxc: Modify bitmap operations to take void pointers Andrew Cooper
2016-04-07 13:00   ` Wei Liu
2016-04-08 16:34   ` Konrad Rzeszutek Wilk
2016-04-07 11:57 ` [PATCH v5 16/21] tools/libxc: Use public/featureset.h for cpuid policy generation Andrew Cooper
2016-04-08 16:37   ` Konrad Rzeszutek Wilk
2016-04-07 11:57 ` [PATCH v5 17/21] tools/libxc: Expose the automatically generated cpu featuremask information Andrew Cooper
2016-04-08 16:38   ` Konrad Rzeszutek Wilk
2016-04-07 11:57 ` [PATCH v5 18/21] tools: Utility for dealing with featuresets Andrew Cooper
2016-04-07 11:57 ` [PATCH v5 19/21] tools/libxc: Wire a featureset through to cpuid policy logic Andrew Cooper
2016-04-07 11:57 ` [PATCH v5 20/21] tools/libxc: Use featuresets rather than guesswork Andrew Cooper
2016-04-07 11:57 ` [PATCH v5 21/21] tools/libxc: Calculate xstate cpuid leaf from guest information Andrew Cooper
2016-04-07 12:58   ` Wei Liu
2016-04-08 21:00   ` Jan Beulich
2016-04-08 21:45     ` Andrew Cooper
2016-04-08 22:38       ` Jan Beulich

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