From: Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> To: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Cc: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>, Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Alexandre Courbot <gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>, Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>, Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>, "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" <linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>, "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>, "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>, "linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" <linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> Subject: Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Date: Fri, 15 Apr 2016 10:38:46 -0600 [thread overview] Message-ID: <57111916.8030304@wwwdotorg.org> (raw) In-Reply-To: <5710A8A4.90309-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> On 04/15/2016 02:39 AM, Laxman Dewangan wrote: > > On Friday 15 April 2016 01:38 PM, Linus Walleij wrote: >> On Tue, Apr 12, 2016 at 4:56 PM, Laxman Dewangan >> <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: >> >>> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V >>> or 3.3V I/O voltage levels. Also the IO pads can be configured >>> for power down state if it is not used. SW needs to configure the >>> voltage level of IO pads based on IO rail voltage and its power >>> state based on platform usage. >>> >>> The voltage and power state configurations of pads are provided >>> through pin control frameworks. Add pin control driver for Tegra's >>> IO pads' voltage and power state configurations. >> Even if Tegra is not using the generic code for handling the >> standard bindings (GENERIC_PINCONF) it doesn't stop >> you from using the generic bindings and contributing to them. >> >> Historically you have a few custom bindings like these: >> >> nvidia,pins >> nvidia,function >> nvidia,pull >> nvidia,tristate >> >> etc etc, but that is just unfortunate and due to preceding the >> generic bindings. I would appreciate if you started to support >> the generic bindings in parallel, but I'm not gonna push that issue. > > Yaah, these are in my plate to cleanup. Let me work with Stephen, what > he think here. For existing chips, we must always support the existing bindings. There's no point moving to the new bindings since it'll just add more code that just does the same thing. For new chips perhaps it makes sense to move to the new standardized properties. That said, I don't expect we'll need pinmux on those chips since it's guaranteed that FW will set up the static pinmux, and HW explicitly doesn't support dynamic pinmuxing? -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html
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From: Stephen Warren <swarren@wwwdotorg.org> To: Laxman Dewangan <ldewangan@nvidia.com> Cc: Linus Walleij <linus.walleij@linaro.org>, Thierry Reding <thierry.reding@gmail.com>, Alexandre Courbot <gnurou@gmail.com>, Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Jon Hunter <jonathanh@nvidia.com>, "linux-tegra@vger.kernel.org" <linux-tegra@vger.kernel.org>, "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>, "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>, "linux-gpio@vger.kernel.org" <linux-gpio@vger.kernel.org> Subject: Re: [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Date: Fri, 15 Apr 2016 10:38:46 -0600 [thread overview] Message-ID: <57111916.8030304@wwwdotorg.org> (raw) In-Reply-To: <5710A8A4.90309@nvidia.com> On 04/15/2016 02:39 AM, Laxman Dewangan wrote: > > On Friday 15 April 2016 01:38 PM, Linus Walleij wrote: >> On Tue, Apr 12, 2016 at 4:56 PM, Laxman Dewangan >> <ldewangan@nvidia.com> wrote: >> >>> NVIDIA Tegra210 supports the IO pads which can operate at 1.8V >>> or 3.3V I/O voltage levels. Also the IO pads can be configured >>> for power down state if it is not used. SW needs to configure the >>> voltage level of IO pads based on IO rail voltage and its power >>> state based on platform usage. >>> >>> The voltage and power state configurations of pads are provided >>> through pin control frameworks. Add pin control driver for Tegra's >>> IO pads' voltage and power state configurations. >> Even if Tegra is not using the generic code for handling the >> standard bindings (GENERIC_PINCONF) it doesn't stop >> you from using the generic bindings and contributing to them. >> >> Historically you have a few custom bindings like these: >> >> nvidia,pins >> nvidia,function >> nvidia,pull >> nvidia,tristate >> >> etc etc, but that is just unfortunate and due to preceding the >> generic bindings. I would appreciate if you started to support >> the generic bindings in parallel, but I'm not gonna push that issue. > > Yaah, these are in my plate to cleanup. Let me work with Stephen, what > he think here. For existing chips, we must always support the existing bindings. There's no point moving to the new bindings since it'll just add more code that just does the same thing. For new chips perhaps it makes sense to move to the new standardized properties. That said, I don't expect we'll need pinmux on those chips since it's guaranteed that FW will set up the static pinmux, and HW explicitly doesn't support dynamic pinmuxing?
next prev parent reply other threads:[~2016-04-15 16:38 UTC|newest] Thread overview: 105+ messages / expand[flat|nested] mbox.gz Atom feed top 2016-04-12 14:56 [PATCH 0/7] pinctrl: soc/tegra: Add support to configure IO rail voltage and pad power states Laxman Dewangan 2016-04-12 14:56 ` Laxman Dewangan [not found] ` <1460473007-11535-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-12 14:56 ` [PATCH 1/7] soc/tegra: pmc: Use BIT macro for register field definition Laxman Dewangan 2016-04-12 14:56 ` Laxman Dewangan [not found] ` <1460473007-11535-2-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-12 15:26 ` Thierry Reding 2016-04-12 15:26 ` Thierry Reding 2016-04-12 16:58 ` Laxman Dewangan 2016-04-12 16:58 ` Laxman Dewangan 2016-04-15 7:44 ` Linus Walleij 2016-04-12 14:56 ` [PATCH 2/7] soc/tegra: pmc: Add new Tegra210 IO rails Laxman Dewangan 2016-04-12 14:56 ` Laxman Dewangan [not found] ` <1460473007-11535-3-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-12 15:28 ` Thierry Reding 2016-04-12 15:28 ` Thierry Reding [not found] ` <20160412152830.GB30211-EkSeR96xj6Pcmrwk2tT4+A@public.gmane.org> 2016-04-12 16:59 ` Laxman Dewangan 2016-04-12 16:59 ` Laxman Dewangan 2016-04-12 18:03 ` Jon Hunter 2016-04-12 18:03 ` Jon Hunter 2016-04-12 17:57 ` Laxman Dewangan 2016-04-12 17:57 ` Laxman Dewangan 2016-04-12 14:56 ` [PATCH 3/7] soc/tegra: pmc: Add interface to get IO rail power status Laxman Dewangan 2016-04-12 14:56 ` Laxman Dewangan [not found] ` <1460473007-11535-4-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-12 18:06 ` kbuild test robot 2016-04-12 18:06 ` kbuild test robot 2016-04-12 18:13 ` Jon Hunter 2016-04-12 18:13 ` Jon Hunter 2016-04-12 14:56 ` [PATCH 4/7] soc/tegra: pmc: Add interface to set voltage of IO rails Laxman Dewangan 2016-04-12 14:56 ` Laxman Dewangan 2016-04-13 8:47 ` Jon Hunter 2016-04-13 8:47 ` Jon Hunter 2016-04-13 9:00 ` Laxman Dewangan 2016-04-13 9:00 ` Laxman Dewangan 2016-04-13 9:25 ` Jon Hunter 2016-04-13 9:25 ` Jon Hunter [not found] ` <570E109D.6070805-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-13 9:20 ` Laxman Dewangan 2016-04-13 9:20 ` Laxman Dewangan 2016-04-13 9:56 ` Jon Hunter 2016-04-13 9:56 ` Jon Hunter [not found] ` <1460473007-11535-5-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-15 7:54 ` Linus Walleij 2016-04-15 7:54 ` Linus Walleij [not found] ` <CACRpkdbueJ=0+WtNefQ7GHoqU5HY7WFYjL2geFq4vkpTbZesZA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2016-04-15 8:00 ` Mark Brown 2016-04-15 8:00 ` Mark Brown [not found] ` <20160415080027.GB3217-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> 2016-04-15 8:25 ` Laxman Dewangan 2016-04-15 8:25 ` Laxman Dewangan [not found] ` <5710A583.2010102-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-15 9:19 ` Linus Walleij 2016-04-15 9:19 ` Linus Walleij 2016-04-15 16:24 ` Stephen Warren 2016-04-15 16:21 ` Laxman Dewangan 2016-04-15 16:21 ` Laxman Dewangan [not found] ` <57111524.60708-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-15 16:41 ` Stephen Warren 2016-04-15 16:41 ` Stephen Warren [not found] ` <571119D5.3040309-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> 2016-04-15 16:33 ` Laxman Dewangan 2016-04-15 16:33 ` Laxman Dewangan 2016-04-15 16:59 ` Stephen Warren 2016-04-12 14:56 ` [PATCH 5/7] soc/tegra: pmc: Register sub-devices of PMC Laxman Dewangan 2016-04-12 14:56 ` Laxman Dewangan [not found] ` <1460473007-11535-6-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-15 16:31 ` Stephen Warren 2016-04-15 16:31 ` Stephen Warren 2016-04-12 14:56 ` [PATCH 6/7] pinctrl: tegra: Add DT binding for io pads control Laxman Dewangan 2016-04-12 14:56 ` Laxman Dewangan 2016-04-13 9:04 ` Jon Hunter 2016-04-13 9:04 ` Jon Hunter [not found] ` <570E0BAE.8090404-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-13 9:08 ` Laxman Dewangan 2016-04-13 9:08 ` Laxman Dewangan 2016-04-13 9:31 ` Jon Hunter 2016-04-13 9:31 ` Jon Hunter 2016-04-15 14:16 ` Jon Hunter 2016-04-15 14:16 ` Jon Hunter 2016-04-15 14:12 ` Laxman Dewangan 2016-04-15 14:12 ` Laxman Dewangan [not found] ` <5710F6CA.6060700-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-15 15:14 ` Jon Hunter 2016-04-15 15:14 ` Jon Hunter [not found] ` <57110560.80004-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-15 15:14 ` Laxman Dewangan 2016-04-15 15:14 ` Laxman Dewangan 2016-04-15 15:45 ` Jon Hunter 2016-04-15 15:45 ` Jon Hunter 2016-04-15 16:41 ` Laxman Dewangan 2016-04-15 16:41 ` Laxman Dewangan 2016-04-15 17:44 ` Jon Hunter 2016-04-15 17:44 ` Jon Hunter [not found] ` <5711288D.7060701-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-15 17:49 ` Laxman Dewangan 2016-04-15 17:49 ` Laxman Dewangan 2016-04-15 18:30 ` Jon Hunter 2016-04-15 18:30 ` Jon Hunter [not found] ` <57113340.6090701-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-15 18:43 ` Laxman Dewangan 2016-04-15 18:43 ` Laxman Dewangan 2016-04-15 16:35 ` Stephen Warren 2016-04-15 16:31 ` Laxman Dewangan 2016-04-15 16:31 ` Laxman Dewangan 2016-04-12 14:56 ` [PATCH 7/7] pinctrl: tegra: Add driver to configure voltage and power state of io pads Laxman Dewangan 2016-04-12 14:56 ` Laxman Dewangan 2016-04-15 8:08 ` Linus Walleij 2016-04-15 8:39 ` Laxman Dewangan 2016-04-15 9:25 ` Linus Walleij 2016-04-15 9:55 ` Laxman Dewangan 2016-04-15 11:15 ` Linus Walleij [not found] ` <CACRpkdbr-9Z1JKMVmwNFyMq+Pg+3hT5c9rKZ1y4wZecnidW9Cg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 2016-04-15 11:47 ` Laxman Dewangan 2016-04-15 11:47 ` Laxman Dewangan 2016-04-15 14:03 ` Linus Walleij 2016-04-15 13:59 ` Laxman Dewangan [not found] ` <5710F3DC.7090906-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-19 9:49 ` Laxman Dewangan 2016-04-19 9:49 ` Laxman Dewangan 2016-04-26 13:32 ` Laxman Dewangan 2016-04-26 15:31 ` Stephen Warren [not found] ` <5710A8A4.90309-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> 2016-04-15 16:38 ` Stephen Warren [this message] 2016-04-15 16:38 ` Stephen Warren
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