* Polymorphic to_i915()
@ 2016-04-15 17:45 Chris Wilson
2016-04-15 17:46 ` [PATCH 1/6] drm/i915: Rename the magic polymorphic macro __I915__ Chris Wilson
` (6 more replies)
0 siblings, 7 replies; 16+ messages in thread
From: Chris Wilson @ 2016-04-15 17:45 UTC (permalink / raw)
To: intel-gfx
Final canvas for opinions for using a magic macro to reduce typing in
the common operation of getting our drm_i915_private from the object.
21 files changed, 333 insertions(+), 392 deletions(-)
Not to mention the ease it makes for later patches to reduce the pointer
dance.
-Chris
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/6] drm/i915: Rename the magic polymorphic macro __I915__
2016-04-15 17:45 Polymorphic to_i915() Chris Wilson
@ 2016-04-15 17:46 ` Chris Wilson
2016-04-20 14:27 ` Dave Gordon
2016-04-15 17:46 ` [PATCH 2/6] drm/i915: Allow passing any known pointer to for_each_engine() Chris Wilson
` (5 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Chris Wilson @ 2016-04-15 17:46 UTC (permalink / raw)
To: intel-gfx
To open up the future of using a generic to_i915() convenience macro,
rename the existing __I915__ superconvenience macro.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 78231cc5f40b..6569ebfe8cf1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2004,14 +2004,14 @@ struct drm_i915_private {
*/
};
-static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
+static inline struct drm_i915_private *__to_i915(const struct drm_device *dev)
{
return dev->dev_private;
}
-static inline struct drm_i915_private *dev_to_i915(struct device *dev)
+static inline struct drm_i915_private *dev_to_i915(const struct device *dev)
{
- return to_i915(dev_get_drvdata(dev));
+ return __to_i915(dev_get_drvdata(dev));
}
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
@@ -2492,20 +2492,20 @@ struct drm_i915_cmd_table {
};
/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
-#define __I915__(p) ({ \
+#define to_i915(p) ({ \
struct drm_i915_private *__p; \
if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
__p = (struct drm_i915_private *)p; \
else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
- __p = to_i915((struct drm_device *)p); \
+ __p = __to_i915((struct drm_device *)p); \
else \
BUILD_BUG(); \
__p; \
})
-#define INTEL_INFO(p) (&__I915__(p)->info)
+#define INTEL_INFO(p) (&to_i915(p)->info)
#define INTEL_GEN(p) (INTEL_INFO(p)->gen)
#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
-#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
+#define INTEL_REVID(p) (to_i915(p)->dev->pdev->revision)
#define REVID_FOREVER 0xff
/*
@@ -2630,7 +2630,7 @@ struct drm_i915_cmd_table {
#define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
#define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
-#define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
+#define HAS_EDRAM(dev) (to_i915(dev)->edram_cap & EDRAM_ENABLED)
#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
HAS_EDRAM(dev))
#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
@@ -2714,11 +2714,11 @@ struct drm_i915_cmd_table {
#define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
-#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
+#define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
-#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
-#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
+#define HAS_PCH_LPT_LP(dev) (to_i915(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
+#define HAS_PCH_LPT_H(dev) (to_i915(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
--
2.8.0.rc3
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/6] drm/i915: Allow passing any known pointer to for_each_engine()
2016-04-15 17:45 Polymorphic to_i915() Chris Wilson
2016-04-15 17:46 ` [PATCH 1/6] drm/i915: Rename the magic polymorphic macro __I915__ Chris Wilson
@ 2016-04-15 17:46 ` Chris Wilson
2016-04-15 17:46 ` [PATCH 3/6] drm/i915: Extend magic to_i915() to work with drm_i915_gem_object Chris Wilson
` (4 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2016-04-15 17:46 UTC (permalink / raw)
To: intel-gfx
Rather than require the user to grab a drm_i915_private, allow them to
pass anything that we know how to derive such a pointer user to_i915()
Note this fixes a macro bug in for_each_engine_masked() which was not
using its dev_priv__ parameter.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 18 +++++++++---------
drivers/gpu/drm/i915/i915_gem_context.c | 4 ++--
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6569ebfe8cf1..0a62354ba53d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2020,24 +2020,24 @@ static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
}
/* Simple iterator over all initialised engines */
-#define for_each_engine(engine__, dev_priv__) \
- for ((engine__) = &(dev_priv__)->engine[0]; \
- (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
+#define for_each_engine(engine__, ptr__) \
+ for ((engine__) = &to_i915(ptr__)->engine[0]; \
+ (engine__) < &to_i915(ptr__)->engine[I915_NUM_ENGINES]; \
(engine__)++) \
for_each_if (intel_engine_initialized(engine__))
/* Iterator with engine_id */
-#define for_each_engine_id(engine__, dev_priv__, id__) \
- for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
- (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
+#define for_each_engine_id(engine__, ptr__, id__) \
+ for ((engine__) = &to_i915(ptr__)->engine[0], (id__) = 0; \
+ (engine__) < &to_i915(ptr__)->engine[I915_NUM_ENGINES]; \
(engine__)++) \
for_each_if (((id__) = (engine__)->id, \
intel_engine_initialized(engine__)))
/* Iterator over subset of engines selected by mask */
-#define for_each_engine_masked(engine__, dev_priv__, mask__) \
- for ((engine__) = &(dev_priv__)->engine[0]; \
- (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
+#define for_each_engine_masked(engine__, ptr__, mask__) \
+ for ((engine__) = &to_i915(ptr__)->engine[0]; \
+ (engine__) < &to_i915(ptr__)->engine[I915_NUM_ENGINES]; \
(engine__)++) \
for_each_if (((mask__) & intel_engine_flag(engine__)) && \
intel_engine_initialized(engine__))
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index e5acc3916f75..b8439971c9bb 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -553,7 +553,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
intel_ring_emit(engine,
MI_LOAD_REGISTER_IMM(num_rings));
- for_each_engine(signaller, to_i915(engine->dev)) {
+ for_each_engine(signaller, engine->dev) {
if (signaller == engine)
continue;
@@ -583,7 +583,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
intel_ring_emit(engine,
MI_LOAD_REGISTER_IMM(num_rings));
- for_each_engine(signaller, to_i915(engine->dev)) {
+ for_each_engine(signaller, engine->dev) {
if (signaller == engine)
continue;
--
2.8.0.rc3
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/6] drm/i915: Extend magic to_i915() to work with drm_i915_gem_object
2016-04-15 17:45 Polymorphic to_i915() Chris Wilson
2016-04-15 17:46 ` [PATCH 1/6] drm/i915: Rename the magic polymorphic macro __I915__ Chris Wilson
2016-04-15 17:46 ` [PATCH 2/6] drm/i915: Allow passing any known pointer to for_each_engine() Chris Wilson
@ 2016-04-15 17:46 ` Chris Wilson
2016-04-15 17:46 ` [PATCH 4/6] drm/i915: Use to_i915() instead of guc_to_i915() Chris Wilson
` (3 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2016-04-15 17:46 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 7 ++---
drivers/gpu/drm/i915/i915_drv.h | 18 ++++++-----
drivers/gpu/drm/i915/i915_gem.c | 48 +++++++++++-------------------
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 21 +++++--------
drivers/gpu/drm/i915/i915_gem_fence.c | 8 ++---
drivers/gpu/drm/i915/i915_gem_gtt.c | 5 ++--
drivers/gpu/drm/i915/i915_gem_shrinker.c | 2 +-
drivers/gpu/drm/i915/i915_gem_stolen.c | 4 +--
drivers/gpu/drm/i915/i915_gem_tiling.c | 4 +--
drivers/gpu/drm/i915/i915_gem_userptr.c | 6 ++--
drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
11 files changed, 54 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 931dc6086f3b..f5f9f48f8001 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -135,7 +135,6 @@ static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
static void
describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
struct intel_engine_cs *engine;
struct i915_vma *vma;
int pin_count = 0;
@@ -153,13 +152,13 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
obj->base.size / 1024,
obj->base.read_domains,
obj->base.write_domain);
- for_each_engine_id(engine, dev_priv, id)
+ for_each_engine_id(engine, obj, id)
seq_printf(m, "%x ",
i915_gem_request_get_seqno(obj->last_read_req[id]));
seq_printf(m, "] %x %x%s%s%s",
i915_gem_request_get_seqno(obj->last_write_req),
i915_gem_request_get_seqno(obj->last_fenced_req),
- i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
+ i915_cache_level_str(to_i915(obj), obj->cache_level),
obj->dirty ? " dirty" : "",
obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
if (obj->base.name)
@@ -349,7 +348,7 @@ static int per_file_stats(int id, void *ptr, void *data)
if (obj->base.name || obj->base.dma_buf)
stats->shared += obj->base.size;
- if (USES_FULL_PPGTT(obj->base.dev)) {
+ if (USES_FULL_PPGTT(obj)) {
list_for_each_entry(vma, &obj->vma_list, obj_link) {
struct i915_hw_ppgtt *ppgtt;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0a62354ba53d..282d89d097ae 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2229,6 +2229,12 @@ struct drm_i915_gem_object {
};
#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
+static inline struct drm_i915_private *
+__obj_to_i915(const struct drm_i915_gem_object *obj)
+{
+ return __to_i915(obj->base.dev);
+}
+
void i915_gem_track_fb(struct drm_i915_gem_object *old,
struct drm_i915_gem_object *new,
unsigned frontbuffer_bits);
@@ -2498,6 +2504,8 @@ struct drm_i915_cmd_table {
__p = (struct drm_i915_private *)p; \
else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
__p = __to_i915((struct drm_device *)p); \
+ else if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_gem_object)) \
+ __p = __obj_to_i915((struct drm_i915_gem_object *)p); \
else \
BUILD_BUG(); \
__p; \
@@ -3254,8 +3262,7 @@ static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
static inline unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ struct i915_ggtt *ggtt = &to_i915(obj)->ggtt;
return i915_gem_obj_size(obj, &ggtt->base);
}
@@ -3265,8 +3272,7 @@ i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
uint32_t alignment,
unsigned flags)
{
- struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ struct i915_ggtt *ggtt = &to_i915(obj)->ggtt;
return i915_gem_object_pin(obj, &ggtt->base,
alignment, flags | PIN_GLOBAL);
@@ -3392,9 +3398,7 @@ void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
/* i915_gem_tiling.c */
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
-
- return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
+ return to_i915(obj)->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
obj->tiling_mode != I915_TILING_NONE;
}
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 2a0cb9b17ccd..bbd7bfadbaef 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -356,14 +356,12 @@ out:
void *i915_gem_object_alloc(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
- return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL);
+ return kmem_cache_zalloc(to_i915(dev)->objects, GFP_KERNEL);
}
void i915_gem_object_free(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
- kmem_cache_free(dev_priv->objects, obj);
+ kmem_cache_free(to_i915(obj)->objects, obj);
}
static int
@@ -2019,7 +2017,7 @@ i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(obj);
int ret;
if (drm_vma_node_has_offset(&obj->base.vma_node))
@@ -2240,7 +2238,7 @@ i915_gem_object_put_pages(struct drm_i915_gem_object *obj)
static int
i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(obj);
int page_count, i;
struct address_space *mapping;
struct sg_table *st;
@@ -2375,7 +2373,7 @@ err_pages:
int
i915_gem_object_get_pages(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(obj);
const struct drm_i915_gem_object_ops *ops = obj->ops;
int ret;
@@ -2495,8 +2493,7 @@ i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring)
* so that we don't steal from recently used but inactive objects
* (unless we are forced to ofc!)
*/
- list_move_tail(&obj->global_list,
- &to_i915(obj->base.dev)->mm.bound_list);
+ list_move_tail(&obj->global_list, &to_i915(obj)->mm.bound_list);
list_for_each_entry(vma, &obj->vma_list, obj_link) {
if (!list_empty(&vma->vm_link))
@@ -3218,7 +3215,7 @@ __i915_gem_object_sync(struct drm_i915_gem_object *obj,
return 0;
if (!i915_semaphore_is_enabled(obj->base.dev)) {
- struct drm_i915_private *i915 = to_i915(obj->base.dev);
+ struct drm_i915_private *i915 = to_i915(obj);
ret = __i915_wait_request(from_req,
i915->mm.interruptible,
NULL,
@@ -3354,7 +3351,7 @@ static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
static int __i915_vma_unbind(struct i915_vma *vma, bool wait)
{
struct drm_i915_gem_object *obj = vma->obj;
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(obj);
int ret;
if (list_empty(&vma->obj_link))
@@ -3758,9 +3755,6 @@ i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
int
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
{
- struct drm_device *dev = obj->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
uint32_t old_write_domain, old_read_domains;
struct i915_vma *vma;
int ret;
@@ -3815,7 +3809,7 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
vma = i915_gem_obj_to_ggtt(obj);
if (vma && drm_mm_node_allocated(&vma->node) && !obj->active)
list_move_tail(&vma->vm_link,
- &ggtt->base.inactive_list);
+ &to_i915(obj)->ggtt.base.inactive_list);
return 0;
}
@@ -3836,7 +3830,6 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
enum i915_cache_level cache_level)
{
- struct drm_device *dev = obj->base.dev;
struct i915_vma *vma, *next;
bool bound = false;
int ret = 0;
@@ -3882,7 +3875,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
if (ret)
return ret;
- if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) {
+ if (!HAS_LLC(obj) && cache_level != I915_CACHE_NONE) {
/* Access to snoopable pages through the GTT is
* incoherent and on some machines causes a hard
* lockup. Relinquish the CPU mmaping to force
@@ -4053,7 +4046,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
* with that bit in the PTE to main memory with just one PIPE_CONTROL.
*/
ret = i915_gem_object_set_cache_level(obj,
- HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE);
+ HAS_WT(obj) ? I915_CACHE_WT : I915_CACHE_NONE);
if (ret)
goto err_unpin_display;
@@ -4250,7 +4243,7 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
(vma->node.start & (fence_alignment - 1)) == 0);
mappable = (vma->node.start + fence_size <=
- to_i915(obj->base.dev)->ggtt.mappable_end);
+ to_i915(obj)->ggtt.mappable_end);
obj->map_and_fenceable = mappable && fenceable;
}
@@ -4262,7 +4255,7 @@ i915_gem_object_do_pin(struct drm_i915_gem_object *obj,
uint32_t alignment,
uint64_t flags)
{
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(obj);
struct i915_vma *vma;
unsigned bound;
int ret;
@@ -4344,9 +4337,7 @@ i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
uint32_t alignment,
uint64_t flags)
{
- struct drm_device *dev = obj->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ struct i915_ggtt *ggtt = &to_i915(obj)->ggtt;
BUG_ON(!view);
@@ -4497,7 +4488,7 @@ void i915_gem_object_init(struct drm_i915_gem_object *obj,
obj->fence_reg = I915_FENCE_REG_NONE;
obj->madv = I915_MADV_WILLNEED;
- i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size);
+ i915_gem_info_add_obj(to_i915(obj), obj->base.size);
}
static const struct drm_i915_gem_object_ops i915_gem_object_ops = {
@@ -4590,8 +4581,7 @@ static bool discard_backing_storage(struct drm_i915_gem_object *obj)
void i915_gem_free_object(struct drm_gem_object *gem_obj)
{
struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
- struct drm_device *dev = obj->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(obj);
struct i915_vma *vma, *next;
intel_runtime_pm_get(dev_priv);
@@ -4666,9 +4656,7 @@ struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
const struct i915_ggtt_view *view)
{
- struct drm_device *dev = obj->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ struct i915_ggtt *ggtt = &to_i915(obj)->ggtt;
struct i915_vma *vma;
BUG_ON(!view);
@@ -4693,7 +4681,7 @@ void i915_gem_vma_destroy(struct i915_vma *vma)
list_del(&vma->obj_link);
- kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma);
+ kmem_cache_free(to_i915(vma->obj)->vmas, vma);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 6f4f2a6cdf93..86911dcafb6a 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -241,7 +241,7 @@ static void eb_destroy(struct eb_vmas *eb)
static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
{
- return (HAS_LLC(obj->base.dev) ||
+ return (HAS_LLC(obj) ||
obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
obj->cache_level != I915_CACHE_NONE);
}
@@ -276,7 +276,6 @@ relocate_entry_cpu(struct drm_i915_gem_object *obj,
struct drm_i915_gem_relocation_entry *reloc,
uint64_t target_offset)
{
- struct drm_device *dev = obj->base.dev;
uint32_t page_offset = offset_in_page(reloc->offset);
uint64_t delta = relocation_target(reloc, target_offset);
char *vaddr;
@@ -290,7 +289,7 @@ relocate_entry_cpu(struct drm_i915_gem_object *obj,
reloc->offset >> PAGE_SHIFT));
*(uint32_t *)(vaddr + page_offset) = lower_32_bits(delta);
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_INFO(obj)->gen >= 8) {
page_offset = offset_in_page(page_offset + sizeof(uint32_t));
if (page_offset == 0) {
@@ -312,9 +311,7 @@ relocate_entry_gtt(struct drm_i915_gem_object *obj,
struct drm_i915_gem_relocation_entry *reloc,
uint64_t target_offset)
{
- struct drm_device *dev = obj->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ struct i915_ggtt *ggtt = &to_i915(obj)->ggtt;
uint64_t delta = relocation_target(reloc, target_offset);
uint64_t offset;
void __iomem *reloc_page;
@@ -335,7 +332,7 @@ relocate_entry_gtt(struct drm_i915_gem_object *obj,
offset & PAGE_MASK);
iowrite32(lower_32_bits(delta), reloc_page + offset_in_page(offset));
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_INFO(obj)->gen >= 8) {
offset += sizeof(uint32_t);
if (offset_in_page(offset) == 0) {
@@ -368,7 +365,6 @@ relocate_entry_clflush(struct drm_i915_gem_object *obj,
struct drm_i915_gem_relocation_entry *reloc,
uint64_t target_offset)
{
- struct drm_device *dev = obj->base.dev;
uint32_t page_offset = offset_in_page(reloc->offset);
uint64_t delta = relocation_target(reloc, target_offset);
char *vaddr;
@@ -382,7 +378,7 @@ relocate_entry_clflush(struct drm_i915_gem_object *obj,
reloc->offset >> PAGE_SHIFT));
clflush_write32(vaddr + page_offset, lower_32_bits(delta));
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_INFO(obj)->gen >= 8) {
page_offset = offset_in_page(page_offset + sizeof(uint32_t));
if (page_offset == 0) {
@@ -404,7 +400,6 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
struct eb_vmas *eb,
struct drm_i915_gem_relocation_entry *reloc)
{
- struct drm_device *dev = obj->base.dev;
struct drm_gem_object *target_obj;
struct drm_i915_gem_object *target_i915_obj;
struct i915_vma *target_vma;
@@ -423,7 +418,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
/* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
* pipe_control writes because the gpu doesn't properly redirect them
* through the ppgtt for non_secure batchbuffers. */
- if (unlikely(IS_GEN6(dev) &&
+ if (unlikely(IS_GEN6(obj) &&
reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION)) {
ret = i915_vma_bind(target_vma, target_i915_obj->cache_level,
PIN_GLOBAL);
@@ -465,7 +460,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
/* Check that the relocation address is valid... */
if (unlikely(reloc->offset >
- obj->base.size - (INTEL_INFO(dev)->gen >= 8 ? 8 : 4))) {
+ obj->base.size - (INTEL_INFO(obj)->gen >= 8 ? 8 : 4))) {
DRM_DEBUG("Relocation beyond object bounds: "
"obj %p target %d offset %d size %d.\n",
obj, reloc->target_handle,
@@ -673,7 +668,7 @@ need_reloc_mappable(struct i915_vma *vma)
return false;
/* See also use_cpu_reloc() */
- if (HAS_LLC(vma->obj->base.dev))
+ if (HAS_LLC(vma->obj))
return false;
if (vma->obj->base.write_domain == I915_GEM_DOMAIN_CPU)
diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index a2b938ec01a7..b1a3a5270bad 100644
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -229,7 +229,7 @@ static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj,
struct drm_i915_fence_reg *fence,
bool enable)
{
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(obj);
int reg = fence_number(dev_priv, fence);
i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL);
@@ -286,7 +286,7 @@ i915_gem_object_wait_fence(struct drm_i915_gem_object *obj)
int
i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(obj);
struct drm_i915_fence_reg *fence;
int ret;
@@ -433,7 +433,7 @@ bool
i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
{
if (obj->fence_reg != I915_FENCE_REG_NONE) {
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(obj);
struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj);
WARN_ON(!ggtt_vma ||
@@ -457,7 +457,7 @@ void
i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
{
if (obj->fence_reg != I915_FENCE_REG_NONE) {
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(obj);
WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
dev_priv->fence_regs[obj->fence_reg].pin_count--;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 9f165feb54ae..627a4accc6e3 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3308,7 +3308,7 @@ __i915_gem_vma_create(struct drm_i915_gem_object *obj,
if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view))
return ERR_PTR(-EINVAL);
- vma = kmem_cache_zalloc(to_i915(obj->base.dev)->vmas, GFP_KERNEL);
+ vma = kmem_cache_zalloc(to_i915(obj)->vmas, GFP_KERNEL);
if (vma == NULL)
return ERR_PTR(-ENOMEM);
@@ -3347,8 +3347,7 @@ struct i915_vma *
i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
const struct i915_ggtt_view *view)
{
- struct drm_device *dev = obj->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(obj);
struct i915_ggtt *ggtt = &dev_priv->ggtt;
struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view);
diff --git a/drivers/gpu/drm/i915/i915_gem_shrinker.c b/drivers/gpu/drm/i915/i915_gem_shrinker.c
index adde5d8c3c18..a261f60066f1 100644
--- a/drivers/gpu/drm/i915/i915_gem_shrinker.c
+++ b/drivers/gpu/drm/i915/i915_gem_shrinker.c
@@ -431,7 +431,7 @@ static bool can_migrate_page(struct drm_i915_gem_object *obj)
static int do_migrate_page(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
+ struct drm_i915_private *dev_priv = to_i915(obj);
int ret = 0;
if (!can_migrate_page(obj))
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index ea06da012d32..51da16d9eee0 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -546,10 +546,8 @@ static void i915_gem_object_put_pages_stolen(struct drm_i915_gem_object *obj)
static void
i915_gem_object_release_stolen(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
-
if (obj->stolen) {
- i915_gem_stolen_remove_node(dev_priv, obj->stolen);
+ i915_gem_stolen_remove_node(to_i915(obj), obj->stolen);
kfree(obj->stolen);
obj->stolen = NULL;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 7410f6c962e7..bc4cb7f4fe80 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -122,10 +122,10 @@ i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
if (tiling_mode == I915_TILING_NONE)
return true;
- if (INTEL_INFO(obj->base.dev)->gen >= 4)
+ if (INTEL_INFO(obj)->gen >= 4)
return true;
- if (INTEL_INFO(obj->base.dev)->gen == 3) {
+ if (INTEL_INFO(obj)->gen == 3) {
if (i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK)
return false;
} else {
diff --git a/drivers/gpu/drm/i915/i915_gem_userptr.c b/drivers/gpu/drm/i915/i915_gem_userptr.c
index 32d9726e38b1..3692bdb0feeb 100644
--- a/drivers/gpu/drm/i915/i915_gem_userptr.c
+++ b/drivers/gpu/drm/i915/i915_gem_userptr.c
@@ -344,7 +344,7 @@ __i915_mm_struct_find(struct drm_i915_private *dev_priv, struct mm_struct *real)
static int
i915_gem_userptr_init__mm_struct(struct drm_i915_gem_object *obj)
{
- struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
+ struct drm_i915_private *dev_priv = to_i915(obj);
struct i915_mm_struct *mm;
int ret = 0;
@@ -368,7 +368,7 @@ i915_gem_userptr_init__mm_struct(struct drm_i915_gem_object *obj)
}
kref_init(&mm->kref);
- mm->i915 = to_i915(obj->base.dev);
+ mm->i915 = to_i915(obj);
mm->mm = current->mm;
atomic_inc(¤t->mm->mm_count);
@@ -417,7 +417,7 @@ i915_gem_userptr_release__mm_struct(struct drm_i915_gem_object *obj)
kref_put_mutex(&obj->userptr.mm->kref,
__i915_mm_struct_free,
- &to_i915(obj->base.dev)->mm_lock);
+ &to_i915(obj)->mm_lock);
obj->userptr.mm = NULL;
}
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0d24494904ef..89811fbe723e 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -2083,7 +2083,7 @@ static int init_phys_status_page(struct intel_engine_cs *engine)
void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf)
{
- if (HAS_LLC(ringbuf->obj->base.dev) && !ringbuf->obj->stolen)
+ if (HAS_LLC(ringbuf->obj) && !ringbuf->obj->stolen)
i915_gem_object_unpin_map(ringbuf->obj);
else
iounmap(ringbuf->virtual_start);
--
2.8.0.rc3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/6] drm/i915: Use to_i915() instead of guc_to_i915()
2016-04-15 17:45 Polymorphic to_i915() Chris Wilson
` (2 preceding siblings ...)
2016-04-15 17:46 ` [PATCH 3/6] drm/i915: Extend magic to_i915() to work with drm_i915_gem_object Chris Wilson
@ 2016-04-15 17:46 ` Chris Wilson
2016-04-15 17:46 ` [PATCH 5/6] drm/i915: Teach to_i915() how to extract drm_i915_private from requests Chris Wilson
` (2 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2016-04-15 17:46 UTC (permalink / raw)
To: intel-gfx
The convenience of saving a few characters by using a consistent
interface to obtain our drm_i915_private struct from intel_guc.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 5 ++++-
drivers/gpu/drm/i915/i915_guc_submission.c | 17 +++++++----------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 282d89d097ae..76eeb47c9c15 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2014,7 +2014,8 @@ static inline struct drm_i915_private *dev_to_i915(const struct device *dev)
return __to_i915(dev_get_drvdata(dev));
}
-static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
+static inline struct drm_i915_private *
+__guc_to_i915(const struct intel_guc *guc)
{
return container_of(guc, struct drm_i915_private, guc);
}
@@ -2506,6 +2507,8 @@ struct drm_i915_cmd_table {
__p = __to_i915((struct drm_device *)p); \
else if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_gem_object)) \
__p = __obj_to_i915((struct drm_i915_gem_object *)p); \
+ else if (__builtin_types_compatible_p(typeof(*p), struct intel_guc)) \
+ __p = __guc_to_i915((struct intel_guc *)p); \
else \
BUILD_BUG(); \
__p; \
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c
index da86bdbba275..c10cb13d0fc9 100644
--- a/drivers/gpu/drm/i915/i915_guc_submission.c
+++ b/drivers/gpu/drm/i915/i915_guc_submission.c
@@ -77,7 +77,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv,
static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = to_i915(guc);
u32 status;
int i;
int ret;
@@ -152,7 +152,7 @@ static int host2guc_release_doorbell(struct intel_guc *guc,
static int host2guc_sample_forcewake(struct intel_guc *guc,
struct i915_guc_client *client)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = to_i915(guc);
struct drm_device *dev = dev_priv->dev;
u32 data[2];
@@ -254,7 +254,7 @@ static int guc_ring_doorbell(struct i915_guc_client *gc)
static void guc_disable_doorbell(struct intel_guc *guc,
struct i915_guc_client *client)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = to_i915(guc);
struct guc_doorbell_info *doorbell;
void *base;
i915_reg_t drbreg = GEN8_DRBREGL(client->doorbell_id);
@@ -376,7 +376,6 @@ static void guc_init_proc_desc(struct intel_guc *guc,
static void guc_init_ctx_desc(struct intel_guc *guc,
struct i915_guc_client *client)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct intel_engine_cs *engine;
struct intel_context *ctx = client->owner;
struct guc_context_desc desc;
@@ -390,7 +389,7 @@ static void guc_init_ctx_desc(struct intel_guc *guc,
desc.priority = client->priority;
desc.db_id = client->doorbell_id;
- for_each_engine_id(engine, dev_priv, id) {
+ for_each_engine_id(engine, guc, id) {
struct guc_execlist_context *lrc = &desc.lrc[engine->guc_id];
struct drm_i915_gem_object *obj;
uint64_t ctx_desc;
@@ -772,7 +771,6 @@ err:
static void guc_create_log(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
struct drm_i915_gem_object *obj;
unsigned long offset;
uint32_t size, flags;
@@ -791,7 +789,7 @@ static void guc_create_log(struct intel_guc *guc)
obj = guc->log_obj;
if (!obj) {
- obj = gem_allocate_guc_obj(dev_priv->dev, size);
+ obj = gem_allocate_guc_obj(to_i915(guc)->dev, size);
if (!obj) {
/* logging will be off */
i915.guc_log_level = -1;
@@ -835,7 +833,7 @@ static void init_guc_policies(struct guc_policies *policies)
static void guc_create_ads(struct intel_guc *guc)
{
- struct drm_i915_private *dev_priv = guc_to_i915(guc);
+ struct drm_i915_private *dev_priv = to_i915(guc);
struct drm_i915_gem_object *obj;
struct guc_ads *ads;
struct guc_policies *policies;
@@ -868,8 +866,7 @@ static void guc_create_ads(struct intel_guc *guc)
* so its address won't change after we've told the GuC where
* to find it.
*/
- engine = &dev_priv->engine[RCS];
- ads->golden_context_lrca = engine->status_page.gfx_addr;
+ ads->golden_context_lrca = dev_priv->engine[RCS].status_page.gfx_addr;
for_each_engine(engine, dev_priv)
ads->eng_state_size[engine->guc_id] = intel_lr_context_size(engine);
--
2.8.0.rc3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 5/6] drm/i915: Teach to_i915() how to extract drm_i915_private from requests
2016-04-15 17:45 Polymorphic to_i915() Chris Wilson
` (3 preceding siblings ...)
2016-04-15 17:46 ` [PATCH 4/6] drm/i915: Use to_i915() instead of guc_to_i915() Chris Wilson
@ 2016-04-15 17:46 ` Chris Wilson
2016-04-15 17:46 ` [PATCH 6/6] drm/i915: Teach to_i915() how to extract drm_i915_private from engines Chris Wilson
2016-04-18 9:18 ` Polymorphic to_i915() Jani Nikula
6 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2016-04-15 17:46 UTC (permalink / raw)
To: intel-gfx
Since drm_i915_gem_request already contains a backpointer to
drm_i915_private, this is a fairly trivial operation. However, using a
consistent interface does lean convenience to when we need to query
device properties, for example.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 8 +++++++
drivers/gpu/drm/i915/i915_gem.c | 18 ++++++--------
drivers/gpu/drm/i915/i915_gem_context.c | 21 ++++++++---------
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 3 +--
drivers/gpu/drm/i915/i915_gem_gtt.c | 3 +--
drivers/gpu/drm/i915/intel_lrc.c | 19 +++++++--------
drivers/gpu/drm/i915/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 3 +--
drivers/gpu/drm/i915/intel_ringbuffer.c | 38 +++++++++++++-----------------
9 files changed, 54 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 76eeb47c9c15..c6ead62bc411 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2338,6 +2338,12 @@ struct drm_i915_gem_request {
};
+static inline struct drm_i915_private *
+__request_to_i915(const struct drm_i915_gem_request *request)
+{
+ return request->i915;
+}
+
struct drm_i915_gem_request * __must_check
i915_gem_request_alloc(struct intel_engine_cs *engine,
struct intel_context *ctx);
@@ -2509,6 +2515,8 @@ struct drm_i915_cmd_table {
__p = __obj_to_i915((struct drm_i915_gem_object *)p); \
else if (__builtin_types_compatible_p(typeof(*p), struct intel_guc)) \
__p = __guc_to_i915((struct intel_guc *)p); \
+ else if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_gem_request)) \
+ __p = __request_to_i915((struct drm_i915_gem_request *)(p)); \
else \
BUILD_BUG(); \
__p; \
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index bbd7bfadbaef..237d5e884610 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1442,18 +1442,16 @@ __i915_gem_request_retire__upto(struct drm_i915_gem_request *req)
int
i915_wait_request(struct drm_i915_gem_request *req)
{
- struct drm_device *dev;
struct drm_i915_private *dev_priv;
bool interruptible;
int ret;
BUG_ON(req == NULL);
- dev = req->engine->dev;
- dev_priv = dev->dev_private;
+ dev_priv = to_i915(req);
interruptible = dev_priv->mm.interruptible;
- BUG_ON(!mutex_is_locked(&dev->struct_mutex));
+ BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
ret = __i915_wait_request(req, interruptible, NULL, NULL);
if (ret)
@@ -2589,7 +2587,7 @@ void __i915_add_request(struct drm_i915_gem_request *request,
return;
engine = request->engine;
- dev_priv = request->i915;
+ dev_priv = to_i915(request);
ringbuf = request->ringbuf;
/*
@@ -2721,13 +2719,13 @@ void i915_gem_request_free(struct kref *req_ref)
i915_gem_request_remove_from_client(req);
if (ctx) {
- if (i915.enable_execlists && ctx != req->i915->kernel_context)
+ if (i915.enable_execlists && ctx != to_i915(req)->kernel_context)
intel_lr_context_unpin(ctx, req->engine);
i915_gem_context_unreference(ctx);
}
- kmem_cache_free(req->i915->requests, req);
+ kmem_cache_free(to_i915(req)->requests, req);
}
static inline int
@@ -4729,12 +4727,10 @@ err:
int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
{
struct intel_engine_cs *engine = req->engine;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
+ u32 *remap_info = to_i915(req)->l3_parity.remap_info[slice];
int i, ret;
- if (!HAS_L3_DPF(dev) || !remap_info)
+ if (!HAS_L3_DPF(req) || !remap_info)
return 0;
ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index b8439971c9bb..e53889498696 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -515,7 +515,7 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
const int num_rings =
/* Use an extended w/a on ivb+ if signalling from other rings */
i915_semaphore_is_enabled(engine->dev) ?
- hweight32(INTEL_INFO(engine->dev)->ring_mask) - 1 :
+ hweight32(INTEL_INFO(req)->ring_mask) - 1 :
0;
int len, ret;
@@ -524,21 +524,21 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
* explicitly, so we rely on the value at ring init, stored in
* itlb_before_ctx_switch.
*/
- if (IS_GEN6(engine->dev)) {
+ if (IS_GEN6(req)) {
ret = engine->flush(req, I915_GEM_GPU_DOMAINS, 0);
if (ret)
return ret;
}
/* These flags are for resource streamer on HSW+ */
- if (IS_HASWELL(engine->dev) || INTEL_INFO(engine->dev)->gen >= 8)
+ if (IS_HASWELL(req) || INTEL_INFO(req)->gen >= 8)
flags |= (HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN);
- else if (INTEL_INFO(engine->dev)->gen < 8)
+ else if (INTEL_INFO(req)->gen < 8)
flags |= (MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN);
len = 4;
- if (INTEL_INFO(engine->dev)->gen >= 7)
+ if (INTEL_INFO(req)->gen >= 7)
len += 2 + (num_rings ? 4*num_rings + 6 : 0);
ret = intel_ring_begin(req, len);
@@ -546,14 +546,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
return ret;
/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
- if (INTEL_INFO(engine->dev)->gen >= 7) {
+ if (INTEL_INFO(req)->gen >= 7) {
intel_ring_emit(engine, MI_ARB_ON_OFF | MI_ARB_DISABLE);
if (num_rings) {
struct intel_engine_cs *signaller;
intel_ring_emit(engine,
MI_LOAD_REGISTER_IMM(num_rings));
- for_each_engine(signaller, engine->dev) {
+ for_each_engine(signaller, req) {
if (signaller == engine)
continue;
@@ -576,14 +576,14 @@ mi_set_context(struct drm_i915_gem_request *req, u32 hw_flags)
*/
intel_ring_emit(engine, MI_NOOP);
- if (INTEL_INFO(engine->dev)->gen >= 7) {
+ if (INTEL_INFO(req)->gen >= 7) {
if (num_rings) {
struct intel_engine_cs *signaller;
i915_reg_t last_reg = {}; /* keep gcc quiet */
intel_ring_emit(engine,
MI_LOAD_REGISTER_IMM(num_rings));
- for_each_engine(signaller, engine->dev) {
+ for_each_engine(signaller, req) {
if (signaller == engine)
continue;
@@ -817,10 +817,9 @@ unpin_out:
int i915_switch_context(struct drm_i915_gem_request *req)
{
struct intel_engine_cs *engine = req->engine;
- struct drm_i915_private *dev_priv = req->i915;
WARN_ON(i915.enable_execlists);
- WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
+ WARN_ON(!mutex_is_locked(&to_i915(req)->dev->struct_mutex));
if (engine->id != RCS ||
req->ctx->legacy_hw_ctx.rcs_state == NULL) {
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 86911dcafb6a..9c582c815af2 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1095,7 +1095,6 @@ void
i915_gem_execbuffer_move_to_active(struct list_head *vmas,
struct drm_i915_gem_request *req)
{
- struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
struct i915_vma *vma;
list_for_each_entry(vma, vmas, exec_list) {
@@ -1122,7 +1121,7 @@ i915_gem_execbuffer_move_to_active(struct list_head *vmas,
if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
i915_gem_request_assign(&obj->last_fenced_req, req);
if (entry->flags & __EXEC_OBJECT_HAS_FENCE) {
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = to_i915(req);
list_move_tail(&dev_priv->fence_regs[obj->fence_reg].lru_list,
&dev_priv->mm.fence_list);
}
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 627a4accc6e3..780e3ad3ca10 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2182,8 +2182,7 @@ int i915_ppgtt_init_hw(struct drm_device *dev)
int i915_ppgtt_init_ring(struct drm_i915_gem_request *req)
{
- struct drm_i915_private *dev_priv = req->i915;
- struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
+ struct i915_hw_ppgtt *ppgtt = to_i915(req)->mm.aliasing_ppgtt;
if (i915.enable_execlists)
return 0;
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 7141a2a3f481..1926bef2e612 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -612,7 +612,7 @@ static void execlists_context_queue(struct drm_i915_gem_request *request)
struct drm_i915_gem_request *cursor;
int num_elements = 0;
- if (request->ctx != request->i915->kernel_context)
+ if (request->ctx != to_i915(request)->kernel_context)
intel_lr_context_pin(request->ctx, engine);
i915_gem_request_reference(request);
@@ -708,14 +708,14 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
* going any further, as the i915_add_request() call
* later on mustn't fail ...
*/
- struct intel_guc *guc = &request->i915->guc;
+ struct intel_guc *guc = &to_i915(request)->guc;
ret = i915_guc_wq_check_space(guc->execbuf_client);
if (ret)
return ret;
}
- if (request->ctx != request->i915->kernel_context)
+ if (request->ctx != to_i915(request)->kernel_context)
ret = intel_lr_context_pin(request->ctx, request->engine);
return ret;
@@ -776,7 +776,7 @@ static int
intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
{
struct intel_ringbuffer *ringbuf = request->ringbuf;
- struct drm_i915_private *dev_priv = request->i915;
+ struct drm_i915_private *dev_priv = to_i915(request);
struct intel_engine_cs *engine = request->engine;
intel_logical_ring_advance(ringbuf);
@@ -798,7 +798,7 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
if (engine->last_context != request->ctx) {
if (engine->last_context)
intel_lr_context_unpin(engine->last_context, engine);
- if (request->ctx != request->i915->kernel_context) {
+ if (request->ctx != to_i915(request)->kernel_context) {
intel_lr_context_pin(request->ctx, engine);
engine->last_context = request->ctx;
} else {
@@ -1030,7 +1030,7 @@ void intel_execlists_retire_requests(struct intel_engine_cs *engine)
struct drm_i915_gem_object *ctx_obj =
ctx->engine[engine->id].state;
- if (ctx_obj && (ctx != req->i915->kernel_context))
+ if (ctx_obj && (ctx != to_i915(req)->kernel_context))
intel_lr_context_unpin(ctx, engine);
list_del(&req->execlist_link);
@@ -1168,8 +1168,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
int ret, i;
struct intel_engine_cs *engine = req->engine;
struct intel_ringbuffer *ringbuf = req->ringbuf;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(req);
struct i915_workarounds *w = &dev_priv->workarounds;
if (w->count == 0)
@@ -1708,8 +1707,8 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
* not needed in 48-bit.*/
if (req->ctx->ppgtt &&
(intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
- if (!USES_FULL_48BIT_PPGTT(req->i915) &&
- !intel_vgpu_active(req->i915->dev)) {
+ if (!USES_FULL_48BIT_PPGTT(req) &&
+ !intel_vgpu_active(to_i915(req)->dev)) {
ret = intel_logical_ring_emit_pdps(req);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index 23b8545ad6b0..b7b5fefa0cec 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -405,7 +405,7 @@ int intel_rcs_context_init_mocs(struct drm_i915_gem_request *req)
struct drm_i915_mocs_table t;
int ret;
- if (get_mocs_settings(req->i915, &t)) {
+ if (get_mocs_settings(to_i915(req), &t)) {
/* Program the RCS control registers */
ret = emit_mocs_control_table(req, &t);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b7c218602c6e..f7bb0084a557 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7363,8 +7363,7 @@ static void __intel_rps_boost_work(struct work_struct *work)
struct drm_i915_gem_request *req = boost->req;
if (!i915_gem_request_completed(req, true))
- gen6_rps_boost(to_i915(req->engine->dev), NULL,
- req->emitted_jiffies);
+ gen6_rps_boost(to_i915(req), NULL, req->emitted_jiffies);
i915_gem_request_unreference__unlocked(req);
kfree(boost);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 89811fbe723e..0c8c2d40987f 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -107,7 +107,6 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
u32 flush_domains)
{
struct intel_engine_cs *engine = req->engine;
- struct drm_device *dev = engine->dev;
u32 cmd;
int ret;
@@ -146,7 +145,7 @@ gen4_render_ring_flush(struct drm_i915_gem_request *req,
cmd |= MI_EXE_FLUSH;
if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
- (IS_G4X(dev) || IS_GEN5(dev)))
+ (IS_G4X(req) || IS_GEN5(req)))
cmd |= MI_INVALIDATE_ISP;
ret = intel_ring_begin(req, 2);
@@ -710,8 +709,7 @@ static int intel_ring_workarounds_emit(struct drm_i915_gem_request *req)
{
int ret, i;
struct intel_engine_cs *engine = req->engine;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(req);
struct i915_workarounds *w = &dev_priv->workarounds;
if (w->count == 0)
@@ -1278,13 +1276,12 @@ static int gen8_rcs_signal(struct drm_i915_gem_request *signaller_req,
{
#define MBOX_UPDATE_DWORDS 8
struct intel_engine_cs *signaller = signaller_req->engine;
- struct drm_device *dev = signaller->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(signaller_req);
struct intel_engine_cs *waiter;
enum intel_engine_id id;
int ret, num_rings;
- num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
+ num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
#undef MBOX_UPDATE_DWORDS
@@ -1320,13 +1317,12 @@ static int gen8_xcs_signal(struct drm_i915_gem_request *signaller_req,
{
#define MBOX_UPDATE_DWORDS 6
struct intel_engine_cs *signaller = signaller_req->engine;
- struct drm_device *dev = signaller->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(signaller_req);
struct intel_engine_cs *waiter;
enum intel_engine_id id;
int ret, num_rings;
- num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
+ num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
num_dwords += (num_rings-1) * MBOX_UPDATE_DWORDS;
#undef MBOX_UPDATE_DWORDS
@@ -1359,14 +1355,13 @@ static int gen6_signal(struct drm_i915_gem_request *signaller_req,
unsigned int num_dwords)
{
struct intel_engine_cs *signaller = signaller_req->engine;
- struct drm_device *dev = signaller->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(signaller_req);
struct intel_engine_cs *useless;
enum intel_engine_id id;
int ret, num_rings;
#define MBOX_UPDATE_DWORDS 3
- num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
+ num_rings = hweight32(INTEL_INFO(dev_priv)->ring_mask);
num_dwords += round_up((num_rings-1) * MBOX_UPDATE_DWORDS, 2);
#undef MBOX_UPDATE_DWORDS
@@ -1446,7 +1441,7 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req,
u32 seqno)
{
struct intel_engine_cs *waiter = waiter_req->engine;
- struct drm_i915_private *dev_priv = waiter->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(waiter_req);
int ret;
ret = intel_ring_begin(waiter_req, 4);
@@ -2367,7 +2362,7 @@ int intel_engine_idle(struct intel_engine_cs *engine)
/* Make sure we do not trigger any retires */
return __i915_wait_request(req,
- req->i915->mm.interruptible,
+ to_i915(req)->mm.interruptible,
NULL, NULL);
}
@@ -2495,7 +2490,7 @@ int intel_ring_begin(struct drm_i915_gem_request *req,
WARN_ON(req == NULL);
engine = req->engine;
- dev_priv = req->i915;
+ dev_priv = to_i915(req);
ret = __intel_ring_prepare(engine, num_dwords * sizeof(uint32_t));
if (ret)
@@ -2608,7 +2603,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
return ret;
cmd = MI_FLUSH_DW;
- if (INTEL_INFO(engine->dev)->gen >= 8)
+ if (INTEL_INFO(req)->gen >= 8)
cmd += 1;
/* We always require a command barrier so that subsequent
@@ -2630,7 +2625,7 @@ static int gen6_bsd_ring_flush(struct drm_i915_gem_request *req,
intel_ring_emit(engine, cmd);
intel_ring_emit(engine,
I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
- if (INTEL_INFO(engine->dev)->gen >= 8) {
+ if (INTEL_INFO(req)->gen >= 8) {
intel_ring_emit(engine, 0); /* upper addr */
intel_ring_emit(engine, 0); /* value */
} else {
@@ -2647,7 +2642,7 @@ gen8_ring_dispatch_execbuffer(struct drm_i915_gem_request *req,
unsigned dispatch_flags)
{
struct intel_engine_cs *engine = req->engine;
- bool ppgtt = USES_PPGTT(engine->dev) &&
+ bool ppgtt = USES_PPGTT(req) &&
!(dispatch_flags & I915_DISPATCH_SECURE);
int ret;
@@ -2721,7 +2716,6 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
u32 invalidate, u32 flush)
{
struct intel_engine_cs *engine = req->engine;
- struct drm_device *dev = engine->dev;
uint32_t cmd;
int ret;
@@ -2730,7 +2724,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
return ret;
cmd = MI_FLUSH_DW;
- if (INTEL_INFO(dev)->gen >= 8)
+ if (INTEL_INFO(req)->gen >= 8)
cmd += 1;
/* We always require a command barrier so that subsequent
@@ -2751,7 +2745,7 @@ static int gen6_ring_flush(struct drm_i915_gem_request *req,
intel_ring_emit(engine, cmd);
intel_ring_emit(engine,
I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
- if (INTEL_INFO(dev)->gen >= 8) {
+ if (INTEL_INFO(req)->gen >= 8) {
intel_ring_emit(engine, 0); /* upper addr */
intel_ring_emit(engine, 0); /* value */
} else {
--
2.8.0.rc3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 6/6] drm/i915: Teach to_i915() how to extract drm_i915_private from engines
2016-04-15 17:45 Polymorphic to_i915() Chris Wilson
` (4 preceding siblings ...)
2016-04-15 17:46 ` [PATCH 5/6] drm/i915: Teach to_i915() how to extract drm_i915_private from requests Chris Wilson
@ 2016-04-15 17:46 ` Chris Wilson
2016-04-18 9:18 ` Polymorphic to_i915() Jani Nikula
6 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2016-04-15 17:46 UTC (permalink / raw)
To: intel-gfx
This is primarily intended to simplify later patches that add various
backpointers to the structs, but in the meantime we can enjoy various
little syntactic conveniences.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 12 +-
drivers/gpu/drm/i915/i915_drv.h | 12 +-
drivers/gpu/drm/i915/i915_gem.c | 7 +-
drivers/gpu/drm/i915/i915_gem_context.c | 6 +-
drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
drivers/gpu/drm/i915/i915_irq.c | 28 ++--
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_lrc.c | 132 ++++++++----------
drivers/gpu/drm/i915/intel_mocs.c | 2 +-
drivers/gpu/drm/i915/intel_ringbuffer.c | 212 +++++++++++++----------------
drivers/gpu/drm/i915/intel_uncore.c | 4 +-
12 files changed, 194 insertions(+), 229 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index a337f33bec5b..bd8b1aef4882 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -750,12 +750,12 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
int cmd_table_count;
int ret;
- if (!IS_GEN7(engine->dev))
+ if (!IS_GEN7(engine))
return 0;
switch (engine->id) {
case RCS:
- if (IS_HASWELL(engine->dev)) {
+ if (IS_HASWELL(engine)) {
cmd_tables = hsw_render_ring_cmds;
cmd_table_count =
ARRAY_SIZE(hsw_render_ring_cmds);
@@ -764,7 +764,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
cmd_table_count = ARRAY_SIZE(gen7_render_cmds);
}
- if (IS_HASWELL(engine->dev)) {
+ if (IS_HASWELL(engine)) {
engine->reg_tables = hsw_render_reg_tables;
engine->reg_table_count = ARRAY_SIZE(hsw_render_reg_tables);
} else {
@@ -780,7 +780,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
engine->get_cmd_length_mask = gen7_bsd_get_cmd_length_mask;
break;
case BCS:
- if (IS_HASWELL(engine->dev)) {
+ if (IS_HASWELL(engine)) {
cmd_tables = hsw_blt_ring_cmds;
cmd_table_count = ARRAY_SIZE(hsw_blt_ring_cmds);
} else {
@@ -788,7 +788,7 @@ int i915_cmd_parser_init_ring(struct intel_engine_cs *engine)
cmd_table_count = ARRAY_SIZE(gen7_blt_cmds);
}
- if (IS_HASWELL(engine->dev)) {
+ if (IS_HASWELL(engine)) {
engine->reg_tables = hsw_blt_reg_tables;
engine->reg_table_count = ARRAY_SIZE(hsw_blt_reg_tables);
} else {
@@ -1035,7 +1035,7 @@ bool i915_needs_cmd_parser(struct intel_engine_cs *engine)
if (!engine->needs_cmd_parser)
return false;
- if (!USES_PPGTT(engine->dev))
+ if (!USES_PPGTT(engine))
return false;
return (i915.enable_cmd_parser == 1);
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c6ead62bc411..6349f9bf7c78 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2035,7 +2035,7 @@ __guc_to_i915(const struct intel_guc *guc)
for_each_if (((id__) = (engine__)->id, \
intel_engine_initialized(engine__)))
-/* Iterator over subset of engines selected by mask */
+/* Iterate over initialised rings */
#define for_each_engine_masked(engine__, ptr__, mask__) \
for ((engine__) = &to_i915(ptr__)->engine[0]; \
(engine__) < &to_i915(ptr__)->engine[I915_NUM_ENGINES]; \
@@ -2043,6 +2043,12 @@ __guc_to_i915(const struct intel_guc *guc)
for_each_if (((mask__) & intel_engine_flag(engine__)) && \
intel_engine_initialized(engine__))
+static inline struct drm_i915_private *
+__engine_to_i915(const struct intel_engine_cs *engine)
+{
+ return __to_i915(engine->dev);
+}
+
enum hdmi_force_audio {
HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
HDMI_AUDIO_OFF, /* force turn off HDMI audio */
@@ -2517,6 +2523,10 @@ struct drm_i915_cmd_table {
__p = __guc_to_i915((struct intel_guc *)p); \
else if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_gem_request)) \
__p = __request_to_i915((struct drm_i915_gem_request *)(p)); \
+ else if (__builtin_types_compatible_p(typeof(*p), struct intel_engine_cs)) \
+ __p = __engine_to_i915((struct intel_engine_cs *)(p)); \
+ else if (__builtin_types_compatible_p(typeof(*p), struct intel_ringbuffer)) \
+ __p = __engine_to_i915(((struct intel_ringbuffer *)(p))->engine); \
else \
BUILD_BUG(); \
__p; \
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 237d5e884610..cf50e3386de4 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1228,8 +1228,7 @@ int __i915_wait_request(struct drm_i915_gem_request *req,
struct intel_rps_client *rps)
{
struct intel_engine_cs *engine = i915_gem_request_get_engine(req);
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(req);
const bool irq_test_in_progress =
ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_engine_flag(engine);
int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE;
@@ -2733,7 +2732,7 @@ __i915_gem_request_alloc(struct intel_engine_cs *engine,
struct intel_context *ctx,
struct drm_i915_gem_request **req_out)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error);
struct drm_i915_gem_request *req;
int ret;
@@ -2825,7 +2824,7 @@ i915_gem_request_alloc(struct intel_engine_cs *engine,
int err;
if (ctx == NULL)
- ctx = to_i915(engine->dev)->kernel_context;
+ ctx = to_i915(engine)->kernel_context;
err = __i915_gem_request_alloc(engine, ctx, &req);
return err ? ERR_PTR(err) : req;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index e53889498696..ad20a0250218 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -107,11 +107,11 @@ static size_t get_context_alignment(struct drm_device *dev)
static int get_context_size(struct drm_device *dev)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(dev);
int ret;
u32 reg;
- switch (INTEL_INFO(dev)->gen) {
+ switch (INTEL_INFO(dev_priv)->gen) {
case 6:
reg = I915_READ(CXT_SIZE);
ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
@@ -638,7 +638,7 @@ needs_pd_load_pre(struct intel_engine_cs *engine, struct intel_context *to)
if (engine->id != RCS)
return true;
- if (INTEL_INFO(engine->dev)->gen < 8)
+ if (INTEL_INFO(engine)->gen < 8)
return true;
return false;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 9c582c815af2..fc5b19c71bfe 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -719,7 +719,7 @@ i915_gem_execbuffer_reserve(struct intel_engine_cs *engine,
struct i915_address_space *vm;
struct list_head ordered_vmas;
struct list_head pinned_vmas;
- bool has_fenced_gpu_access = INTEL_INFO(engine->dev)->gen < 4;
+ bool has_fenced_gpu_access = INTEL_INFO(engine)->gen < 4;
int retry;
i915_gem_retire_requests_ring(engine);
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 89725c9efc25..9bff5e2cad43 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -958,7 +958,7 @@ static void i915_record_ring_state(struct drm_device *dev,
mmio = VEBOX_HWS_PGA_GEN7;
break;
}
- } else if (IS_GEN6(engine->dev)) {
+ } else if (IS_GEN6(engine)) {
mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
} else {
/* XXX: gen8 returns to sanity */
@@ -998,7 +998,7 @@ static void i915_gem_record_active_context(struct intel_engine_cs *engine,
struct drm_i915_error_state *error,
struct drm_i915_error_ring *ering)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
struct drm_i915_gem_object *obj;
/* Currently render ring is the only HW context user */
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 93da4feb3048..d4b1867b06d4 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2884,11 +2884,10 @@ static struct intel_engine_cs *
semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
u64 offset)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
struct intel_engine_cs *signaller;
- if (INTEL_INFO(dev_priv)->gen >= 8) {
- for_each_engine(signaller, dev_priv) {
+ if (INTEL_INFO(engine)->gen >= 8) {
+ for_each_engine(signaller, engine) {
if (engine == signaller)
continue;
@@ -2898,7 +2897,7 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
} else {
u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
- for_each_engine(signaller, dev_priv) {
+ for_each_engine(signaller, engine) {
if(engine == signaller)
continue;
@@ -2916,7 +2915,7 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
static struct intel_engine_cs *
semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
u32 cmd, ipehr, head;
u64 offset = 0;
int i, backwards;
@@ -2954,7 +2953,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
* ringbuffer itself.
*/
head = I915_READ_HEAD(engine) & HEAD_ADDR;
- backwards = (INTEL_INFO(engine->dev)->gen >= 8) ? 5 : 4;
+ backwards = (INTEL_INFO(engine)->gen >= 8) ? 5 : 4;
for (i = backwards; i; --i) {
/*
@@ -2976,7 +2975,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
return NULL;
*seqno = ioread32(engine->buffer->virtual_start + head + 4) + 1;
- if (INTEL_INFO(engine->dev)->gen >= 8) {
+ if (INTEL_INFO(engine)->gen >= 8) {
offset = ioread32(engine->buffer->virtual_start + head + 12);
offset <<= 32;
offset = ioread32(engine->buffer->virtual_start + head + 8);
@@ -2986,7 +2985,7 @@ semaphore_waits_for(struct intel_engine_cs *engine, u32 *seqno)
static int semaphore_passed(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
struct intel_engine_cs *signaller;
u32 seqno;
@@ -3069,8 +3068,7 @@ head_stuck(struct intel_engine_cs *engine, u64 acthd)
static enum intel_ring_hangcheck_action
ring_stuck(struct intel_engine_cs *engine, u64 acthd)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
enum intel_ring_hangcheck_action ha;
u32 tmp;
@@ -3078,7 +3076,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
if (ha != HANGCHECK_HUNG)
return ha;
- if (IS_GEN2(dev))
+ if (IS_GEN2(engine))
return HANGCHECK_HUNG;
/* Is the chip hanging on a WAIT_FOR_EVENT?
@@ -3088,19 +3086,19 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
*/
tmp = I915_READ_CTL(engine);
if (tmp & RING_WAIT) {
- i915_handle_error(dev, 0,
+ i915_handle_error(engine->dev, 0,
"Kicking stuck wait on %s",
engine->name);
I915_WRITE_CTL(engine, tmp);
return HANGCHECK_KICK;
}
- if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
+ if (INTEL_INFO(engine)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
switch (semaphore_passed(engine)) {
default:
return HANGCHECK_HUNG;
case 1:
- i915_handle_error(dev, 0,
+ i915_handle_error(engine->dev, 0,
"Kicking stuck semaphore on %s",
engine->name);
I915_WRITE_CTL(engine, tmp);
@@ -3115,7 +3113,7 @@ ring_stuck(struct intel_engine_cs *engine, u64 acthd)
static unsigned kick_waiters(struct intel_engine_cs *engine)
{
- struct drm_i915_private *i915 = to_i915(engine->dev);
+ struct drm_i915_private *i915 = to_i915(engine);
unsigned user_interrupts = READ_ONCE(engine->user_interrupts);
if (engine->hangcheck.user_interrupts == user_interrupts &&
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4cca155376be..55472ffd6be5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -11265,7 +11265,7 @@ static bool use_mmio_flip(struct intel_engine_cs *engine,
if (engine == NULL)
return true;
- if (INTEL_INFO(engine->dev)->gen < 5)
+ if (INTEL_INFO(engine)->gen < 5)
return false;
if (i915.use_mmio_flip < 0)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 1926bef2e612..ee195b22d68a 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -266,19 +266,18 @@ int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists
static void
logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
-
- if (IS_GEN8(dev) || IS_GEN9(dev))
+ if (IS_GEN8(engine) || IS_GEN9(engine))
engine->idle_lite_restore_wa = ~0;
- engine->disable_lite_restore_wa = (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1)) &&
- (engine->id == VCS || engine->id == VCS2);
+ engine->disable_lite_restore_wa =
+ (IS_SKL_REVID(engine, 0, SKL_REVID_B0) ||
+ IS_BXT_REVID(engine, 0, BXT_REVID_A1)) &&
+ (engine->id == VCS || engine->id == VCS2);
engine->ctx_desc_template = GEN8_CTX_VALID;
- engine->ctx_desc_template |= GEN8_CTX_ADDRESSING_MODE(dev) <<
- GEN8_CTX_ADDRESSING_MODE_SHIFT;
- if (IS_GEN8(dev))
+ engine->ctx_desc_template |=
+ GEN8_CTX_ADDRESSING_MODE(engine) << GEN8_CTX_ADDRESSING_MODE_SHIFT;
+ if (IS_GEN8(engine))
engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
@@ -359,8 +358,7 @@ static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
{
struct intel_engine_cs *engine = rq0->engine;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
uint64_t desc[2];
if (rq1) {
@@ -396,9 +394,8 @@ execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
static void execlists_update_context(struct drm_i915_gem_request *rq)
{
- struct intel_engine_cs *engine = rq->engine;
struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
- uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state;
+ uint32_t *reg_state = rq->ctx->engine[rq->engine->id].lrc_reg_state;
reg_state[CTX_RING_TAIL+1] = rq->tail;
@@ -407,14 +404,14 @@ static void execlists_update_context(struct drm_i915_gem_request *rq)
* PML4 is allocated during ppgtt init, so this is not needed
* in 48-bit mode.
*/
- if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
+ if (ppgtt && !USES_FULL_48BIT_PPGTT(rq))
execlists_update_context_pdps(ppgtt, reg_state);
}
static void execlists_submit_requests(struct drm_i915_gem_request *rq0,
struct drm_i915_gem_request *rq1)
{
- struct drm_i915_private *dev_priv = rq0->i915;
+ struct drm_i915_private *dev_priv = to_i915(rq0);
unsigned int fw_domains = rq0->engine->fw_domains;
execlists_update_context(rq0);
@@ -442,7 +439,7 @@ static void execlists_context_unqueue(struct intel_engine_cs *engine)
* If irqs are not active generate a warning as batches that finish
* without the irqs may get lost and a GPU Hang may occur.
*/
- WARN_ON(!intel_irqs_enabled(engine->dev->dev_private));
+ WARN_ON(!intel_irqs_enabled(to_i915(engine)));
/* Try to read in pairs */
list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
@@ -517,7 +514,7 @@ static u32
get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
u32 *context_id)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
u32 status;
read_pointer %= GEN8_CSB_ENTRIES;
@@ -543,7 +540,7 @@ get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
static void intel_lrc_irq_handler(unsigned long data)
{
struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
u32 status_pointer;
unsigned int read_pointer, write_pointer;
u32 csb[GEN8_CSB_ENTRIES][2];
@@ -1040,7 +1037,7 @@ void intel_execlists_retire_requests(struct intel_engine_cs *engine)
void intel_logical_ring_stop(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
int ret;
if (!intel_engine_initialized(engine))
@@ -1079,8 +1076,7 @@ int logical_ring_flush_all_caches(struct drm_i915_gem_request *req)
static int intel_lr_context_do_pin(struct intel_context *ctx,
struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = ctx->i915;
struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
struct intel_ringbuffer *ringbuf = ctx->engine[engine->id].ringbuf;
void *vaddr;
@@ -1240,7 +1236,7 @@ static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
* this batch updates GEN8_L3SQCREG4 with default value we need to
* set this bit here to retain the WA during flush.
*/
- if (IS_SKL_REVID(engine->dev, 0, SKL_REVID_E0))
+ if (IS_SKL_REVID(engine, 0, SKL_REVID_E0))
l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;
wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
@@ -1329,7 +1325,7 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
- if (IS_BROADWELL(engine->dev)) {
+ if (IS_BROADWELL(engine)) {
int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
if (rc < 0)
return rc;
@@ -1401,12 +1397,11 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
uint32_t *offset)
{
int ret;
- struct drm_device *dev = engine->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
/* WaDisableCtxRestoreArbitration:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_SKL_REVID(engine, 0, SKL_REVID_D0) ||
+ IS_BXT_REVID(engine, 0, BXT_REVID_A1))
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
@@ -1427,12 +1422,11 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
uint32_t *const batch,
uint32_t *offset)
{
- struct drm_device *dev = engine->dev;
uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_SKL_REVID(engine, 0, SKL_REVID_B0) ||
+ IS_BXT_REVID(engine, 0, BXT_REVID_A1)) {
wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
wa_ctx_emit(batch, index,
@@ -1441,7 +1435,7 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
}
/* WaClearTdlStateAckDirtyBits:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
+ if (IS_BXT_REVID(engine, 0, BXT_REVID_B0)) {
wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));
wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
@@ -1460,8 +1454,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
}
/* WaDisableCtxRestoreArbitration:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_SKL_REVID(engine, 0, SKL_REVID_D0) ||
+ IS_BXT_REVID(engine, 0, BXT_REVID_A1))
wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
@@ -1511,9 +1505,9 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
WARN_ON(engine->id != RCS);
/* update this when WA for higher Gen are added */
- if (INTEL_INFO(engine->dev)->gen > 9) {
+ if (INTEL_INFO(engine)->gen > 9) {
DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
- INTEL_INFO(engine->dev)->gen);
+ INTEL_INFO(engine)->gen);
return 0;
}
@@ -1533,7 +1527,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
batch = kmap_atomic(page);
offset = 0;
- if (INTEL_INFO(engine->dev)->gen == 8) {
+ if (INTEL_INFO(engine)->gen == 8) {
ret = gen8_init_indirectctx_bb(engine,
&wa_ctx->indirect_ctx,
batch,
@@ -1547,7 +1541,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
&offset);
if (ret)
goto out;
- } else if (INTEL_INFO(engine->dev)->gen == 9) {
+ } else if (INTEL_INFO(engine)->gen == 9) {
ret = gen9_init_indirectctx_bb(engine,
&wa_ctx->indirect_ctx,
batch,
@@ -1573,7 +1567,7 @@ out:
static void lrc_init_hws(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
I915_WRITE(RING_HWS_PGA(engine->mmio_base),
(u32)engine->status_page.gfx_addr);
@@ -1582,8 +1576,7 @@ static void lrc_init_hws(struct intel_engine_cs *engine)
static int gen8_init_common_ring(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned int next_context_status_buffer_hw;
lrc_init_hws(engine);
@@ -1630,8 +1623,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
static int gen8_init_render_ring(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
int ret;
ret = gen8_init_common_ring(engine);
@@ -1736,8 +1728,7 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1756,8 +1747,7 @@ static bool gen8_logical_ring_get_irq(struct intel_engine_cs *engine)
static void gen8_logical_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1774,8 +1764,7 @@ static int gen8_emit_flush(struct drm_i915_gem_request *request,
{
struct intel_ringbuffer *ringbuf = request->ringbuf;
struct intel_engine_cs *engine = ringbuf->engine;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(request);
uint32_t cmd;
int ret;
@@ -1843,7 +1832,7 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
* On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
* pipe control.
*/
- if (IS_GEN9(engine->dev))
+ if (IS_GEN9(request))
vf_flush_wa = true;
}
@@ -2028,8 +2017,6 @@ static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
*/
void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv;
-
if (!intel_engine_initialized(engine))
return;
@@ -2040,9 +2027,8 @@ void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
tasklet_kill(&engine->irq_tasklet);
- dev_priv = engine->dev->dev_private;
-
if (engine->buffer) {
+ struct drm_i915_private *dev_priv = to_i915(engine);
intel_logical_ring_stop(engine);
WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
}
@@ -2078,7 +2064,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
engine->emit_bb_start = gen8_emit_bb_start;
engine->get_seqno = gen8_get_seqno;
engine->set_seqno = gen8_set_seqno;
- if (IS_BXT_REVID(engine->dev, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(engine, 0, BXT_REVID_A1)) {
engine->irq_seqno_barrier = bxt_a_seqno_barrier;
engine->set_seqno = bxt_a_set_seqno;
}
@@ -2170,7 +2156,7 @@ logical_ring_setup(struct drm_device *dev, int id,
static int
logical_ring_init(struct intel_engine_cs *engine)
{
- struct intel_context *dctx = to_i915(engine->dev)->kernel_context;
+ struct intel_context *dctx = to_i915(engine)->kernel_context;
int ret;
ret = i915_cmd_parser_init_ring(engine);
@@ -2360,7 +2346,7 @@ cleanup_render_ring:
}
static u32
-make_rpcs(struct drm_device *dev)
+make_rpcs(struct intel_engine_cs *engine)
{
u32 rpcs = 0;
@@ -2368,7 +2354,7 @@ make_rpcs(struct drm_device *dev)
* No explicit RPCS request is needed to ensure full
* slice/subslice/EU enablement prior to Gen9.
*/
- if (INTEL_INFO(dev)->gen < 9)
+ if (INTEL_INFO(engine)->gen < 9)
return 0;
/*
@@ -2377,24 +2363,24 @@ make_rpcs(struct drm_device *dev)
* must make an explicit request through RPCS for full
* enablement.
*/
- if (INTEL_INFO(dev)->has_slice_pg) {
+ if (INTEL_INFO(engine)->has_slice_pg) {
rpcs |= GEN8_RPCS_S_CNT_ENABLE;
- rpcs |= INTEL_INFO(dev)->slice_total <<
+ rpcs |= INTEL_INFO(engine)->slice_total <<
GEN8_RPCS_S_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (INTEL_INFO(dev)->has_subslice_pg) {
+ if (INTEL_INFO(engine)->has_subslice_pg) {
rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
- rpcs |= INTEL_INFO(dev)->subslice_per_slice <<
+ rpcs |= INTEL_INFO(engine)->subslice_per_slice <<
GEN8_RPCS_SS_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (INTEL_INFO(dev)->has_eu_pg) {
- rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
+ if (INTEL_INFO(engine)->has_eu_pg) {
+ rpcs |= INTEL_INFO(engine)->eu_per_subslice <<
GEN8_RPCS_EU_MIN_SHIFT;
- rpcs |= INTEL_INFO(dev)->eu_per_subslice <<
+ rpcs |= INTEL_INFO(engine)->eu_per_subslice <<
GEN8_RPCS_EU_MAX_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
@@ -2406,9 +2392,9 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
{
u32 indirect_ctx_offset;
- switch (INTEL_INFO(engine->dev)->gen) {
+ switch (INTEL_INFO(engine)->gen) {
default:
- MISSING_CASE(INTEL_INFO(engine->dev)->gen);
+ MISSING_CASE(INTEL_INFO(engine)->gen);
/* fall through */
case 9:
indirect_ctx_offset =
@@ -2429,8 +2415,7 @@ populate_lr_context(struct intel_context *ctx,
struct intel_engine_cs *engine,
struct intel_ringbuffer *ringbuf)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = ctx->i915;
struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
void *vaddr;
u32 *reg_state;
@@ -2468,7 +2453,7 @@ populate_lr_context(struct intel_context *ctx,
RING_CONTEXT_CONTROL(engine),
_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
- (HAS_RESOURCE_STREAMER(dev) ?
+ (HAS_RESOURCE_STREAMER(engine) ?
CTX_CTRL_RS_CTX_ENABLE : 0)));
ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
0);
@@ -2539,7 +2524,7 @@ populate_lr_context(struct intel_context *ctx,
ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
0);
- if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
+ if (USES_FULL_48BIT_PPGTT(engine)) {
/* 64b PPGTT (48bit canonical)
* PDP0_DESCRIPTOR contains the base address to PML4 and
* other PDP Descriptors are ignored.
@@ -2557,7 +2542,7 @@ populate_lr_context(struct intel_context *ctx,
if (engine->id == RCS) {
reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
- make_rpcs(dev));
+ make_rpcs(engine));
}
i915_gem_object_unpin_map(ctx_obj);
@@ -2614,11 +2599,11 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
{
int ret = 0;
- WARN_ON(INTEL_INFO(engine->dev)->gen < 8);
+ WARN_ON(INTEL_INFO(engine)->gen < 8);
switch (engine->id) {
case RCS:
- if (INTEL_INFO(engine->dev)->gen >= 9)
+ if (INTEL_INFO(engine)->gen >= 9)
ret = GEN9_LR_CONTEXT_RENDER_SIZE;
else
ret = GEN8_LR_CONTEXT_RENDER_SIZE;
@@ -2651,7 +2636,6 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
int intel_lr_context_deferred_alloc(struct intel_context *ctx,
struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
struct drm_i915_gem_object *ctx_obj;
uint32_t context_size;
struct intel_ringbuffer *ringbuf;
@@ -2665,7 +2649,7 @@ int intel_lr_context_deferred_alloc(struct intel_context *ctx,
/* One extra page as the sharing data between driver and GuC */
context_size += PAGE_SIZE * LRC_PPHWSP_PN;
- ctx_obj = i915_gem_alloc_object(dev, context_size);
+ ctx_obj = i915_gem_alloc_object(engine->dev, context_size);
if (!ctx_obj) {
DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
return -ENOMEM;
diff --git a/drivers/gpu/drm/i915/intel_mocs.c b/drivers/gpu/drm/i915/intel_mocs.c
index b7b5fefa0cec..9958a745e0cd 100644
--- a/drivers/gpu/drm/i915/intel_mocs.c
+++ b/drivers/gpu/drm/i915/intel_mocs.c
@@ -189,7 +189,7 @@ static i915_reg_t mocs_register(enum intel_engine_id ring, int index)
*/
int intel_mocs_init_engine(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = to_i915(engine);
struct drm_i915_mocs_table table;
unsigned int index;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 0c8c2d40987f..e43507244527 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -61,7 +61,7 @@ int intel_ring_space(struct intel_ringbuffer *ringbuf)
bool intel_engine_stopped(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
return dev_priv->gpu_error.stop_rings & intel_engine_flag(engine);
}
@@ -431,19 +431,19 @@ gen8_render_ring_flush(struct drm_i915_gem_request *req,
static void ring_write_tail(struct intel_engine_cs *engine,
u32 value)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
I915_WRITE_TAIL(engine, value);
}
u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
u64 acthd;
- if (INTEL_INFO(engine->dev)->gen >= 8)
+ if (INTEL_INFO(engine)->gen >= 8)
acthd = I915_READ64_2x32(RING_ACTHD(engine->mmio_base),
RING_ACTHD_UDW(engine->mmio_base));
- else if (INTEL_INFO(engine->dev)->gen >= 4)
+ else if (INTEL_INFO(engine)->gen >= 4)
acthd = I915_READ(RING_ACTHD(engine->mmio_base));
else
acthd = I915_READ(ACTHD);
@@ -453,25 +453,24 @@ u64 intel_ring_get_active_head(struct intel_engine_cs *engine)
static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
u32 addr;
addr = dev_priv->status_page_dmah->busaddr;
- if (INTEL_INFO(engine->dev)->gen >= 4)
+ if (INTEL_INFO(engine)->gen >= 4)
addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
I915_WRITE(HWS_PGA, addr);
}
static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
i915_reg_t mmio;
/* The ring status page addresses are no longer next to the rest of
* the ring registers as of gen7.
*/
- if (IS_GEN7(dev)) {
+ if (IS_GEN7(engine)) {
switch (engine->id) {
case RCS:
mmio = RENDER_HWS_PGA_GEN7;
@@ -491,7 +490,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
mmio = VEBOX_HWS_PGA_GEN7;
break;
}
- } else if (IS_GEN6(engine->dev)) {
+ } else if (IS_GEN6(engine)) {
mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
} else {
/* XXX: gen8 returns to sanity */
@@ -508,7 +507,7 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
* arises: do we still need this and if so how should we go about
* invalidating the TLB?
*/
- if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
+ if (INTEL_INFO(engine)->gen >= 6 && INTEL_INFO(engine)->gen < 8) {
i915_reg_t reg = RING_INSTPM(engine->mmio_base);
/* ring should be idle before issuing a sync flush*/
@@ -526,9 +525,9 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
static bool stop_ring(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = to_i915(engine);
- if (!IS_GEN2(engine->dev)) {
+ if (!IS_GEN2(engine)) {
I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
DRM_ERROR("%s : timed out trying to stop ring\n",
@@ -546,7 +545,7 @@ static bool stop_ring(struct intel_engine_cs *engine)
I915_WRITE_HEAD(engine, 0);
engine->write_tail(engine, 0);
- if (!IS_GEN2(engine->dev)) {
+ if (!IS_GEN2(engine)) {
(void)I915_READ_CTL(engine);
I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
}
@@ -561,8 +560,7 @@ void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
static int init_ring_common(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
struct intel_ringbuffer *ringbuf = engine->buffer;
struct drm_i915_gem_object *obj = ringbuf->obj;
int ret = 0;
@@ -592,7 +590,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
}
}
- if (I915_NEED_GFX_HWS(dev))
+ if (I915_NEED_GFX_HWS(dev_priv))
intel_ring_setup_status_page(engine);
else
ring_setup_phys_status_page(engine);
@@ -649,12 +647,10 @@ out:
void
intel_fini_pipe_control(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
-
if (engine->scratch.obj == NULL)
return;
- if (INTEL_INFO(dev)->gen >= 5) {
+ if (INTEL_INFO(engine)->gen >= 5) {
kunmap(sg_page(engine->scratch.obj->pages->sgl));
i915_gem_object_ggtt_unpin(engine->scratch.obj);
}
@@ -799,7 +795,7 @@ static int wa_add(struct drm_i915_private *dev_priv,
static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
i915_reg_t reg)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
struct i915_workarounds *wa = &dev_priv->workarounds;
const uint32_t index = wa->hw_whitelist_count[engine->id];
@@ -815,8 +811,7 @@ static int wa_ring_whitelist_reg(struct intel_engine_cs *engine,
static int gen8_init_workarounds(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
WA_SET_BIT_MASKED(INSTPM, INSTPM_FORCE_ORDERING);
@@ -867,9 +862,8 @@ static int gen8_init_workarounds(struct intel_engine_cs *engine)
static int bdw_init_workarounds(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = to_i915(engine);
int ret;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen8_init_workarounds(engine);
if (ret)
@@ -889,16 +883,15 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine)
/* WaForceContextSaveRestoreNonCoherent:bdw */
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
/* WaDisableFenceDestinationToSLM:bdw (pre-prod) */
- (IS_BDW_GT3(dev) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
+ (IS_BDW_GT3(engine) ? HDC_FENCE_DEST_SLM_DISABLE : 0));
return 0;
}
static int chv_init_workarounds(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = to_i915(engine);
int ret;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen8_init_workarounds(engine);
if (ret)
@@ -915,8 +908,7 @@ static int chv_init_workarounds(struct intel_engine_cs *engine)
static int gen9_init_workarounds(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
uint32_t tmp;
int ret;
@@ -939,14 +931,14 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
/* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_SKL_REVID(engine, 0, SKL_REVID_B0) ||
+ IS_BXT_REVID(engine, 0, BXT_REVID_A1))
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_DG_MIRROR_FIX_ENABLE);
/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_SKL_REVID(engine, 0, SKL_REVID_B0) ||
+ IS_BXT_REVID(engine, 0, BXT_REVID_A1)) {
WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
GEN9_RHWO_OPTIMIZATION_DISABLE);
/*
@@ -957,7 +949,8 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
}
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt */
- if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER) || IS_BROXTON(dev))
+ if (IS_SKL_REVID(engine, SKL_REVID_C0, REVID_FOREVER) ||
+ IS_BROXTON(engine))
WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
GEN9_ENABLE_YV12_BUGFIX);
@@ -971,20 +964,20 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
GEN9_CCS_TLB_PREFETCH_ENABLE);
/* WaDisableMaskBasedCammingInRCC:skl,bxt */
- if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_C0) ||
- IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_SKL_REVID(engine, SKL_REVID_C0, SKL_REVID_C0) ||
+ IS_BXT_REVID(engine, 0, BXT_REVID_A1))
WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
PIXEL_MASK_CAMMING_DISABLE);
/* WaForceContextSaveRestoreNonCoherent:skl,bxt */
tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
- if (IS_SKL_REVID(dev, SKL_REVID_F0, REVID_FOREVER) ||
- IS_BXT_REVID(dev, BXT_REVID_B0, REVID_FOREVER))
+ if (IS_SKL_REVID(engine, SKL_REVID_F0, REVID_FOREVER) ||
+ IS_BXT_REVID(engine, BXT_REVID_B0, REVID_FOREVER))
tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt */
- if (IS_SKYLAKE(dev) || IS_BXT_REVID(dev, 0, BXT_REVID_B0))
+ if (IS_SKYLAKE(engine) || IS_BXT_REVID(engine, 0, BXT_REVID_B0))
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
@@ -1010,8 +1003,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
u8 vals[3] = { 0, 0, 0 };
unsigned int i;
@@ -1052,9 +1044,8 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
static int skl_init_workarounds(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = to_i915(engine);
int ret;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen9_init_workarounds(engine);
if (ret)
@@ -1065,12 +1056,12 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
* until D0 which is the default case so this is equivalent to
* !WaDisablePerCtxtPreemptionGranularityControl:skl
*/
- if (IS_SKL_REVID(dev, SKL_REVID_E0, REVID_FOREVER)) {
+ if (IS_SKL_REVID(engine, SKL_REVID_E0, REVID_FOREVER)) {
I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
_MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
}
- if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) {
+ if (IS_SKL_REVID(engine, 0, SKL_REVID_D0)) {
/* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
I915_WRITE(FF_SLICE_CS_CHICKEN2,
_MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
@@ -1079,24 +1070,24 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
/* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
* involving this register should also be added to WA batch as required.
*/
- if (IS_SKL_REVID(dev, 0, SKL_REVID_E0))
+ if (IS_SKL_REVID(engine, 0, SKL_REVID_E0))
/* WaDisableLSQCROPERFforOCL:skl */
I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
GEN8_LQSC_RO_PERF_DIS);
/* WaEnableGapsTsvCreditFix:skl */
- if (IS_SKL_REVID(dev, SKL_REVID_C0, REVID_FOREVER)) {
+ if (IS_SKL_REVID(engine, SKL_REVID_C0, REVID_FOREVER)) {
I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
GEN9_GAPS_TSV_CREDIT_DISABLE));
}
/* WaDisablePowerCompilerClockGating:skl */
- if (IS_SKL_REVID(dev, SKL_REVID_B0, SKL_REVID_B0))
+ if (IS_SKL_REVID(engine, SKL_REVID_B0, SKL_REVID_B0))
WA_SET_BIT_MASKED(HIZ_CHICKEN,
BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
/* This is tied to WaForceContextSaveRestoreNonCoherent */
- if (IS_SKL_REVID(dev, 0, REVID_FOREVER)) {
+ if (IS_SKL_REVID(engine, 0, REVID_FOREVER)) {
/*
*Use Force Non-Coherent whenever executing a 3D context. This
* is a workaround for a possible hang in the unlikely event
@@ -1112,13 +1103,13 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
}
/* WaBarrierPerformanceFixDisable:skl */
- if (IS_SKL_REVID(dev, SKL_REVID_C0, SKL_REVID_D0))
+ if (IS_SKL_REVID(engine, SKL_REVID_C0, SKL_REVID_D0))
WA_SET_BIT_MASKED(HDC_CHICKEN0,
HDC_FENCE_DEST_SLM_DISABLE |
HDC_BARRIER_PERFORMANCE_DISABLE);
/* WaDisableSbeCacheDispatchPortSharing:skl */
- if (IS_SKL_REVID(dev, 0, SKL_REVID_F0))
+ if (IS_SKL_REVID(engine, 0, SKL_REVID_F0))
WA_SET_BIT_MASKED(
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
@@ -1133,9 +1124,8 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
static int bxt_init_workarounds(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = to_i915(engine);
int ret;
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
ret = gen9_init_workarounds(engine);
if (ret)
@@ -1143,11 +1133,11 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
/* WaStoreMultiplePTEenable:bxt */
/* This is a requirement according to Hardware specification */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
+ if (IS_BXT_REVID(engine, 0, BXT_REVID_A1))
I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
/* WaSetClckGatingDisableMedia:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(engine, 0, BXT_REVID_A1)) {
I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
}
@@ -1157,7 +1147,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
STALL_DOP_GATING_DISABLE);
/* WaDisableSbeCacheDispatchPortSharing:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_B0)) {
+ if (IS_BXT_REVID(engine, 0, BXT_REVID_B0)) {
WA_SET_BIT_MASKED(
GEN7_HALF_SLICE_CHICKEN1,
GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
@@ -1167,7 +1157,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
/* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
/* WaDisableObjectLevelPreemtionForInstanceId:bxt */
/* WaDisableLSQCROPERFforOCL:bxt */
- if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
+ if (IS_BXT_REVID(engine, 0, BXT_REVID_A1)) {
ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
if (ret)
return ret;
@@ -1182,24 +1172,23 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
int init_workarounds_ring(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
WARN_ON(engine->id != RCS);
dev_priv->workarounds.count = 0;
dev_priv->workarounds.hw_whitelist_count[RCS] = 0;
- if (IS_BROADWELL(dev))
+ if (IS_BROADWELL(engine))
return bdw_init_workarounds(engine);
- if (IS_CHERRYVIEW(dev))
+ if (IS_CHERRYVIEW(engine))
return chv_init_workarounds(engine);
- if (IS_SKYLAKE(dev))
+ if (IS_SKYLAKE(engine))
return skl_init_workarounds(engine);
- if (IS_BROXTON(dev))
+ if (IS_BROXTON(engine))
return bxt_init_workarounds(engine);
return 0;
@@ -1207,14 +1196,13 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
static int init_render_ring(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
int ret = init_ring_common(engine);
if (ret)
return ret;
/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
- if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7)
+ if (INTEL_INFO(engine)->gen >= 4 && INTEL_INFO(engine)->gen < 7)
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
/* We need to disable the AsyncFlip performance optimisations in order
@@ -1223,22 +1211,22 @@ static int init_render_ring(struct intel_engine_cs *engine)
*
* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
*/
- if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
+ if (INTEL_INFO(engine)->gen >= 6 && INTEL_INFO(engine)->gen < 8)
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
/* Required for the hardware to program scanline values for waiting */
/* WaEnableFlushTlbInvalidationMode:snb */
- if (INTEL_INFO(dev)->gen == 6)
+ if (INTEL_INFO(engine)->gen == 6)
I915_WRITE(GFX_MODE,
_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
- if (IS_GEN7(dev))
+ if (IS_GEN7(engine))
I915_WRITE(GFX_MODE_GEN7,
_MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
_MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
- if (IS_GEN6(dev)) {
+ if (IS_GEN6(engine)) {
/* From the Sandybridge PRM, volume 1 part 3, page 24:
* "If this bit is set, STCunit will have LRA as replacement
* policy. [...] This bit must be reset. LRA replacement
@@ -1248,19 +1236,18 @@ static int init_render_ring(struct intel_engine_cs *engine)
_MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
}
- if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8)
+ if (INTEL_INFO(engine)->gen >= 6 && INTEL_INFO(engine)->gen < 8)
I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
- if (HAS_L3_DPF(dev))
- I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
+ if (HAS_L3_DPF(engine))
+ I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(engine));
return init_workarounds_ring(engine);
}
static void render_ring_cleanup(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
if (dev_priv->semaphore_obj) {
i915_gem_object_ggtt_unpin(dev_priv->semaphore_obj);
@@ -1423,8 +1410,7 @@ gen6_add_request(struct drm_i915_gem_request *req)
static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
u32 seqno)
{
- struct drm_i915_private *dev_priv = dev->dev_private;
- return dev_priv->last_seqno < seqno;
+ return to_i915(dev)->last_seqno < seqno;
}
/**
@@ -1579,7 +1565,7 @@ gen6_seqno_barrier(struct intel_engine_cs *engine)
* batch i.e. much more frequent than a delay when waiting for the
* interrupt (with the same net latency).
*/
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
}
@@ -1610,8 +1596,7 @@ pc_render_set_seqno(struct intel_engine_cs *engine, u32 seqno)
static bool
gen5_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1628,8 +1613,7 @@ gen5_ring_get_irq(struct intel_engine_cs *engine)
static void
gen5_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1641,8 +1625,7 @@ gen5_ring_put_irq(struct intel_engine_cs *engine)
static bool
i9xx_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
if (!intel_irqs_enabled(dev_priv))
@@ -1662,8 +1645,7 @@ i9xx_ring_get_irq(struct intel_engine_cs *engine)
static void
i9xx_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1678,8 +1660,7 @@ i9xx_ring_put_irq(struct intel_engine_cs *engine)
static bool
i8xx_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
if (!intel_irqs_enabled(dev_priv))
@@ -1699,8 +1680,7 @@ i8xx_ring_get_irq(struct intel_engine_cs *engine)
static void
i8xx_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1753,8 +1733,7 @@ i9xx_add_request(struct drm_i915_gem_request *req)
static bool
gen6_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1762,10 +1741,10 @@ gen6_ring_get_irq(struct intel_engine_cs *engine)
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (engine->irq_refcount++ == 0) {
- if (HAS_L3_DPF(dev) && engine->id == RCS)
+ if (HAS_L3_DPF(engine) && engine->id == RCS)
I915_WRITE_IMR(engine,
~(engine->irq_enable_mask |
- GT_PARITY_ERROR(dev)));
+ GT_PARITY_ERROR(engine)));
else
I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
@@ -1778,14 +1757,13 @@ gen6_ring_get_irq(struct intel_engine_cs *engine)
static void
gen6_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (--engine->irq_refcount == 0) {
- if (HAS_L3_DPF(dev) && engine->id == RCS)
- I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(dev));
+ if (HAS_L3_DPF(engine) && engine->id == RCS)
+ I915_WRITE_IMR(engine, ~GT_PARITY_ERROR(engine));
else
I915_WRITE_IMR(engine, ~0);
gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
@@ -1796,8 +1774,7 @@ gen6_ring_put_irq(struct intel_engine_cs *engine)
static bool
hsw_vebox_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1816,8 +1793,7 @@ hsw_vebox_get_irq(struct intel_engine_cs *engine)
static void
hsw_vebox_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
@@ -1831,8 +1807,7 @@ hsw_vebox_put_irq(struct intel_engine_cs *engine)
static bool
gen8_ring_get_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
if (WARN_ON(!intel_irqs_enabled(dev_priv)))
@@ -1840,7 +1815,7 @@ gen8_ring_get_irq(struct intel_engine_cs *engine)
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (engine->irq_refcount++ == 0) {
- if (HAS_L3_DPF(dev) && engine->id == RCS) {
+ if (HAS_L3_DPF(engine) && engine->id == RCS) {
I915_WRITE_IMR(engine,
~(engine->irq_enable_mask |
GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
@@ -1857,13 +1832,12 @@ gen8_ring_get_irq(struct intel_engine_cs *engine)
static void
gen8_ring_put_irq(struct intel_engine_cs *engine)
{
- struct drm_device *dev = engine->dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
unsigned long flags;
spin_lock_irqsave(&dev_priv->irq_lock, flags);
if (--engine->irq_refcount == 0) {
- if (HAS_L3_DPF(dev) && engine->id == RCS) {
+ if (HAS_L3_DPF(engine) && engine->id == RCS) {
I915_WRITE_IMR(engine,
~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
} else {
@@ -1985,7 +1959,7 @@ i915_dispatch_execbuffer(struct drm_i915_gem_request *req,
static void cleanup_phys_status_page(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = to_i915(engine);
if (!dev_priv->status_page_dmah)
return;
@@ -2027,7 +2001,7 @@ static int init_status_page(struct intel_engine_cs *engine)
goto err_unref;
flags = 0;
- if (!HAS_LLC(engine->dev))
+ if (!HAS_LLC(engine))
/* On g33, we cannot place HWS above 256MiB, so
* restrict its pinning to the low mappable arena.
* Though this restriction is not documented for
@@ -2061,7 +2035,7 @@ err_unref:
static int init_phys_status_page(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
if (!dev_priv->status_page_dmah) {
dev_priv->status_page_dmah =
@@ -2188,7 +2162,7 @@ intel_engine_create_ringbuffer(struct intel_engine_cs *engine, int size)
* of the buffer.
*/
ring->effective_size = size;
- if (IS_I830(engine->dev) || IS_845G(engine->dev))
+ if (IS_I830(engine) || IS_845G(engine))
ring->effective_size -= 2 * CACHELINE_BYTES;
ring->last_retired_head = -1;
@@ -2277,11 +2251,11 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
if (!intel_engine_initialized(engine))
return;
- dev_priv = to_i915(engine->dev);
+ dev_priv = to_i915(engine);
if (engine->buffer) {
intel_stop_engine(engine);
- WARN_ON(!IS_GEN2(engine->dev) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
+ WARN_ON(!IS_GEN2(engine) && (I915_READ_MODE(engine) & MODE_IDLE) == 0);
intel_unpin_ringbuffer_obj(engine->buffer);
intel_ringbuffer_free(engine->buffer);
@@ -2291,7 +2265,7 @@ void intel_cleanup_engine(struct intel_engine_cs *engine)
if (engine->cleanup)
engine->cleanup(engine);
- if (I915_NEED_GFX_HWS(engine->dev)) {
+ if (I915_NEED_GFX_HWS(engine)) {
cleanup_status_page(engine);
} else {
WARN_ON(engine->id != RCS);
@@ -2525,7 +2499,7 @@ int intel_ring_cacheline_align(struct drm_i915_gem_request *req)
void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
{
- struct drm_i915_private *dev_priv = to_i915(engine->dev);
+ struct drm_i915_private *dev_priv = to_i915(engine);
/* Our semaphore implementation is strictly monotonic (i.e. we proceed
* so long as the semaphore value in the register/page is greater
@@ -2561,7 +2535,7 @@ void intel_ring_init_seqno(struct intel_engine_cs *engine, u32 seqno)
static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
u32 value)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
/* Every tail move must follow the sequence below */
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 4f1dfe616856..655dd5e0536c 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1663,8 +1663,8 @@ static int wait_for_register_fw(struct drm_i915_private *dev_priv,
static int gen8_request_engine_reset(struct intel_engine_cs *engine)
{
+ struct drm_i915_private *dev_priv = to_i915(engine);
int ret;
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET));
@@ -1682,7 +1682,7 @@ static int gen8_request_engine_reset(struct intel_engine_cs *engine)
static void gen8_unrequest_engine_reset(struct intel_engine_cs *engine)
{
- struct drm_i915_private *dev_priv = engine->dev->dev_private;
+ struct drm_i915_private *dev_priv = to_i915(engine);
I915_WRITE_FW(RING_RESET_CTL(engine->mmio_base),
_MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
--
2.8.0.rc3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: Polymorphic to_i915()
2016-04-15 17:45 Polymorphic to_i915() Chris Wilson
` (5 preceding siblings ...)
2016-04-15 17:46 ` [PATCH 6/6] drm/i915: Teach to_i915() how to extract drm_i915_private from engines Chris Wilson
@ 2016-04-18 9:18 ` Jani Nikula
2016-04-18 11:11 ` Dave Gordon
2016-04-20 12:57 ` Daniel Vetter
6 siblings, 2 replies; 16+ messages in thread
From: Jani Nikula @ 2016-04-18 9:18 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On Fri, 15 Apr 2016, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> Final canvas for opinions for using a magic macro to reduce typing in
> the common operation of getting our drm_i915_private from the object.
>
> 21 files changed, 333 insertions(+), 392 deletions(-)
>
> Not to mention the ease it makes for later patches to reduce the pointer
> dance.
I've expressed my reservations about this the last time.
My compromise proposal is this: let's add the to_i915()
"superconvenience macro", but let's not embed that into other
macros. Instead, move away from convenience macros in them, explicitly
requiring dev_priv.
This would make just one macro special, and would keep the rest less
surprising and "C-like". We already need dev_priv all over the place, so
I don't think having a local variable or an explicit to_i915() is a big
burden.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: Polymorphic to_i915()
2016-04-18 9:18 ` Polymorphic to_i915() Jani Nikula
@ 2016-04-18 11:11 ` Dave Gordon
2016-04-18 11:49 ` Jani Nikula
2016-04-20 12:57 ` Daniel Vetter
1 sibling, 1 reply; 16+ messages in thread
From: Dave Gordon @ 2016-04-18 11:11 UTC (permalink / raw)
To: Jani Nikula, Chris Wilson, intel-gfx
On 18/04/16 10:18, Jani Nikula wrote:
> On Fri, 15 Apr 2016, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> Final canvas for opinions for using a magic macro to reduce typing in
>> the common operation of getting our drm_i915_private from the object.
>>
>> 21 files changed, 333 insertions(+), 392 deletions(-)
>>
>> Not to mention the ease it makes for later patches to reduce the pointer
>> dance.
>
> I've expressed my reservations about this the last time.
>
> My compromise proposal is this: let's add the to_i915()
> "superconvenience macro", but let's not embed that into other
> macros. Instead, move away from convenience macros in them, explicitly
> requiring dev_priv.
>
> This would make just one macro special, and would keep the rest less
> surprising and "C-like". We already need dev_priv all over the place, so
> I don't think having a local variable or an explicit to_i915() is a big
> burden.
>
> BR,
> Jani.
I'm quite happy with the first patch of this series (various renames),
but not so keen on the second (pass anything to for_each_engine(). The
reason for this is that the dev_priv parameter to this macro is used
repeatedly in the resulting loop, so the caller should be encouraged to
supply as an actual parameter the expression that needs the least
evaluation on each iteration i.e. a local variable. Allowing such things
as to_i915(dev) or, worse, to_i915(engine) may encourage uses which end
up generating four levels of memory indirection :(
e.g. engine->dev->dev_priv->engine(!)
So I think it should be regarded as better (more efficient) style to write
struct drm_i915_private *i915 = to_i915(...);
...
for_each_engine(engine, i915) {
...
}
rather than
for_each_engine(engine, to_i915(...)) {
...
}
OTOH I have no objection to
if (USES_FULL_PPGTT(to_i915(obj)) ...
(not a loop) but I'm not so keen on
if (USES_FULL_PPGTT(obj))
as this suggests that it's a property of the object, and different
objects might therefore return different values.
The GuC changes are OK, and we might as well convert "dev_priv" to
"i915" at the same time, if that's now the preferred name.
In the end, I think I agree with Jani: let's have a thoroughly
polymorphic to_i915() that works on anything, and then have everything
else require that.
Regards,
.Dave.
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: Polymorphic to_i915()
2016-04-18 11:11 ` Dave Gordon
@ 2016-04-18 11:49 ` Jani Nikula
2016-04-18 12:09 ` Chris Wilson
0 siblings, 1 reply; 16+ messages in thread
From: Jani Nikula @ 2016-04-18 11:49 UTC (permalink / raw)
To: Dave Gordon, Chris Wilson, intel-gfx
On Mon, 18 Apr 2016, Dave Gordon <david.s.gordon@intel.com> wrote:
> The GuC changes are OK, and we might as well convert "dev_priv" to
> "i915" at the same time, if that's now the preferred name.
Hmph, I see that "struct drm_i915_private *i915" is already being used
in a few places. This is more than a little confusing since "struct
i915_params i915" in i915_params.c is also the struct we currently use
to hold the module parameters. Rather annoyingly, there are no warnings
about the module wide i915 being shadowed.
I oppose to having both around. Please figure this out before adding a
single new "struct drm_i915_private *i915".
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: Polymorphic to_i915()
2016-04-18 11:49 ` Jani Nikula
@ 2016-04-18 12:09 ` Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2016-04-18 12:09 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, Apr 18, 2016 at 02:49:26PM +0300, Jani Nikula wrote:
> On Mon, 18 Apr 2016, Dave Gordon <david.s.gordon@intel.com> wrote:
> > The GuC changes are OK, and we might as well convert "dev_priv" to
> > "i915" at the same time, if that's now the preferred name.
>
> Hmph, I see that "struct drm_i915_private *i915" is already being used
> in a few places. This is more than a little confusing since "struct
> i915_params i915" in i915_params.c is also the struct we currently use
> to hold the module parameters. Rather annoyingly, there are no warnings
> about the module wide i915 being shadowed.
>
> I oppose to having both around. Please figure this out before adding a
> single new "struct drm_i915_private *i915".
I did change it name quite some time ago... It's trivial to do.
-Chris
--
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: Polymorphic to_i915()
2016-04-18 9:18 ` Polymorphic to_i915() Jani Nikula
2016-04-18 11:11 ` Dave Gordon
@ 2016-04-20 12:57 ` Daniel Vetter
2016-04-20 14:29 ` Dave Gordon
2016-04-20 15:26 ` Mika Kuoppala
1 sibling, 2 replies; 16+ messages in thread
From: Daniel Vetter @ 2016-04-20 12:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, Apr 18, 2016 at 12:18:23PM +0300, Jani Nikula wrote:
> On Fri, 15 Apr 2016, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > Final canvas for opinions for using a magic macro to reduce typing in
> > the common operation of getting our drm_i915_private from the object.
> >
> > 21 files changed, 333 insertions(+), 392 deletions(-)
> >
> > Not to mention the ease it makes for later patches to reduce the pointer
> > dance.
>
> I've expressed my reservations about this the last time.
>
> My compromise proposal is this: let's add the to_i915()
> "superconvenience macro", but let's not embed that into other
> macros. Instead, move away from convenience macros in them, explicitly
> requiring dev_priv.
>
> This would make just one macro special, and would keep the rest less
> surprising and "C-like". We already need dev_priv all over the place, so
> I don't think having a local variable or an explicit to_i915() is a big
> burden.
Not much more to add, but I'm not strongly opinionated here really. But I
do think that a trick of this magnitude needs much more enthusiastic
support from a bunch of people before we can merge it.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/6] drm/i915: Rename the magic polymorphic macro __I915__
2016-04-15 17:46 ` [PATCH 1/6] drm/i915: Rename the magic polymorphic macro __I915__ Chris Wilson
@ 2016-04-20 14:27 ` Dave Gordon
0 siblings, 0 replies; 16+ messages in thread
From: Dave Gordon @ 2016-04-20 14:27 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 15/04/16 18:46, Chris Wilson wrote:
> To open up the future of using a generic to_i915() convenience macro,
> rename the existing __I915__ superconvenience macro.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 78231cc5f40b..6569ebfe8cf1 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -2004,14 +2004,14 @@ struct drm_i915_private {
> */
> };
>
> -static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
> +static inline struct drm_i915_private *__to_i915(const struct drm_device *dev)
> {
> return dev->dev_private;
> }
Could we call this drm_to_i915() ? I like the pattern of XXX_to_i915()
for XXX in { dev, drm, guc, obj, req, ... }
.Dave.
> -static inline struct drm_i915_private *dev_to_i915(struct device *dev)
> +static inline struct drm_i915_private *dev_to_i915(const struct device *dev)
> {
> - return to_i915(dev_get_drvdata(dev));
> + return __to_i915(dev_get_drvdata(dev));
> }
>
> static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
> @@ -2492,20 +2492,20 @@ struct drm_i915_cmd_table {
> };
>
> /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
> -#define __I915__(p) ({ \
> +#define to_i915(p) ({ \
> struct drm_i915_private *__p; \
> if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
> __p = (struct drm_i915_private *)p; \
> else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
> - __p = to_i915((struct drm_device *)p); \
> + __p = __to_i915((struct drm_device *)p); \
> else \
> BUILD_BUG(); \
> __p; \
> })
> -#define INTEL_INFO(p) (&__I915__(p)->info)
> +#define INTEL_INFO(p) (&to_i915(p)->info)
> #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
> #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
> -#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
> +#define INTEL_REVID(p) (to_i915(p)->dev->pdev->revision)
>
> #define REVID_FOREVER 0xff
> /*
> @@ -2630,7 +2630,7 @@ struct drm_i915_cmd_table {
> #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
> #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
> #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
> -#define HAS_EDRAM(dev) (__I915__(dev)->edram_cap & EDRAM_ENABLED)
> +#define HAS_EDRAM(dev) (to_i915(dev)->edram_cap & EDRAM_ENABLED)
> #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
> HAS_EDRAM(dev))
> #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
> @@ -2714,11 +2714,11 @@ struct drm_i915_cmd_table {
> #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
> #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
>
> -#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
> +#define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
> #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
> #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
> -#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> -#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
> +#define HAS_PCH_LPT_LP(dev) (to_i915(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
> +#define HAS_PCH_LPT_H(dev) (to_i915(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
> #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
> #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
> #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: Polymorphic to_i915()
2016-04-20 12:57 ` Daniel Vetter
@ 2016-04-20 14:29 ` Dave Gordon
2016-04-20 15:26 ` Mika Kuoppala
1 sibling, 0 replies; 16+ messages in thread
From: Dave Gordon @ 2016-04-20 14:29 UTC (permalink / raw)
To: Daniel Vetter, Jani Nikula; +Cc: intel-gfx
On 20/04/16 13:57, Daniel Vetter wrote:
> On Mon, Apr 18, 2016 at 12:18:23PM +0300, Jani Nikula wrote:
>> On Fri, 15 Apr 2016, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>>> Final canvas for opinions for using a magic macro to reduce typing in
>>> the common operation of getting our drm_i915_private from the object.
>>>
>>> 21 files changed, 333 insertions(+), 392 deletions(-)
>>>
>>> Not to mention the ease it makes for later patches to reduce the pointer
>>> dance.
>>
>> I've expressed my reservations about this the last time.
>>
>> My compromise proposal is this: let's add the to_i915()
>> "superconvenience macro", but let's not embed that into other
>> macros. Instead, move away from convenience macros in them, explicitly
>> requiring dev_priv.
>>
>> This would make just one macro special, and would keep the rest less
>> surprising and "C-like". We already need dev_priv all over the place, so
>> I don't think having a local variable or an explicit to_i915() is a big
>> burden.
>
> Not much more to add, but I'm not strongly opinionated here really. But I
> do think that a trick of this magnitude needs much more enthusiastic
> support from a bunch of people before we can merge it.
> -Daniel
How about taking the just smallest of these patches (items 1/6 and 4/6)
now, dropping 2 entirely, and leaving the more intrusive 3, 5, and 6 for
later, maybe at a time when there's not too much code churn?
.Dave.
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: Polymorphic to_i915()
2016-04-20 12:57 ` Daniel Vetter
2016-04-20 14:29 ` Dave Gordon
@ 2016-04-20 15:26 ` Mika Kuoppala
1 sibling, 0 replies; 16+ messages in thread
From: Mika Kuoppala @ 2016-04-20 15:26 UTC (permalink / raw)
To: Daniel Vetter, Jani Nikula; +Cc: intel-gfx
Daniel Vetter <daniel@ffwll.ch> writes:
> [ text/plain ]
> On Mon, Apr 18, 2016 at 12:18:23PM +0300, Jani Nikula wrote:
>> On Fri, 15 Apr 2016, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> > Final canvas for opinions for using a magic macro to reduce typing in
>> > the common operation of getting our drm_i915_private from the object.
>> >
>> > 21 files changed, 333 insertions(+), 392 deletions(-)
>> >
>> > Not to mention the ease it makes for later patches to reduce the pointer
>> > dance.
>>
>> I've expressed my reservations about this the last time.
>>
>> My compromise proposal is this: let's add the to_i915()
>> "superconvenience macro", but let's not embed that into other
>> macros. Instead, move away from convenience macros in them, explicitly
>> requiring dev_priv.
>>
>> This would make just one macro special, and would keep the rest less
>> surprising and "C-like". We already need dev_priv all over the place, so
>> I don't think having a local variable or an explicit to_i915() is a big
>> burden.
>
> Not much more to add, but I'm not strongly opinionated here really. But I
> do think that a trick of this magnitude needs much more enthusiastic
> support from a bunch of people before we can merge it.
This reduces boilerplate code. And compiler watches our back?
I fail to see the traps underneath, so I am leaning on the
supporting side.
Perhaps I need to reread the reservations post that Jani mentioned.
-Mika
> -Daniel
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/6] drm/i915: Rename the magic polymorphic macro __I915__
@ 2016-03-18 21:16 Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2016-03-18 21:16 UTC (permalink / raw)
To: intel-gfx
To open up the future of using a generic to_i915() convenience macro,
rename the existing __I915__ superconvenience macro.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f330a53c19b9..8606e2c7db04 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1972,14 +1972,14 @@ struct drm_i915_private {
*/
};
-static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
+static inline struct drm_i915_private *__to_i915(const struct drm_device *dev)
{
return dev->dev_private;
}
static inline struct drm_i915_private *dev_to_i915(struct device *dev)
{
- return to_i915(dev_get_drvdata(dev));
+ return __to_i915(dev_get_drvdata(dev));
}
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
@@ -2449,19 +2449,19 @@ struct drm_i915_cmd_table {
};
/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
-#define __I915__(p) ({ \
+#define to_i915(p) ({ \
struct drm_i915_private *__p; \
if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
__p = (struct drm_i915_private *)p; \
else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
- __p = to_i915((struct drm_device *)p); \
+ __p = __to_i915((struct drm_device *)p); \
else \
BUILD_BUG(); \
__p; \
})
-#define INTEL_INFO(p) (&__I915__(p)->info)
+#define INTEL_INFO(p) (&to_i915(p)->info)
#define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
-#define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
+#define INTEL_REVID(p) (to_i915(p)->dev->pdev->revision)
#define REVID_FOREVER 0xff
/*
@@ -2587,7 +2587,7 @@ struct drm_i915_cmd_table {
#define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
#define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
#define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
- __I915__(dev)->ellc_size)
+ to_i915(dev)->ellc_size)
#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
@@ -2667,11 +2667,11 @@ struct drm_i915_cmd_table {
#define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
-#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
+#define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
-#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
-#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
+#define HAS_PCH_LPT_LP(dev) (to_i915(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
+#define HAS_PCH_LPT_H(dev) (to_i915(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
--
2.8.0.rc3
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^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2016-04-20 15:29 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-04-15 17:45 Polymorphic to_i915() Chris Wilson
2016-04-15 17:46 ` [PATCH 1/6] drm/i915: Rename the magic polymorphic macro __I915__ Chris Wilson
2016-04-20 14:27 ` Dave Gordon
2016-04-15 17:46 ` [PATCH 2/6] drm/i915: Allow passing any known pointer to for_each_engine() Chris Wilson
2016-04-15 17:46 ` [PATCH 3/6] drm/i915: Extend magic to_i915() to work with drm_i915_gem_object Chris Wilson
2016-04-15 17:46 ` [PATCH 4/6] drm/i915: Use to_i915() instead of guc_to_i915() Chris Wilson
2016-04-15 17:46 ` [PATCH 5/6] drm/i915: Teach to_i915() how to extract drm_i915_private from requests Chris Wilson
2016-04-15 17:46 ` [PATCH 6/6] drm/i915: Teach to_i915() how to extract drm_i915_private from engines Chris Wilson
2016-04-18 9:18 ` Polymorphic to_i915() Jani Nikula
2016-04-18 11:11 ` Dave Gordon
2016-04-18 11:49 ` Jani Nikula
2016-04-18 12:09 ` Chris Wilson
2016-04-20 12:57 ` Daniel Vetter
2016-04-20 14:29 ` Dave Gordon
2016-04-20 15:26 ` Mika Kuoppala
-- strict thread matches above, loose matches on Subject: below --
2016-03-18 21:16 [PATCH 1/6] drm/i915: Rename the magic polymorphic macro __I915__ Chris Wilson
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