[PATCH V10 00/28] Add new powerpc specific ELF core notes

[PATCH V10 00/28] Add new powerpc specific ELF core notes

[Anshuman Khandual]

	This patch series adds twelve new ELF core note sections which can
be used with existing ptrace request PTRACE_GETREGSET-SETREGSET for accessing
various transactional memory and other miscellaneous debug register sets on
powerpc platform.

Test Result (All tests pass on both BE and LE)
----------------------------------------------
ptrace-ebb		PASS
ptrace-gpr		PASS
ptrace-tm-gpr		PASS
ptrace-tm-spd-gpr	PASS
ptrace-tar		PASS
ptrace-tm-tar		PASS
ptrace-tm-spd-tar	PASS
ptrace-vsx		PASS
ptrace-tm-vsx		PASS
ptrace-tm-spd-vsx	PASS
ptrace-tm-spr		PASS

Previous versions:
==================
RFC: https://lkml.org/lkml/2014/4/1/292
V1:  https://lkml.org/lkml/2014/4/2/43
V2:  https://lkml.org/lkml/2014/5/5/88
V3:  https://lkml.org/lkml/2014/5/23/486
V4:  https://lkml.org/lkml/2014/11/11/6
V5:  https://lkml.org/lkml/2014/11/25/134
V6:  https://lkml.org/lkml/2014/12/2/98
V7:  https://lkml.org/lkml/2015/1/14/19
V8:  https://lkml.org/lkml/2015/5/19/700
V9:  https://lkml.org/lkml/2015/10/8/522

Changes in V10:
---------------
- Rebased against the latest mainline
- Fixed couple of build failures in the test cases related to aux vector

Changes in V9:
--------------
- Fixed static build check failure after tm_orig_msr got dropped
- Fixed asm volatile construct for used registers set
- Fixed EBB, VSX, VMX tests for LE
- Fixed TAR test which was failing because of system calls
- Added checks for PPC_FEATURE2_HTM aux feature in the tests
- Fixed copyright statements

Changes in V8:
--------------
- Split the misc register set into individual ELF core notes
- Implemented support for VSX register set (on and off TM)
- Implemented support for EBB register set
- Implemented review comments on previous versions
- Some code re-arrangements, re-writes and documentation
- Added comprehensive list of test cases into selftests

Changes in V7:
--------------
- Fixed a config directive in the MISC code
- Merged the two gitignore patches into a single one

Changes in V6:
--------------
- Added two git ignore patches for powerpc selftests
- Re-formatted all in-code function definitions in kernel-doc format

Changes in V5:
--------------
- Changed flush_tmregs_to_thread, so not to take into account self tracing
- Dropped the 3rd patch in the series which had merged two functions
- Fixed one build problem for the misc debug register patch
- Accommodated almost all the review comments from Suka on the 6th patch
- Minor changes to the self test program
- Changed commit messages for some of the patches

Changes in V4:
--------------
- Added one test program into the powerpc selftest bucket in this regard
- Split the 2nd patch in the previous series into four different patches
- Accommodated most of the review comments on the previous patch series
- Added a patch to merge functions __switch_to_tm and tm_reclaim_task

Changes in V3:
--------------
- Added two new error paths in every TM related get/set functions when regset
  support is not present on the system (ENODEV) or when the process does not
  have any transaction active (ENODATA) in the context
- Installed the active hooks for all the newly added regset core note types

Changes in V2:
--------------
- Removed all the power specific ptrace requests corresponding to new NT_PPC_*
  elf core note types. Now all the register sets can be accessed from ptrace
  through PTRACE_GETREGSET/PTRACE_SETREGSET using the individual NT_PPC* core
  note type instead
- Fixed couple of attribute values for REGSET_TM_CGPR register set
- Renamed flush_tmreg_to_thread as flush_tmregs_to_thread
- Fixed 32 bit checkpointed GPR support
- Changed commit messages accordingly


Anshuman Khandual (28):
  elf: Add powerpc specific core note sections
  powerpc, process: Add the function flush_tmregs_to_thread
  powerpc, ptrace: Enable in transaction NT_PRFPREG ptrace requests
  powerpc, ptrace: Enable in transaction NT_PPC_VMX ptrace requests
  powerpc, ptrace: Enable in transaction NT_PPC_VSX ptrace requests
  powerpc, ptrace: Adapt gpr32_get, gpr32_set functions for transaction
  powerpc, ptrace: Enable support for NT_PPC_CGPR
  powerpc, ptrace: Enable support for NT_PPC_CFPR
  powerpc, ptrace: Enable support for NT_PPC_CVMX
  powerpc, ptrace: Enable support for NT_PPC_CVSX
  powerpc, ptrace: Enable support for TM SPR state
  powerpc, ptrace: Enable NT_PPC_TM_CTAR, NT_PPC_TM_CPPR, NT_PPC_TM_CDSCR
  powerpc, ptrace: Enable support for NT_PPPC_TAR, NT_PPC_PPR, NT_PPC_DSCR
  powerpc, ptrace: Enable support for EBB registers
  selftests, powerpc: Move 'reg.h' file outside of 'ebb' sub directory
  selftests, powerpc: Add more SPR numbers, TM & VMX instructions to 'reg.h'
  selftests, powerpc: Add ptrace tests for EBB
  selftests, powerpc: Add ptrace tests for GPR/FPR registers
  selftests, powerpc: Add ptrace tests for GPR/FPR registers in TM
  selftests, powerpc: Add ptrace tests for GPR/FPR registers in suspended TM
  selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR registers
  selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR in TM
  selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR in suspended TM
  selftests, powerpc: Add ptrace tests for VSX, VMX registers
  selftests, powerpc: Add ptrace tests for VSX, VMX registers in TM
  selftests, powerpc: Add ptrace tests for VSX, VMX registers in suspended TM
  selftests, powerpc: Add ptrace tests for TM SPR registers
  selftests, powerpc: Add .gitignore file for ptrace executables

 arch/powerpc/include/asm/switch_to.h               |    8 +
 arch/powerpc/include/uapi/asm/elf.h                |    6 +
 arch/powerpc/kernel/process.c                      |   20 +
 arch/powerpc/kernel/ptrace.c                       | 1737 ++++++++++++++++++--
 include/uapi/linux/elf.h                           |   12 +
 tools/testing/selftests/powerpc/Makefile           |    3 +-
 tools/testing/selftests/powerpc/pmu/ebb/ebb.c      |    2 +-
 tools/testing/selftests/powerpc/pmu/ebb/ebb.h      |    2 +-
 .../selftests/powerpc/pmu/ebb/ebb_handler.S        |    2 +-
 tools/testing/selftests/powerpc/pmu/ebb/reg.h      |   49 -
 .../selftests/powerpc/pmu/ebb/reg_access_test.c    |    2 +-
 tools/testing/selftests/powerpc/ptrace/.gitignore  |   11 +
 tools/testing/selftests/powerpc/ptrace/Makefile    |   12 +
 .../testing/selftests/powerpc/ptrace/ptrace-ebb.c  |  150 ++
 .../testing/selftests/powerpc/ptrace/ptrace-ebb.h  |  103 ++
 .../testing/selftests/powerpc/ptrace/ptrace-gpr.c  |  191 +++
 .../testing/selftests/powerpc/ptrace/ptrace-gpr.h  |   73 +
 .../testing/selftests/powerpc/ptrace/ptrace-tar.c  |  151 ++
 .../testing/selftests/powerpc/ptrace/ptrace-tar.h  |   50 +
 .../selftests/powerpc/ptrace/ptrace-tm-gpr.c       |  288 ++++
 .../selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c   |  319 ++++
 .../selftests/powerpc/ptrace/ptrace-tm-spd-tar.c   |  184 +++
 .../selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c   |  212 +++
 .../selftests/powerpc/ptrace/ptrace-tm-spr.c       |  157 ++
 .../selftests/powerpc/ptrace/ptrace-tm-tar.c       |  170 ++
 .../selftests/powerpc/ptrace/ptrace-tm-vsx.c       |  196 +++
 .../testing/selftests/powerpc/ptrace/ptrace-vsx.c  |  138 ++
 .../testing/selftests/powerpc/ptrace/ptrace-vsx.h  |  104 ++
 tools/testing/selftests/powerpc/ptrace/ptrace.S    |  396 +++++
 tools/testing/selftests/powerpc/ptrace/ptrace.h    |  766 +++++++++
 tools/testing/selftests/powerpc/reg.h              |   70 +
 31 files changed, 5406 insertions(+), 178 deletions(-)
 delete mode 100644 tools/testing/selftests/powerpc/pmu/ebb/reg.h
 create mode 100644 tools/testing/selftests/powerpc/ptrace/.gitignore
 create mode 100644 tools/testing/selftests/powerpc/ptrace/Makefile
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-ebb.h
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tar.h
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-gpr.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spr.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-vsx.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-vsx.h
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace.S
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace.h
 create mode 100644 tools/testing/selftests/powerpc/reg.h

-- 
2.1.0

[PATCH V10 01/28] elf: Add powerpc specific core note sections

[Anshuman Khandual]

This patch adds twelve ELF core note sections for powerpc
architecture for various registers and register sets which
need to be accessed from ptrace interface and then gdb.
These additions include special purpose registers like TAR,
PPR, DSCR, TM running and checkpointed state for various
register sets, EBB related register set etc. Addition of
these new ELF core note sections extends the existing ELF
ABI on powerpc arch without affecting it in any manner.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 include/uapi/linux/elf.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index 71e1d0e..58654c2 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -379,6 +379,18 @@ typedef struct elf64_shdr {
 #define NT_PPC_VMX	0x100		/* PowerPC Altivec/VMX registers */
 #define NT_PPC_SPE	0x101		/* PowerPC SPE/EVR registers */
 #define NT_PPC_VSX	0x102		/* PowerPC VSX registers */
+#define NT_PPC_TAR	0x103		/* Target Address Register */
+#define NT_PPC_PPR	0x104		/* Program Priority Register */
+#define NT_PPC_DSCR	0x105		/* Data Stream Control Register */
+#define NT_PPC_EBB	0x106		/* Event Based Branch Registers */
+#define NT_PPC_TM_CGPR	0x107		/* TM checkpointed GPR Registers */
+#define NT_PPC_TM_CFPR	0x108		/* TM checkpointed FPR Registers */
+#define NT_PPC_TM_CVMX	0x109		/* TM checkpointed VMX Registers */
+#define NT_PPC_TM_CVSX	0x10a		/* TM checkpointed VSX Registers */
+#define NT_PPC_TM_SPR	0x10b		/* TM Special Purpose Registers */
+#define NT_PPC_TM_CTAR	0x10c		/* TM checkpointed Target Address Register */
+#define NT_PPC_TM_CPPR	0x10d		/* TM checkpointed Program Priority Register */
+#define NT_PPC_TM_CDSCR	0x10e		/* TM checkpointed Data Stream Control Register */
 #define NT_386_TLS	0x200		/* i386 TLS slots (struct user_desc) */
 #define NT_386_IOPERM	0x201		/* x86 io permission bitmap (1=deny) */
 #define NT_X86_XSTATE	0x202		/* x86 extended state using xsave */
-- 
2.1.0

[PATCH V10 02/28] powerpc, process: Add the function flush_tmregs_to_thread

[Anshuman Khandual]

This patch creates a function flush_tmregs_to_thread which
will then be used by subsequent patches in this series. The
function checks for self tracing ptrace interface attempts
while in the TM context and logs appropriate warning message.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/powerpc/include/asm/switch_to.h |  8 ++++++++
 arch/powerpc/kernel/process.c        | 20 ++++++++++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h
index 5b268b6..7b297bf 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -70,6 +70,14 @@ static inline void disable_kernel_spe(void)
 }
 #endif
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+extern void flush_tmregs_to_thread(struct task_struct *);
+#else
+static inline void flush_tmregs_to_thread(struct task_struct *t)
+{
+}
+#endif
+
 static inline void clear_task_ebb(struct task_struct *t)
 {
 #ifdef CONFIG_PPC_BOOK3S_64
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index dccc87e..2c4fa7f 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -918,6 +918,26 @@ static inline void restore_sprs(struct thread_struct *old_thread,
 #endif
 }
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+void flush_tmregs_to_thread(struct task_struct *tsk)
+{
+	/*
+	 * Process self tracing is not yet supported through
+	 * ptrace interface. Ptrace generic code should have
+	 * prevented this from happening in the first place.
+	 * Warn once here with the message, if some how it
+	 * is attempted.
+	 */
+	WARN_ONCE(tsk == current,
+		"Not expecting ptrace on self: TM regs may be incorrect\n");
+
+	/*
+	 * If task is not current, it should have been flushed
+	 * already to it's thread_struct during __switch_to().
+	 */
+}
+#endif
+
 struct task_struct *__switch_to(struct task_struct *prev,
 	struct task_struct *new)
 {
-- 
2.1.0

[PATCH V10 03/28] powerpc, ptrace: Enable in transaction NT_PRFPREG ptrace requests

[Anshuman Khandual]

This patch enables in transaction NT_PRFPREG ptrace requests.
The function fpr_get which gets the running value of all FPR
registers and the function fpr_set which sets the running
value of of all FPR registers work on the running set of FPR
registers whose location will be different if transaction is
active. This patch makes these functions adapt to situations
when the transaction is active.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/ptrace.c | 93 ++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 89 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 30a03c0..547a979 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -358,6 +358,29 @@ static int gpr_set(struct task_struct *target, const struct user_regset *regset,
 	return ret;
 }
 
+/*
+ * When the transaction is active, 'transact_fp' holds the current running
+ * value of all FPR registers and 'fp_state' holds the last checkpointed
+ * value of all FPR registers for the current transaction. When transaction
+ * is not active 'fp_state' holds the current running state of all the FPR
+ * registers. So this function which returns the current running values of
+ * all the FPR registers, needs to know whether any transaction is active
+ * or not.
+ *
+ * Userspace interface buffer layout:
+ *
+ * struct data {
+ *	u64	fpr[32];
+ *	u64	fpscr;
+ * };
+ *
+ * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM
+ * which determines the final code in this function. All the combinations of
+ * these two config options are possible except the one below as transactional
+ * memory config pulls in CONFIG_VSX automatically.
+ *
+ *	!defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
+ */
 static int fpr_get(struct task_struct *target, const struct user_regset *regset,
 		   unsigned int pos, unsigned int count,
 		   void *kbuf, void __user *ubuf)
@@ -368,14 +391,31 @@ static int fpr_get(struct task_struct *target, const struct user_regset *regset,
 #endif
 	flush_fp_to_thread(target);
 
-#ifdef CONFIG_VSX
+#if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
+	/* copy to local buffer then write that out */
+	if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
+		flush_altivec_to_thread(target);
+		flush_tmregs_to_thread(target);
+		for (i = 0; i < 32 ; i++)
+			buf[i] = target->thread.TS_TRANS_FPR(i);
+		buf[32] = target->thread.transact_fp.fpscr;
+	} else {
+		for (i = 0; i < 32 ; i++)
+			buf[i] = target->thread.TS_FPR(i);
+		buf[32] = target->thread.fp_state.fpscr;
+	}
+	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
+#endif
+
+#if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
 	/* copy to local buffer then write that out */
 	for (i = 0; i < 32 ; i++)
 		buf[i] = target->thread.TS_FPR(i);
 	buf[32] = target->thread.fp_state.fpscr;
 	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
+#endif
 
-#else
+#if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
 	BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
 		     offsetof(struct thread_fp_state, fpr[32][0]));
 
@@ -384,6 +424,29 @@ static int fpr_get(struct task_struct *target, const struct user_regset *regset,
 #endif
 }
 
+/*
+ * When the transaction is active, 'transact_fp' holds the current running
+ * value of all FPR registers and 'fp_state' holds the last checkpointed
+ * value of all FPR registers for the current transaction. When transaction
+ * is not active 'fp_state' holds the current running state of all the FPR
+ * registers. So this function which setss the current running values of
+ * all the FPR registers, needs to know whether any transaction is active
+ * or not.
+ *
+ * Userspace interface buffer layout:
+ *
+ * struct data {
+ *	u64	fpr[32];
+ *	u64	fpscr;
+ * };
+ *
+ * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM
+ * which determines the final code in this function. All the combinations of
+ * these two config options are possible except the one below as transactional
+ * memory config pulls in CONFIG_VSX automatically.
+ *
+ *	!defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
+ */
 static int fpr_set(struct task_struct *target, const struct user_regset *regset,
 		   unsigned int pos, unsigned int count,
 		   const void *kbuf, const void __user *ubuf)
@@ -394,7 +457,27 @@ static int fpr_set(struct task_struct *target, const struct user_regset *regset,
 #endif
 	flush_fp_to_thread(target);
 
-#ifdef CONFIG_VSX
+#if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
+	/* copy to local buffer then write that out */
+	i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
+	if (i)
+		return i;
+
+	if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
+		flush_altivec_to_thread(target);
+		flush_tmregs_to_thread(target);
+		for (i = 0; i < 32 ; i++)
+			target->thread.TS_TRANS_FPR(i) = buf[i];
+		target->thread.transact_fp.fpscr = buf[32];
+	} else {
+		for (i = 0; i < 32 ; i++)
+			target->thread.TS_FPR(i) = buf[i];
+		target->thread.fp_state.fpscr = buf[32];
+	}
+	return 0;
+#endif
+
+#if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
 	/* copy to local buffer then write that out */
 	i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
 	if (i)
@@ -403,7 +486,9 @@ static int fpr_set(struct task_struct *target, const struct user_regset *regset,
 		target->thread.TS_FPR(i) = buf[i];
 	target->thread.fp_state.fpscr = buf[32];
 	return 0;
-#else
+#endif
+
+#if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
 	BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
 		     offsetof(struct thread_fp_state, fpr[32][0]));
 
-- 
2.1.0

[PATCH V10 04/28] powerpc, ptrace: Enable in transaction NT_PPC_VMX ptrace requests

[Anshuman Khandual]

This patch enables in transaction NT_PPC_VMX ptrace requests. The
function vr_get which gets the running value of all VMX registers
and the function vr_set which sets the running value of of all VMX
registers work on the running set of VMX registers whose location
will be different if transaction is active. This patch makes these
functions adapt to situations when the transaction is active.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/ptrace.c | 90 ++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 87 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 547a979..8e21e2c 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -518,10 +518,28 @@ static int vr_active(struct task_struct *target,
 	return target->thread.used_vr ? regset->n : 0;
 }
 
+/*
+ * When the transaction is active, 'transact_vr' holds the current running
+ * value of all the VMX registers and 'vr_state' holds the last checkpointed
+ * value of all the VMX registers for the current transaction to fall back
+ * on in case it aborts. When transaction is not active 'vr_state' holds
+ * the current running state of all the VMX registers. So this function which
+ * gets the current running values of all the VMX registers, needs to know
+ * whether any transaction is active or not.
+ *
+ * Userspace interface buffer layout:
+ *
+ * struct data {
+ *	vector128	vr[32];
+ *	vector128	vscr;
+ *	vector128	vrsave;
+ * };
+ */
 static int vr_get(struct task_struct *target, const struct user_regset *regset,
 		  unsigned int pos, unsigned int count,
 		  void *kbuf, void __user *ubuf)
 {
+	struct thread_vr_state *addr;
 	int ret;
 
 	flush_altivec_to_thread(target);
@@ -529,8 +547,19 @@ static int vr_get(struct task_struct *target, const struct user_regset *regset,
 	BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
 		     offsetof(struct thread_vr_state, vr[32]));
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
+		flush_fp_to_thread(target);
+		flush_tmregs_to_thread(target);
+		addr = &target->thread.transact_vr;
+	} else {
+		addr = &target->thread.vr_state;
+	}
+#else
+	addr = &target->thread.vr_state;
+#endif
 	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
-				  &target->thread.vr_state, 0,
+				  addr, 0,
 				  33 * sizeof(vector128));
 	if (!ret) {
 		/*
@@ -541,7 +570,16 @@ static int vr_get(struct task_struct *target, const struct user_regset *regset,
 			u32 word;
 		} vrsave;
 		memset(&vrsave, 0, sizeof(vrsave));
+
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+		if (MSR_TM_ACTIVE(target->thread.regs->msr))
+			vrsave.word = target->thread.transact_vrsave;
+		else
+			vrsave.word = target->thread.vrsave;
+#else
 		vrsave.word = target->thread.vrsave;
+#endif
+
 		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
 					  33 * sizeof(vector128), -1);
 	}
@@ -549,10 +587,28 @@ static int vr_get(struct task_struct *target, const struct user_regset *regset,
 	return ret;
 }
 
+/*
+ * When the transaction is active, 'transact_vr' holds the current running
+ * value of all the VMX registers and 'vr_state' holds the last checkpointed
+ * value of all the VMX registers for the current transaction to fall back
+ * on in case it aborts. When transaction is not active 'vr_state' holds
+ * the current running state of all the VMX registers. So this function which
+ * sets the current running values of all the VMX registers, needs to know
+ * whether any transaction is active or not.
+ *
+ * Userspace interface buffer layout:
+ *
+ * struct data {
+ *	vector128	vr[32];
+ *	vector128	vscr;
+ *	vector128	vrsave;
+ * };
+ */
 static int vr_set(struct task_struct *target, const struct user_regset *regset,
 		  unsigned int pos, unsigned int count,
 		  const void *kbuf, const void __user *ubuf)
 {
+	struct thread_vr_state *addr;
 	int ret;
 
 	flush_altivec_to_thread(target);
@@ -560,8 +616,19 @@ static int vr_set(struct task_struct *target, const struct user_regset *regset,
 	BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
 		     offsetof(struct thread_vr_state, vr[32]));
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
+		flush_fp_to_thread(target);
+		flush_tmregs_to_thread(target);
+		addr = &target->thread.transact_vr;
+	} else {
+		addr = &target->thread.vr_state;
+	}
+#else
+	addr = &target->thread.vr_state;
+#endif
 	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
-				 &target->thread.vr_state, 0,
+				 addr, 0,
 				 33 * sizeof(vector128));
 	if (!ret && count > 0) {
 		/*
@@ -572,11 +639,28 @@ static int vr_set(struct task_struct *target, const struct user_regset *regset,
 			u32 word;
 		} vrsave;
 		memset(&vrsave, 0, sizeof(vrsave));
+
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+		if (MSR_TM_ACTIVE(target->thread.regs->msr))
+			vrsave.word = target->thread.transact_vrsave;
+		else
+			vrsave.word = target->thread.vrsave;
+#else
 		vrsave.word = target->thread.vrsave;
+#endif
 		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
 					 33 * sizeof(vector128), -1);
-		if (!ret)
+		if (!ret) {
+
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+			if (MSR_TM_ACTIVE(target->thread.regs->msr))
+				target->thread.transact_vrsave = vrsave.word;
+			else
+				target->thread.vrsave = vrsave.word;
+#else
 			target->thread.vrsave = vrsave.word;
+#endif
+		}
 	}
 
 	return ret;
-- 
2.1.0

[PATCH V10 05/28] powerpc, ptrace: Enable in transaction NT_PPC_VSX ptrace requests

[Anshuman Khandual]

This patch enables in transaction NT_PPC_VSX ptrace requests. The
function vsr_get which gets the running value of all VSX registers
and the function vsr_set which sets the running value of of all VSX
registers work on the running set of VMX registers whose location
will be different if transaction is active. This patch makes these
functions adapt to situations when the transaction is active.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/ptrace.c | 64 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)

diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 8e21e2c..255b598 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -681,6 +681,21 @@ static int vsr_active(struct task_struct *target,
 	return target->thread.used_vsr ? regset->n : 0;
 }
 
+/*
+ * When the transaction is active, 'transact_fp' holds the current running
+ * value of all FPR registers and 'fp_state' holds the last checkpointed
+ * value of all FPR registers for the current transaction. When transaction
+ * is not active 'fp_state' holds the current running state of all the FPR
+ * registers. So this function which returns the current running values of
+ * all the FPR registers, needs to know whether any transaction is active
+ * or not.
+ *
+ * Userspace interface buffer layout:
+ *
+ * struct data {
+ *	u64	vsx[32];
+ * };
+ */
 static int vsr_get(struct task_struct *target, const struct user_regset *regset,
 		   unsigned int pos, unsigned int count,
 		   void *kbuf, void __user *ubuf)
@@ -688,16 +703,47 @@ static int vsr_get(struct task_struct *target, const struct user_regset *regset,
 	u64 buf[32];
 	int ret, i;
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+#endif
 	flush_vsx_to_thread(target);
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
+		for (i = 0; i < 32 ; i++)
+			buf[i] = target->thread.
+				transact_fp.fpr[i][TS_VSRLOWOFFSET];
+	} else {
+		for (i = 0; i < 32 ; i++)
+			buf[i] = target->thread.
+				fp_state.fpr[i][TS_VSRLOWOFFSET];
+	}
+#else
 	for (i = 0; i < 32 ; i++)
 		buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
+#endif
 	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 				  buf, 0, 32 * sizeof(double));
 
 	return ret;
 }
 
+/*
+ * When the transaction is active, 'transact_fp' holds the current running
+ * value of all FPR registers and 'fp_state' holds the last checkpointed
+ * value of all FPR registers for the current transaction. When transaction
+ * is not active 'fp_state' holds the current running state of all the FPR
+ * registers. So this function which sets the current running values of all
+ * the FPR registers, needs to know whether any transaction is active or not.
+ *
+ * Userspace interface buffer layout:
+ *
+ * struct data {
+ *	u64	vsx[32];
+ * };
+ */
 static int vsr_set(struct task_struct *target, const struct user_regset *regset,
 		   unsigned int pos, unsigned int count,
 		   const void *kbuf, const void __user *ubuf)
@@ -705,12 +751,30 @@ static int vsr_set(struct task_struct *target, const struct user_regset *regset,
 	u64 buf[32];
 	int ret,i;
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+#endif
 	flush_vsx_to_thread(target);
 
 	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 				 buf, 0, 32 * sizeof(double));
+
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
+		for (i = 0; i < 32 ; i++)
+			target->thread.transact_fp.
+				fpr[i][TS_VSRLOWOFFSET] = buf[i];
+	} else {
+		for (i = 0; i < 32 ; i++)
+			target->thread.fp_state.
+				fpr[i][TS_VSRLOWOFFSET] = buf[i];
+	}
+#else
 	for (i = 0; i < 32 ; i++)
 		target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i];
+#endif
 
 
 	return ret;
-- 
2.1.0

[PATCH V10 06/28] powerpc, ptrace: Adapt gpr32_get, gpr32_set functions for transaction

[Anshuman Khandual]

This patch splits gpr32_get, gpr32_set functions to accommodate
in transaction ptrace requests implemented in patches later in
the series.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/ptrace.c | 64 +++++++++++++++++++++++++++++++++++---------
 1 file changed, 51 insertions(+), 13 deletions(-)

diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 255b598..6e0e035 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -907,24 +907,35 @@ static const struct user_regset_view user_ppc_native_view = {
 #ifdef CONFIG_PPC64
 #include <linux/compat.h>
 
-static int gpr32_get(struct task_struct *target,
+static int gpr32_get_common(struct task_struct *target,
 		     const struct user_regset *regset,
 		     unsigned int pos, unsigned int count,
-		     void *kbuf, void __user *ubuf)
+			    void *kbuf, void __user *ubuf, bool tm_active)
 {
 	const unsigned long *regs = &target->thread.regs->gpr[0];
+	const unsigned long *ckpt_regs;
 	compat_ulong_t *k = kbuf;
 	compat_ulong_t __user *u = ubuf;
 	compat_ulong_t reg;
 	int i;
 
-	if (target->thread.regs == NULL)
-		return -EIO;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	ckpt_regs = &target->thread.ckpt_regs.gpr[0];
+#endif
+	if (tm_active) {
+		regs = ckpt_regs;
+	} else {
+		if (target->thread.regs == NULL)
+			return -EIO;
 
-	if (!FULL_REGS(target->thread.regs)) {
-		/* We have a partial register set.  Fill 14-31 with bogus values */
-		for (i = 14; i < 32; i++)
-			target->thread.regs->gpr[i] = NV_REG_POISON; 
+		if (!FULL_REGS(target->thread.regs)) {
+			/*
+			 * We have a partial register set.
+			 * Fill 14-31 with bogus values.
+			 */
+			for (i = 14; i < 32; i++)
+				target->thread.regs->gpr[i] = NV_REG_POISON;
+		}
 	}
 
 	pos /= sizeof(reg);
@@ -964,20 +975,31 @@ static int gpr32_get(struct task_struct *target,
 					PT_REGS_COUNT * sizeof(reg), -1);
 }
 
-static int gpr32_set(struct task_struct *target,
+static int gpr32_set_common(struct task_struct *target,
 		     const struct user_regset *regset,
 		     unsigned int pos, unsigned int count,
-		     const void *kbuf, const void __user *ubuf)
+		     const void *kbuf, const void __user *ubuf, bool tm_active)
 {
 	unsigned long *regs = &target->thread.regs->gpr[0];
+	unsigned long *ckpt_regs;
 	const compat_ulong_t *k = kbuf;
 	const compat_ulong_t __user *u = ubuf;
 	compat_ulong_t reg;
 
-	if (target->thread.regs == NULL)
-		return -EIO;
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	ckpt_regs = &target->thread.ckpt_regs.gpr[0];
+#endif
 
-	CHECK_FULL_REGS(target->thread.regs);
+	if (tm_active) {
+		regs = ckpt_regs;
+	} else {
+		regs = &target->thread.regs->gpr[0];
+
+		if (target->thread.regs == NULL)
+			return -EIO;
+
+		CHECK_FULL_REGS(target->thread.regs);
+	}
 
 	pos /= sizeof(reg);
 	count /= sizeof(reg);
@@ -1037,6 +1059,22 @@ static int gpr32_set(struct task_struct *target,
 					 (PT_TRAP + 1) * sizeof(reg), -1);
 }
 
+static int gpr32_get(struct task_struct *target,
+		     const struct user_regset *regset,
+		     unsigned int pos, unsigned int count,
+		     void *kbuf, void __user *ubuf)
+{
+	return gpr32_get_common(target, regset, pos, count, kbuf, ubuf, 0);
+}
+
+static int gpr32_set(struct task_struct *target,
+		     const struct user_regset *regset,
+		     unsigned int pos, unsigned int count,
+		     const void *kbuf, const void __user *ubuf)
+{
+	return gpr32_set_common(target, regset, pos, count, kbuf, ubuf, 0);
+}
+
 /*
  * These are the regset flavors matching the CONFIG_PPC32 native set.
  */
-- 
2.1.0

[PATCH V10 07/28] powerpc, ptrace: Enable support for NT_PPC_CGPR

[Anshuman Khandual]

This patch enables support for TM checkpointed GPR register
set ELF core note NT_PPC_CGPR based ptrace requests through
PTRACE_GETREGSET, PTRACE_SETREGSET calls. This is achieved
through adding a register set REGSET_CGPR in powerpc
corresponding to the ELF core note section added. It
implements the get, set and active functions for this new
register set added.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/ptrace.c | 222 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 222 insertions(+)

diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 6e0e035..8462c7e 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -181,6 +181,26 @@ static int set_user_msr(struct task_struct *task, unsigned long msr)
 	return 0;
 }
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+static unsigned long get_user_ckpt_msr(struct task_struct *task)
+{
+	return task->thread.ckpt_regs.msr | task->thread.fpexc_mode;
+}
+
+static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr)
+{
+	task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE;
+	task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE;
+	return 0;
+}
+
+static int set_user_ckpt_trap(struct task_struct *task, unsigned long trap)
+{
+	task->thread.ckpt_regs.trap = trap & 0xfff0;
+	return 0;
+}
+#endif
+
 #ifdef CONFIG_PPC64
 static int get_user_dscr(struct task_struct *task, unsigned long *data)
 {
@@ -847,6 +867,172 @@ static int evr_set(struct task_struct *target, const struct user_regset *regset,
 }
 #endif /* CONFIG_SPE */
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+/**
+ * tm_cgpr_active - get active number of registers in CGPR
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ *
+ * This function checks for the active number of available
+ * regisers in transaction checkpointed GPR category.
+ */
+static int tm_cgpr_active(struct task_struct *target,
+			  const struct user_regset *regset)
+{
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return 0;
+
+	return regset->n;
+}
+
+/**
+ * tm_cgpr_get - get CGPR registers
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ * @pos:	The buffer position.
+ * @count:	Number of bytes to copy.
+ * @kbuf:	Kernel buffer to copy from.
+ * @ubuf:	User buffer to copy into.
+ *
+ * This function gets transaction checkpointed GPR registers.
+ *
+ * When the transaction is active, 'ckpt_regs' holds all the checkpointed
+ * GPR register values for the current transaction to fall back on if it
+ * aborts in between. This function gets those checkpointed GPR registers.
+ * The userspace interface buffer layout is as follows.
+ *
+ * struct data {
+ *	struct pt_regs ckpt_regs;
+ * };
+ */
+static int tm_cgpr_get(struct task_struct *target,
+			const struct user_regset *regset,
+			unsigned int pos, unsigned int count,
+			void *kbuf, void __user *ubuf)
+{
+	int ret;
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+
+	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				  &target->thread.ckpt_regs,
+				  0, offsetof(struct pt_regs, msr));
+	if (!ret) {
+		unsigned long msr = get_user_ckpt_msr(target);
+
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
+					  offsetof(struct pt_regs, msr),
+					  offsetof(struct pt_regs, msr) +
+					  sizeof(msr));
+	}
+
+	BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
+		     offsetof(struct pt_regs, msr) + sizeof(long));
+
+	if (!ret)
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+					  &target->thread.ckpt_regs.orig_gpr3,
+					  offsetof(struct pt_regs, orig_gpr3),
+					  sizeof(struct pt_regs));
+	if (!ret)
+		ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
+					       sizeof(struct pt_regs), -1);
+
+	return ret;
+}
+
+/*
+ * tm_cgpr_set - set the CGPR registers
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ * @pos:	The buffer position.
+ * @count:	Number of bytes to copy.
+ * @kbuf:	Kernel buffer to copy into.
+ * @ubuf:	User buffer to copy from.
+ *
+ * This function sets in transaction checkpointed GPR registers.
+ *
+ * When the transaction is active, 'ckpt_regs' holds the checkpointed
+ * GPR register values for the current transaction to fall back on if it
+ * aborts in between. This function sets those checkpointed GPR registers.
+ * The userspace interface buffer layout is as follows.
+ *
+ * struct data {
+ *	struct pt_regs ckpt_regs;
+ * };
+ */
+static int tm_cgpr_set(struct task_struct *target,
+			const struct user_regset *regset,
+			unsigned int pos, unsigned int count,
+			const void *kbuf, const void __user *ubuf)
+{
+	unsigned long reg;
+	int ret;
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				 &target->thread.ckpt_regs,
+				 0, PT_MSR * sizeof(reg));
+
+	if (!ret && count > 0) {
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
+					 PT_MSR * sizeof(reg),
+					 (PT_MSR + 1) * sizeof(reg));
+		if (!ret)
+			ret = set_user_ckpt_msr(target, reg);
+	}
+
+	BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
+		     offsetof(struct pt_regs, msr) + sizeof(long));
+
+	if (!ret)
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+					 &target->thread.ckpt_regs.orig_gpr3,
+					 PT_ORIG_R3 * sizeof(reg),
+					 (PT_MAX_PUT_REG + 1) * sizeof(reg));
+
+	if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
+		ret = user_regset_copyin_ignore(
+			&pos, &count, &kbuf, &ubuf,
+			(PT_MAX_PUT_REG + 1) * sizeof(reg),
+			PT_TRAP * sizeof(reg));
+
+	if (!ret && count > 0) {
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
+					 PT_TRAP * sizeof(reg),
+					 (PT_TRAP + 1) * sizeof(reg));
+		if (!ret)
+			ret = set_user_ckpt_trap(target, reg);
+	}
+
+	if (!ret)
+		ret = user_regset_copyin_ignore(
+			&pos, &count, &kbuf, &ubuf,
+			(PT_TRAP + 1) * sizeof(reg), -1);
+
+	return ret;
+}
+#endif
 
 /*
  * These are our native regset flavors.
@@ -863,6 +1049,9 @@ enum powerpc_regset {
 #ifdef CONFIG_SPE
 	REGSET_SPE,
 #endif
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	REGSET_TM_CGPR,		/* TM checkpointed GPR registers */
+#endif
 };
 
 static const struct user_regset native_regsets[] = {
@@ -897,6 +1086,13 @@ static const struct user_regset native_regsets[] = {
 		.active = evr_active, .get = evr_get, .set = evr_set
 	},
 #endif
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	[REGSET_TM_CGPR] = {
+		.core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG,
+		.size = sizeof(long), .align = sizeof(long),
+		.active = tm_cgpr_active, .get = tm_cgpr_get, .set = tm_cgpr_set
+	},
+#endif
 };
 
 static const struct user_regset_view user_ppc_native_view = {
@@ -1059,6 +1255,24 @@ static int gpr32_set_common(struct task_struct *target,
 					 (PT_TRAP + 1) * sizeof(reg), -1);
 }
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+static int tm_cgpr32_get(struct task_struct *target,
+		     const struct user_regset *regset,
+		     unsigned int pos, unsigned int count,
+		     void *kbuf, void __user *ubuf)
+{
+	return gpr32_get_common(target, regset, pos, count, kbuf, ubuf, 1);
+}
+
+static int tm_cgpr32_set(struct task_struct *target,
+		     const struct user_regset *regset,
+		     unsigned int pos, unsigned int count,
+		     const void *kbuf, const void __user *ubuf)
+{
+	return gpr32_set_common(target, regset, pos, count, kbuf, ubuf, 1);
+}
+#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
+
 static int gpr32_get(struct task_struct *target,
 		     const struct user_regset *regset,
 		     unsigned int pos, unsigned int count,
@@ -1103,6 +1317,14 @@ static const struct user_regset compat_regsets[] = {
 		.active = evr_active, .get = evr_get, .set = evr_set
 	},
 #endif
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	[REGSET_TM_CGPR] = {
+		.core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG,
+		.size = sizeof(long), .align = sizeof(long),
+		.active = tm_cgpr_active,
+		.get = tm_cgpr32_get, .set = tm_cgpr32_set
+	},
+#endif
 };
 
 static const struct user_regset_view user_ppc_compat_view = {
-- 
2.1.0

[PATCH V10 08/28] powerpc, ptrace: Enable support for NT_PPC_CFPR

[Anshuman Khandual]

This patch enables support for TM checkpointed FPR register
set ELF core note NT_PPC_CFPR based ptrace requests through
PTRACE_GETREGSET, PTRACE_SETREGSET calls. This is achieved
through adding a register set REGSET_CFPR in powerpc
corresponding to the ELF core note section added. It
implements the get, set and active functions for this new
register set added.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/ptrace.c | 126 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 126 insertions(+)

diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 8462c7e..13b3ec6 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -1032,6 +1032,121 @@ static int tm_cgpr_set(struct task_struct *target,
 
 	return ret;
 }
+
+/**
+ * tm_cfpr_active - get active number of registers in CFPR
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ *
+ * This function checks for the active number of available
+ * regisers in transaction checkpointed FPR category.
+ */
+static int tm_cfpr_active(struct task_struct *target,
+				const struct user_regset *regset)
+{
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return 0;
+
+	return regset->n;
+}
+
+/**
+ * tm_cfpr_get - get CFPR registers
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ * @pos:	The buffer position.
+ * @count:	Number of bytes to copy.
+ * @kbuf:	Kernel buffer to copy from.
+ * @ubuf:	User buffer to copy into.
+ *
+ * This function gets in transaction checkpointed FPR registers.
+ *
+ * When the transaction is active 'fp_state' holds the checkpointed
+ * values for the current transaction to fall back on if it aborts
+ * in between. This function gets those checkpointed FPR registers.
+ * The userspace interface buffer layout is as follows.
+ *
+ * struct data {
+ *	u64	fpr[32];
+ *	u64	fpscr;
+ *};
+ */
+static int tm_cfpr_get(struct task_struct *target,
+			const struct user_regset *regset,
+			unsigned int pos, unsigned int count,
+			void *kbuf, void __user *ubuf)
+{
+	u64 buf[33];
+	int i;
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+
+	/* copy to local buffer then write that out */
+	for (i = 0; i < 32 ; i++)
+		buf[i] = target->thread.TS_FPR(i);
+	buf[32] = target->thread.fp_state.fpscr;
+	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
+}
+
+/**
+ * tm_cfpr_set - set CFPR registers
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ * @pos:	The buffer position.
+ * @count:	Number of bytes to copy.
+ * @kbuf:	Kernel buffer to copy into.
+ * @ubuf:	User buffer to copy from.
+ *
+ * This function sets in transaction checkpointed FPR registers.
+ *
+ * When the transaction is active 'fp_state' holds the checkpointed
+ * FPR register values for the current transaction to fall back on
+ * if it aborts in between. This function sets these checkpointed
+ * FPR registers. The userspace interface buffer layout is as follows.
+ *
+ * struct data {
+ *	u64	fpr[32];
+ *	u64	fpscr;
+ *};
+ */
+static int tm_cfpr_set(struct task_struct *target,
+			const struct user_regset *regset,
+			unsigned int pos, unsigned int count,
+			const void *kbuf, const void __user *ubuf)
+{
+	u64 buf[33];
+	int i;
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+
+	/* copy to local buffer then write that out */
+	i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
+	if (i)
+		return i;
+	for (i = 0; i < 32 ; i++)
+		target->thread.TS_FPR(i) = buf[i];
+	target->thread.fp_state.fpscr = buf[32];
+	return 0;
+}
 #endif
 
 /*
@@ -1051,6 +1166,7 @@ enum powerpc_regset {
 #endif
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 	REGSET_TM_CGPR,		/* TM checkpointed GPR registers */
+	REGSET_TM_CFPR,		/* TM checkpointed FPR registers */
 #endif
 };
 
@@ -1092,6 +1208,11 @@ static const struct user_regset native_regsets[] = {
 		.size = sizeof(long), .align = sizeof(long),
 		.active = tm_cgpr_active, .get = tm_cgpr_get, .set = tm_cgpr_set
 	},
+	[REGSET_TM_CFPR] = {
+		.core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG,
+		.size = sizeof(double), .align = sizeof(double),
+		.active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
+	},
 #endif
 };
 
@@ -1324,6 +1445,11 @@ static const struct user_regset compat_regsets[] = {
 		.active = tm_cgpr_active,
 		.get = tm_cgpr32_get, .set = tm_cgpr32_set
 	},
+	[REGSET_TM_CFPR] = {
+		.core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG,
+		.size = sizeof(double), .align = sizeof(double),
+		.active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
+	},
 #endif
 };
 
-- 
2.1.0

[PATCH V10 09/28] powerpc, ptrace: Enable support for NT_PPC_CVMX

[Anshuman Khandual]

This patch enables support for TM checkpointed VMX register
set ELF core note NT_PPC_CVMX based ptrace requests through
PTRACE_GETREGSET, PTRACE_SETREGSET calls. This is achieved
through adding a register set REGSET_CVMX in powerpc
corresponding to the ELF core note section added. It
implements the get, set and active functions for this new
register set added.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/powerpc/include/uapi/asm/elf.h |   1 +
 arch/powerpc/kernel/ptrace.c        | 158 ++++++++++++++++++++++++++++++++++++
 2 files changed, 159 insertions(+)

diff --git a/arch/powerpc/include/uapi/asm/elf.h b/arch/powerpc/include/uapi/asm/elf.h
index c2d21d1..ecb4e84 100644
--- a/arch/powerpc/include/uapi/asm/elf.h
+++ b/arch/powerpc/include/uapi/asm/elf.h
@@ -91,6 +91,7 @@
 
 #define ELF_NGREG	48	/* includes nip, msr, lr, etc. */
 #define ELF_NFPREG	33	/* includes fpscr */
+#define ELF_NVMX	34	/* includes all vector registers */
 
 typedef unsigned long elf_greg_t64;
 typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 13b3ec6..123a03c 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -64,6 +64,8 @@ struct pt_regs_offset {
 	{.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
 #define REG_OFFSET_END {.name = NULL, .offset = 0}
 
+#define TVSO(f)	(offsetof(struct thread_vr_state, f))
+
 static const struct pt_regs_offset regoffset_table[] = {
 	GPR_OFFSET_NAME(0),
 	GPR_OFFSET_NAME(1),
@@ -1147,6 +1149,151 @@ static int tm_cfpr_set(struct task_struct *target,
 	target->thread.fp_state.fpscr = buf[32];
 	return 0;
 }
+
+/**
+ * tm_cvmx_active - get active number of registers in CVMX
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ *
+ * This function checks for the active number of available
+ * regisers in checkpointed VMX category.
+ */
+static int tm_cvmx_active(struct task_struct *target,
+				const struct user_regset *regset)
+{
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return 0;
+
+	return regset->n;
+}
+
+/**
+ * tm_cvmx_get - get CMVX registers
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ * @pos:	The buffer position.
+ * @count:	Number of bytes to copy.
+ * @kbuf:	Kernel buffer to copy from.
+ * @ubuf:	User buffer to copy into.
+ *
+ * This function gets in transaction checkpointed VMX registers.
+ *
+ * When the transaction is active 'vr_state' and 'vr_save' hold
+ * the checkpointed values for the current transaction to fall
+ * back on if it aborts in between. The userspace interface buffer
+ * layout is as follows.
+ *
+ * struct data {
+ *	vector128	vr[32];
+ *	vector128	vscr;
+ *	vector128	vrsave;
+ *};
+ */
+static int tm_cvmx_get(struct task_struct *target,
+			const struct user_regset *regset,
+			unsigned int pos, unsigned int count,
+			void *kbuf, void __user *ubuf)
+{
+	int ret;
+
+	BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32]));
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	/* Flush the state */
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+
+	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+					&target->thread.vr_state, 0,
+					33 * sizeof(vector128));
+	if (!ret) {
+		/*
+		 * Copy out only the low-order word of vrsave.
+		 */
+		union {
+			elf_vrreg_t reg;
+			u32 word;
+		} vrsave;
+		memset(&vrsave, 0, sizeof(vrsave));
+		vrsave.word = target->thread.vrsave;
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
+						33 * sizeof(vector128), -1);
+	}
+
+	return ret;
+}
+
+/**
+ * tm_cvmx_set - set CMVX registers
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ * @pos:	The buffer position.
+ * @count:	Number of bytes to copy.
+ * @kbuf:	Kernel buffer to copy into.
+ * @ubuf:	User buffer to copy from.
+ *
+ * This function sets in transaction checkpointed VMX registers.
+ *
+ * When the transaction is active 'vr_state' and 'vr_save' hold
+ * the checkpointed values for the current transaction to fall
+ * back on if it aborts in between. The userspace interface buffer
+ * layout is as follows.
+ *
+ * struct data {
+ *	vector128	vr[32];
+ *	vector128	vscr;
+ *	vector128	vrsave;
+ *};
+ */
+static int tm_cvmx_set(struct task_struct *target,
+			const struct user_regset *regset,
+			unsigned int pos, unsigned int count,
+			const void *kbuf, const void __user *ubuf)
+{
+	int ret;
+
+	BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32]));
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+					&target->thread.vr_state, 0,
+					33 * sizeof(vector128));
+	if (!ret && count > 0) {
+		/*
+		 * We use only the low-order word of vrsave.
+		 */
+		union {
+			elf_vrreg_t reg;
+			u32 word;
+		} vrsave;
+		memset(&vrsave, 0, sizeof(vrsave));
+		vrsave.word = target->thread.vrsave;
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
+						33 * sizeof(vector128), -1);
+		if (!ret)
+			target->thread.vrsave = vrsave.word;
+	}
+
+	return ret;
+}
 #endif
 
 /*
@@ -1167,6 +1314,7 @@ enum powerpc_regset {
 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 	REGSET_TM_CGPR,		/* TM checkpointed GPR registers */
 	REGSET_TM_CFPR,		/* TM checkpointed FPR registers */
+	REGSET_TM_CVMX,		/* TM checkpointed VMX registers */
 #endif
 };
 
@@ -1213,6 +1361,11 @@ static const struct user_regset native_regsets[] = {
 		.size = sizeof(double), .align = sizeof(double),
 		.active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
 	},
+	[REGSET_TM_CVMX] = {
+		.core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX,
+		.size = sizeof(vector128), .align = sizeof(vector128),
+		.active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
+	},
 #endif
 };
 
@@ -1450,6 +1603,11 @@ static const struct user_regset compat_regsets[] = {
 		.size = sizeof(double), .align = sizeof(double),
 		.active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
 	},
+	[REGSET_TM_CVMX] = {
+		.core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX,
+		.size = sizeof(vector128), .align = sizeof(vector128),
+		.active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
+	},
 #endif
 };
 
-- 
2.1.0

[PATCH V10 10/28] powerpc, ptrace: Enable support for NT_PPC_CVSX

[Anshuman Khandual]

This patch enables support for TM checkpointed VSX register
set ELF core note NT_PPC_CVSX based ptrace requests through
PTRACE_GETREGSET, PTRACE_SETREGSET calls. This is achieved
through adding a register set REGSET_CVSX in powerpc
corresponding to the ELF core note section added. It
implements the get, set and active functions for this new
register set added.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/powerpc/include/uapi/asm/elf.h |   1 +
 arch/powerpc/kernel/ptrace.c        | 129 ++++++++++++++++++++++++++++++++++++
 2 files changed, 130 insertions(+)

diff --git a/arch/powerpc/include/uapi/asm/elf.h b/arch/powerpc/include/uapi/asm/elf.h
index ecb4e84..1549172 100644
--- a/arch/powerpc/include/uapi/asm/elf.h
+++ b/arch/powerpc/include/uapi/asm/elf.h
@@ -92,6 +92,7 @@
 #define ELF_NGREG	48	/* includes nip, msr, lr, etc. */
 #define ELF_NFPREG	33	/* includes fpscr */
 #define ELF_NVMX	34	/* includes all vector registers */
+#define ELF_NVSX	32	/* includes all VSX registers */
 
 typedef unsigned long elf_greg_t64;
 typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 123a03c..5ddf040 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -65,6 +65,7 @@ struct pt_regs_offset {
 #define REG_OFFSET_END {.name = NULL, .offset = 0}
 
 #define TVSO(f)	(offsetof(struct thread_vr_state, f))
+#define TFSO(f)	(offsetof(struct thread_fp_state, f))
 
 static const struct pt_regs_offset regoffset_table[] = {
 	GPR_OFFSET_NAME(0),
@@ -1294,6 +1295,123 @@ static int tm_cvmx_set(struct task_struct *target,
 
 	return ret;
 }
+
+/**
+ * tm_cvsx_active - get active number of registers in CVSX
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ *
+ * This function checks for the active number of available
+ * regisers in transaction checkpointed VSX category.
+ */
+static int tm_cvsx_active(struct task_struct *target,
+				const struct user_regset *regset)
+{
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return 0;
+
+	flush_vsx_to_thread(target);
+	return target->thread.used_vsr ? regset->n : 0;
+}
+
+/**
+ * tm_cvsx_get - get CVSX registers
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ * @pos:	The buffer position.
+ * @count:	Number of bytes to copy.
+ * @kbuf:	Kernel buffer to copy from.
+ * @ubuf:	User buffer to copy into.
+ *
+ * This function gets in transaction checkpointed VSX registers.
+ *
+ * When the transaction is active 'fp_state' holds the checkpointed
+ * values for the current transaction to fall back on if it aborts
+ * in between. This function gets those checkpointed VSX registers.
+ * The userspace interface buffer layout is as follows.
+ *
+ * struct data {
+ *	u64	vsx[32];
+ *};
+ */
+static int tm_cvsx_get(struct task_struct *target,
+			const struct user_regset *regset,
+			unsigned int pos, unsigned int count,
+			void *kbuf, void __user *ubuf)
+{
+	u64 buf[32];
+	int ret, i;
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	/* Flush the state */
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+	flush_vsx_to_thread(target);
+
+	for (i = 0; i < 32 ; i++)
+		buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
+	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				  buf, 0, 32 * sizeof(double));
+
+	return ret;
+}
+
+/**
+ * tm_cvsx_set - set CFPR registers
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ * @pos:	The buffer position.
+ * @count:	Number of bytes to copy.
+ * @kbuf:	Kernel buffer to copy into.
+ * @ubuf:	User buffer to copy from.
+ *
+ * This function sets in transaction checkpointed VSX registers.
+ *
+ * When the transaction is active 'fp_state' holds the checkpointed
+ * VSX register values for the current transaction to fall back on
+ * if it aborts in between. This function sets these checkpointed
+ * FPR registers. The userspace interface buffer layout is as follows.
+ *
+ * struct data {
+ *	u64	vsx[32];
+ *};
+ */
+static int tm_cvsx_set(struct task_struct *target,
+			const struct user_regset *regset,
+			unsigned int pos, unsigned int count,
+			const void *kbuf, const void __user *ubuf)
+{
+	u64 buf[32];
+	int ret, i;
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	/* Flush the state */
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+	flush_vsx_to_thread(target);
+
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				 buf, 0, 32 * sizeof(double));
+	for (i = 0; i < 32 ; i++)
+		target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i];
+
+	return ret;
+}
 #endif
 
 /*
@@ -1315,6 +1433,7 @@ enum powerpc_regset {
 	REGSET_TM_CGPR,		/* TM checkpointed GPR registers */
 	REGSET_TM_CFPR,		/* TM checkpointed FPR registers */
 	REGSET_TM_CVMX,		/* TM checkpointed VMX registers */
+	REGSET_TM_CVSX,		/* TM checkpointed VSX registers */
 #endif
 };
 
@@ -1366,6 +1485,11 @@ static const struct user_regset native_regsets[] = {
 		.size = sizeof(vector128), .align = sizeof(vector128),
 		.active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
 	},
+	[REGSET_TM_CVSX] = {
+		.core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX,
+		.size = sizeof(double), .align = sizeof(double),
+		.active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
+	},
 #endif
 };
 
@@ -1608,6 +1732,11 @@ static const struct user_regset compat_regsets[] = {
 		.size = sizeof(vector128), .align = sizeof(vector128),
 		.active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
 	},
+	[REGSET_TM_CVSX] = {
+		.core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX,
+		.size = sizeof(double), .align = sizeof(double),
+		.active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
+	},
 #endif
 };
 
-- 
2.1.0

[PATCH V10 11/28] powerpc, ptrace: Enable support for TM SPR state

[Anshuman Khandual]

This patch enables support for TM SPR state related ELF core
note NT_PPC_TM_SPR based ptrace requests through PTRACE_GETREGSET,
PTRACE_SETREGSET calls. This is achieved through adding a register
set REGSET_TM_SPR in powerpc corresponding to the ELF core note
section added. It implements the get, set and active functions for
this new register set added.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/powerpc/include/uapi/asm/elf.h |   1 +
 arch/powerpc/kernel/ptrace.c        | 143 +++++++++++++++++++++++++++++++++++-
 2 files changed, 143 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/include/uapi/asm/elf.h b/arch/powerpc/include/uapi/asm/elf.h
index 1549172..e703c64 100644
--- a/arch/powerpc/include/uapi/asm/elf.h
+++ b/arch/powerpc/include/uapi/asm/elf.h
@@ -93,6 +93,7 @@
 #define ELF_NFPREG	33	/* includes fpscr */
 #define ELF_NVMX	34	/* includes all vector registers */
 #define ELF_NVSX	32	/* includes all VSX registers */
+#define ELF_NTMSPRREG	3	/* include tfhar, tfiar, texasr */
 
 typedef unsigned long elf_greg_t64;
 typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 5ddf040..b2dec4a 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -66,6 +66,7 @@ struct pt_regs_offset {
 
 #define TVSO(f)	(offsetof(struct thread_vr_state, f))
 #define TFSO(f)	(offsetof(struct thread_fp_state, f))
+#define TSO(f)	(offsetof(struct thread_struct, f))
 
 static const struct pt_regs_offset regoffset_table[] = {
 	GPR_OFFSET_NAME(0),
@@ -1412,7 +1413,136 @@ static int tm_cvsx_set(struct task_struct *target,
 
 	return ret;
 }
-#endif
+
+/**
+ * tm_spr_active - get active number of registers in TM SPR
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ *
+ * This function checks the active number of available
+ * regisers in the transactional memory SPR category.
+ */
+static int tm_spr_active(struct task_struct *target,
+			 const struct user_regset *regset)
+{
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	return regset->n;
+}
+
+/**
+ * tm_spr_get - get the TM related SPR registers
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ * @pos:	The buffer position.
+ * @count:	Number of bytes to copy.
+ * @kbuf:	Kernel buffer to copy from.
+ * @ubuf:	User buffer to copy into.
+ *
+ * This function gets transactional memory related SPR registers.
+ * The userspace interface buffer layout is as follows.
+ *
+ * struct {
+ *	u64		tm_tfhar;
+ *	u64		tm_texasr;
+ *	u64		tm_tfiar;
+ * };
+ */
+static int tm_spr_get(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      void *kbuf, void __user *ubuf)
+{
+	int ret;
+
+	/* Build tests */
+	BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
+	BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
+	BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	/* Flush the states */
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+
+	/* TFHAR register */
+	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_tfhar, 0, sizeof(u64));
+
+	/* TEXASR register */
+	if (!ret)
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_texasr, sizeof(u64),
+				2 * sizeof(u64));
+
+	/* TFIAR register */
+	if (!ret)
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_tfiar,
+				2 * sizeof(u64), 3 * sizeof(u64));
+	return ret;
+}
+
+/**
+ * tm_spr_set - set the TM related SPR registers
+ * @target:	The target task.
+ * @regset:	The user regset structure.
+ * @pos:	The buffer position.
+ * @count:	Number of bytes to copy.
+ * @kbuf:	Kernel buffer to copy into.
+ * @ubuf:	User buffer to copy from.
+ *
+ * This function sets transactional memory related SPR registers.
+ * The userspace interface buffer layout is as follows.
+ *
+ * struct {
+ *	u64		tm_tfhar;
+ *	u64		tm_texasr;
+ *	u64		tm_tfiar;
+ * };
+ */
+static int tm_spr_set(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      const void *kbuf, const void __user *ubuf)
+{
+	int ret;
+
+	/* Build tests */
+	BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
+	BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
+	BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	/* Flush the states */
+	flush_fp_to_thread(target);
+	flush_altivec_to_thread(target);
+	flush_tmregs_to_thread(target);
+
+	/* TFHAR register */
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_tfhar, 0, sizeof(u64));
+
+	/* TEXASR register */
+	if (!ret)
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_texasr, sizeof(u64),
+				2 * sizeof(u64));
+
+	/* TFIAR register */
+	if (!ret)
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_tfiar,
+				 2 * sizeof(u64), 3 * sizeof(u64));
+	return ret;
+}
+#endif	/* CONFIG_PPC_TRANSACTIONAL_MEM */
 
 /*
  * These are our native regset flavors.
@@ -1434,6 +1564,7 @@ enum powerpc_regset {
 	REGSET_TM_CFPR,		/* TM checkpointed FPR registers */
 	REGSET_TM_CVMX,		/* TM checkpointed VMX registers */
 	REGSET_TM_CVSX,		/* TM checkpointed VSX registers */
+	REGSET_TM_SPR,		/* TM specific SPR registers */
 #endif
 };
 
@@ -1490,6 +1621,11 @@ static const struct user_regset native_regsets[] = {
 		.size = sizeof(double), .align = sizeof(double),
 		.active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
 	},
+	[REGSET_TM_SPR] = {
+		.core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
+	},
 #endif
 };
 
@@ -1737,6 +1873,11 @@ static const struct user_regset compat_regsets[] = {
 		.size = sizeof(double), .align = sizeof(double),
 		.active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
 	},
+	[REGSET_TM_SPR] = {
+		.core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
+	},
 #endif
 };
 
-- 
2.1.0

[PATCH V10 12/28] powerpc, ptrace: Enable NT_PPC_TM_CTAR, NT_PPC_TM_CPPR, NT_PPC_TM_CDSCR

[Anshuman Khandual]

This patch enables support for all three TM checkpointed SPR
states related ELF core note  NT_PPC_TM_CTAR, NT_PPC_TM_CPPR,
NT_PPC_TM_CDSCR based ptrace requests through PTRACE_GETREGSET,
PTRACE_SETREGSET calls. This is achieved through adding three
new register sets REGSET_TM_CTAR, REGSET_TM_CPPR and
REGSET_TM_CDSCR in powerpc corresponding to the ELF core note
sections added. It implements the get, set and active functions
for all these new register sets added.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/ptrace.c | 178 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 178 insertions(+)

diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index b2dec4a..c3339a0 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -1542,6 +1542,151 @@ static int tm_spr_set(struct task_struct *target,
 				 2 * sizeof(u64), 3 * sizeof(u64));
 	return ret;
 }
+
+static int tm_tar_active(struct task_struct *target,
+			 const struct user_regset *regset)
+{
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (MSR_TM_ACTIVE(target->thread.regs->msr))
+		return regset->n;
+
+	return 0;
+}
+
+static int tm_tar_get(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      void *kbuf, void __user *ubuf)
+{
+	int ret;
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_tar, 0, sizeof(u64));
+	return ret;
+}
+
+static int tm_tar_set(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      const void *kbuf, const void __user *ubuf)
+{
+	int ret;
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_tar, 0, sizeof(u64));
+	return ret;
+}
+
+static int tm_ppr_active(struct task_struct *target,
+			 const struct user_regset *regset)
+{
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (MSR_TM_ACTIVE(target->thread.regs->msr))
+		return regset->n;
+
+	return 0;
+}
+
+
+static int tm_ppr_get(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      void *kbuf, void __user *ubuf)
+{
+	int ret;
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_ppr, 0, sizeof(u64));
+	return ret;
+}
+
+static int tm_ppr_set(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      const void *kbuf, const void __user *ubuf)
+{
+	int ret;
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_ppr, 0, sizeof(u64));
+	return ret;
+}
+
+static int tm_dscr_active(struct task_struct *target,
+			 const struct user_regset *regset)
+{
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (MSR_TM_ACTIVE(target->thread.regs->msr))
+		return regset->n;
+
+	return 0;
+}
+
+static int tm_dscr_get(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      void *kbuf, void __user *ubuf)
+{
+	int ret;
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_dscr, 0, sizeof(u64));
+	return ret;
+}
+
+static int tm_dscr_set(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      const void *kbuf, const void __user *ubuf)
+{
+	int ret;
+
+	if (!cpu_has_feature(CPU_FTR_TM))
+		return -ENODEV;
+
+	if (!MSR_TM_ACTIVE(target->thread.regs->msr))
+		return -ENODATA;
+
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tm_dscr, 0, sizeof(u64));
+	return ret;
+}
 #endif	/* CONFIG_PPC_TRANSACTIONAL_MEM */
 
 /*
@@ -1565,6 +1710,9 @@ enum powerpc_regset {
 	REGSET_TM_CVMX,		/* TM checkpointed VMX registers */
 	REGSET_TM_CVSX,		/* TM checkpointed VSX registers */
 	REGSET_TM_SPR,		/* TM specific SPR registers */
+	REGSET_TM_CTAR,		/* TM checkpointed TAR register */
+	REGSET_TM_CPPR,		/* TM checkpointed PPR register */
+	REGSET_TM_CDSCR,	/* TM checkpointed DSCR register */
 #endif
 };
 
@@ -1626,6 +1774,21 @@ static const struct user_regset native_regsets[] = {
 		.size = sizeof(u64), .align = sizeof(u64),
 		.active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
 	},
+	[REGSET_TM_CTAR] = {
+		.core_note_type = NT_PPC_TM_CTAR, .n = 1,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
+	},
+	[REGSET_TM_CPPR] = {
+		.core_note_type = NT_PPC_TM_CPPR, .n = 1,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
+	},
+	[REGSET_TM_CDSCR] = {
+		.core_note_type = NT_PPC_TM_CDSCR, .n = 1,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
+	},
 #endif
 };
 
@@ -1878,6 +2041,21 @@ static const struct user_regset compat_regsets[] = {
 		.size = sizeof(u64), .align = sizeof(u64),
 		.active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
 	},
+	[REGSET_TM_CTAR] = {
+		.core_note_type = NT_PPC_TM_CTAR, .n = 1,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
+	},
+	[REGSET_TM_CPPR] = {
+		.core_note_type = NT_PPC_TM_CPPR, .n = 1,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
+	},
+	[REGSET_TM_CDSCR] = {
+		.core_note_type = NT_PPC_TM_CDSCR, .n = 1,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
+	},
 #endif
 };
 
-- 
2.1.0

[PATCH V10 13/28] powerpc, ptrace: Enable support for NT_PPPC_TAR, NT_PPC_PPR, NT_PPC_DSCR

[Anshuman Khandual]

This patch enables support for running TAR, PPR, DSCR registers
related ELF core notes NT_PPPC_TAR, NT_PPC_PPR, NT_PPC_DSCR based
ptrace requests through PTRACE_GETREGSET, PTRACE_SETREGSET calls.
This is achieved through adding three new register sets REGSET_TAR,
REGSET_PPR, REGSET_DSCR in powerpc corresponding to the ELF core
note sections added in this regad. It implements the get, set and
active functions for all these new register sets added.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/ptrace.c | 117 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 117 insertions(+)

diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index c3339a0..587f031 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -1689,6 +1689,78 @@ static int tm_dscr_set(struct task_struct *target,
 }
 #endif	/* CONFIG_PPC_TRANSACTIONAL_MEM */
 
+#ifdef CONFIG_PPC64
+static int ppr_get(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      void *kbuf, void __user *ubuf)
+{
+	int ret;
+
+	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				&target->thread.ppr, 0, sizeof(u64));
+	return ret;
+}
+
+static int ppr_set(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      const void *kbuf, const void __user *ubuf)
+{
+	int ret;
+
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				&target->thread.ppr, 0, sizeof(u64));
+	return ret;
+}
+
+static int dscr_get(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      void *kbuf, void __user *ubuf)
+{
+	int ret;
+
+	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				&target->thread.dscr, 0, sizeof(u64));
+	return ret;
+}
+static int dscr_set(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      const void *kbuf, const void __user *ubuf)
+{
+	int ret;
+
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				&target->thread.dscr, 0, sizeof(u64));
+	return ret;
+}
+#endif
+#ifdef CONFIG_PPC_BOOK3S_64
+static int tar_get(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      void *kbuf, void __user *ubuf)
+{
+	int ret;
+
+	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tar, 0, sizeof(u64));
+	return ret;
+}
+static int tar_set(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      const void *kbuf, const void __user *ubuf)
+{
+	int ret;
+
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+				&target->thread.tar, 0, sizeof(u64));
+	return ret;
+}
+#endif
 /*
  * These are our native regset flavors.
  */
@@ -1714,6 +1786,13 @@ enum powerpc_regset {
 	REGSET_TM_CPPR,		/* TM checkpointed PPR register */
 	REGSET_TM_CDSCR,	/* TM checkpointed DSCR register */
 #endif
+#ifdef CONFIG_PPC64
+	REGSET_PPR,		/* PPR register */
+	REGSET_DSCR,		/* DSCR register */
+#endif
+#ifdef CONFIG_PPC_BOOK3S_64
+	REGSET_TAR,		/* TAR register */
+#endif
 };
 
 static const struct user_regset native_regsets[] = {
@@ -1790,6 +1869,25 @@ static const struct user_regset native_regsets[] = {
 		.active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
 	},
 #endif
+#ifdef CONFIG_PPC64
+	[REGSET_PPR] = {
+		.core_note_type = NT_PPC_PPR, .n = 1,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.get = ppr_get, .set = ppr_set
+	},
+	[REGSET_DSCR] = {
+		.core_note_type = NT_PPC_DSCR, .n = 1,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.get = dscr_get, .set = dscr_set
+	},
+#endif
+#ifdef CONFIG_PPC_BOOK3S_64
+	[REGSET_TAR] = {
+		.core_note_type = NT_PPC_TAR, .n = 1,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.get = tar_get, .set = tar_set
+	},
+#endif
 };
 
 static const struct user_regset_view user_ppc_native_view = {
@@ -2057,6 +2155,25 @@ static const struct user_regset compat_regsets[] = {
 		.active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
 	},
 #endif
+#ifdef CONFIG_PPC64
+	[REGSET_PPR] = {
+		.core_note_type = NT_PPC_PPR, .n = 1,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.get = ppr_get, .set = ppr_set
+	},
+	[REGSET_DSCR] = {
+		.core_note_type = NT_PPC_DSCR, .n = 1,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.get = dscr_get, .set = dscr_set
+	},
+#endif
+#ifdef CONFIG_PPC_BOOK3S_64
+	[REGSET_TAR] = {
+		.core_note_type = NT_PPC_TAR, .n = 1,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.get = tar_get, .set = tar_set
+	},
+#endif
 };
 
 static const struct user_regset_view user_ppc_compat_view = {
-- 
2.1.0

[PATCH V10 14/28] powerpc, ptrace: Enable support for EBB registers

[Anshuman Khandual]

This patch enables support for EBB state registers related
ELF core note NT_PPC_EBB based ptrace requests through
PTRACE_GETREGSET, PTRACE_SETREGSET calls. This is achieved
through adding one new register sets REGSET_EBB in powerpc
corresponding to the ELF core note sections added in this
regard. It also implements the get, set and active functions
for this new register sets added.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 arch/powerpc/include/uapi/asm/elf.h |   3 +
 arch/powerpc/kernel/ptrace.c        | 147 ++++++++++++++++++++++++++++++++++++
 2 files changed, 150 insertions(+)

diff --git a/arch/powerpc/include/uapi/asm/elf.h b/arch/powerpc/include/uapi/asm/elf.h
index e703c64..64945d2 100644
--- a/arch/powerpc/include/uapi/asm/elf.h
+++ b/arch/powerpc/include/uapi/asm/elf.h
@@ -94,6 +94,9 @@
 #define ELF_NVMX	34	/* includes all vector registers */
 #define ELF_NVSX	32	/* includes all VSX registers */
 #define ELF_NTMSPRREG	3	/* include tfhar, tfiar, texasr */
+#define ELF_NEBB	8	/* includes ebbrr, ebbhr, bescr, siar,
+				 * sdar, sier, mmcr2, mmcr0
+				 */
 
 typedef unsigned long elf_greg_t64;
 typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 587f031..b063fc4 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -1760,6 +1760,142 @@ static int tar_set(struct task_struct *target,
 				&target->thread.tar, 0, sizeof(u64));
 	return ret;
 }
+
+static int ebb_active(struct task_struct *target,
+			 const struct user_regset *regset)
+{
+	if (!cpu_has_feature(CPU_FTR_ARCH_207S))
+		return -ENODEV;
+
+	if (target->thread.used_ebb)
+		return regset->n;
+
+	return 0;
+}
+
+static int ebb_get(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      void *kbuf, void __user *ubuf)
+{
+	int ret;
+
+	/* Build tests */
+	BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr));
+	BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr));
+	BUILD_BUG_ON(TSO(bescr) + sizeof(unsigned long) != TSO(siar));
+	BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar));
+	BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier));
+	BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2));
+	BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0));
+
+	if (!cpu_has_feature(CPU_FTR_ARCH_207S))
+		return -ENODEV;
+
+	if (!target->thread.used_ebb)
+		return -ENODATA;
+
+	ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+			&target->thread.ebbrr, 0, sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+			&target->thread.ebbhr, sizeof(unsigned long),
+			2 * sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+			&target->thread.bescr,
+			2 * sizeof(unsigned long), 3 * sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+			&target->thread.siar, 3 * sizeof(unsigned long),
+			4 * sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+			&target->thread.sdar, 4 * sizeof(unsigned long),
+			5 * sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+			&target->thread.sier, 5 * sizeof(unsigned long),
+			6 * sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+			&target->thread.mmcr2, 6 * sizeof(unsigned long),
+			7 * sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+			&target->thread.mmcr0, 7 * sizeof(unsigned long),
+			8 * sizeof(unsigned long));
+	return ret;
+}
+
+static int ebb_set(struct task_struct *target,
+		      const struct user_regset *regset,
+		      unsigned int pos, unsigned int count,
+		      const void *kbuf, const void __user *ubuf)
+{
+	int ret = 0;
+
+	/* Build tests */
+	BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr));
+	BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr));
+	BUILD_BUG_ON(TSO(bescr) + sizeof(unsigned long) != TSO(siar));
+	BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar));
+	BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier));
+	BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2));
+	BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0));
+
+	if (!cpu_has_feature(CPU_FTR_ARCH_207S))
+		return -ENODEV;
+
+	if (target->thread.used_ebb)
+		return -ENODATA;
+
+	ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+			&target->thread.ebbrr, 0, sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+			&target->thread.ebbhr, sizeof(unsigned long),
+			2 * sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+			&target->thread.bescr,
+			2 * sizeof(unsigned long), 3 * sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+			&target->thread.siar, 3 * sizeof(unsigned long),
+			4 * sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+			&target->thread.sdar, 4 * sizeof(unsigned long),
+			5 * sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+			&target->thread.sier, 5 * sizeof(unsigned long),
+			6 * sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+			&target->thread.mmcr2, 6 * sizeof(unsigned long),
+			7 * sizeof(unsigned long));
+
+	if (!ret)
+		ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+			&target->thread.mmcr0, 7 * sizeof(unsigned long),
+			8 * sizeof(unsigned long));
+	return ret;
+}
 #endif
 /*
  * These are our native regset flavors.
@@ -1792,6 +1928,7 @@ enum powerpc_regset {
 #endif
 #ifdef CONFIG_PPC_BOOK3S_64
 	REGSET_TAR,		/* TAR register */
+	REGSET_EBB,		/* EBB registers */
 #endif
 };
 
@@ -1887,6 +2024,11 @@ static const struct user_regset native_regsets[] = {
 		.size = sizeof(u64), .align = sizeof(u64),
 		.get = tar_get, .set = tar_set
 	},
+	[REGSET_EBB] = {
+		.core_note_type = NT_PPC_EBB, .n = ELF_NEBB,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.active = ebb_active, .get = ebb_get, .set = ebb_set
+	},
 #endif
 };
 
@@ -2173,6 +2315,11 @@ static const struct user_regset compat_regsets[] = {
 		.size = sizeof(u64), .align = sizeof(u64),
 		.get = tar_get, .set = tar_set
 	},
+	[REGSET_EBB] = {
+		.core_note_type = NT_PPC_EBB, .n = ELF_NEBB,
+		.size = sizeof(u64), .align = sizeof(u64),
+		.active = ebb_active, .get = ebb_get, .set = ebb_set
+	},
 #endif
 };
 
-- 
2.1.0

[PATCH V10 15/28] selftests, powerpc: Move 'reg.h' file outside of 'ebb' sub directory

[Anshuman Khandual]

This patch moves 'reg.h' file from pmu 'ebb' sub directory
to the powerpc root directory to make all the register
definitions and instructions available for tests present
in other subsystems.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/pmu/ebb/ebb.c      |  2 +-
 tools/testing/selftests/powerpc/pmu/ebb/ebb.h      |  2 +-
 .../selftests/powerpc/pmu/ebb/ebb_handler.S        |  2 +-
 tools/testing/selftests/powerpc/pmu/ebb/reg.h      | 49 ----------------------
 .../selftests/powerpc/pmu/ebb/reg_access_test.c    |  2 +-
 tools/testing/selftests/powerpc/reg.h              | 49 ++++++++++++++++++++++
 6 files changed, 53 insertions(+), 53 deletions(-)
 delete mode 100644 tools/testing/selftests/powerpc/pmu/ebb/reg.h
 create mode 100644 tools/testing/selftests/powerpc/reg.h

diff --git a/tools/testing/selftests/powerpc/pmu/ebb/ebb.c b/tools/testing/selftests/powerpc/pmu/ebb/ebb.c
index e67452f..346749b 100644
--- a/tools/testing/selftests/powerpc/pmu/ebb/ebb.c
+++ b/tools/testing/selftests/powerpc/pmu/ebb/ebb.c
@@ -15,7 +15,7 @@
 #include <sys/ioctl.h>
 
 #include "trace.h"
-#include "reg.h"
+#include "../../reg.h"
 #include "ebb.h"
 
 
diff --git a/tools/testing/selftests/powerpc/pmu/ebb/ebb.h b/tools/testing/selftests/powerpc/pmu/ebb/ebb.h
index f87e761..db7103d 100644
--- a/tools/testing/selftests/powerpc/pmu/ebb/ebb.h
+++ b/tools/testing/selftests/powerpc/pmu/ebb/ebb.h
@@ -9,7 +9,7 @@
 #include "../event.h"
 #include "../lib.h"
 #include "trace.h"
-#include "reg.h"
+#include "../../reg.h"
 
 #define PMC_INDEX(pmc)	((pmc)-1)
 
diff --git a/tools/testing/selftests/powerpc/pmu/ebb/ebb_handler.S b/tools/testing/selftests/powerpc/pmu/ebb/ebb_handler.S
index 14274ea..42cd367 100644
--- a/tools/testing/selftests/powerpc/pmu/ebb/ebb_handler.S
+++ b/tools/testing/selftests/powerpc/pmu/ebb/ebb_handler.S
@@ -4,7 +4,7 @@
  */
 
 #include <ppc-asm.h>
-#include "reg.h"
+#include "../../reg.h"
 
 
 /* ppc-asm.h defines most of the reg aliases, but not r1/r2. */
diff --git a/tools/testing/selftests/powerpc/pmu/ebb/reg.h b/tools/testing/selftests/powerpc/pmu/ebb/reg.h
deleted file mode 100644
index 5921b0d..0000000
--- a/tools/testing/selftests/powerpc/pmu/ebb/reg.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright 2014, Michael Ellerman, IBM Corp.
- * Licensed under GPLv2.
- */
-
-#ifndef _SELFTESTS_POWERPC_REG_H
-#define _SELFTESTS_POWERPC_REG_H
-
-#define __stringify_1(x)        #x
-#define __stringify(x)          __stringify_1(x)
-
-#define mfspr(rn)       ({unsigned long rval; \
-                         asm volatile("mfspr %0," __stringify(rn) \
-                                 : "=r" (rval)); rval; })
-#define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : \
-                                    : "r" ((unsigned long)(v)) \
-                                    : "memory")
-
-#define mb()		asm volatile("sync" : : : "memory");
-
-#define SPRN_MMCR2     769
-#define SPRN_MMCRA     770
-#define SPRN_MMCR0     779
-#define   MMCR0_PMAO   0x00000080
-#define   MMCR0_PMAE   0x04000000
-#define   MMCR0_FC     0x80000000
-#define SPRN_EBBHR     804
-#define SPRN_EBBRR     805
-#define SPRN_BESCR     806     /* Branch event status & control register */
-#define SPRN_BESCRS    800     /* Branch event status & control set (1 bits set to 1) */
-#define SPRN_BESCRSU   801     /* Branch event status & control set upper */
-#define SPRN_BESCRR    802     /* Branch event status & control REset (1 bits set to 0) */
-#define SPRN_BESCRRU   803     /* Branch event status & control REset upper */
-
-#define BESCR_PMEO     0x1     /* PMU Event-based exception Occurred */
-#define BESCR_PME      (0x1ul << 32) /* PMU Event-based exception Enable */
-
-#define SPRN_PMC1      771
-#define SPRN_PMC2      772
-#define SPRN_PMC3      773
-#define SPRN_PMC4      774
-#define SPRN_PMC5      775
-#define SPRN_PMC6      776
-
-#define SPRN_SIAR      780
-#define SPRN_SDAR      781
-#define SPRN_SIER      768
-
-#endif /* _SELFTESTS_POWERPC_REG_H */
diff --git a/tools/testing/selftests/powerpc/pmu/ebb/reg_access_test.c b/tools/testing/selftests/powerpc/pmu/ebb/reg_access_test.c
index 5b1188f..b209c6b 100644
--- a/tools/testing/selftests/powerpc/pmu/ebb/reg_access_test.c
+++ b/tools/testing/selftests/powerpc/pmu/ebb/reg_access_test.c
@@ -7,7 +7,7 @@
 #include <stdlib.h>
 
 #include "ebb.h"
-#include "reg.h"
+#include "../../reg.h"
 
 
 /*
diff --git a/tools/testing/selftests/powerpc/reg.h b/tools/testing/selftests/powerpc/reg.h
new file mode 100644
index 0000000..5921b0d
--- /dev/null
+++ b/tools/testing/selftests/powerpc/reg.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2014, Michael Ellerman, IBM Corp.
+ * Licensed under GPLv2.
+ */
+
+#ifndef _SELFTESTS_POWERPC_REG_H
+#define _SELFTESTS_POWERPC_REG_H
+
+#define __stringify_1(x)        #x
+#define __stringify(x)          __stringify_1(x)
+
+#define mfspr(rn)       ({unsigned long rval; \
+                         asm volatile("mfspr %0," __stringify(rn) \
+                                 : "=r" (rval)); rval; })
+#define mtspr(rn, v)    asm volatile("mtspr " __stringify(rn) ",%0" : \
+                                    : "r" ((unsigned long)(v)) \
+                                    : "memory")
+
+#define mb()		asm volatile("sync" : : : "memory");
+
+#define SPRN_MMCR2     769
+#define SPRN_MMCRA     770
+#define SPRN_MMCR0     779
+#define   MMCR0_PMAO   0x00000080
+#define   MMCR0_PMAE   0x04000000
+#define   MMCR0_FC     0x80000000
+#define SPRN_EBBHR     804
+#define SPRN_EBBRR     805
+#define SPRN_BESCR     806     /* Branch event status & control register */
+#define SPRN_BESCRS    800     /* Branch event status & control set (1 bits set to 1) */
+#define SPRN_BESCRSU   801     /* Branch event status & control set upper */
+#define SPRN_BESCRR    802     /* Branch event status & control REset (1 bits set to 0) */
+#define SPRN_BESCRRU   803     /* Branch event status & control REset upper */
+
+#define BESCR_PMEO     0x1     /* PMU Event-based exception Occurred */
+#define BESCR_PME      (0x1ul << 32) /* PMU Event-based exception Enable */
+
+#define SPRN_PMC1      771
+#define SPRN_PMC2      772
+#define SPRN_PMC3      773
+#define SPRN_PMC4      774
+#define SPRN_PMC5      775
+#define SPRN_PMC6      776
+
+#define SPRN_SIAR      780
+#define SPRN_SDAR      781
+#define SPRN_SIER      768
+
+#endif /* _SELFTESTS_POWERPC_REG_H */
-- 
2.1.0

[PATCH V10 16/28] selftests, powerpc: Add more SPR numbers, TM & VMX instructions to 'reg.h'

[Anshuman Khandual]

This patch adds SPR number for TAR, PPR, DSCR special
purpose registers. It also adds TM, VSX, VMX related
instructions which will then be used by patches later
in the series.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/reg.h | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/tools/testing/selftests/powerpc/reg.h b/tools/testing/selftests/powerpc/reg.h
index 5921b0d..76f170d 100644
--- a/tools/testing/selftests/powerpc/reg.h
+++ b/tools/testing/selftests/powerpc/reg.h
@@ -18,6 +18,19 @@
 
 #define mb()		asm volatile("sync" : : : "memory");
 
+/* Vector Instructions */
+#define VSX_XX1(xs, ra, rb)	(((xs) & 0x1f) << 21 | ((ra) << 16) |  \
+				 ((rb) << 11) | (((xs) >> 5)))
+#define STXVD2X(xs, ra, rb)	.long (0x7c000798 | VSX_XX1((xs), (ra), (rb)))
+#define LXVD2X(xs, ra, rb)	.long (0x7c000698 | VSX_XX1((xs), (ra), (rb)))
+
+/* TM instructions */
+#define TBEGIN		".long 0x7C00051D;"
+#define TABORT		".long 0x7C00071D;"
+#define TEND		".long 0x7C00055D;"
+#define TSUSPEND	".long 0x7C0005DD;"
+#define TRESUME		".long 0x7C2005DD;"
+
 #define SPRN_MMCR2     769
 #define SPRN_MMCRA     770
 #define SPRN_MMCR0     779
@@ -46,4 +59,12 @@
 #define SPRN_SDAR      781
 #define SPRN_SIER      768
 
+#define SPRN_DSCR      3	/* Data Stream Control Register */
+#define SPRN_TAR       815	/* Target Address Register */
+#define SPRN_PPR       896	/* Program Priority Register */
+
+#define SPRN_TFHAR	0x80	/* TM Failure Handle Register */
+#define SPRN_TFIAR	0x81	/* TM Failure Instruction Address Register */
+#define SPRN_TEXASR	0x82	/* TM Exception and Status Register */
+
 #endif /* _SELFTESTS_POWERPC_REG_H */
-- 
2.1.0

[PATCH V10 17/28] selftests, powerpc: Add ptrace tests for EBB

[Anshuman Khandual]

This patch adds ptrace interface test for EBB specific
registers. This also adds some generic ptrace interface
based helper functions to be used by other patches later
on in the series.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/Makefile           |   3 +-
 tools/testing/selftests/powerpc/ptrace/Makefile    |   7 +
 .../testing/selftests/powerpc/ptrace/ptrace-ebb.c  | 150 ++++++++++++++
 .../testing/selftests/powerpc/ptrace/ptrace-ebb.h  | 103 ++++++++++
 tools/testing/selftests/powerpc/ptrace/ptrace.h    | 225 +++++++++++++++++++++
 5 files changed, 487 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/powerpc/ptrace/Makefile
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-ebb.h
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace.h

diff --git a/tools/testing/selftests/powerpc/Makefile b/tools/testing/selftests/powerpc/Makefile
index 0c2706b..5b3c62c 100644
--- a/tools/testing/selftests/powerpc/Makefile
+++ b/tools/testing/selftests/powerpc/Makefile
@@ -22,7 +22,8 @@ SUB_DIRS = benchmarks 		\
 	   switch_endian	\
 	   syscalls		\
 	   tm			\
-	   vphn
+	   vphn			\
+	   ptrace
 
 endif
 
diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
new file mode 100644
index 0000000..8666ac0
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/Makefile
@@ -0,0 +1,7 @@
+TEST_PROGS := ptrace-ebb
+all: $(TEST_PROGS)
+
+$(TEST_PROGS): ../harness.c ptrace.S ../utils.c
+ptrace-ebb: ../pmu/event.c ../pmu/lib.c ../pmu/ebb/ebb_handler.S ../pmu/ebb/busy_loop.S
+clean:
+	rm -f $(TEST_PROGS) *.o
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c b/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c
new file mode 100644
index 0000000..e1ca608
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c
@@ -0,0 +1,150 @@
+/*
+ * Ptrace interface test for EBB
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include "../pmu/ebb/ebb.h"
+#include "ptrace.h"
+#include "ptrace-ebb.h"
+
+void ebb(void)
+{
+	struct event event;
+
+	event_init_named(&event, 0x1001e, "cycles");
+	event.attr.config |= (1ull << 63);
+        event.attr.exclusive = 1;
+        event.attr.pinned = 1;
+	event.attr.exclude_kernel = 1;
+	event.attr.exclude_hv = 1;
+	event.attr.exclude_idle = 1;
+
+	if (event_open(&event)) {
+		perror("event_open() failed");
+		exit(1);
+	}
+
+	setup_ebb_handler(standard_ebb_callee);
+	mtspr(SPRN_BESCR, 0x8000000100000000ull);
+
+	mb();
+
+	if (ebb_event_enable(&event)) {
+		perror("ebb_event_handler() failed");
+		exit(1);
+	}
+
+	mtspr(SPRN_PMC1, pmc_sample_period(SAMPLE_PERIOD));
+	while(1)
+		core_busy_loop();
+	exit(0);
+}
+
+int validate_ebb(struct ebb_regs *regs)
+{
+	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+	struct opd *opd = (struct opd *) ebb_handler;
+	#endif
+
+	printf("EBBRR: %lx\n", regs->ebbrr);
+	printf("EBBHR: %lx\n", regs->ebbhr);
+	printf("BESCR: %lx\n", regs->bescr);
+	printf("SIAR:  %lx\n", regs->siar);
+	printf("SDAR:  %lx\n", regs->sdar);
+	printf("SIER:  %lx\n", regs->sier);
+	printf("MMCR2: %lx\n", regs->mmcr2);
+	printf("MMCR0: %lx\n", regs->mmcr0);
+
+	/* Validate EBBHR */
+	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+	if (regs->ebbhr != opd->entry)
+		return TEST_FAIL;
+	#else
+	if (regs->ebbhr != (unsigned long) ebb_handler)
+		return TEST_FAIL;
+	#endif
+
+	/* Validate SIER */
+	if (regs->sier != SIER_EXP)
+		return TEST_FAIL;
+
+	/* Validate MMCR2 */
+	if (regs->mmcr2 != MMCR2_EXP)
+		return TEST_FAIL;
+
+	/* Validate MMCR0 */
+	if (regs->mmcr0 != MMCR0_EXP)
+		return TEST_FAIL;
+
+	return TEST_PASS;
+}
+
+int trace_ebb(pid_t child)
+{
+	struct ebb_regs regs;
+	int ret;
+
+	sleep(2);
+	ret = start_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_ebb_registers(child, &regs);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_ebb(&regs);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = stop_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	return TEST_PASS;
+}
+
+int ptrace_ebb(void)
+{
+	pid_t pid;
+	int ret, status;
+
+	pid = fork();
+	if (pid < 0) {
+		perror("fork() failed");
+		return TEST_FAIL;
+	}
+
+	if (pid == 0)
+		ebb();
+
+	if (pid) {
+		ret = trace_ebb(pid);
+		if (ret)
+			return TEST_FAIL;
+
+		kill(pid, SIGKILL);
+		ret = wait(&status);
+		if (ret != pid) {
+			printf("Child's exit status not captured\n");
+			return TEST_FAIL;
+		}
+
+		if (WIFEXITED(status)) {
+			if(WEXITSTATUS(status))
+				return TEST_FAIL;
+		}
+		return TEST_PASS;
+	}
+	return TEST_PASS;
+}
+
+int main(int argc, char *argv[])
+{
+	return test_harness(ptrace_ebb, "ptrace_ebb");
+}
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.h b/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.h
new file mode 100644
index 0000000..9b38edc
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.h
@@ -0,0 +1,103 @@
+/*
+ * Inspired mostly from the EBB selftest
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#define SAMPLE_PERIOD 100	/* EBB event sample persiod */
+
+/* Standard expected values */
+#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+#define MMCR0_EXP	0x8000008000000001
+#else
+#define MMCR0_EXP	0x180000080
+#endif
+
+#define MMCR2_EXP	0
+#define SIER_EXP	0x2000000
+
+struct opd
+{
+	u64 entry;
+	u64 toc;
+};
+
+void (*ebb_user_func)(void);
+extern void ebb_handler(void);	/* Defined in ebb_handle.S */
+
+void ebb_hook(void)		/* Called by ebb_handler */
+{
+        if (ebb_user_func)
+                ebb_user_func();
+}
+
+void setup_ebb_handler(void (*callee)(void))
+{
+        u64 entry;
+
+#if defined(_CALL_ELF) && _CALL_ELF == 2
+        entry = (u64)ebb_handler;
+#else
+	struct opd *opd;
+
+        opd = (struct opd *)ebb_handler;
+        entry = opd->entry;
+#endif
+        ebb_user_func = callee;
+
+        /* Ensure ebb_user_func is set before we set the handler */
+        mb();
+        mtspr(SPRN_EBBHR, entry);
+
+        /* Make sure the handler is set before we return */
+        mb();
+}
+
+void reset_ebb_with_clear_mask(unsigned long mmcr0_clear_mask)
+{
+        u64 val;
+
+        /* 2) clear MMCR0[PMAO] - docs say BESCR[PMEO] should do this */
+        /* 3) set MMCR0[PMAE]   - docs say BESCR[PME] should do this */
+        val = mfspr(SPRN_MMCR0);
+        mtspr(SPRN_MMCR0, (val & ~mmcr0_clear_mask) | MMCR0_PMAE);
+
+        /* 4) clear BESCR[PMEO] */
+        mtspr(SPRN_BESCRR, BESCR_PMEO);
+
+        /* 5) set BESCR[PME] */
+        mtspr(SPRN_BESCRS, BESCR_PME);
+
+        /* 6) rfebb 1 - done in our caller */
+}
+
+void standard_ebb_callee(void)
+{
+	u64 val;
+
+	val = mfspr(SPRN_BESCR);
+        if (!(val & BESCR_PMEO))
+		printf("Spurious interrupt\n");
+
+	mtspr(SPRN_PMC1, pmc_sample_period(SAMPLE_PERIOD));
+	reset_ebb_with_clear_mask(MMCR0_PMAO | MMCR0_FC);
+}
+
+int ebb_event_enable(struct event *e)
+{
+	int rc;
+
+	mb();
+
+        rc = ioctl(e->fd, PERF_EVENT_IOC_ENABLE);
+        if (rc)
+                return rc;
+        rc = event_read(e);
+
+        mb();
+        return rc;
+}
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace.h b/tools/testing/selftests/powerpc/ptrace/ptrace.h
new file mode 100644
index 0000000..44256d2
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace.h
@@ -0,0 +1,225 @@
+/*
+ * Ptrace interface test helper functions
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <inttypes.h>
+#include <unistd.h>
+#include <stdlib.h>
+#include <string.h>
+#include <malloc.h>
+#include <errno.h>
+#include <time.h>
+#include <sys/ptrace.h>
+#include <sys/ioctl.h>
+#include <sys/uio.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+#include <sys/signal.h>
+#include <sys/ipc.h>
+#include <sys/shm.h>
+#include <sys/user.h>
+#include <linux/elf.h>
+#include <linux/types.h>
+#include <linux/auxvec.h>
+#include "../reg.h"
+#include "utils.h"
+
+/* ELF core note sections */
+#define NT_PPC_TAR	0x103		/* Target Address Register */
+#define NT_PPC_PPR	0x104		/* Program Priority Register */
+#define NT_PPC_DSCR	0x105		/* Data Stream Control Register */
+#define NT_PPC_EBB	0x106		/* Event Based Branch Registers */
+#define NT_PPC_TM_CGPR	0x107		/* TM checkpointed GPR Registers */
+#define NT_PPC_TM_CFPR	0x108		/* TM checkpointed FPR Registers */
+#define NT_PPC_TM_CVMX	0x109		/* TM checkpointed VMX Registers */
+#define NT_PPC_TM_CVSX	0x10a		/* TM checkpointed VSX Registers */
+#define NT_PPC_TM_SPR	0x10b		/* TM Special Purpose Registers */
+#define NT_PPC_TM_CTAR	0x10c		/* TM checkpointed Target Address Register */
+#define NT_PPC_TM_CPPR	0x10d		/* TM checkpointed Program Priority Register */
+#define NT_PPC_TM_CDSCR	0x10e		/* TM checkpointed Data Stream Control Register */
+
+/* TEXASR register bits */
+#define TEXASR_FC	0xFE00000000000000
+#define TEXASR_FP	0x0100000000000000
+#define TEXASR_DA	0x0080000000000000
+#define TEXASR_NO	0x0040000000000000
+#define TEXASR_FO	0x0020000000000000
+#define TEXASR_SIC	0x0010000000000000
+#define TEXASR_NTC	0x0008000000000000
+#define TEXASR_TC	0x0004000000000000
+#define TEXASR_TIC	0x0002000000000000
+#define TEXASR_IC	0x0001000000000000
+#define TEXASR_IFC	0x0000800000000000
+#define TEXASR_ABT	0x0000000100000000
+#define TEXASR_SPD	0x0000000080000000
+#define TEXASR_HV	0x0000000020000000
+#define TEXASR_PR	0x0000000010000000
+#define TEXASR_FS	0x0000000008000000
+#define TEXASR_TE	0x0000000004000000
+#define TEXASR_ROT	0x0000000002000000
+
+#define TEST_PASS 0
+#define TEST_FAIL 1
+
+struct ebb_regs {
+	unsigned long	ebbrr;
+	unsigned long	ebbhr;
+	unsigned long	bescr;
+	unsigned long	siar;
+	unsigned long	sdar;
+	unsigned long	sier;
+	unsigned long	mmcr2;
+	unsigned long	mmcr0;
+};
+
+struct fpr_regs {
+	unsigned long fpr[32];
+	unsigned long fpscr;
+};
+
+
+/* Basic ptrace operations */
+int start_trace(pid_t child)
+{
+	int ret;
+
+	ret = ptrace(PTRACE_ATTACH, child, NULL, NULL);
+	if (ret) {
+		perror("ptrace(PTRACE_ATTACH) failed");
+		return TEST_FAIL;
+	}
+	ret = waitpid(child, NULL, 0);
+	if (ret != child) {
+		perror("waitpid() failed");
+		return TEST_FAIL;
+	}
+	return TEST_PASS;
+}
+
+int stop_trace(pid_t child)
+{
+	int ret;
+
+	ret = ptrace(PTRACE_DETACH, child, NULL, NULL);
+	if (ret) {
+		perror("ptrace(PTRACE_DETACH) failed");
+		return TEST_FAIL;
+	}
+	return TEST_PASS;
+}
+
+int cont_trace(pid_t child)
+{
+	int ret;
+
+	ret = ptrace(PTRACE_CONT, child, NULL, NULL);
+	if (ret) {
+		perror("ptrace(PTRACE_CONT) failed");
+		return TEST_FAIL;
+	}
+	return TEST_PASS;
+}
+
+/* EBB */
+int show_ebb_registers(pid_t child, struct ebb_regs *regs)
+{
+	struct ebb_regs *ebb;
+	struct iovec iov;
+	int ret;
+
+	ebb = malloc(sizeof(struct ebb_regs));
+	if (!ebb) {
+		perror("malloc() failed");
+		return TEST_FAIL;
+	}
+
+	iov.iov_base = (struct ebb_regs *) ebb;
+	iov.iov_len = sizeof(struct ebb_regs);
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_EBB, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		goto fail;
+	}
+
+	if (regs)
+		memcpy(regs, ebb, sizeof(struct ebb_regs));
+
+	free(ebb);
+	return TEST_PASS;
+fail:
+	free(ebb);
+	return TEST_FAIL;
+}
+
+/* Analyse TEXASR after TM failure */
+inline unsigned long get_tfiar(void)
+{
+	unsigned long ret;
+
+	asm volatile("mfspr %0,%1" : "=r" (ret): "i" (SPRN_TFIAR));
+	return ret;
+}
+
+void analyse_texasr(unsigned long texasr)
+{
+	printf("TEXASR: %16lx\t", texasr);
+
+	if (texasr & TEXASR_FP)
+		printf("TEXASR_FP  ");
+
+	if (texasr & TEXASR_DA)
+		printf("TEXASR_DA  ");
+
+	if (texasr & TEXASR_NO)
+		printf("TEXASR_NO  ");
+
+	if (texasr & TEXASR_FO)
+		printf("TEXASR_FO  ");
+
+	if (texasr & TEXASR_SIC)
+		printf("TEXASR_SIC  ");
+
+	if (texasr & TEXASR_NTC)
+		printf("TEXASR_NTC  ");
+
+	if (texasr & TEXASR_TC)
+		printf("TEXASR_TC  ");
+
+	if (texasr & TEXASR_TIC)
+		printf("TEXASR_TIC  ");
+
+	if (texasr & TEXASR_IC)
+		printf("TEXASR_IC  ");
+
+	if (texasr & TEXASR_IFC)
+		printf("TEXASR_IFC  ");
+
+	if (texasr & TEXASR_ABT)
+		printf("TEXASR_ABT  ");
+
+	if (texasr & TEXASR_SPD)
+		printf("TEXASR_SPD  ");
+
+	if (texasr & TEXASR_HV)
+		printf("TEXASR_HV  ");
+
+	if (texasr & TEXASR_PR)
+		printf("TEXASR_PR  ");
+
+	if (texasr & TEXASR_FS)
+		printf("TEXASR_FS  ");
+
+	if (texasr & TEXASR_TE)
+		printf("TEXASR_TE  ");
+
+	if (texasr & TEXASR_ROT)
+		printf("TEXASR_ROT  ");
+
+	printf("TFIAR :%lx\n", get_tfiar());
+}
-- 
2.1.0

[PATCH V10 18/28] selftests, powerpc: Add ptrace tests for GPR/FPR registers

[Anshuman Khandual]

This patch adds ptrace interface test for GPR/FPR registers.
This adds ptrace interface based helper functions related to
GPR/FPR access and some assembly helper functions related to
GPR/FPR registers.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/ptrace/Makefile    |   3 +-
 .../testing/selftests/powerpc/ptrace/ptrace-gpr.c  | 191 +++++++++++++++++++
 .../testing/selftests/powerpc/ptrace/ptrace-gpr.h  |  73 ++++++++
 tools/testing/selftests/powerpc/ptrace/ptrace.S    | 131 +++++++++++++
 tools/testing/selftests/powerpc/ptrace/ptrace.h    | 208 +++++++++++++++++++++
 5 files changed, 605 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace.S

diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
index 8666ac0..f5f62d0 100644
--- a/tools/testing/selftests/powerpc/ptrace/Makefile
+++ b/tools/testing/selftests/powerpc/ptrace/Makefile
@@ -1,4 +1,5 @@
-TEST_PROGS := ptrace-ebb
+TEST_PROGS := ptrace-ebb ptrace-gpr
+
 all: $(TEST_PROGS)
 
 $(TEST_PROGS): ../harness.c ptrace.S ../utils.c
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c b/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c
new file mode 100644
index 0000000..f84f0e4
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c
@@ -0,0 +1,191 @@
+/*
+ * Ptrace test for GPR/FPR registers
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include "ptrace.h"
+#include "ptrace-gpr.h"
+
+/* Tracer and Tracee Shared Data */
+int shm_id;
+volatile int *cptr, *pptr;
+
+extern void store_gpr(unsigned long *addr);
+extern void store_fpr(float *addr);
+
+float a = FPR_1;
+float b = FPR_2;
+float c = FPR_3;
+
+void gpr(void)
+{
+	unsigned long gpr_buf[18];
+	float fpr_buf[32];
+
+	cptr = (int *)shmat(shm_id, NULL, 0);
+
+	asm __volatile__(
+		"li 14, %[gpr_1];"
+		"li 15, %[gpr_1];"
+		"li 16, %[gpr_1];"
+		"li 17, %[gpr_1];"
+		"li 18, %[gpr_1];"
+		"li 19, %[gpr_1];"
+		"li 20, %[gpr_1];"
+		"li 21, %[gpr_1];"
+		"li 22, %[gpr_1];"
+		"li 23, %[gpr_1];"
+		"li 24, %[gpr_1];"
+		"li 25, %[gpr_1];"
+		"li 26, %[gpr_1];"
+		"li 27, %[gpr_1];"
+		"li 28, %[gpr_1];"
+		"li 29, %[gpr_1];"
+		"li 30, %[gpr_1];"
+		"li 31, %[gpr_1];"
+
+		"lfs 0, 0(%[flt_1]);"
+		"lfs 1, 0(%[flt_1]);"
+		"lfs 2, 0(%[flt_1]);"
+		"lfs 3, 0(%[flt_1]);"
+		"lfs 4, 0(%[flt_1]);"
+		"lfs 5, 0(%[flt_1]);"
+		"lfs 6, 0(%[flt_1]);"
+		"lfs 7, 0(%[flt_1]);"
+		"lfs 8, 0(%[flt_1]);"
+		"lfs 9, 0(%[flt_1]);"
+		"lfs 10, 0(%[flt_1]);"
+		"lfs 11, 0(%[flt_1]);"
+		"lfs 12, 0(%[flt_1]);"
+		"lfs 13, 0(%[flt_1]);"
+		"lfs 14, 0(%[flt_1]);"
+		"lfs 15, 0(%[flt_1]);"
+		"lfs 16, 0(%[flt_1]);"
+		"lfs 17, 0(%[flt_1]);"
+		"lfs 18, 0(%[flt_1]);"
+		"lfs 19, 0(%[flt_1]);"
+		"lfs 20, 0(%[flt_1]);"
+		"lfs 21, 0(%[flt_1]);"
+		"lfs 22, 0(%[flt_1]);"
+		"lfs 23, 0(%[flt_1]);"
+		"lfs 24, 0(%[flt_1]);"
+		"lfs 25, 0(%[flt_1]);"
+		"lfs 26, 0(%[flt_1]);"
+		"lfs 27, 0(%[flt_1]);"
+		"lfs 28, 0(%[flt_1]);"
+		"lfs 29, 0(%[flt_1]);"
+		"lfs 30, 0(%[flt_1]);"
+		"lfs 31, 0(%[flt_1]);"
+
+		:
+		:[gpr_1]"i"(GPR_1), [flt_1] "r" (&a)
+		: "memory", "r6", "r7", "r8", "r9", "r10",
+		"r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20",
+		"r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
+		);
+
+	while(!cptr[0]);
+
+	store_gpr(gpr_buf);
+	store_fpr(fpr_buf);
+
+	if (validate_gpr(gpr_buf, GPR_3))
+		exit(1);
+
+	if (validate_fpr_float(fpr_buf, c))
+		exit(1);
+
+	exit(0);
+}
+
+int trace_gpr(pid_t child)
+{
+	unsigned long gpr[18];
+	unsigned long fpr[32];
+	int ret;
+
+	sleep(1);
+	ret = start_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_gpr(child, gpr);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_gpr(gpr, GPR_1);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_fpr(child, fpr);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_fpr(fpr, FPR_1_REP);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = write_gpr(child, GPR_3);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = write_fpr(child, FPR_3_REP);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = stop_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	return TEST_PASS;
+}
+
+int ptrace_gpr(void)
+{
+	pid_t pid;
+	int ret, status;
+
+	shm_id = shmget(IPC_PRIVATE, sizeof(int) * 1, 0777|IPC_CREAT);
+	pid = fork();
+	if (pid < 0) {
+		perror("fork() failed");
+		return TEST_FAIL;
+	}
+	if (pid == 0)
+		gpr();
+
+	if (pid) {
+		pptr = (int *)shmat(shm_id, NULL, 0);
+		ret = trace_gpr(pid);
+		if (ret) {
+			kill(pid, SIGTERM);
+			return TEST_FAIL;
+		}
+
+		pptr[0] = 1;
+		shmdt((void *)pptr);
+
+		ret = wait(&status);
+		if (ret != pid) {
+			printf("Child's exit status not captured\n");
+			return TEST_FAIL;
+		}
+
+		if (WIFEXITED(status)) {
+			if(WEXITSTATUS(status))
+				return TEST_FAIL;
+		}
+		return TEST_PASS;
+	}
+	return TEST_PASS;
+}
+
+int main(int argc, char *argv[])
+{
+	return test_harness(ptrace_gpr, "ptrace_gpr");
+}
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h b/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h
new file mode 100644
index 0000000..6d49f1f
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#define GPR_1	1
+#define GPR_2	2
+#define GPR_3	3
+#define GPR_4	4
+
+#define FPR_1	0.001
+#define FPR_2	0.002
+#define FPR_3	0.003
+#define FPR_4	0.004
+
+#define FPR_1_REP 0x3f50624de0000000
+#define FPR_2_REP 0x3f60624de0000000
+#define FPR_3_REP 0x3f689374c0000000
+#define FPR_4_REP 0x3f70624de0000000
+
+/* Buffer must have 18 elements */
+int validate_gpr(unsigned long *gpr, unsigned long val)
+{
+	int i, found = 1;
+
+	for (i = 0; i < 18; i++) {
+		if (gpr[i] != val) {
+			printf("GPR[%d]: %lx Expected: %lx\n", i+14, gpr[i], val);
+			found = 0;
+		}
+	}
+
+	if (!found)
+		return TEST_FAIL;
+	return TEST_PASS;
+}
+
+/* Buffer must have 32 elements */
+int validate_fpr(unsigned long *fpr, unsigned long val)
+{
+	int i, found = 1;
+
+	for (i = 0; i < 32; i++) {
+		if (fpr[i] != val) {
+			printf("FPR[%d]: %lx Expected: %lx\n", i, fpr[i], val);
+			found = 0;
+		}
+	}
+
+	if (!found)
+		return TEST_FAIL;
+	return TEST_PASS;
+}
+
+/* Buffer must have 32 elements */
+int validate_fpr_float(float *fpr, float val)
+{
+	int i, found = 1;
+
+	for (i = 0; i < 32; i++) {
+		if (fpr[i] != val) {
+			printf("FPR[%d]: %f Expected: %f\n", i, fpr[i], val);
+			found = 0;
+		}
+	}
+
+	if (!found)
+		return TEST_FAIL;
+	return TEST_PASS;
+}
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace.S b/tools/testing/selftests/powerpc/ptrace/ptrace.S
new file mode 100644
index 0000000..193beea
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace.S
@@ -0,0 +1,131 @@
+/*
+ * Ptrace interface test helper assembly functions
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <ppc-asm.h>
+#include "../reg.h"
+
+
+/* Non volatile GPR - unsigned long buf[18] */
+FUNC_START(load_gpr)
+	ld	14, 0*8(3)
+	ld	15, 1*8(3)
+	ld	16, 2*8(3)
+	ld	17, 3*8(3)
+	ld	18, 4*8(3)
+	ld	19, 5*8(3)
+	ld	20, 6*8(3)
+	ld	21, 7*8(3)
+	ld	22, 8*8(3)
+	ld	23, 9*8(3)
+	ld	24, 10*8(3)
+	ld	25, 11*8(3)
+	ld	26, 12*8(3)
+	ld	27, 13*8(3)
+	ld	28, 14*8(3)
+	ld	29, 15*8(3)
+	ld	30, 16*8(3)
+	ld	31, 17*8(3)
+	blr
+FUNC_END(load_gpr)
+
+FUNC_START(store_gpr)
+	std	14, 0*8(3)
+	std	15, 1*8(3)
+	std	16, 2*8(3)
+	std	17, 3*8(3)
+	std	18, 4*8(3)
+	std	19, 5*8(3)
+	std	20, 6*8(3)
+	std	21, 7*8(3)
+	std	22, 8*8(3)
+	std	23, 9*8(3)
+	std	24, 10*8(3)
+	std	25, 11*8(3)
+	std	26, 12*8(3)
+	std	27, 13*8(3)
+	std	28, 14*8(3)
+	std	29, 15*8(3)
+	std	30, 16*8(3)
+	std	31, 17*8(3)
+	blr
+FUNC_END(store_gpr)
+
+/* Single Precision Float - float buf[32] */
+FUNC_START(load_fpr)
+	lfs 0, 0*4(3)
+	lfs 1, 1*4(3)
+	lfs 2, 2*4(3)
+	lfs 3, 3*4(3)
+	lfs 4, 4*4(3)
+	lfs 5, 5*4(3)
+	lfs 6, 6*4(3)
+	lfs 7, 7*4(3)
+	lfs 8, 8*4(3)
+	lfs 9, 9*4(3)
+	lfs 10, 10*4(3)
+	lfs 11, 11*4(3)
+	lfs 12, 12*4(3)
+	lfs 13, 13*4(3)
+	lfs 14, 14*4(3)
+	lfs 15, 15*4(3)
+	lfs 16, 16*4(3)
+	lfs 17, 17*4(3)
+	lfs 18, 18*4(3)
+	lfs 19, 19*4(3)
+	lfs 20, 20*4(3)
+	lfs 21, 21*4(3)
+	lfs 22, 22*4(3)
+	lfs 23, 23*4(3)
+	lfs 24, 24*4(3)
+	lfs 25, 25*4(3)
+	lfs 26, 26*4(3)
+	lfs 27, 27*4(3)
+	lfs 28, 28*4(3)
+	lfs 29, 29*4(3)
+	lfs 30, 30*4(3)
+	lfs 31, 31*4(3)
+	blr
+FUNC_END(load_fpr)
+
+FUNC_START(store_fpr)
+	stfs 0, 0*4(3)
+	stfs 1, 1*4(3)
+	stfs 2, 2*4(3)
+	stfs 3, 3*4(3)
+	stfs 4, 4*4(3)
+	stfs 5, 5*4(3)
+	stfs 6, 6*4(3)
+	stfs 7, 7*4(3)
+	stfs 8, 8*4(3)
+	stfs 9, 9*4(3)
+	stfs 10, 10*4(3)
+	stfs 11, 11*4(3)
+	stfs 12, 12*4(3)
+	stfs 13, 13*4(3)
+	stfs 14, 14*4(3)
+	stfs 15, 15*4(3)
+	stfs 16, 16*4(3)
+	stfs 17, 17*4(3)
+	stfs 18, 18*4(3)
+	stfs 19, 19*4(3)
+	stfs 20, 20*4(3)
+	stfs 21, 21*4(3)
+	stfs 22, 22*4(3)
+	stfs 23, 23*4(3)
+	stfs 24, 24*4(3)
+	stfs 25, 25*4(3)
+	stfs 26, 26*4(3)
+	stfs 27, 27*4(3)
+	stfs 28, 28*4(3)
+	stfs 29, 29*4(3)
+	stfs 30, 30*4(3)
+	stfs 31, 31*4(3)
+	blr
+FUNC_END(store_fpr)
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace.h b/tools/testing/selftests/powerpc/ptrace/ptrace.h
index 44256d2..439fb65 100644
--- a/tools/testing/selftests/powerpc/ptrace/ptrace.h
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace.h
@@ -157,6 +157,214 @@ fail:
 	return TEST_FAIL;
 }
 
+/* FPR */
+int show_fpr(pid_t child, unsigned long *fpr)
+{
+	struct fpr_regs *regs;
+	int ret, i;
+
+	regs = (struct fpr_regs *) malloc(sizeof(struct fpr_regs));
+	ret = ptrace(PTRACE_GETFPREGS, child, NULL, regs);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		return TEST_FAIL;
+	}
+
+	if (fpr) {
+		for (i = 0; i < 32; i++)
+			fpr[i] = regs->fpr[i];
+	}
+	return TEST_PASS;
+}
+
+int write_fpr(pid_t child, unsigned long val)
+{
+	struct fpr_regs *regs;
+	int ret, i;
+
+	regs = (struct fpr_regs *) malloc(sizeof(struct fpr_regs));
+	ret = ptrace(PTRACE_GETFPREGS, child, NULL, regs);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		return TEST_FAIL;
+	}
+
+	for (i = 0; i < 32; i++)
+		regs->fpr[i] = val;
+
+	ret = ptrace(PTRACE_SETFPREGS, child, NULL, regs);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		return TEST_FAIL;
+	}
+	return TEST_PASS;
+}
+
+int show_ckpt_fpr(pid_t child, unsigned long *fpr)
+{
+	struct fpr_regs *regs;
+	struct iovec iov;
+	int ret, i;
+
+	regs = (struct fpr_regs *) malloc(sizeof(struct fpr_regs));
+	iov.iov_base = regs;
+	iov.iov_len = sizeof(struct fpr_regs);
+
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_CFPR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		return TEST_FAIL;
+	}
+
+	if (fpr) {
+		for (i = 0; i < 32; i++)
+			fpr[i] = regs->fpr[i];
+	}
+
+	return TEST_PASS;
+}
+
+int write_ckpt_fpr(pid_t child, unsigned long val)
+{
+	struct fpr_regs *regs;
+	struct iovec iov;
+	int ret, i;
+
+	regs = (struct fpr_regs *) malloc(sizeof(struct fpr_regs));
+	iov.iov_base = regs;
+	iov.iov_len = sizeof(struct fpr_regs);
+
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_CFPR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		return TEST_FAIL;
+	}
+
+	for (i = 0; i < 32; i++)
+		regs->fpr[i] = val;
+
+	ret = ptrace(PTRACE_SETREGSET, child, NT_PPC_TM_CFPR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		return TEST_FAIL;
+	}
+	return TEST_PASS;
+}
+
+/* GPR */
+int show_gpr(pid_t child, unsigned long *gpr)
+{
+	struct pt_regs *regs;
+	int ret, i;
+
+	regs = (struct pt_regs *) malloc(sizeof(struct pt_regs));
+	if (!regs) {
+		perror("malloc() failed");
+		return TEST_FAIL;
+	}
+
+	ret = ptrace(PTRACE_GETREGS, child, NULL, regs);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		return TEST_FAIL;
+	}
+
+	if (gpr) {
+		for (i = 14; i < 32; i++)
+			gpr[i-14] = regs->gpr[i];
+	}
+
+	return TEST_PASS;
+}
+
+int write_gpr(pid_t child, unsigned long val)
+{
+	struct pt_regs *regs;
+	int i, ret;
+
+	regs = (struct pt_regs *) malloc(sizeof(struct pt_regs));
+	if (!regs) {
+		perror("malloc() failed");
+		return TEST_FAIL;
+	}
+
+	ret = ptrace(PTRACE_GETREGS, child, NULL, regs);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		return TEST_FAIL;
+	}
+
+	for (i = 14; i < 32; i++)
+		regs->gpr[i] = val;
+
+	ret = ptrace(PTRACE_SETREGS, child, NULL, regs);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		return TEST_FAIL;
+	}
+	return TEST_PASS;
+}
+
+int show_ckpt_gpr(pid_t child, unsigned long *gpr)
+{
+	struct pt_regs *regs;
+	struct iovec iov;
+	int ret, i;
+
+	regs = (struct pt_regs *) malloc(sizeof(struct pt_regs));
+	if (!regs) {
+		perror("malloc() failed");
+		return TEST_FAIL;
+	}
+
+	iov.iov_base = (u64 *) regs;
+	iov.iov_len = sizeof(struct pt_regs);
+
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_CGPR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		return TEST_FAIL;
+	}
+
+	if (gpr) {
+		for (i = 14; i < 32; i++)
+			gpr[i-14] = regs->gpr[i];
+	}
+
+	return TEST_PASS;
+}
+
+int write_ckpt_gpr(pid_t child, unsigned long val)
+{
+	struct pt_regs *regs;
+	struct iovec iov;
+	int ret, i;
+
+	regs = (struct pt_regs *) malloc(sizeof(struct pt_regs));
+	if (!regs) {
+		perror("malloc() failed\n");
+		return TEST_FAIL;
+	}
+	iov.iov_base = (u64 *) regs;
+	iov.iov_len = sizeof(struct pt_regs);
+
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_CGPR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		return TEST_FAIL;
+	}
+
+	for (i = 14; i < 32; i++)
+		regs->gpr[i] = val;
+
+	ret = ptrace(PTRACE_SETREGSET, child, NT_PPC_TM_CGPR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		return TEST_FAIL;
+	}
+	return TEST_PASS;
+}
+
 /* Analyse TEXASR after TM failure */
 inline unsigned long get_tfiar(void)
 {
-- 
2.1.0

[PATCH V10 19/28] selftests, powerpc: Add ptrace tests for GPR/FPR registers in TM

[Anshuman Khandual]

This patch adds ptrace interface test for GPR/FPR registers
inside TM context. This adds ptrace interface based helper
functions related to checkpointed GPR/FPR access.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/ptrace/Makefile    |   3 +-
 .../selftests/powerpc/ptrace/ptrace-tm-gpr.c       | 288 +++++++++++++++++++++
 2 files changed, 290 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-gpr.c

diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
index f5f62d0..bfdfe5e 100644
--- a/tools/testing/selftests/powerpc/ptrace/Makefile
+++ b/tools/testing/selftests/powerpc/ptrace/Makefile
@@ -1,8 +1,9 @@
-TEST_PROGS := ptrace-ebb ptrace-gpr
+TEST_PROGS := ptrace-ebb ptrace-gpr ptrace-tm-gpr
 
 all: $(TEST_PROGS)
 
 $(TEST_PROGS): ../harness.c ptrace.S ../utils.c
 ptrace-ebb: ../pmu/event.c ../pmu/lib.c ../pmu/ebb/ebb_handler.S ../pmu/ebb/busy_loop.S
+
 clean:
 	rm -f $(TEST_PROGS) *.o
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-gpr.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-gpr.c
new file mode 100644
index 0000000..3efa5d6
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-gpr.c
@@ -0,0 +1,288 @@
+/*
+ * Ptrace test for GPR/FPR registers in TM context
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include "ptrace.h"
+#include "ptrace-gpr.h"
+
+/* Tracer and Tracee Shared Data */
+int shm_id;
+volatile int *cptr, *pptr;
+
+extern void store_gpr(unsigned long *addr);
+extern void store_fpr(float *addr);
+
+float a = FPR_1;
+float b = FPR_2;
+float c = FPR_3;
+
+void tm_gpr(void)
+{
+	unsigned long gpr_buf[18];
+	unsigned long result, texasr;
+	float fpr_buf[32];
+
+	printf("Starting the child\n");
+	cptr = (int *)shmat(shm_id, NULL, 0);
+
+trans:
+	asm __volatile__(
+
+		"li 14, %[gpr_1];"
+		"li 15, %[gpr_1];"
+		"li 16, %[gpr_1];"
+		"li 17, %[gpr_1];"
+		"li 18, %[gpr_1];"
+		"li 19, %[gpr_1];"
+		"li 20, %[gpr_1];"
+		"li 21, %[gpr_1];"
+		"li 22, %[gpr_1];"
+		"li 23, %[gpr_1];"
+		"li 24, %[gpr_1];"
+		"li 25, %[gpr_1];"
+		"li 26, %[gpr_1];"
+		"li 27, %[gpr_1];"
+		"li 28, %[gpr_1];"
+		"li 29, %[gpr_1];"
+		"li 30, %[gpr_1];"
+		"li 31, %[gpr_1];"
+
+		"lfs 0, 0(%[flt_1]);"
+		"lfs 1, 0(%[flt_1]);"
+		"lfs 2, 0(%[flt_1]);"
+		"lfs 3, 0(%[flt_1]);"
+		"lfs 4, 0(%[flt_1]);"
+		"lfs 5, 0(%[flt_1]);"
+		"lfs 6, 0(%[flt_1]);"
+		"lfs 7, 0(%[flt_1]);"
+		"lfs 8, 0(%[flt_1]);"
+		"lfs 9, 0(%[flt_1]);"
+		"lfs 10, 0(%[flt_1]);"
+		"lfs 11, 0(%[flt_1]);"
+		"lfs 12, 0(%[flt_1]);"
+		"lfs 13, 0(%[flt_1]);"
+		"lfs 14, 0(%[flt_1]);"
+		"lfs 15, 0(%[flt_1]);"
+		"lfs 16, 0(%[flt_1]);"
+		"lfs 17, 0(%[flt_1]);"
+		"lfs 18, 0(%[flt_1]);"
+		"lfs 19, 0(%[flt_1]);"
+		"lfs 20, 0(%[flt_1]);"
+		"lfs 21, 0(%[flt_1]);"
+		"lfs 22, 0(%[flt_1]);"
+		"lfs 23, 0(%[flt_1]);"
+		"lfs 24, 0(%[flt_1]);"
+		"lfs 25, 0(%[flt_1]);"
+		"lfs 26, 0(%[flt_1]);"
+		"lfs 27, 0(%[flt_1]);"
+		"lfs 28, 0(%[flt_1]);"
+		"lfs 29, 0(%[flt_1]);"
+		"lfs 30, 0(%[flt_1]);"
+		"lfs 31, 0(%[flt_1]);"
+
+		"1: ;"
+		TBEGIN
+		"beq 2f;"
+
+		"li 14, %[gpr_2];"
+		"li 15, %[gpr_2];"
+		"li 16, %[gpr_2];"
+		"li 17, %[gpr_2];"
+		"li 18, %[gpr_2];"
+		"li 19, %[gpr_2];"
+		"li 20, %[gpr_2];"
+		"li 21, %[gpr_2];"
+		"li 22, %[gpr_2];"
+		"li 23, %[gpr_2];"
+		"li 24, %[gpr_2];"
+		"li 25, %[gpr_2];"
+		"li 26, %[gpr_2];"
+		"li 27, %[gpr_2];"
+		"li 28, %[gpr_2];"
+		"li 29, %[gpr_2];"
+		"li 30, %[gpr_2];"
+		"li 31, %[gpr_2];"
+
+
+		"lfs 0, 0(%[flt_2]);"
+		"lfs 1, 0(%[flt_2]);"
+		"lfs 2, 0(%[flt_2]);"
+		"lfs 3, 0(%[flt_2]);"
+		"lfs 4, 0(%[flt_2]);"
+		"lfs 5, 0(%[flt_2]);"
+		"lfs 6, 0(%[flt_2]);"
+		"lfs 7, 0(%[flt_2]);"
+		"lfs 8, 0(%[flt_2]);"
+		"lfs 9, 0(%[flt_2]);"
+		"lfs 10, 0(%[flt_2]);"
+		"lfs 11, 0(%[flt_2]);"
+		"lfs 12, 0(%[flt_2]);"
+		"lfs 13, 0(%[flt_2]);"
+		"lfs 14, 0(%[flt_2]);"
+		"lfs 15, 0(%[flt_2]);"
+		"lfs 16, 0(%[flt_2]);"
+		"lfs 17, 0(%[flt_2]);"
+		"lfs 18, 0(%[flt_2]);"
+		"lfs 19, 0(%[flt_2]);"
+		"lfs 20, 0(%[flt_2]);"
+		"lfs 21, 0(%[flt_2]);"
+		"lfs 22, 0(%[flt_2]);"
+		"lfs 23, 0(%[flt_2]);"
+		"lfs 24, 0(%[flt_2]);"
+		"lfs 25, 0(%[flt_2]);"
+		"lfs 26, 0(%[flt_2]);"
+		"lfs 27, 0(%[flt_2]);"
+		"lfs 28, 0(%[flt_2]);"
+		"lfs 29, 0(%[flt_2]);"
+		"lfs 30, 0(%[flt_2]);"
+		"lfs 31, 0(%[flt_2]);"
+		TSUSPEND
+		TRESUME
+		"b .;"
+
+		TEND
+		"li 0, 0;"
+		"ori %[res], 0, 0;"
+		"b 3f;"
+
+		/* Transaction abort handler */
+		"2: ;"
+		"li 0, 1;"
+		"ori %[res], 0, 0;"
+		"mfspr %[texasr], %[sprn_texasr];"
+
+		"3: ;"
+		:[res] "=r" (result), [texasr] "=r" (texasr)
+		:[gpr_1]"i"(GPR_1), [gpr_2]"i"(GPR_2), [sprn_texasr] "i" (SPRN_TEXASR),
+		[flt_1] "r" (&a), [flt_2] "r" (&b)
+		: "memory", "r7", "r8", "r9", "r10",
+		"r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20",
+		"r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
+		);
+
+	if (result) {
+		if (!cptr[0])
+			goto trans;
+
+		store_gpr(gpr_buf);
+		store_fpr(fpr_buf);
+
+		if (validate_gpr(gpr_buf, GPR_3))
+			exit(1);
+
+		if (validate_fpr_float(fpr_buf, c))
+			exit(1);
+		exit(0);
+	}
+	exit(1);
+}
+
+int trace_tm_gpr(pid_t child)
+{
+	unsigned long gpr[18];
+	unsigned long fpr[32];
+	int ret;
+
+	sleep(1);
+	ret = start_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_gpr(child, gpr);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_gpr(gpr, GPR_2);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_fpr(child, fpr);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_fpr(fpr, FPR_2_REP);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_ckpt_fpr(child, fpr);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_fpr(fpr, FPR_1_REP);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_ckpt_gpr(child, gpr);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_gpr(gpr, GPR_1);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = write_ckpt_gpr(child, GPR_3);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = write_ckpt_fpr(child, FPR_3_REP);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = stop_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	return TEST_PASS;
+}
+
+int ptrace_tm_gpr(void)
+{
+	pid_t pid;
+	int ret, status;
+
+	SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
+	shm_id = shmget(IPC_PRIVATE, sizeof(int) * 1, 0777|IPC_CREAT);
+	pid = fork();
+	if (pid < 0) {
+		perror("fork() failed");
+		return TEST_FAIL;
+	}
+	if (pid == 0)
+		tm_gpr();
+
+	if (pid) {
+		pptr = (int *)shmat(shm_id, NULL, 0);
+		ret = trace_tm_gpr(pid);
+		if (ret) {
+			kill(pid, SIGTERM);
+			return TEST_FAIL;
+		}
+
+		pptr[0] = 1;
+		shmdt((void *)pptr);
+
+		ret = wait(&status);
+		if (ret != pid) {
+			printf("Child's exit status not captured\n");
+			return TEST_FAIL;
+		}
+
+		if (WIFEXITED(status)) {
+			if(WEXITSTATUS(status))
+				return TEST_FAIL;
+		}
+		return TEST_PASS;
+	}
+	return TEST_PASS;
+}
+
+int main(int argc, char *argv[])
+{
+	return test_harness(ptrace_tm_gpr, "ptrace_tm_gpr");
+}
-- 
2.1.0

[PATCH V10 20/28] selftests, powerpc: Add ptrace tests for GPR/FPR registers in suspended TM

[Anshuman Khandual]

This patch adds ptrace interface test for GPR/FPR registers
inside suspended TM context.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/ptrace/Makefile    |   2 +-
 .../selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c   | 319 +++++++++++++++++++++
 2 files changed, 320 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c

diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
index bfdfe5e..34e2d91 100644
--- a/tools/testing/selftests/powerpc/ptrace/Makefile
+++ b/tools/testing/selftests/powerpc/ptrace/Makefile
@@ -1,4 +1,4 @@
-TEST_PROGS := ptrace-ebb ptrace-gpr ptrace-tm-gpr
+TEST_PROGS := ptrace-ebb ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr
 
 all: $(TEST_PROGS)
 
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c
new file mode 100644
index 0000000..2c73b0d
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c
@@ -0,0 +1,319 @@
+/*
+ * Ptrace test for GPR/FPR registers in TM Suspend context
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include "ptrace.h"
+#include "ptrace-gpr.h"
+
+/* Tracer and Tracee Shared Data */
+int shm_id;
+volatile int *cptr, *pptr;
+
+extern void store_gpr(unsigned long *addr);
+extern void store_fpr(float *addr);
+
+float a = FPR_1;
+float b = FPR_2;
+float c = FPR_3;
+float d = FPR_4;
+
+__attribute__((used)) void wait_parent(void)
+{
+	while(!cptr[1]);
+}
+
+void tm_spd_gpr(void)
+{
+	unsigned long gpr_buf[18];
+	unsigned long result, texasr;
+	float fpr_buf[32];
+
+	cptr = (int *)shmat(shm_id, NULL, 0);
+
+trans:
+	asm __volatile__(
+
+		"li 14, %[gpr_1];"
+		"li 15, %[gpr_1];"
+		"li 16, %[gpr_1];"
+		"li 17, %[gpr_1];"
+		"li 18, %[gpr_1];"
+		"li 19, %[gpr_1];"
+		"li 20, %[gpr_1];"
+		"li 21, %[gpr_1];"
+		"li 22, %[gpr_1];"
+		"li 23, %[gpr_1];"
+		"li 24, %[gpr_1];"
+		"li 25, %[gpr_1];"
+		"li 26, %[gpr_1];"
+		"li 27, %[gpr_1];"
+		"li 28, %[gpr_1];"
+		"li 29, %[gpr_1];"
+		"li 30, %[gpr_1];"
+		"li 31, %[gpr_1];"
+
+		"lfs 0, 0(%[flt_1]);"
+		"lfs 1, 0(%[flt_1]);"
+		"lfs 2, 0(%[flt_1]);"
+		"lfs 3, 0(%[flt_1]);"
+		"lfs 4, 0(%[flt_1]);"
+		"lfs 5, 0(%[flt_1]);"
+		"lfs 6, 0(%[flt_1]);"
+		"lfs 7, 0(%[flt_1]);"
+		"lfs 8, 0(%[flt_1]);"
+		"lfs 9, 0(%[flt_1]);"
+		"lfs 10, 0(%[flt_1]);"
+		"lfs 11, 0(%[flt_1]);"
+		"lfs 12, 0(%[flt_1]);"
+		"lfs 13, 0(%[flt_1]);"
+		"lfs 14, 0(%[flt_1]);"
+		"lfs 15, 0(%[flt_1]);"
+		"lfs 16, 0(%[flt_1]);"
+		"lfs 17, 0(%[flt_1]);"
+		"lfs 18, 0(%[flt_1]);"
+		"lfs 19, 0(%[flt_1]);"
+		"lfs 20, 0(%[flt_1]);"
+		"lfs 21, 0(%[flt_1]);"
+		"lfs 22, 0(%[flt_1]);"
+		"lfs 23, 0(%[flt_1]);"
+		"lfs 24, 0(%[flt_1]);"
+		"lfs 25, 0(%[flt_1]);"
+		"lfs 26, 0(%[flt_1]);"
+		"lfs 27, 0(%[flt_1]);"
+		"lfs 28, 0(%[flt_1]);"
+		"lfs 29, 0(%[flt_1]);"
+		"lfs 30, 0(%[flt_1]);"
+		"lfs 31, 0(%[flt_1]);"
+
+		"1: ;"
+		TBEGIN
+		"beq 2f;"
+
+		"li 14, %[gpr_2];"
+		"li 15, %[gpr_2];"
+		"li 16, %[gpr_2];"
+		"li 17, %[gpr_2];"
+		"li 18, %[gpr_2];"
+		"li 19, %[gpr_2];"
+		"li 20, %[gpr_2];"
+		"li 21, %[gpr_2];"
+		"li 22, %[gpr_2];"
+		"li 23, %[gpr_2];"
+		"li 24, %[gpr_2];"
+		"li 25, %[gpr_2];"
+		"li 26, %[gpr_2];"
+		"li 27, %[gpr_2];"
+		"li 28, %[gpr_2];"
+		"li 29, %[gpr_2];"
+		"li 30, %[gpr_2];"
+		"li 31, %[gpr_2];"
+
+		TSUSPEND
+
+		"li 14, %[gpr_4];"
+		"li 15, %[gpr_4];"
+		"li 16, %[gpr_4];"
+		"li 17, %[gpr_4];"
+		"li 18, %[gpr_4];"
+		"li 19, %[gpr_4];"
+		"li 20, %[gpr_4];"
+		"li 21, %[gpr_4];"
+		"li 22, %[gpr_4];"
+		"li 23, %[gpr_4];"
+		"li 24, %[gpr_4];"
+		"li 25, %[gpr_4];"
+		"li 26, %[gpr_4];"
+		"li 27, %[gpr_4];"
+		"li 28, %[gpr_4];"
+		"li 29, %[gpr_4];"
+		"li 30, %[gpr_4];"
+		"li 31, %[gpr_4];"
+
+		"lfs 0, 0(%[flt_4]);"
+		"lfs 1, 0(%[flt_4]);"
+		"lfs 2, 0(%[flt_4]);"
+		"lfs 3, 0(%[flt_4]);"
+		"lfs 4, 0(%[flt_4]);"
+		"lfs 5, 0(%[flt_4]);"
+		"lfs 6, 0(%[flt_4]);"
+		"lfs 7, 0(%[flt_4]);"
+		"lfs 8, 0(%[flt_4]);"
+		"lfs 9, 0(%[flt_4]);"
+		"lfs 10, 0(%[flt_4]);"
+		"lfs 11, 0(%[flt_4]);"
+		"lfs 12, 0(%[flt_4]);"
+		"lfs 13, 0(%[flt_4]);"
+		"lfs 14, 0(%[flt_4]);"
+		"lfs 15, 0(%[flt_4]);"
+		"lfs 16, 0(%[flt_4]);"
+		"lfs 17, 0(%[flt_4]);"
+		"lfs 18, 0(%[flt_4]);"
+		"lfs 19, 0(%[flt_4]);"
+		"lfs 20, 0(%[flt_4]);"
+		"lfs 21, 0(%[flt_4]);"
+		"lfs 22, 0(%[flt_4]);"
+		"lfs 23, 0(%[flt_4]);"
+		"lfs 24, 0(%[flt_4]);"
+		"lfs 25, 0(%[flt_4]);"
+		"lfs 26, 0(%[flt_4]);"
+		"lfs 27, 0(%[flt_4]);"
+		"lfs 28, 0(%[flt_4]);"
+		"lfs 29, 0(%[flt_4]);"
+		"lfs 30, 0(%[flt_4]);"
+		"lfs 31, 0(%[flt_4]);"
+		"bl wait_parent;"
+
+		TRESUME
+
+		TEND
+		"li 0, 0;"
+		"ori %[res], 0, 0;"
+		"b 3f;"
+
+		/* Transaction abort handler */
+		"2: ;"
+		"li 0, 1;"
+		"ori %[res], 0, 0;"
+		"mfspr %[texasr], %[sprn_texasr];"
+
+		"3: ;"
+		:[res] "=r" (result), [texasr] "=r" (texasr)
+		:[gpr_1]"i"(GPR_1), [gpr_2]"i"(GPR_2), [gpr_4]"i"(GPR_4), [sprn_texasr] "i" (SPRN_TEXASR),
+		[flt_1] "r" (&a), [flt_2] "r" (&b), [flt_4] "r" (&d)
+		: "memory", "r5", "r6", "r7",
+		"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16",
+		"r17", "r18", "r19", "r20", "r21", "r22", "r23", "r24", "r25",
+		"r26", "r27", "r28", "r29", "r30", "r31"
+		);
+
+	if (result) {
+		if (!cptr[0])
+			goto trans;
+
+		store_gpr(gpr_buf);
+		store_fpr(fpr_buf);
+
+		if (validate_gpr(gpr_buf, GPR_3))
+			exit(1);
+
+		if (validate_fpr_float(fpr_buf, c))
+			exit(1);
+		exit(0);
+	}
+	exit(1);
+}
+
+int trace_tm_spd_gpr(pid_t child)
+{
+	unsigned long gpr[18];
+	unsigned long fpr[32];
+	int ret;
+
+	sleep(1);
+	ret = start_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_gpr(child, gpr);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_gpr(gpr, GPR_4);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_fpr(child, fpr);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_fpr(fpr, FPR_4_REP);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_ckpt_fpr(child, fpr);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_fpr(fpr, FPR_1_REP);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_ckpt_gpr(child, gpr);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_gpr(gpr, GPR_1);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = write_ckpt_gpr(child, GPR_3);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = write_ckpt_fpr(child, FPR_3_REP);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = stop_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	return TEST_PASS;
+}
+
+int ptrace_tm_spd_gpr(void)
+{
+	pid_t pid;
+	int ret, status;
+
+	SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
+	shm_id = shmget(IPC_PRIVATE, sizeof(int) * 2, 0777|IPC_CREAT);
+	pid = fork();
+	if (pid < 0) {
+		perror("fork() failed");
+		return TEST_FAIL;
+	}
+
+	if (pid == 0)
+		tm_spd_gpr();
+
+	if (pid) {
+		pptr = (int *)shmat(shm_id, NULL, 0);
+		pptr[0] = 0;
+		pptr[1] = 0;
+
+		ret = trace_tm_spd_gpr(pid);
+		if (ret) {
+			kill(pid, SIGTERM);
+			return TEST_FAIL;
+		}
+
+		pptr[0] = 1;
+		pptr[1] = 1;
+		shmdt((void *)pptr);
+
+		ret = wait(&status);
+		if (ret != pid) {
+			printf("Child's exit status not captured\n");
+			return TEST_FAIL;
+		}
+
+		if (WIFEXITED(status)) {
+			if(WEXITSTATUS(status))
+				return TEST_FAIL;
+		}
+		return TEST_PASS;
+	}
+	return TEST_PASS;
+}
+
+int main(int argc, char *argv[])
+{
+	return test_harness(ptrace_tm_spd_gpr, "ptrace_tm_spd_gpr");
+}
-- 
2.1.0

[PATCH V10 21/28] selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR registers

[Anshuman Khandual]

This patch adds ptrace interface test for TAR, PPR, DSCR
registers. This also adds ptrace interface based helper
functions related to TAR, PPR, DSCR register access.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/ptrace/Makefile    |   3 +-
 .../testing/selftests/powerpc/ptrace/ptrace-tar.c  | 151 +++++++++++++++++
 .../testing/selftests/powerpc/ptrace/ptrace-tar.h  |  50 ++++++
 tools/testing/selftests/powerpc/ptrace/ptrace.h    | 179 +++++++++++++++++++++
 4 files changed, 382 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tar.h

diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
index 34e2d91..0f93e8d 100644
--- a/tools/testing/selftests/powerpc/ptrace/Makefile
+++ b/tools/testing/selftests/powerpc/ptrace/Makefile
@@ -1,4 +1,5 @@
-TEST_PROGS := ptrace-ebb ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr
+TEST_PROGS := ptrace-ebb ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr \
+ptrace-tar
 
 all: $(TEST_PROGS)
 
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tar.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tar.c
new file mode 100644
index 0000000..51978aa
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tar.c
@@ -0,0 +1,151 @@
+/*
+ * Ptrace test for TAR, PPR, DSCR registers
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include "ptrace.h"
+#include "ptrace-tar.h"
+
+/* Tracer and Tracee Shared Data */
+int shm_id;
+volatile int *cptr;
+volatile int *pptr;
+
+void tar(void)
+{
+	unsigned long reg[3];
+	int ret;
+
+	cptr = (int *)shmat(shm_id, NULL, 0);
+	printf("%-30s TAR: %u PPR: %lx DSCR: %u\n", user_write, TAR_1, PPR_1, DSCR_1);
+
+	mtspr(SPRN_TAR, TAR_1);
+	mtspr(SPRN_PPR, PPR_1);
+	mtspr(SPRN_DSCR, DSCR_1);
+
+	/* Wait on parent */
+	while (!cptr[0]);
+
+	reg[0] = mfspr(SPRN_TAR);
+	reg[1] = mfspr(SPRN_PPR);
+	reg[2] = mfspr(SPRN_DSCR);
+
+	printf("%-30s TAR: %lu PPR: %lx DSCR: %lu\n", user_read, reg[0], reg[1], reg[2]);
+
+	/* Unblock the parent now */
+	cptr[1] = 1;
+	shmdt((int *)cptr);
+
+	ret = validate_tar_registers(reg, TAR_2, PPR_2, DSCR_2);
+	if (ret)
+		exit(1);
+	exit(0);
+}
+
+int trace_tar(pid_t child)
+{
+	unsigned long reg[3];
+	int ret;
+
+	sleep(1);
+	ret = start_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_tar_registers(child, reg);
+	if (ret)
+		return TEST_FAIL;
+
+	printf("%-30s TAR: %lu PPR: %lx DSCR: %lu\n", ptrace_read_running, reg[0], reg[1], reg[2]);
+
+	ret = validate_tar_registers(reg, TAR_1, PPR_1, DSCR_1);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = stop_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	return TEST_PASS;
+}
+
+int trace_tar_write(pid_t child)
+{
+	int ret;
+
+	ret = start_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = write_tar_registers(child, TAR_2, PPR_2, DSCR_2);
+	if (ret)
+		return TEST_FAIL;
+
+	printf("%-30s TAR: %u PPR: %lx DSCR: %u\n", ptrace_write_running, TAR_2, PPR_2, DSCR_2);
+
+	ret = stop_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	return TEST_PASS;
+}
+
+int ptrace_tar(void)
+{
+	pid_t pid;
+	int ret, status;
+
+	shm_id = shmget(IPC_PRIVATE, sizeof(int) * 2, 0777|IPC_CREAT);
+	pid = fork();
+	if (pid < 0) {
+		perror("fork() failed");
+		return TEST_FAIL;
+	}
+
+	if (pid == 0)
+		tar();
+
+	if (pid) {
+		pptr = (int *)shmat(shm_id, NULL, 0);
+		pptr[0] = 0;
+		pptr[1] = 0;
+		ret = trace_tar(pid);
+		if (ret)
+			return ret;
+
+		ret = trace_tar_write(pid);
+		if (ret)
+			return ret;
+
+		/* Unblock the child now */
+		pptr[0] = 1;
+
+		/* Wait on child */
+		while(!pptr[1]);
+
+		shmdt((int *)pptr);
+
+		ret = wait(&status);
+		if (ret != pid) {
+			printf("Child's exit status not captured\n");
+			return TEST_PASS;
+		}
+
+		if (WIFEXITED(status)) {
+			if(WEXITSTATUS(status))
+				return TEST_FAIL;
+		}
+		return TEST_PASS;
+	}
+	return TEST_PASS;
+}
+
+int main(int argc, char *argv[])
+{
+	return test_harness(ptrace_tar, "ptrace_tar");
+}
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tar.h b/tools/testing/selftests/powerpc/ptrace/ptrace-tar.h
new file mode 100644
index 0000000..5031e46
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tar.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#define TAR_1   10
+#define TAR_2   20
+#define TAR_3   30
+#define TAR_4   40
+#define TAR_5   50
+
+#define DSCR_1  100
+#define DSCR_2  200
+#define DSCR_3  300
+#define DSCR_4  400
+#define DSCR_5  500
+
+#define PPR_1   0x4000000000000         /* or 31,31,31*/
+#define PPR_2   0x8000000000000         /* or 1,1,1 */
+#define PPR_3   0xc000000000000         /* or 6,6,6 */
+#define PPR_4   0x10000000000000        /* or 2,2,2 */
+
+char *user_read="[User Read (Running)]";
+char *user_write="[User Write (Running)]";
+char *ptrace_read_running="[Ptrace Read (Running)]";
+char *ptrace_write_running="[Ptrace Write (Running)]";
+char *ptrace_read_ckpt="[Ptrace Read (Checkpointed)]";
+char *ptrace_write_ckpt="[Ptrace Write (Checkpointed)]";
+
+int validate_tar_registers(unsigned long *reg, unsigned long tar,
+				unsigned long ppr, unsigned long dscr)
+{
+	int match = 1;
+
+	if (reg[0] != tar)
+		match = 0;
+
+	if (reg[1] != ppr)
+		match = 0;
+
+	if (reg[2] != dscr)
+		match = 0;
+
+	if (!match)
+		return TEST_FAIL;
+	return TEST_PASS;
+}
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace.h b/tools/testing/selftests/powerpc/ptrace/ptrace.h
index 439fb65..a5efdee 100644
--- a/tools/testing/selftests/powerpc/ptrace/ptrace.h
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace.h
@@ -157,6 +157,185 @@ fail:
 	return TEST_FAIL;
 }
 
+/* TAR, PPR, DSCR */
+int show_tar_registers(pid_t child, unsigned long *out)
+{
+	struct iovec iov;
+	unsigned long *reg;
+	int ret;
+
+	reg = malloc(sizeof(unsigned long));
+	if (!reg) {
+		perror("malloc() failed");
+		return TEST_FAIL;
+	}
+	iov.iov_base = (u64 *) reg;
+	iov.iov_len = sizeof(unsigned long);
+
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TAR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		goto fail;
+	}
+	if (out)
+		out[0] = *reg;
+
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_PPR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		goto fail;
+	}
+	if (out)
+		out[1] = *reg;
+
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_DSCR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		goto fail;
+	}
+	if (out)
+		out[2] = *reg;
+
+	free(reg);
+	return TEST_PASS;
+fail:
+	free(reg);
+	return TEST_FAIL;
+}
+
+int write_tar_registers(pid_t child, unsigned long tar, unsigned long ppr, unsigned long dscr)
+{
+	struct iovec iov;
+	unsigned long *reg;
+	int ret;
+
+	reg = malloc(sizeof(unsigned long));
+	if (!reg) {
+		perror("malloc() failed");
+		return TEST_FAIL;
+	}
+
+	iov.iov_base = (u64 *) reg;
+	iov.iov_len = sizeof(unsigned long);
+
+	*reg = tar;
+	ret = ptrace(PTRACE_SETREGSET, child, NT_PPC_TAR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_SETREGSET) failed");
+		goto fail;
+	}
+
+	*reg = ppr;
+	ret = ptrace(PTRACE_SETREGSET, child, NT_PPC_PPR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_SETREGSET) failed");
+		goto fail;
+	}
+
+	*reg = dscr;
+	ret = ptrace(PTRACE_SETREGSET, child, NT_PPC_DSCR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_SETREGSET) failed");
+		goto fail;
+	}
+
+	free(reg);
+	return TEST_PASS;
+fail:
+	free(reg);
+	return TEST_FAIL;
+}
+
+int show_tm_checkpointed_state(pid_t child, unsigned long *out)
+{
+	struct iovec iov;
+	unsigned long *reg;
+	int ret;
+
+	reg = malloc(sizeof(unsigned long));
+	if (!reg) {
+		perror("malloc() failed");
+		return TEST_FAIL;
+	}
+
+	iov.iov_base = (u64 *) reg;
+	iov.iov_len = sizeof(unsigned long);
+
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_CTAR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		goto fail;
+	}
+	if (out)
+		out[0] = *reg;
+
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_CPPR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		goto fail;
+	}
+	if (out)
+		out[1] = *reg;
+
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_CDSCR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		goto fail;
+	}
+	if (out)
+		out[2] = *reg;
+
+	free(reg);
+	return TEST_PASS;
+
+fail:
+	free(reg);
+	return TEST_FAIL;
+}
+
+int write_ckpt_tar_registers(pid_t child, unsigned long tar, unsigned long ppr, unsigned long dscr)
+{
+	struct iovec iov;
+	unsigned long *reg;
+	int ret;
+
+	reg = malloc(sizeof(unsigned long));
+	if (!reg) {
+		perror("malloc() failed");
+		return TEST_FAIL;
+	}
+
+	iov.iov_base = (u64 *) reg;
+	iov.iov_len = sizeof(unsigned long);
+
+	*reg = tar;
+	ret = ptrace(PTRACE_SETREGSET, child, NT_PPC_TM_CTAR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		goto fail;
+	}
+
+	*reg = ppr;
+	ret = ptrace(PTRACE_SETREGSET, child, NT_PPC_TM_CPPR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		goto fail;
+	}
+
+	*reg = dscr;
+	ret = ptrace(PTRACE_SETREGSET, child, NT_PPC_TM_CDSCR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		goto fail;
+	}
+
+	free(reg);
+	return TEST_PASS;
+fail:
+	free(reg);
+	return TEST_FAIL;
+}
+
 /* FPR */
 int show_fpr(pid_t child, unsigned long *fpr)
 {
-- 
2.1.0

[PATCH V10 22/28] selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR in TM

[Anshuman Khandual]

This patch adds ptrace interface test for TAR, PPR, DSCR
registers inside TM context. This also adds ptrace
interface based helper functions related to checkpointed
TAR, PPR, DSCR register access.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/ptrace/Makefile    |   2 +-
 .../selftests/powerpc/ptrace/ptrace-tm-tar.c       | 170 +++++++++++++++++++++
 2 files changed, 171 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c

diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
index 0f93e8d..464fa61 100644
--- a/tools/testing/selftests/powerpc/ptrace/Makefile
+++ b/tools/testing/selftests/powerpc/ptrace/Makefile
@@ -1,5 +1,5 @@
 TEST_PROGS := ptrace-ebb ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr \
-ptrace-tar
+ptrace-tar ptrace-tm-tar
 
 all: $(TEST_PROGS)
 
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c
new file mode 100644
index 0000000..45b6fa3
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c
@@ -0,0 +1,170 @@
+/*
+ * Ptrace test for TAR, PPR, DSCR registers in the TM context
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include "ptrace.h"
+#include "ptrace-tar.h"
+
+int shm_id;
+volatile int *cptr, *pptr;
+
+
+void tm_tar(void)
+{
+	unsigned long result, texasr;
+	unsigned long regs[3];
+	int ret;
+
+	cptr = (int *)shmat(shm_id, NULL, 0);
+trans:
+	asm __volatile__(
+		"li	4, %[tar_1];"
+		"mtspr %[sprn_tar],  4;"	/* TAR_1 */
+		"li	4, %[dscr_1];"
+		"mtspr %[sprn_dscr], 4;"	/* DSCR_1 */
+		"or     31,31,31;"		/* PPR_1*/
+
+		"1: ;"
+		TBEGIN
+		"beq 2f;"
+
+		"li	4, %[tar_2];"
+		"mtspr %[sprn_tar],  4;"	/* TAR_2 */
+		"li	4, %[dscr_2];"
+		"mtspr %[sprn_dscr], 4;"	/* DSCR_2 */
+		"or     1,1,1;"			/* PPR_2 */
+		TSUSPEND
+		TRESUME
+		"b .;"
+
+		TEND
+		"li 0, 0;"
+		"ori %[res], 0, 0;"
+		"b 3f;"
+
+		/* Transaction abort handler */
+		"2: ;"
+		"li 0, 1;"
+		"ori %[res], 0, 0;"
+		"mfspr %[texasr], %[sprn_texasr];"
+
+		"3: ;"
+
+		:[res] "=r" (result), [texasr] "=r" (texasr)
+		:[sprn_dscr]"i"(SPRN_DSCR), [sprn_tar]"i"(SPRN_TAR), [sprn_ppr]"i"(SPRN_PPR), [sprn_texasr]"i"(SPRN_TEXASR),
+		[tar_1]"i"(TAR_1), [dscr_1]"i"(DSCR_1),
+		[tar_2]"i"(TAR_2), [dscr_2]"i"(DSCR_2)
+		: "memory", "r0", "r1", "r3", "r4", "r5", "r6"
+		);
+
+	/* TM failed, analyse */
+	if (result) {
+		if (!cptr[0])
+			goto trans;
+
+		regs[0] = mfspr(SPRN_TAR);
+		regs[1] = mfspr(SPRN_PPR);
+		regs[2] = mfspr(SPRN_DSCR);
+
+		shmdt(&cptr);
+		printf("%-30s TAR: %lu PPR: %lx DSCR: %lu\n", user_read, regs[0], regs[1], regs[2]);
+
+		ret = validate_tar_registers(regs, TAR_4, PPR_4, DSCR_4);
+		if (ret)
+			exit(1);
+		exit(0);
+	}
+	shmdt(&cptr);
+	exit(1);
+}
+
+int trace_tm_tar(pid_t child)
+{
+	unsigned long regs[3];
+	int ret;
+
+	sleep(1);
+	ret = start_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_tar_registers(child, regs);
+	if (ret)
+		return TEST_FAIL;
+
+	printf("%-30s TAR: %lu PPR: %lx DSCR: %lu\n", ptrace_read_running, regs[0], regs[1], regs[2]);
+
+	ret = validate_tar_registers(regs, TAR_2, PPR_2, DSCR_2);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_tm_checkpointed_state(child, regs);
+	if (ret)
+		return TEST_FAIL;
+
+	printf("%-30s TAR: %lu PPR: %lx DSCR: %lu\n", ptrace_read_ckpt, regs[0], regs[1], regs[2]);
+
+	ret = validate_tar_registers(regs, TAR_1, PPR_1, DSCR_1);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = write_ckpt_tar_registers(child, TAR_4, PPR_4, DSCR_4);
+	if (ret)
+		return TEST_FAIL;
+
+	printf("%-30s TAR: %u PPR: %lx DSCR: %u\n", ptrace_write_ckpt, TAR_4, PPR_4, DSCR_4);
+
+	ret = stop_trace(child);
+	if (ret)
+		return TEST_FAIL;
+	return TEST_PASS;
+}
+
+int ptrace_tm_tar(void)
+{
+	pid_t pid;
+	int ret, status;
+
+	SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
+	shm_id = shmget(IPC_PRIVATE, sizeof(int) * 1, 0777|IPC_CREAT);
+	pid = fork();
+	if (pid == 0)
+		tm_tar();
+
+	pptr = (int *)shmat(shm_id, NULL, 0);
+	pptr[0] = 0;
+
+	if (pid) {
+		ret = trace_tm_tar(pid);
+		if (ret) {
+			kill(pid, SIGTERM);
+			return TEST_FAIL;
+		}
+		pptr[0] = 1;
+		shmdt(&pptr);
+
+		ret = wait(&status);
+		if (ret != pid) {
+			printf("Child's exit status not captured\n");
+			return TEST_FAIL;
+		}
+
+		if (WIFEXITED(status)) {
+			if(WEXITSTATUS(status))
+				return TEST_FAIL;
+		}
+		return TEST_PASS;
+	}
+	return TEST_PASS;
+}
+
+int main(int argc, char *argv[])
+{
+	return test_harness(ptrace_tm_tar, "ptrace_tm_tar");
+}
-- 
2.1.0

[PATCH V10 23/28] selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR in suspended TM

[Anshuman Khandual]

This patch adds ptrace interface test for TAR, PPR, DSCR
registers inside suspended TM context.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/ptrace/Makefile    |   2 +-
 .../selftests/powerpc/ptrace/ptrace-tm-spd-tar.c   | 184 +++++++++++++++++++++
 2 files changed, 185 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c

diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
index 464fa61..5703b68 100644
--- a/tools/testing/selftests/powerpc/ptrace/Makefile
+++ b/tools/testing/selftests/powerpc/ptrace/Makefile
@@ -1,5 +1,5 @@
 TEST_PROGS := ptrace-ebb ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr \
-ptrace-tar ptrace-tm-tar
+ptrace-tar ptrace-tm-tar ptrace-tm-spd-tar
 
 all: $(TEST_PROGS)
 
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c
new file mode 100644
index 0000000..56f604b
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c
@@ -0,0 +1,184 @@
+/*
+ * Ptrace test for TAR, PPR, DSCR registers in the TM Suspend context
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include "ptrace.h"
+#include "ptrace-tar.h"
+
+int shm_id;
+volatile int *cptr, *pptr;
+
+__attribute__((used)) void wait_parent(void)
+{
+	while(!cptr[1]);
+}
+
+void tm_spd_tar(void)
+{
+	unsigned long result, texasr;
+	unsigned long regs[3];
+	int ret;
+
+	cptr = (int *)shmat(shm_id, NULL, 0);
+trans:
+	asm __volatile__(
+		"li	4, %[tar_1];"
+		"mtspr %[sprn_tar],  4;"	/* TAR_1 */
+		"li	4, %[dscr_1];"
+		"mtspr %[sprn_dscr], 4;"	/* DSCR_1 */
+		"or     31,31,31;"		/* PPR_1*/
+
+		"1: ;"
+		TBEGIN
+		"beq 2f;"
+
+		"li	4, %[tar_2];"
+		"mtspr %[sprn_tar],  4;"	/* TAR_2 */
+		"li	4, %[dscr_2];"
+		"mtspr %[sprn_dscr], 4;"	/* DSCR_2 */
+		"or     1,1,1;"			/* PPR_2 */
+
+		TSUSPEND
+		"li	4, %[tar_3];"
+		"mtspr %[sprn_tar],  4;"	/* TAR_3 */
+		"li	4, %[dscr_3];"
+		"mtspr %[sprn_dscr], 4;"	/* DSCR_3 */
+		"or     6,6,6;"			/* PPR_3 */
+		"bl wait_parent;"
+		TRESUME
+
+		TEND
+		"li 0, 0;"
+		"ori %[res], 0, 0;"
+		"b 3f;"
+
+		/* Transaction abort handler */
+		"2: ;"
+		"li 0, 1;"
+		"ori %[res], 0, 0;"
+		"mfspr %[texasr], %[sprn_texasr];"
+
+		"3: ;"
+
+		:[res] "=r" (result), [texasr] "=r" (texasr)
+		:[val] "r" (cptr[1]), [sprn_dscr]"i"(SPRN_DSCR), [sprn_tar]"i"(SPRN_TAR), [sprn_ppr]"i"(SPRN_PPR), [sprn_texasr]"i"(SPRN_TEXASR),
+		[tar_1]"i"(TAR_1), [dscr_1]"i"(DSCR_1),
+		[tar_2]"i"(TAR_2), [dscr_2]"i"(DSCR_2),
+		[tar_3]"i"(TAR_3), [dscr_3]"i"(DSCR_3)
+		: "memory", "r0", "r1", "r3", "r4", "r5", "r6"
+		);
+
+	/* TM failed, analyse */
+	if (result) {
+		if (!cptr[0])
+			goto trans;
+
+		regs[0] = mfspr(SPRN_TAR);
+		regs[1] = mfspr(SPRN_PPR);
+		regs[2] = mfspr(SPRN_DSCR);
+
+		shmdt(&cptr);
+		printf("%-30s TAR: %lu PPR: %lx DSCR: %lu\n", user_read, regs[0], regs[1], regs[2]);
+
+		ret = validate_tar_registers(regs, TAR_4, PPR_4, DSCR_4);
+		if (ret)
+			exit(1);
+		exit(0);
+	}
+	shmdt(&cptr);
+	exit(1);
+}
+
+int trace_tm_spd_tar(pid_t child)
+{
+	unsigned long regs[3];
+	int ret;
+
+	sleep(1);
+	ret = start_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_tar_registers(child, regs);
+	if (ret)
+		return TEST_FAIL;
+
+	printf("%-30s TAR: %lu PPR: %lx DSCR: %lu\n", ptrace_read_running, regs[0], regs[1], regs[2]);
+
+	ret = validate_tar_registers(regs, TAR_3, PPR_3, DSCR_3);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_tm_checkpointed_state(child, regs);
+	if (ret)
+		return TEST_FAIL;
+
+	printf("%-30s TAR: %lu PPR: %lx DSCR: %lu\n", ptrace_read_ckpt, regs[0], regs[1], regs[2]);
+
+	ret = validate_tar_registers(regs, TAR_1, PPR_1, DSCR_1);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = write_ckpt_tar_registers(child, TAR_4, PPR_4, DSCR_4);
+	if (ret)
+		return TEST_FAIL;
+
+	printf("%-30s TAR: %u PPR: %lx DSCR: %u\n", ptrace_write_ckpt, TAR_4, PPR_4, DSCR_4);
+
+	ret = stop_trace(child);
+	if (ret)
+		return TEST_FAIL;
+	return TEST_PASS;
+}
+
+int ptrace_tm_spd_tar(void)
+{
+	pid_t pid;
+	int ret, status;
+
+	SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
+	shm_id = shmget(IPC_PRIVATE, sizeof(int) * 2, 0777|IPC_CREAT);
+	pid = fork();
+	if (pid == 0)
+		tm_spd_tar();
+
+	pptr = (int *)shmat(shm_id, NULL, 0);
+	pptr[0] = 0;
+	pptr[1] = 0;
+
+	if (pid) {
+		ret = trace_tm_spd_tar(pid);
+		if (ret) {
+			kill(pid, SIGTERM);
+			return TEST_FAIL;
+		}
+
+		pptr[0] = 1;
+		pptr[1] = 1;
+		shmdt(&pptr);
+
+		ret = wait(&status);
+		if (ret != pid) {
+			printf("Child's exit status not captured\n");
+			return TEST_FAIL;
+		}
+
+		if (WIFEXITED(status)) {
+			if(WEXITSTATUS(status))
+				return TEST_FAIL;
+		}
+		return TEST_PASS;
+	}
+	return TEST_PASS;
+}
+
+int main(int argc, char *argv[])
+{
+	return test_harness(ptrace_tm_spd_tar, "ptrace_tm_spd_tar");
+}
-- 
2.1.0

[PATCH V10 24/28] selftests, powerpc: Add ptrace tests for VSX, VMX registers

[Anshuman Khandual]

This patch adds ptrace interface test for VSX, VMX registers.
This also adds ptrace interface based helper functions related
to VSX, VMX registers access. This also adds some assembly
helper functions related to VSX and VMX registers.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/ptrace/Makefile    |   2 +-
 .../testing/selftests/powerpc/ptrace/ptrace-vsx.c  | 138 +++++++++++
 .../testing/selftests/powerpc/ptrace/ptrace-vsx.h  | 104 ++++++++
 tools/testing/selftests/powerpc/ptrace/ptrace.S    | 265 +++++++++++++++++++++
 tools/testing/selftests/powerpc/ptrace/ptrace.h    | 119 +++++++++
 5 files changed, 627 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-vsx.c
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-vsx.h

diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
index 5703b68..d6c02ac 100644
--- a/tools/testing/selftests/powerpc/ptrace/Makefile
+++ b/tools/testing/selftests/powerpc/ptrace/Makefile
@@ -1,5 +1,5 @@
 TEST_PROGS := ptrace-ebb ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr \
-ptrace-tar ptrace-tm-tar ptrace-tm-spd-tar
+ptrace-tar ptrace-tm-tar ptrace-tm-spd-tar ptrace-vsx
 
 all: $(TEST_PROGS)
 
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-vsx.c b/tools/testing/selftests/powerpc/ptrace/ptrace-vsx.c
new file mode 100644
index 0000000..a11b9a3
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-vsx.c
@@ -0,0 +1,138 @@
+/*
+ * Ptrace test for VMX/VSX registers
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include "ptrace.h"
+#include "ptrace-vsx.h"
+
+/* Tracer and Tracee Shared Data */
+int shm_id;
+volatile int *cptr, *pptr;
+
+extern void loadvsx(void *p, int tmp);
+extern void storevsx(void *p, int tmp);
+
+unsigned long fp_load[VEC_MAX];
+unsigned long fp_load_new[VEC_MAX];
+unsigned long fp_store[VEC_MAX];
+
+void vsx(void)
+{
+	int ret;
+
+	cptr = (int *)shmat(shm_id, NULL, 0);
+	loadvsx(fp_load, 0);
+
+	while(!cptr[0]);
+	shmdt((void *) cptr);
+
+	storevsx(fp_store, 0);
+	ret = compare_vsx_vmx(fp_store, fp_load_new);
+	if (ret)
+		exit(1);
+	exit(0);
+}
+
+int trace_vsx(pid_t child)
+{
+	unsigned long vsx[VSX_MAX];
+	unsigned long vmx[VMX_MAX + 2][2];
+	int ret;
+
+	sleep(1);
+	ret = start_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_vsx(child, vsx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_vsx(vsx, fp_load);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_vmx(child, vmx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_vmx(vmx, fp_load);
+	if (ret)
+		return TEST_FAIL;
+
+	memset(vsx, 0, sizeof(vsx));
+	memset(vmx, 0, sizeof(vmx));
+	load_vsx_vmx(fp_load_new, vsx, vmx);
+
+	ret = write_vsx(child, vsx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = write_vmx(child, vmx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = stop_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	return TEST_PASS;
+}
+
+int ptrace_vsx(void)
+{
+	pid_t pid;
+	int ret, status, i;
+
+	shm_id = shmget(IPC_PRIVATE, sizeof(int) * 1, 0777|IPC_CREAT);
+
+	for(i = 0; i < VEC_MAX; i++)
+		fp_load[i] = i + rand();
+
+	for(i = 0; i < VEC_MAX; i++)
+		fp_load_new[i] = i + 2 * rand();
+
+	pid = fork();
+	if (pid < 0) {
+		perror("fork() failed");
+		return TEST_FAIL;
+	}
+
+	if (pid == 0)
+		vsx();
+
+	if (pid) {
+		pptr = (int *)shmat(shm_id, NULL, 0);
+		ret = trace_vsx(pid);
+		if (ret) {
+			kill(pid, SIGTERM);
+			return TEST_FAIL;
+		}
+
+		pptr[0] = 1;
+		shmdt((void *)pptr);
+
+		ret = wait(&status);
+		if (ret != pid) {
+			printf("Child's exit status not captured\n");
+			return TEST_FAIL;
+		}
+
+		if (WIFEXITED(status)) {
+			if(WEXITSTATUS(status))
+				return TEST_FAIL;
+		}
+	}
+	return TEST_PASS;
+}
+
+int main(int argc, char *argv[])
+{
+	return test_harness(ptrace_vsx, "ptrace_vsx");
+}
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-vsx.h b/tools/testing/selftests/powerpc/ptrace/ptrace-vsx.h
new file mode 100644
index 0000000..8a3eaae
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-vsx.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#define VEC_MAX 128
+#define VSX_MAX 32
+#define VMX_MAX 32
+
+/*
+ * unsigned long vsx[32]
+ * unsigned long load[128]
+ */
+int validate_vsx(unsigned long *vsx, unsigned long *load)
+{
+	int i;
+
+	for (i = 0; i < VSX_MAX; i++) {
+		if (vsx[i] != load[2 * i + 1]) {
+			printf("vsx[%d]: %lx load[%d] %lx\n", i, vsx[i], 2 * i + 1, load[2 * i + 1]);
+			return TEST_FAIL;
+		}
+	}
+	return TEST_PASS;
+}
+
+/*
+ * unsigned long vmx[32][2]
+ * unsigned long load[128]
+ */
+int validate_vmx(unsigned long vmx[][2], unsigned long *load)
+{
+	int i;
+
+	for (i = 0; i < VMX_MAX; i++) {
+		#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+		if ((vmx[i][0] != load[64 + 2 * i]) || (vmx[i][1] != load[65 + 2 * i])) {
+			printf("vmx[%d][0]: %lx load[%d] %lx\n", i, vmx[i][0], 64 + 2 * i, load[64 + 2 * i]);
+			printf("vmx[%d][1]: %lx load[%d] %lx\n", i, vmx[i][1], 65 + 2 * i, load[65 + 2 * i]);
+			return TEST_FAIL;
+		}
+		#else	/* In LE each value pair is stored in an alternate manner */
+		if ((vmx[i][0] != load[65 + 2 * i]) || (vmx[i][1] != load[64 + 2 * i])) {
+			printf("vmx[%d][0]: %lx load[%d] %lx\n", i, vmx[i][0], 65 + 2 * i, load[65 + 2 * i]);
+			printf("vmx[%d][1]: %lx load[%d] %lx\n", i, vmx[i][1], 64 + 2 * i, load[64 + 2 * i]);
+			return TEST_FAIL;
+		}
+		#endif
+	}
+	return TEST_PASS;
+}
+
+/*
+ * unsigned long store[128]
+ * unsigned long load[128]
+ */
+int compare_vsx_vmx(unsigned long *store, unsigned long *load)
+{
+	int i;
+
+	for (i = 0; i < VSX_MAX; i++) {
+		if (store[1 + 2 * i] != load[1 + 2 * i]) {
+			printf("store[%d]: %lx load[%d] %lx\n", 1 + 2 * i, store[i], 1 + 2 * i, load[i]);
+			return TEST_FAIL;
+		}
+	}
+
+	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
+	for (i = 64; i < VEC_MAX; i++) {
+		if (store[i] != load[i]) {
+			printf("store[%d]: %lx load[%d] %lx\n", i, store[i], i, load[i]);
+			return TEST_FAIL;
+		}
+	}
+	#else	/* In LE each value pair is stored in an alternate manner */
+	for (i = 64; i < VEC_MAX; i++) {
+		if (!(i % 2) && (store[i] != load[i+1])) {
+			printf("store[%d]: %lx load[%d] %lx\n", i, store[i], i+1, load[i+1]);
+			return TEST_FAIL;
+		}
+		if ((i % 2) && (store[i] != load[i-1])) {
+			printf("here store[%d]: %lx load[%d] %lx\n", i, store[i], i-1, load[i-1]);
+			return TEST_FAIL;
+		}
+	}
+	#endif
+	return TEST_PASS;
+}
+
+void load_vsx_vmx(unsigned long *load, unsigned long *vsx, unsigned long vmx[][2])
+{
+	int i;
+
+	for (i = 0; i < VSX_MAX; i++)
+		vsx[i] = load[1 + 2 * i];
+
+	for (i = 0; i < VMX_MAX; i++) {
+		vmx[i][0] = load[64 + 2 * i];
+		vmx[i][1] = load[65 + 2 * i];
+	}
+}
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace.S b/tools/testing/selftests/powerpc/ptrace/ptrace.S
index 193beea..2407792 100644
--- a/tools/testing/selftests/powerpc/ptrace/ptrace.S
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace.S
@@ -129,3 +129,268 @@ FUNC_START(store_fpr)
 	stfs 31, 31*4(3)
 	blr
 FUNC_END(store_fpr)
+
+/* VMX/VSX registers - unsigned long buf[128] */
+FUNC_START(loadvsx)
+	lis	4, 0
+	LXVD2X	(0,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(1,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(2,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(3,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(4,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(5,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(6,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(7,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(8,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(9,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(10,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(11,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(12,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(13,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(14,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(15,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(16,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(17,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(18,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(19,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(20,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(21,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(22,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(23,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(24,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(25,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(26,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(27,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(28,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(29,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(30,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(31,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(32,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(33,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(34,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(35,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(36,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(37,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(38,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(39,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(40,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(41,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(42,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(43,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(44,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(45,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(46,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(47,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(48,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(49,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(50,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(51,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(52,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(53,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(54,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(55,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(56,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(57,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(58,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(59,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(60,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(61,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(62,(4),(3))
+	addi	4, 4, 16
+	LXVD2X	(63,(4),(3))
+	blr
+FUNC_END(loadvsx)
+
+FUNC_START(storevsx)
+	lis	4, 0
+	STXVD2X	(0,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(1,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(2,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(3,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(4,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(5,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(6,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(7,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(8,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(9,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(10,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(11,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(12,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(13,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(14,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(15,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(16,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(17,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(18,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(19,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(20,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(21,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(22,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(23,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(24,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(25,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(26,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(27,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(28,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(29,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(30,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(31,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(32,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(33,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(34,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(35,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(36,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(37,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(38,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(39,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(40,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(41,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(42,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(43,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(44,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(45,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(46,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(47,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(48,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(49,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(50,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(51,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(52,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(53,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(54,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(55,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(56,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(57,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(58,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(59,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(60,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(61,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(62,(4),(3))
+	addi	4, 4, 16
+	STXVD2X	(63,(4),(3))
+	blr
+FUNC_END(storevsx)
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace.h b/tools/testing/selftests/powerpc/ptrace/ptrace.h
index a5efdee..3793ff6 100644
--- a/tools/testing/selftests/powerpc/ptrace/ptrace.h
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace.h
@@ -544,6 +544,125 @@ int write_ckpt_gpr(pid_t child, unsigned long val)
 	return TEST_PASS;
 }
 
+/* VMX */
+int show_vmx(pid_t child, unsigned long vmx[][2])
+{
+	int ret;
+
+	ret = ptrace(PTRACE_GETVRREGS, child, 0, vmx);
+	if (ret) {
+		perror("ptrace(PTRACE_GETVRREGS) failed");
+		return TEST_FAIL;
+	}
+	return TEST_PASS;
+}
+
+int show_vmx_ckpt(pid_t child, unsigned long vmx[][2])
+{
+	unsigned long regs[34][2];
+	struct iovec iov;
+	int ret;
+
+	iov.iov_base = (u64 *) regs;
+	iov.iov_len = sizeof(regs);
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_CVMX, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET, NT_PPC_TM_CVMX) failed");
+		return TEST_FAIL;
+	}
+	memcpy(vmx, regs, sizeof(regs));
+	return TEST_PASS;
+}
+
+
+int write_vmx(pid_t child, unsigned long vmx[][2])
+{
+	int ret;
+
+	ret = ptrace(PTRACE_SETVRREGS, child, 0, vmx);
+	if (ret) {
+		perror("ptrace(PTRACE_SETVRREGS) failed");
+		return TEST_FAIL;
+	}
+	return TEST_PASS;
+}
+
+int write_vmx_ckpt(pid_t child, unsigned long vmx[][2])
+{
+	unsigned long regs[34][2];
+	struct iovec iov;
+	int ret;
+
+	memcpy(regs, vmx, sizeof(regs));
+	iov.iov_base = (u64 *) regs;
+	iov.iov_len = sizeof(regs);
+	ret = ptrace(PTRACE_SETREGSET, child, NT_PPC_TM_CVMX, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_SETREGSET, NT_PPC_TM_CVMX) failed");
+		return TEST_FAIL;
+	}
+	return TEST_PASS;
+}
+
+/* VSX */
+int show_vsx(pid_t child, unsigned long *vsx)
+{
+	int ret;
+
+	ret = ptrace(PTRACE_GETVSRREGS, child, 0, vsx);
+	if (ret) {
+		perror("ptrace(PTRACE_GETVSRREGS) failed");
+		return TEST_FAIL;
+	}
+	return TEST_PASS;
+}
+
+int show_vsx_ckpt(pid_t child, unsigned long *vsx)
+{
+	unsigned long regs[32];
+	struct iovec iov;
+	int ret;
+
+	iov.iov_base = (u64 *) regs;
+	iov.iov_len = sizeof(regs);
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_CVSX, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET, NT_PPC_TM_CVSX) failed");
+		return TEST_FAIL;
+	}
+	memcpy(vsx, regs, sizeof(regs));
+	return TEST_PASS;
+}
+
+int write_vsx(pid_t child, unsigned long *vsx)
+{
+	int ret;
+
+	ret = ptrace(PTRACE_SETVSRREGS, child, 0, vsx);
+	if (ret) {
+		perror("ptrace(PTRACE_SETVSRREGS) failed");
+		return TEST_FAIL;
+	}
+	return TEST_PASS;
+}
+
+int write_vsx_ckpt(pid_t child, unsigned long *vsx)
+{
+	unsigned long regs[32];
+	struct iovec iov;
+	int ret;
+
+	memcpy(regs, vsx, sizeof(regs));
+	iov.iov_base = (u64 *) regs;
+	iov.iov_len = sizeof(regs);
+	ret = ptrace(PTRACE_SETREGSET, child, NT_PPC_TM_CVSX, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_SETREGSET, NT_PPC_TM_CVSX) failed");
+		return TEST_FAIL;
+	}
+	return TEST_PASS;
+}
+
 /* Analyse TEXASR after TM failure */
 inline unsigned long get_tfiar(void)
 {
-- 
2.1.0

[PATCH V10 25/28] selftests, powerpc: Add ptrace tests for VSX, VMX registers in TM

[Anshuman Khandual]

This patch adds ptrace interface test for VSX, VMX registers
inside TM context. This also adds ptrace interface based helper
functions related to chckpointed VSX, VMX registers access.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/ptrace/Makefile    |   3 +-
 .../selftests/powerpc/ptrace/ptrace-tm-vsx.c       | 196 +++++++++++++++++++++
 2 files changed, 198 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c

diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
index d6c02ac..f77a493 100644
--- a/tools/testing/selftests/powerpc/ptrace/Makefile
+++ b/tools/testing/selftests/powerpc/ptrace/Makefile
@@ -1,5 +1,6 @@
 TEST_PROGS := ptrace-ebb ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr \
-ptrace-tar ptrace-tm-tar ptrace-tm-spd-tar ptrace-vsx
+ptrace-tar ptrace-tm-tar ptrace-tm-spd-tar ptrace-vsx ptrace-tm-vsx
+
 
 all: $(TEST_PROGS)
 
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c
new file mode 100644
index 0000000..7ab46d7
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c
@@ -0,0 +1,196 @@
+/*
+ * Ptrace test for VMX/VSX registers in the TM context
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include "ptrace.h"
+#include "ptrace-vsx.h"
+
+int shm_id;
+volatile int *cptr, *pptr;
+
+extern void loadvsx(void *p, int tmp);
+extern void storevsx(void *p, int tmp);
+
+unsigned long fp_load[VEC_MAX];
+unsigned long fp_store[VEC_MAX];
+unsigned long fp_load_ckpt[VEC_MAX];
+unsigned long fp_load_ckpt_new[VEC_MAX];
+
+__attribute__((used)) void load_vsx(void)
+{
+	loadvsx(fp_load, 0);
+}
+
+__attribute__((used)) void load_vsx_ckpt(void)
+{
+	loadvsx(fp_load_ckpt, 0);
+}
+
+void tm_vsx(void)
+{
+	unsigned long result, texasr;
+	int ret;
+
+	cptr = (int *)shmat(shm_id, NULL, 0);
+trans:
+	asm __volatile__(
+		"bl load_vsx_ckpt;"
+
+		"1: ;"
+		TBEGIN
+		"beq 2f;"
+
+		"bl load_vsx;"
+		"b .;"
+
+		TEND
+		"li 0, 0;"
+		"ori %[res], 0, 0;"
+		"b 3f;"
+
+		"2: ;"
+		"li 0, 1;"
+		"ori %[res], 0, 0;"
+		"mfspr %[texasr], %[sprn_texasr];"
+
+		"3: ;"
+		: [res] "=r" (result), [texasr] "=r" (texasr)
+		: [fp_load] "r" (fp_load), [fp_load_ckpt] "r" (fp_load_ckpt), [sprn_texasr] "i"  (SPRN_TEXASR)
+		: "memory", "r0", "r1", "r2", "r3", "r4", "r8", "r9", "r10", "r11"
+		);
+
+	if (result) {
+		if (!cptr[0])
+			goto trans;
+		shmdt((void *)cptr);
+
+		storevsx(fp_store, 0);
+		ret = compare_vsx_vmx(fp_store, fp_load_ckpt_new);
+		if (ret)
+			exit(1);
+		exit(0);
+	}
+	exit(1);
+}
+
+int trace_tm_vsx(pid_t child)
+{
+	unsigned long vsx[VSX_MAX];
+	unsigned long vmx[VMX_MAX + 2][2];
+	int ret;
+
+	sleep(1);
+	ret = start_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_vsx(child, vsx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_vsx(vsx, fp_load);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_vmx(child, vmx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_vmx(vmx, fp_load);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_vsx_ckpt(child, vsx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_vsx(vsx, fp_load_ckpt);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_vmx_ckpt(child, vmx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_vmx(vmx, fp_load_ckpt);
+	if (ret)
+		return TEST_FAIL;
+
+	memset(vsx, 0, sizeof(vsx));
+	memset(vmx, 0, sizeof(vmx));
+
+	load_vsx_vmx(fp_load_ckpt_new, vsx, vmx);
+
+	ret = write_vsx_ckpt(child, vsx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = write_vmx_ckpt(child, vmx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = stop_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	return TEST_PASS;
+}
+
+int ptrace_tm_vsx(void)
+{
+	pid_t pid;
+	int ret, status, i;
+
+	SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
+	shm_id = shmget(IPC_PRIVATE, sizeof(int) * 1, 0777|IPC_CREAT);
+
+	for(i = 0; i < 128; i++) {
+		fp_load[i] = 1 + rand();
+		fp_load_ckpt[i] = 1 + 2 * rand();
+		fp_load_ckpt_new[i] = 1 + 3 * rand();
+	}
+
+	pid = fork();
+	if (pid < 0) {
+		perror("fork() failed");
+		return TEST_FAIL;
+	}
+
+	if (pid == 0)
+		tm_vsx();
+
+	if (pid) {
+		pptr = (int *)shmat(shm_id, NULL, 0);
+		ret = trace_tm_vsx(pid);
+		if (ret) {
+			kill(pid, SIGKILL);
+			return TEST_FAIL;
+		}
+
+		pptr[0] = 1;
+		shmdt((void *)pptr);
+		ret = wait(&status);
+		if (ret != pid) {
+			printf("Child's exit status not captured\n");
+			return TEST_FAIL;
+		}
+
+		if (WIFEXITED(status)) {
+			if(WEXITSTATUS(status))
+				return TEST_FAIL;
+		}
+		return TEST_PASS;
+	}
+	return TEST_PASS;
+}
+
+int main(int argc, char *argv[])
+{
+	return test_harness(ptrace_tm_vsx, "ptrace_tm_vsx");
+}
-- 
2.1.0

[PATCH V10 26/28] selftests, powerpc: Add ptrace tests for VSX, VMX registers in suspended TM

[Anshuman Khandual]

This patch adds ptrace interface test for VSX, VMX registers
inside suspended TM context.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/ptrace/Makefile    |   3 +-
 .../selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c   | 212 +++++++++++++++++++++
 2 files changed, 214 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c

diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
index f77a493..1f38b74 100644
--- a/tools/testing/selftests/powerpc/ptrace/Makefile
+++ b/tools/testing/selftests/powerpc/ptrace/Makefile
@@ -1,5 +1,6 @@
 TEST_PROGS := ptrace-ebb ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr \
-ptrace-tar ptrace-tm-tar ptrace-tm-spd-tar ptrace-vsx ptrace-tm-vsx
+ptrace-tar ptrace-tm-tar ptrace-tm-spd-tar ptrace-vsx ptrace-tm-vsx \
+ptrace-tm-spd-vsx
 
 
 all: $(TEST_PROGS)
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c
new file mode 100644
index 0000000..e52a309
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c
@@ -0,0 +1,212 @@
+/*
+ * Ptrace test for VMX/VSX registers in the TM Suspend context
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include "ptrace.h"
+#include "ptrace-vsx.h"
+
+int shm_id;
+volatile int *cptr, *pptr;
+
+extern void loadvsx(void *p, int tmp);
+extern void storevsx(void *p, int tmp);
+
+unsigned long fp_load[VEC_MAX];
+unsigned long fp_load_new[VEC_MAX];
+unsigned long fp_store[VEC_MAX];
+unsigned long fp_load_ckpt[VEC_MAX];
+unsigned long fp_load_ckpt_new[VEC_MAX];
+
+__attribute__((used)) void load_vsx(void)
+{
+	loadvsx(fp_load, 0);
+}
+
+__attribute__((used)) void load_vsx_new(void)
+{
+	loadvsx(fp_load_new, 0);
+}
+
+__attribute__((used)) void load_vsx_ckpt(void)
+{
+	loadvsx(fp_load_ckpt, 0);
+}
+
+__attribute__((used)) void wait_parent(void)
+{
+	while(!cptr[1]);
+}
+
+void tm_spd_vsx(void)
+{
+	unsigned long result, texasr;
+	int ret;
+
+	cptr = (int *)shmat(shm_id, NULL, 0);
+trans:
+	asm __volatile__(
+		"bl load_vsx_ckpt;"
+
+		"1: ;"
+		TBEGIN
+		"beq 2f;"
+
+		"bl load_vsx_new;"
+		TSUSPEND
+		"bl load_vsx;"
+		"bl wait_parent;"
+		TRESUME
+
+		TEND
+		"li 0, 0;"
+		"ori %[res], 0, 0;"
+		"b 3f;"
+
+		"2: ;"
+		"li 0, 1;"
+		"ori %[res], 0, 0;"
+		"mfspr %[texasr], %[sprn_texasr];"
+
+		"3: ;"
+		: [res] "=r" (result), [texasr] "=r" (texasr)
+		: [fp_load] "r" (fp_load), [fp_load_ckpt] "r" (fp_load_ckpt), [sprn_texasr] "i"  (SPRN_TEXASR)
+		: "memory", "r0", "r1", "r2", "r3", "r4", "r8", "r9", "r10", "r11"
+		);
+
+	if (result) {
+		if (!cptr[0])
+			goto trans;
+		shmdt((void *)cptr);
+
+		storevsx(fp_store, 0);
+		ret = compare_vsx_vmx(fp_store, fp_load_ckpt_new);
+		if (ret)
+			exit(1);
+		exit(0);
+	}
+	exit(1);
+}
+
+int trace_tm_spd_vsx(pid_t child)
+{
+	unsigned long vsx[VSX_MAX];
+	unsigned long vmx[VMX_MAX + 2][2];
+	int ret;
+
+	sleep(1);
+	ret = start_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_vsx(child, vsx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_vsx(vsx, fp_load);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_vmx(child, vmx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_vmx(vmx, fp_load);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_vsx_ckpt(child, vsx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_vsx(vsx, fp_load_ckpt);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_vmx_ckpt(child, vmx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = validate_vmx(vmx, fp_load_ckpt);
+	if (ret)
+		return TEST_FAIL;
+
+	memset(vsx, 0, sizeof(vsx));
+	memset(vmx, 0, sizeof(vmx));
+
+	load_vsx_vmx(fp_load_ckpt_new, vsx, vmx);
+
+	ret = write_vsx_ckpt(child, vsx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = write_vmx_ckpt(child, vmx);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = stop_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	return TEST_PASS;
+}
+
+int ptrace_tm_spd_vsx(void)
+{
+	pid_t pid;
+	int ret, status, i;
+
+	SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
+	shm_id = shmget(IPC_PRIVATE, sizeof(int) * 2, 0777|IPC_CREAT);
+
+	for(i = 0; i < 128; i++) {
+		fp_load[i] = 1 + rand();
+		fp_load_new[i] = 1 + 2 * rand();
+		fp_load_ckpt[i] = 1 + 3 * rand();
+		fp_load_ckpt_new[i] = 1 + 4 * rand();
+	}
+
+	pid = fork();
+	if (pid < 0) {
+		perror("fork() failed");
+		return TEST_FAIL;
+	}
+
+	if (pid == 0)
+		tm_spd_vsx();
+
+	if (pid) {
+		pptr = (int *)shmat(shm_id, NULL, 0);
+		ret = trace_tm_spd_vsx(pid);
+		if (ret) {
+			kill(pid, SIGKILL);
+			return TEST_FAIL;
+		}
+
+		pptr[0] = 1;
+		pptr[1] = 1;
+		shmdt((void *)pptr);
+		ret = wait(&status);
+		if (ret != pid) {
+			printf("Child's exit status not captured\n");
+			return TEST_FAIL;
+		}
+
+		if (WIFEXITED(status)) {
+			if(WEXITSTATUS(status))
+				return TEST_FAIL;
+		}
+		return TEST_PASS;
+	}
+	return TEST_PASS;
+}
+
+int main(int argc, char *argv[])
+{
+	return test_harness(ptrace_tm_spd_vsx, "ptrace_tm_spd_vsx");
+}
-- 
2.1.0

[PATCH V10 27/28] selftests, powerpc: Add ptrace tests for TM SPR registers

[Anshuman Khandual]

This patch adds ptrace interface test for TM SPR registers. This
also adds ptrace interface based helper functions related to TM
SPR registers access.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/ptrace/Makefile    |   2 +-
 .../selftests/powerpc/ptrace/ptrace-tm-spr.c       | 157 +++++++++++++++++++++
 tools/testing/selftests/powerpc/ptrace/ptrace.h    |  35 +++++
 3 files changed, 193 insertions(+), 1 deletion(-)
 create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spr.c

diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
index 1f38b74..05a3975 100644
--- a/tools/testing/selftests/powerpc/ptrace/Makefile
+++ b/tools/testing/selftests/powerpc/ptrace/Makefile
@@ -1,6 +1,6 @@
 TEST_PROGS := ptrace-ebb ptrace-gpr ptrace-tm-gpr ptrace-tm-spd-gpr \
 ptrace-tar ptrace-tm-tar ptrace-tm-spd-tar ptrace-vsx ptrace-tm-vsx \
-ptrace-tm-spd-vsx
+ptrace-tm-spd-vsx ptrace-tm-spr
 
 
 all: $(TEST_PROGS)
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spr.c b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spr.c
new file mode 100644
index 0000000..d70ffb2
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace-tm-spr.c
@@ -0,0 +1,157 @@
+/*
+ * Ptrace test TM SPR registers
+ *
+ * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include "ptrace.h"
+
+/* Tracee and tracer shared data */
+struct shared {
+	int flag;
+	struct tm_spr_regs regs;
+};
+unsigned long tfhar;
+
+int shm_id;
+volatile struct shared *cptr, *pptr;
+
+#define TM_SCHED	0xde0000018c000001
+#define TM_KVM_SCHED	0xe0000001ac000001
+
+int validate_tm_spr(struct tm_spr_regs *regs)
+{
+	if (regs->tm_tfhar != (tfhar - 32))
+		return TEST_FAIL;
+
+	if ((regs->tm_texasr != TM_SCHED) && (regs->tm_texasr != TM_KVM_SCHED))
+		return TEST_FAIL;
+
+	if ((regs->tm_texasr == TM_KVM_SCHED) && (regs->tm_tfiar != 0))
+		return TEST_FAIL;
+
+	return TEST_PASS;
+}
+
+void tm_spr(void)
+{
+	unsigned long result, texasr;
+	int ret;
+
+	cptr = (struct shared *)shmat(shm_id, NULL, 0);
+trans:
+	asm __volatile__(
+		"1: ;"
+		TBEGIN
+		"beq 2f;"
+
+		"b .;"
+
+		TEND
+		"li 0, 0;"
+		"ori %[res], 0, 0;"
+		"b 3f;"
+
+		"2: ;"
+		"mflr 31;"
+		"bl 4f;"	/* $ = TFHAR + 2 */
+		"4: ;"
+		"mflr %[tfhar];"
+		"mtlr 31;"
+
+		"li 0, 1;"
+		"ori %[res], 0, 0;"
+		"mfspr %[texasr], %[sprn_texasr];"
+
+		"3: ;"
+		: [tfhar] "=r" (tfhar), [res] "=r" (result), [texasr] "=r" (texasr)
+		: [sprn_texasr] "i"  (SPRN_TEXASR)
+		: "memory", "r0", "r1", "r2", "r3", "r4", "r8", "r9", "r10", "r11"
+		);
+
+	if (result) {
+		if (!cptr->flag)
+			goto trans;
+
+		ret = validate_tm_spr((struct tm_spr_regs *)&cptr->regs);
+		shmdt((void *)cptr);
+		if (ret)
+			exit(1);
+		exit(0);
+	}
+	shmdt((void *)cptr);
+	exit(1);
+}
+
+int trace_tm_spr(pid_t child)
+{
+	int ret;
+
+	sleep(1);
+	ret = start_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	ret = show_tm_spr(child, (struct tm_spr_regs *)&pptr->regs);
+	if (ret)
+		return TEST_FAIL;
+
+	printf("TFHAR: %lx TEXASR: %lx TFIAR: %lx\n", pptr->regs.tm_tfhar,
+				pptr->regs.tm_texasr, pptr->regs.tm_tfiar);
+
+	ret = stop_trace(child);
+	if (ret)
+		return TEST_FAIL;
+
+	return TEST_PASS;
+}
+
+int ptrace_tm_spr(void)
+{
+	pid_t pid;
+	int ret, status;
+
+	SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
+	shm_id = shmget(IPC_PRIVATE, sizeof(struct shared), 0777|IPC_CREAT);
+	pid = fork();
+	if (pid < 0) {
+		perror("fork() failed");
+		return TEST_FAIL;
+	}
+
+	if (pid == 0)
+		tm_spr();
+
+	if (pid) {
+		pptr = (struct shared *)shmat(shm_id, NULL, 0);
+		ret = trace_tm_spr(pid);
+		if (ret) {
+			kill(pid, SIGKILL);
+			return TEST_FAIL;
+		}
+
+		pptr->flag = 1;
+		shmdt((void *)pptr);
+		ret = wait(&status);
+		if (ret != pid) {
+			printf("Child's exit status not captured\n");
+			return TEST_FAIL;
+		}
+
+		if (WIFEXITED(status)) {
+			if(WEXITSTATUS(status))
+				return TEST_FAIL;
+		}
+		return TEST_PASS;
+	}
+	return TEST_PASS;
+}
+
+int main(int argc, char *argv[])
+{
+	return test_harness(ptrace_tm_spr, "ptrace_tm_spr");
+}
diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace.h b/tools/testing/selftests/powerpc/ptrace/ptrace.h
index 3793ff6..fe655de0 100644
--- a/tools/testing/selftests/powerpc/ptrace/ptrace.h
+++ b/tools/testing/selftests/powerpc/ptrace/ptrace.h
@@ -83,6 +83,11 @@ struct fpr_regs {
 	unsigned long fpscr;
 };
 
+struct tm_spr_regs {
+	unsigned long tm_tfhar;
+	unsigned long tm_texasr;
+	unsigned long tm_tfiar;
+};
 
 /* Basic ptrace operations */
 int start_trace(pid_t child)
@@ -663,6 +668,36 @@ int write_vsx_ckpt(pid_t child, unsigned long *vsx)
 	return TEST_PASS;
 }
 
+/* TM SPR */
+int show_tm_spr(pid_t child, struct tm_spr_regs *out)
+{
+	struct tm_spr_regs *regs;
+	struct iovec iov;
+	int ret;
+
+	regs = (struct tm_spr_regs *) malloc(sizeof(struct tm_spr_regs));
+	if (!regs) {
+		perror("malloc() failed");
+		return TEST_FAIL;
+	}
+
+	iov.iov_base = (u64 *) regs;
+	iov.iov_len = sizeof(struct tm_spr_regs);
+
+	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_SPR, &iov);
+	if (ret) {
+		perror("ptrace(PTRACE_GETREGSET) failed");
+		return TEST_FAIL;
+	}
+
+	if (out)
+		memcpy(out, regs, sizeof(struct tm_spr_regs));
+
+	return TEST_PASS;
+}
+
+
+
 /* Analyse TEXASR after TM failure */
 inline unsigned long get_tfiar(void)
 {
-- 
2.1.0

[PATCH V10 28/28] selftests, powerpc: Add .gitignore file for ptrace executables

[Anshuman Khandual]

This patch adds a .gitignore file for all the executables in
the ptrace test directory thus making invisible with git status
query.

Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
---
 tools/testing/selftests/powerpc/ptrace/.gitignore | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 tools/testing/selftests/powerpc/ptrace/.gitignore

diff --git a/tools/testing/selftests/powerpc/ptrace/.gitignore b/tools/testing/selftests/powerpc/ptrace/.gitignore
new file mode 100644
index 0000000..bdf3566
--- /dev/null
+++ b/tools/testing/selftests/powerpc/ptrace/.gitignore
@@ -0,0 +1,11 @@
+ptrace-ebb
+ptrace-gpr
+ptrace-tm-gpr
+ptrace-tm-spd-gpr
+ptrace-tar
+ptrace-tm-tar
+ptrace-tm-spd-tar
+ptrace-vsx
+ptrace-tm-vsx
+ptrace-tm-spd-vsx
+ptrace-tm-spr
-- 
2.1.0

Re: [PATCH V10 03/28] powerpc, ptrace: Enable in transaction NT_PRFPREG ptrace requests

[Denis Kirjanov]

On 2/16/16, Anshuman Khandual <khandual@linux.vnet.ibm.com> wrote:
> This patch enables in transaction NT_PRFPREG ptrace requests.
> The function fpr_get which gets the running value of all FPR
> registers and the function fpr_set which sets the running
> value of of all FPR registers work on the running set of FPR
> registers whose location will be different if transaction is
> active. This patch makes these functions adapt to situations
> when the transaction is active.
>
> Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
> ---
>  arch/powerpc/kernel/ptrace.c | 93
> ++++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 89 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
> index 30a03c0..547a979 100644
> --- a/arch/powerpc/kernel/ptrace.c
> +++ b/arch/powerpc/kernel/ptrace.c
> @@ -358,6 +358,29 @@ static int gpr_set(struct task_struct *target, const
> struct user_regset *regset,
>  	return ret;
>  }
>
> +/*
> + * When the transaction is active, 'transact_fp' holds the current running
> + * value of all FPR registers and 'fp_state' holds the last checkpointed
> + * value of all FPR registers for the current transaction. When transaction
> + * is not active 'fp_state' holds the current running state of all the FPR
> + * registers. So this function which returns the current running values of
> + * all the FPR registers, needs to know whether any transaction is active
> + * or not.
> + *
> + * Userspace interface buffer layout:
> + *
> + * struct data {
> + *	u64	fpr[32];
> + *	u64	fpscr;
> + * };
> + *
> + * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM
> + * which determines the final code in this function. All the combinations
> of
> + * these two config options are possible except the one below as
> transactional
> + * memory config pulls in CONFIG_VSX automatically.
> + *
> + *	!defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
> + */
>  static int fpr_get(struct task_struct *target, const struct user_regset
> *regset,
>  		   unsigned int pos, unsigned int count,
>  		   void *kbuf, void __user *ubuf)
> @@ -368,14 +391,31 @@ static int fpr_get(struct task_struct *target, const
> struct user_regset *regset,
>  #endif
>  	flush_fp_to_thread(target);
>
> -#ifdef CONFIG_VSX
> +#if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
> +	/* copy to local buffer then write that out */
> +	if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
> +		flush_altivec_to_thread(target);
> +		flush_tmregs_to_thread(target);
> +		for (i = 0; i < 32 ; i++)
use ELF_NFPREG

> +			buf[i] = target->thread.TS_TRANS_FPR(i);
> +		buf[32] = target->thread.transact_fp.fpscr;
> +	} else {
> +		for (i = 0; i < 32 ; i++)
> +			buf[i] = target->thread.TS_FPR(i);
> +		buf[32] = target->thread.fp_state.fpscr;
> +	}
> +	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
> +#endif
> +
> +#if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
>  	/* copy to local buffer then write that out */
>  	for (i = 0; i < 32 ; i++)
>  		buf[i] = target->thread.TS_FPR(i);
>  	buf[32] = target->thread.fp_state.fpscr;
>  	return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
> +#endif
>
> -#else
> +#if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
>  	BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
>  		     offsetof(struct thread_fp_state, fpr[32][0]));
>
> @@ -384,6 +424,29 @@ static int fpr_get(struct task_struct *target, const
> struct user_regset *regset,
>  #endif
>  }
>
> +/*
> + * When the transaction is active, 'transact_fp' holds the current running
> + * value of all FPR registers and 'fp_state' holds the last checkpointed
> + * value of all FPR registers for the current transaction. When transaction
> + * is not active 'fp_state' holds the current running state of all the FPR
> + * registers. So this function which setss the current running values of
> + * all the FPR registers, needs to know whether any transaction is active
> + * or not.
> + *
> + * Userspace interface buffer layout:
> + *
> + * struct data {
> + *	u64	fpr[32];
> + *	u64	fpscr;
> + * };
> + *
> + * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM
> + * which determines the final code in this function. All the combinations
> of
> + * these two config options are possible except the one below as
> transactional
> + * memory config pulls in CONFIG_VSX automatically.
> + *
> + *	!defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
> + */
>  static int fpr_set(struct task_struct *target, const struct user_regset
> *regset,
>  		   unsigned int pos, unsigned int count,
>  		   const void *kbuf, const void __user *ubuf)
> @@ -394,7 +457,27 @@ static int fpr_set(struct task_struct *target, const
> struct user_regset *regset,
>  #endif
>  	flush_fp_to_thread(target);
>
> -#ifdef CONFIG_VSX
> +#if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
> +	/* copy to local buffer then write that out */
> +	i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
> +	if (i)
> +		return i;
> +
> +	if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
> +		flush_altivec_to_thread(target);
> +		flush_tmregs_to_thread(target);
> +		for (i = 0; i < 32 ; i++)
> +			target->thread.TS_TRANS_FPR(i) = buf[i];
> +		target->thread.transact_fp.fpscr = buf[32];
> +	} else {
> +		for (i = 0; i < 32 ; i++)
> +			target->thread.TS_FPR(i) = buf[i];
> +		target->thread.fp_state.fpscr = buf[32];
> +	}
> +	return 0;
> +#endif
> +
> +#if defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
>  	/* copy to local buffer then write that out */
>  	i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
>  	if (i)
> @@ -403,7 +486,9 @@ static int fpr_set(struct task_struct *target, const
> struct user_regset *regset,
>  		target->thread.TS_FPR(i) = buf[i];
>  	target->thread.fp_state.fpscr = buf[32];
>  	return 0;
> -#else
> +#endif
> +
> +#if !defined(CONFIG_VSX) && !defined(CONFIG_PPC_TRANSACTIONAL_MEM)
>  	BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
>  		     offsetof(struct thread_fp_state, fpr[32][0]));
>
> --
> 2.1.0
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev

Re: [PATCH V10 03/28] powerpc, ptrace: Enable in transaction NT_PRFPREG ptrace requests

[Michael Ellerman]

On Tue, 2016-02-16 at 12:09 +0300, Denis Kirjanov wrote:

> On 2/16/16, Anshuman Khandual <khandual@linux.vnet.ibm.com> wrote:

> > This patch enables in transaction NT_PRFPREG ptrace requests.
> > The function fpr_get which gets the running value of all FPR
> > registers and the function fpr_set which sets the running
> > value of of all FPR registers work on the running set of FPR
> > registers whose location will be different if transaction is
> > active. This patch makes these functions adapt to situations
> > when the transaction is active.
> > 
> > Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
> > ---
> >  arch/powerpc/kernel/ptrace.c | 93
> > ++++++++++++++++++++++++++++++++++++++++++--
> >  1 file changed, 89 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
> > index 30a03c0..547a979 100644
> > --- a/arch/powerpc/kernel/ptrace.c
> > +++ b/arch/powerpc/kernel/ptrace.c
> > @@ -358,6 +358,29 @@ static int gpr_set(struct task_struct *target, const
> > struct user_regset *regset,
> >  	return ret;
> >  }
> > 
> > +/*
> > + * When the transaction is active, 'transact_fp' holds the current running
> > + * value of all FPR registers and 'fp_state' holds the last checkpointed
> > + * value of all FPR registers for the current transaction. When transaction
> > + * is not active 'fp_state' holds the current running state of all the FPR
> > + * registers. So this function which returns the current running values of
> > + * all the FPR registers, needs to know whether any transaction is active
> > + * or not.
> > + *
> > + * Userspace interface buffer layout:
> > + *
> > + * struct data {
> > + *	u64	fpr[32];
> > + *	u64	fpscr;
> > + * };
> > + *
> > + * There are two config options CONFIG_VSX and CONFIG_PPC_TRANSACTIONAL_MEM
> > + * which determines the final code in this function. All the combinations
> > of
> > + * these two config options are possible except the one below as
> > transactional
> > + * memory config pulls in CONFIG_VSX automatically.
> > + *
> > + *	!defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
> > + */
> >  static int fpr_get(struct task_struct *target, const struct user_regset
> > *regset,
> >  		   unsigned int pos, unsigned int count,
> >  		   void *kbuf, void __user *ubuf)
> > @@ -368,14 +391,31 @@ static int fpr_get(struct task_struct *target, const
> > struct user_regset *regset,
> >  #endif
> >  	flush_fp_to_thread(target);
> > 
> > -#ifdef CONFIG_VSX
> > +#if defined(CONFIG_VSX) && defined(CONFIG_PPC_TRANSACTIONAL_MEM)
> > +	/* copy to local buffer then write that out */
> > +	if (MSR_TM_ACTIVE(target->thread.regs->msr)) {
> > +		flush_altivec_to_thread(target);
> > +		flush_tmregs_to_thread(target);
> > +		for (i = 0; i < 32 ; i++)

> use ELF_NFPREG

> > +			buf[i] = target->thread.TS_TRANS_FPR(i);
> > +		buf[32] = target->thread.transact_fp.fpscr;

#define ELF_NFPREG	33	/* includes fpscr */

So it's not what he wants here. Unless you mean that he should use i < ELF_NFPREG - 1; ?

We already have several loops over the 32 fprs, I don't think hiding the "32"
behind a macro really buys us anything.

cheers

Re: [PATCH V10 02/28] powerpc, process: Add the function flush_tmregs_to_thread

[Cyril Bur]

On Tue, 16 Feb 2016 14:29:32 +0530
Anshuman Khandual <khandual@linux.vnet.ibm.com> wrote:

> This patch creates a function flush_tmregs_to_thread which
> will then be used by subsequent patches in this series. The
> function checks for self tracing ptrace interface attempts
> while in the TM context and logs appropriate warning message.
> 

Hi Anshuman,

You'll have to bare with me, my ptrace knowledge is non existent so you might
have to walk me though some aspects.

I have been playing with FPU/VMX and VSX saving so I thought I'd take a look.

> Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
> ---
>  arch/powerpc/include/asm/switch_to.h |  8 ++++++++
>  arch/powerpc/kernel/process.c        | 20 ++++++++++++++++++++
>  2 files changed, 28 insertions(+)
> 
> diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h
> index 5b268b6..7b297bf 100644
> --- a/arch/powerpc/include/asm/switch_to.h
> +++ b/arch/powerpc/include/asm/switch_to.h
> @@ -70,6 +70,14 @@ static inline void disable_kernel_spe(void)
>  }
>  #endif
>  
> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> +extern void flush_tmregs_to_thread(struct task_struct *);
> +#else
> +static inline void flush_tmregs_to_thread(struct task_struct *t)
> +{
> +}
> +#endif
> +
>  static inline void clear_task_ebb(struct task_struct *t)
>  {
>  #ifdef CONFIG_PPC_BOOK3S_64
> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
> index dccc87e..2c4fa7f 100644
> --- a/arch/powerpc/kernel/process.c
> +++ b/arch/powerpc/kernel/process.c
> @@ -918,6 +918,26 @@ static inline void restore_sprs(struct thread_struct *old_thread,
>  #endif
>  }
>  



> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> +void flush_tmregs_to_thread(struct task_struct *tsk)
> +{
> +	/*
> +	 * Process self tracing is not yet supported through
> +	 * ptrace interface. Ptrace generic code should have
> +	 * prevented this from happening in the first place.
> +	 * Warn once here with the message, if some how it
> +	 * is attempted.
> +	 */
> +	WARN_ONCE(tsk == current,
> +		"Not expecting ptrace on self: TM regs may be incorrect\n");
> +
> +	/*
> +	 * If task is not current, it should have been flushed
> +	 * already to it's thread_struct during __switch_to().
> +	 */

I totally agree except this highlights something that I notice in subsequent
patches, and existing code. All the *_{get,set}() functions call
flush_*_to_thread() when, as per your comment (and my understanding of task
switching) there really shouldn't be a need to do that. My only thought is that
this could be a relic of uniprocessor days when it would have been necessary but
Anton recently stripped that out. Are you able to shed some light here?

The reason I ask is that if the flush_*_to_thread() calls ARE actually
important then I worry that this function is inadequate...

> +}
> +#endif
> +
>  struct task_struct *__switch_to(struct task_struct *prev,
>  	struct task_struct *new)
>  {

Re: [PATCH V10 17/28] selftests, powerpc: Add ptrace tests for EBB

[Cyril Bur]

On Tue, 16 Feb 2016 14:29:47 +0530
Anshuman Khandual <khandual@linux.vnet.ibm.com> wrote:

> This patch adds ptrace interface test for EBB specific
> registers. This also adds some generic ptrace interface
> based helper functions to be used by other patches later
> on in the series.
> 
> Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
> ---
>  tools/testing/selftests/powerpc/Makefile           |   3 +-
>  tools/testing/selftests/powerpc/ptrace/Makefile    |   7 +
>  .../testing/selftests/powerpc/ptrace/ptrace-ebb.c  | 150 ++++++++++++++
>  .../testing/selftests/powerpc/ptrace/ptrace-ebb.h  | 103 ++++++++++
>  tools/testing/selftests/powerpc/ptrace/ptrace.h    | 225 +++++++++++++++++++++
>  5 files changed, 487 insertions(+), 1 deletion(-)
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/Makefile
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-ebb.h
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace.h
> 
> diff --git a/tools/testing/selftests/powerpc/Makefile b/tools/testing/selftests/powerpc/Makefile
> index 0c2706b..5b3c62c 100644
> --- a/tools/testing/selftests/powerpc/Makefile
> +++ b/tools/testing/selftests/powerpc/Makefile
> @@ -22,7 +22,8 @@ SUB_DIRS = benchmarks 		\
>  	   switch_endian	\
>  	   syscalls		\
>  	   tm			\
> -	   vphn
> +	   vphn			\
> +	   ptrace
>  
>  endif
>  
> diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
> new file mode 100644
> index 0000000..8666ac0
> --- /dev/null
> +++ b/tools/testing/selftests/powerpc/ptrace/Makefile
> @@ -0,0 +1,7 @@
> +TEST_PROGS := ptrace-ebb
> +all: $(TEST_PROGS)
> +
> +$(TEST_PROGS): ../harness.c ptrace.S ../utils.c
> +ptrace-ebb: ../pmu/event.c ../pmu/lib.c ../pmu/ebb/ebb_handler.S ../pmu/ebb/busy_loop.S
> +clean:
> +	rm -f $(TEST_PROGS) *.o

If you:
include ../../lib.mk

Then this Makefile just works with run_tests and install targets from the
base Makefile

> diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c b/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c
> new file mode 100644
> index 0000000..e1ca608
> --- /dev/null
> +++ b/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c
> @@ -0,0 +1,150 @@
> +/*
> + * Ptrace interface test for EBB
> + *
> + * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +#include "../pmu/ebb/ebb.h"
> +#include "ptrace.h"
> +#include "ptrace-ebb.h"
> +

Check out tools/testing/selftests/powerpc/utils.h which provides a nice (and
super hacky) FAIL_IF() macro.

> +void ebb(void)
> +{
> +	struct event event;
> +
> +	event_init_named(&event, 0x1001e, "cycles");
> +	event.attr.config |= (1ull << 63);
> +        event.attr.exclusive = 1;
> +        event.attr.pinned = 1;
> +	event.attr.exclude_kernel = 1;
> +	event.attr.exclude_hv = 1;
> +	event.attr.exclude_idle = 1;
> +
> +	if (event_open(&event)) {
> +		perror("event_open() failed");
> +		exit(1);
> +	}
> +
> +	setup_ebb_handler(standard_ebb_callee);
> +	mtspr(SPRN_BESCR, 0x8000000100000000ull);
> +
> +	mb();
> +
> +	if (ebb_event_enable(&event)) {
> +		perror("ebb_event_handler() failed");
> +		exit(1);
> +	}
> +
> +	mtspr(SPRN_PMC1, pmc_sample_period(SAMPLE_PERIOD));
> +	while(1)
> +		core_busy_loop();
> +	exit(0);
> +}
> +
> +int validate_ebb(struct ebb_regs *regs)
> +{
> +	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +	struct opd *opd = (struct opd *) ebb_handler;
> +	#endif
> +
> +	printf("EBBRR: %lx\n", regs->ebbrr);
> +	printf("EBBHR: %lx\n", regs->ebbhr);
> +	printf("BESCR: %lx\n", regs->bescr);
> +	printf("SIAR:  %lx\n", regs->siar);
> +	printf("SDAR:  %lx\n", regs->sdar);
> +	printf("SIER:  %lx\n", regs->sier);
> +	printf("MMCR2: %lx\n", regs->mmcr2);
> +	printf("MMCR0: %lx\n", regs->mmcr0);
> +
> +	/* Validate EBBHR */
> +	#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +	if (regs->ebbhr != opd->entry)
> +		return TEST_FAIL;
> +	#else
> +	if (regs->ebbhr != (unsigned long) ebb_handler)
> +		return TEST_FAIL;
> +	#endif
> +
> +	/* Validate SIER */
> +	if (regs->sier != SIER_EXP)
> +		return TEST_FAIL;
> +
> +	/* Validate MMCR2 */
> +	if (regs->mmcr2 != MMCR2_EXP)
> +		return TEST_FAIL;
> +
> +	/* Validate MMCR0 */
> +	if (regs->mmcr0 != MMCR0_EXP)
> +		return TEST_FAIL;
> +
> +	return TEST_PASS;
> +}
> +
> +int trace_ebb(pid_t child)
> +{
> +	struct ebb_regs regs;
> +	int ret;
> +
> +	sleep(2);
> +	ret = start_trace(child);
> +	if (ret)
> +		return TEST_FAIL;
> +
> +	ret = show_ebb_registers(child, &regs);
> +	if (ret)
> +		return TEST_FAIL;
> +
> +	ret = validate_ebb(&regs);
> +	if (ret)
> +		return TEST_FAIL;
> +
> +	ret = stop_trace(child);
> +	if (ret)
> +		return TEST_FAIL;
> +
> +	return TEST_PASS;
> +}
> +
> +int ptrace_ebb(void)
> +{
> +	pid_t pid;
> +	int ret, status;
> +
> +	pid = fork();
> +	if (pid < 0) {
> +		perror("fork() failed");
> +		return TEST_FAIL;
> +	}
> +
> +	if (pid == 0)
> +		ebb();
> +
> +	if (pid) {
> +		ret = trace_ebb(pid);
> +		if (ret)
> +			return TEST_FAIL;
> +
> +		kill(pid, SIGKILL);
> +		ret = wait(&status);
> +		if (ret != pid) {
> +			printf("Child's exit status not captured\n");
> +			return TEST_FAIL;
> +		}
> +
> +		if (WIFEXITED(status)) {
> +			if(WEXITSTATUS(status))
> +				return TEST_FAIL;
> +		}
> +		return TEST_PASS;
> +	}
> +	return TEST_PASS;
> +}
> +
> +int main(int argc, char *argv[])
> +{
> +	return test_harness(ptrace_ebb, "ptrace_ebb");
> +}
> diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.h b/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.h
> new file mode 100644
> index 0000000..9b38edc
> --- /dev/null
> +++ b/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.h
> @@ -0,0 +1,103 @@
> +/*
> + * Inspired mostly from the EBB selftest
> + *
> + * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +#define SAMPLE_PERIOD 100	/* EBB event sample persiod */
> +
> +/* Standard expected values */
> +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
> +#define MMCR0_EXP	0x8000008000000001
> +#else
> +#define MMCR0_EXP	0x180000080
> +#endif
> +
> +#define MMCR2_EXP	0
> +#define SIER_EXP	0x2000000
> +
> +struct opd
> +{
> +	u64 entry;
> +	u64 toc;
> +};
> +
> +void (*ebb_user_func)(void);
> +extern void ebb_handler(void);	/* Defined in ebb_handle.S */
> +
> +void ebb_hook(void)		/* Called by ebb_handler */
> +{
> +        if (ebb_user_func)
> +                ebb_user_func();
> +}
> +
> +void setup_ebb_handler(void (*callee)(void))
> +{
> +        u64 entry;
> +
> +#if defined(_CALL_ELF) && _CALL_ELF == 2
> +        entry = (u64)ebb_handler;
> +#else
> +	struct opd *opd;
> +
> +        opd = (struct opd *)ebb_handler;
> +        entry = opd->entry;
> +#endif
> +        ebb_user_func = callee;
> +
> +        /* Ensure ebb_user_func is set before we set the handler */
> +        mb();
> +        mtspr(SPRN_EBBHR, entry);
> +
> +        /* Make sure the handler is set before we return */
> +        mb();
> +}
> +
> +void reset_ebb_with_clear_mask(unsigned long mmcr0_clear_mask)
> +{
> +        u64 val;
> +
> +        /* 2) clear MMCR0[PMAO] - docs say BESCR[PMEO] should do this */
> +        /* 3) set MMCR0[PMAE]   - docs say BESCR[PME] should do this */
> +        val = mfspr(SPRN_MMCR0);
> +        mtspr(SPRN_MMCR0, (val & ~mmcr0_clear_mask) | MMCR0_PMAE);
> +
> +        /* 4) clear BESCR[PMEO] */
> +        mtspr(SPRN_BESCRR, BESCR_PMEO);
> +
> +        /* 5) set BESCR[PME] */
> +        mtspr(SPRN_BESCRS, BESCR_PME);
> +
> +        /* 6) rfebb 1 - done in our caller */
> +}
> +
> +void standard_ebb_callee(void)
> +{
> +	u64 val;
> +
> +	val = mfspr(SPRN_BESCR);
> +        if (!(val & BESCR_PMEO))
> +		printf("Spurious interrupt\n");
> +
> +	mtspr(SPRN_PMC1, pmc_sample_period(SAMPLE_PERIOD));
> +	reset_ebb_with_clear_mask(MMCR0_PMAO | MMCR0_FC);
> +}
> +
> +int ebb_event_enable(struct event *e)
> +{
> +	int rc;
> +
> +	mb();
> +
> +        rc = ioctl(e->fd, PERF_EVENT_IOC_ENABLE);
> +        if (rc)
> +                return rc;
> +        rc = event_read(e);
> +
> +        mb();
> +        return rc;
> +}
> diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace.h b/tools/testing/selftests/powerpc/ptrace/ptrace.h
> new file mode 100644
> index 0000000..44256d2
> --- /dev/null
> +++ b/tools/testing/selftests/powerpc/ptrace/ptrace.h
> @@ -0,0 +1,225 @@
> +/*
> + * Ptrace interface test helper functions
> + *
> + * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +#include <inttypes.h>
> +#include <unistd.h>
> +#include <stdlib.h>
> +#include <string.h>
> +#include <malloc.h>
> +#include <errno.h>
> +#include <time.h>
> +#include <sys/ptrace.h>
> +#include <sys/ioctl.h>
> +#include <sys/uio.h>
> +#include <sys/types.h>
> +#include <sys/wait.h>
> +#include <sys/signal.h>
> +#include <sys/ipc.h>
> +#include <sys/shm.h>
> +#include <sys/user.h>
> +#include <linux/elf.h>
> +#include <linux/types.h>
> +#include <linux/auxvec.h>
> +#include "../reg.h"
> +#include "utils.h"
> +
> +/* ELF core note sections */
> +#define NT_PPC_TAR	0x103		/* Target Address Register */
> +#define NT_PPC_PPR	0x104		/* Program Priority Register */
> +#define NT_PPC_DSCR	0x105		/* Data Stream Control Register */
> +#define NT_PPC_EBB	0x106		/* Event Based Branch Registers */
> +#define NT_PPC_TM_CGPR	0x107		/* TM checkpointed GPR Registers */
> +#define NT_PPC_TM_CFPR	0x108		/* TM checkpointed FPR Registers */
> +#define NT_PPC_TM_CVMX	0x109		/* TM checkpointed VMX Registers */
> +#define NT_PPC_TM_CVSX	0x10a		/* TM checkpointed VSX Registers */
> +#define NT_PPC_TM_SPR	0x10b		/* TM Special Purpose Registers */
> +#define NT_PPC_TM_CTAR	0x10c		/* TM checkpointed Target Address Register */
> +#define NT_PPC_TM_CPPR	0x10d		/* TM checkpointed Program Priority Register */
> +#define NT_PPC_TM_CDSCR	0x10e		/* TM checkpointed Data Stream Control Register */
> +
> +/* TEXASR register bits */
> +#define TEXASR_FC	0xFE00000000000000
> +#define TEXASR_FP	0x0100000000000000
> +#define TEXASR_DA	0x0080000000000000
> +#define TEXASR_NO	0x0040000000000000
> +#define TEXASR_FO	0x0020000000000000
> +#define TEXASR_SIC	0x0010000000000000
> +#define TEXASR_NTC	0x0008000000000000
> +#define TEXASR_TC	0x0004000000000000
> +#define TEXASR_TIC	0x0002000000000000
> +#define TEXASR_IC	0x0001000000000000
> +#define TEXASR_IFC	0x0000800000000000
> +#define TEXASR_ABT	0x0000000100000000
> +#define TEXASR_SPD	0x0000000080000000
> +#define TEXASR_HV	0x0000000020000000
> +#define TEXASR_PR	0x0000000010000000
> +#define TEXASR_FS	0x0000000008000000
> +#define TEXASR_TE	0x0000000004000000
> +#define TEXASR_ROT	0x0000000002000000
> +
> +#define TEST_PASS 0
> +#define TEST_FAIL 1
> +
> +struct ebb_regs {
> +	unsigned long	ebbrr;
> +	unsigned long	ebbhr;
> +	unsigned long	bescr;
> +	unsigned long	siar;
> +	unsigned long	sdar;
> +	unsigned long	sier;
> +	unsigned long	mmcr2;
> +	unsigned long	mmcr0;
> +};
> +
> +struct fpr_regs {
> +	unsigned long fpr[32];
> +	unsigned long fpscr;
> +};
> +
> +
> +/* Basic ptrace operations */
> +int start_trace(pid_t child)
> +{
> +	int ret;
> +
> +	ret = ptrace(PTRACE_ATTACH, child, NULL, NULL);
> +	if (ret) {
> +		perror("ptrace(PTRACE_ATTACH) failed");
> +		return TEST_FAIL;
> +	}
> +	ret = waitpid(child, NULL, 0);
> +	if (ret != child) {
> +		perror("waitpid() failed");
> +		return TEST_FAIL;
> +	}
> +	return TEST_PASS;
> +}
> +
> +int stop_trace(pid_t child)
> +{
> +	int ret;
> +
> +	ret = ptrace(PTRACE_DETACH, child, NULL, NULL);
> +	if (ret) {
> +		perror("ptrace(PTRACE_DETACH) failed");
> +		return TEST_FAIL;
> +	}
> +	return TEST_PASS;
> +}
> +
> +int cont_trace(pid_t child)
> +{
> +	int ret;
> +
> +	ret = ptrace(PTRACE_CONT, child, NULL, NULL);
> +	if (ret) {
> +		perror("ptrace(PTRACE_CONT) failed");
> +		return TEST_FAIL;
> +	}
> +	return TEST_PASS;
> +}
> +
> +/* EBB */
> +int show_ebb_registers(pid_t child, struct ebb_regs *regs)
> +{
> +	struct ebb_regs *ebb;
> +	struct iovec iov;
> +	int ret;
> +
> +	ebb = malloc(sizeof(struct ebb_regs));
> +	if (!ebb) {
> +		perror("malloc() failed");
> +		return TEST_FAIL;
> +	}
> +
> +	iov.iov_base = (struct ebb_regs *) ebb;
> +	iov.iov_len = sizeof(struct ebb_regs);
> +	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_EBB, &iov);
> +	if (ret) {
> +		perror("ptrace(PTRACE_GETREGSET) failed");
> +		goto fail;
> +	}
> +
> +	if (regs)
> +		memcpy(regs, ebb, sizeof(struct ebb_regs));
> +
> +	free(ebb);
> +	return TEST_PASS;
> +fail:
> +	free(ebb);
> +	return TEST_FAIL;
> +}
> +
> +/* Analyse TEXASR after TM failure */
> +inline unsigned long get_tfiar(void)
> +{
> +	unsigned long ret;
> +
> +	asm volatile("mfspr %0,%1" : "=r" (ret): "i" (SPRN_TFIAR));
> +	return ret;
> +}
> +
> +void analyse_texasr(unsigned long texasr)
> +{
> +	printf("TEXASR: %16lx\t", texasr);
> +
> +	if (texasr & TEXASR_FP)
> +		printf("TEXASR_FP  ");
> +
> +	if (texasr & TEXASR_DA)
> +		printf("TEXASR_DA  ");
> +
> +	if (texasr & TEXASR_NO)
> +		printf("TEXASR_NO  ");
> +
> +	if (texasr & TEXASR_FO)
> +		printf("TEXASR_FO  ");
> +
> +	if (texasr & TEXASR_SIC)
> +		printf("TEXASR_SIC  ");
> +
> +	if (texasr & TEXASR_NTC)
> +		printf("TEXASR_NTC  ");
> +
> +	if (texasr & TEXASR_TC)
> +		printf("TEXASR_TC  ");
> +
> +	if (texasr & TEXASR_TIC)
> +		printf("TEXASR_TIC  ");
> +
> +	if (texasr & TEXASR_IC)
> +		printf("TEXASR_IC  ");
> +
> +	if (texasr & TEXASR_IFC)
> +		printf("TEXASR_IFC  ");
> +
> +	if (texasr & TEXASR_ABT)
> +		printf("TEXASR_ABT  ");
> +
> +	if (texasr & TEXASR_SPD)
> +		printf("TEXASR_SPD  ");
> +
> +	if (texasr & TEXASR_HV)
> +		printf("TEXASR_HV  ");
> +
> +	if (texasr & TEXASR_PR)
> +		printf("TEXASR_PR  ");
> +
> +	if (texasr & TEXASR_FS)
> +		printf("TEXASR_FS  ");
> +
> +	if (texasr & TEXASR_TE)
> +		printf("TEXASR_TE  ");
> +
> +	if (texasr & TEXASR_ROT)
> +		printf("TEXASR_ROT  ");
> +
> +	printf("TFIAR :%lx\n", get_tfiar());
> +}

Re: [PATCH V10 18/28] selftests, powerpc: Add ptrace tests for GPR/FPR registers

[Cyril Bur]

On Tue, 16 Feb 2016 14:29:48 +0530
Anshuman Khandual <khandual@linux.vnet.ibm.com> wrote:

> This patch adds ptrace interface test for GPR/FPR registers.
> This adds ptrace interface based helper functions related to
> GPR/FPR access and some assembly helper functions related to
> GPR/FPR registers.
> 

I wonder if with a bit of thought we could share our assembly helper
functions... https://patchwork.ozlabs.org/patch/589703/

Let me know, happy to meet in the middle and augment my series if needed.

Thanks,

Cyril

> Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
> ---
>  tools/testing/selftests/powerpc/ptrace/Makefile    |   3 +-
>  .../testing/selftests/powerpc/ptrace/ptrace-gpr.c  | 191 +++++++++++++++++++
>  .../testing/selftests/powerpc/ptrace/ptrace-gpr.h  |  73 ++++++++
>  tools/testing/selftests/powerpc/ptrace/ptrace.S    | 131 +++++++++++++
>  tools/testing/selftests/powerpc/ptrace/ptrace.h    | 208 +++++++++++++++++++++
>  5 files changed, 605 insertions(+), 1 deletion(-)
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace.S
> 
> diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
> index 8666ac0..f5f62d0 100644
> --- a/tools/testing/selftests/powerpc/ptrace/Makefile
> +++ b/tools/testing/selftests/powerpc/ptrace/Makefile
> @@ -1,4 +1,5 @@
> -TEST_PROGS := ptrace-ebb
> +TEST_PROGS := ptrace-ebb ptrace-gpr
> +
>  all: $(TEST_PROGS)
>  
>  $(TEST_PROGS): ../harness.c ptrace.S ../utils.c
> diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c b/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c
> new file mode 100644
> index 0000000..f84f0e4
> --- /dev/null
> +++ b/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c
> @@ -0,0 +1,191 @@
> +/*
> + * Ptrace test for GPR/FPR registers
> + *
> + * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +#include "ptrace.h"
> +#include "ptrace-gpr.h"
> +
> +/* Tracer and Tracee Shared Data */
> +int shm_id;
> +volatile int *cptr, *pptr;
> +
> +extern void store_gpr(unsigned long *addr);
> +extern void store_fpr(float *addr);
> +
> +float a = FPR_1;
> +float b = FPR_2;
> +float c = FPR_3;
> +
> +void gpr(void)
> +{
> +	unsigned long gpr_buf[18];
> +	float fpr_buf[32];
> +
> +	cptr = (int *)shmat(shm_id, NULL, 0);
> +
> +	asm __volatile__(
> +		"li 14, %[gpr_1];"
> +		"li 15, %[gpr_1];"
> +		"li 16, %[gpr_1];"
> +		"li 17, %[gpr_1];"
> +		"li 18, %[gpr_1];"
> +		"li 19, %[gpr_1];"
> +		"li 20, %[gpr_1];"
> +		"li 21, %[gpr_1];"
> +		"li 22, %[gpr_1];"
> +		"li 23, %[gpr_1];"
> +		"li 24, %[gpr_1];"
> +		"li 25, %[gpr_1];"
> +		"li 26, %[gpr_1];"
> +		"li 27, %[gpr_1];"
> +		"li 28, %[gpr_1];"
> +		"li 29, %[gpr_1];"
> +		"li 30, %[gpr_1];"
> +		"li 31, %[gpr_1];"
> +
> +		"lfs 0, 0(%[flt_1]);"
> +		"lfs 1, 0(%[flt_1]);"
> +		"lfs 2, 0(%[flt_1]);"
> +		"lfs 3, 0(%[flt_1]);"
> +		"lfs 4, 0(%[flt_1]);"
> +		"lfs 5, 0(%[flt_1]);"
> +		"lfs 6, 0(%[flt_1]);"
> +		"lfs 7, 0(%[flt_1]);"
> +		"lfs 8, 0(%[flt_1]);"
> +		"lfs 9, 0(%[flt_1]);"
> +		"lfs 10, 0(%[flt_1]);"
> +		"lfs 11, 0(%[flt_1]);"
> +		"lfs 12, 0(%[flt_1]);"
> +		"lfs 13, 0(%[flt_1]);"
> +		"lfs 14, 0(%[flt_1]);"
> +		"lfs 15, 0(%[flt_1]);"
> +		"lfs 16, 0(%[flt_1]);"
> +		"lfs 17, 0(%[flt_1]);"
> +		"lfs 18, 0(%[flt_1]);"
> +		"lfs 19, 0(%[flt_1]);"
> +		"lfs 20, 0(%[flt_1]);"
> +		"lfs 21, 0(%[flt_1]);"
> +		"lfs 22, 0(%[flt_1]);"
> +		"lfs 23, 0(%[flt_1]);"
> +		"lfs 24, 0(%[flt_1]);"
> +		"lfs 25, 0(%[flt_1]);"
> +		"lfs 26, 0(%[flt_1]);"
> +		"lfs 27, 0(%[flt_1]);"
> +		"lfs 28, 0(%[flt_1]);"
> +		"lfs 29, 0(%[flt_1]);"
> +		"lfs 30, 0(%[flt_1]);"
> +		"lfs 31, 0(%[flt_1]);"
> +
> +		:
> +		:[gpr_1]"i"(GPR_1), [flt_1] "r" (&a)
> +		: "memory", "r6", "r7", "r8", "r9", "r10",
> +		"r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20",
> +		"r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
> +		);
> +
> +	while(!cptr[0]);
> +
> +	store_gpr(gpr_buf);
> +	store_fpr(fpr_buf);
> +
> +	if (validate_gpr(gpr_buf, GPR_3))
> +		exit(1);
> +
> +	if (validate_fpr_float(fpr_buf, c))
> +		exit(1);
> +
> +	exit(0);
> +}
> +
> +int trace_gpr(pid_t child)
> +{
> +	unsigned long gpr[18];
> +	unsigned long fpr[32];
> +	int ret;
> +
> +	sleep(1);
> +	ret = start_trace(child);
> +	if (ret)
> +		return TEST_FAIL;
> +
> +	ret = show_gpr(child, gpr);
> +	if (ret)
> +		return TEST_FAIL;
> +
> +	ret = validate_gpr(gpr, GPR_1);
> +	if (ret)
> +		return TEST_FAIL;
> +
> +	ret = show_fpr(child, fpr);
> +	if (ret)
> +		return TEST_FAIL;
> +
> +	ret = validate_fpr(fpr, FPR_1_REP);
> +	if (ret)
> +		return TEST_FAIL;
> +
> +	ret = write_gpr(child, GPR_3);
> +	if (ret)
> +		return TEST_FAIL;
> +
> +	ret = write_fpr(child, FPR_3_REP);
> +	if (ret)
> +		return TEST_FAIL;
> +
> +	ret = stop_trace(child);
> +	if (ret)
> +		return TEST_FAIL;
> +
> +	return TEST_PASS;
> +}
> +
> +int ptrace_gpr(void)
> +{
> +	pid_t pid;
> +	int ret, status;
> +
> +	shm_id = shmget(IPC_PRIVATE, sizeof(int) * 1, 0777|IPC_CREAT);
> +	pid = fork();
> +	if (pid < 0) {
> +		perror("fork() failed");
> +		return TEST_FAIL;
> +	}
> +	if (pid == 0)
> +		gpr();
> +
> +	if (pid) {
> +		pptr = (int *)shmat(shm_id, NULL, 0);
> +		ret = trace_gpr(pid);
> +		if (ret) {
> +			kill(pid, SIGTERM);
> +			return TEST_FAIL;
> +		}
> +
> +		pptr[0] = 1;
> +		shmdt((void *)pptr);
> +
> +		ret = wait(&status);
> +		if (ret != pid) {
> +			printf("Child's exit status not captured\n");
> +			return TEST_FAIL;
> +		}
> +
> +		if (WIFEXITED(status)) {
> +			if(WEXITSTATUS(status))
> +				return TEST_FAIL;
> +		}
> +		return TEST_PASS;
> +	}
> +	return TEST_PASS;
> +}
> +
> +int main(int argc, char *argv[])
> +{
> +	return test_harness(ptrace_gpr, "ptrace_gpr");
> +}
> diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h b/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h
> new file mode 100644
> index 0000000..6d49f1f
> --- /dev/null
> +++ b/tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h
> @@ -0,0 +1,73 @@
> +/*
> + * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +#define GPR_1	1
> +#define GPR_2	2
> +#define GPR_3	3
> +#define GPR_4	4
> +
> +#define FPR_1	0.001
> +#define FPR_2	0.002
> +#define FPR_3	0.003
> +#define FPR_4	0.004
> +
> +#define FPR_1_REP 0x3f50624de0000000
> +#define FPR_2_REP 0x3f60624de0000000
> +#define FPR_3_REP 0x3f689374c0000000
> +#define FPR_4_REP 0x3f70624de0000000
> +
> +/* Buffer must have 18 elements */
> +int validate_gpr(unsigned long *gpr, unsigned long val)
> +{
> +	int i, found = 1;
> +
> +	for (i = 0; i < 18; i++) {
> +		if (gpr[i] != val) {
> +			printf("GPR[%d]: %lx Expected: %lx\n", i+14, gpr[i], val);
> +			found = 0;
> +		}
> +	}
> +
> +	if (!found)
> +		return TEST_FAIL;
> +	return TEST_PASS;
> +}
> +
> +/* Buffer must have 32 elements */
> +int validate_fpr(unsigned long *fpr, unsigned long val)
> +{
> +	int i, found = 1;
> +
> +	for (i = 0; i < 32; i++) {
> +		if (fpr[i] != val) {
> +			printf("FPR[%d]: %lx Expected: %lx\n", i, fpr[i], val);
> +			found = 0;
> +		}
> +	}
> +
> +	if (!found)
> +		return TEST_FAIL;
> +	return TEST_PASS;
> +}
> +
> +/* Buffer must have 32 elements */
> +int validate_fpr_float(float *fpr, float val)
> +{
> +	int i, found = 1;
> +
> +	for (i = 0; i < 32; i++) {
> +		if (fpr[i] != val) {
> +			printf("FPR[%d]: %f Expected: %f\n", i, fpr[i], val);
> +			found = 0;
> +		}
> +	}
> +
> +	if (!found)
> +		return TEST_FAIL;
> +	return TEST_PASS;
> +}
> diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace.S b/tools/testing/selftests/powerpc/ptrace/ptrace.S
> new file mode 100644
> index 0000000..193beea
> --- /dev/null
> +++ b/tools/testing/selftests/powerpc/ptrace/ptrace.S
> @@ -0,0 +1,131 @@
> +/*
> + * Ptrace interface test helper assembly functions
> + *
> + * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + */
> +#include <ppc-asm.h>
> +#include "../reg.h"
> +
> +
> +/* Non volatile GPR - unsigned long buf[18] */
> +FUNC_START(load_gpr)
> +	ld	14, 0*8(3)
> +	ld	15, 1*8(3)
> +	ld	16, 2*8(3)
> +	ld	17, 3*8(3)
> +	ld	18, 4*8(3)
> +	ld	19, 5*8(3)
> +	ld	20, 6*8(3)
> +	ld	21, 7*8(3)
> +	ld	22, 8*8(3)
> +	ld	23, 9*8(3)
> +	ld	24, 10*8(3)
> +	ld	25, 11*8(3)
> +	ld	26, 12*8(3)
> +	ld	27, 13*8(3)
> +	ld	28, 14*8(3)
> +	ld	29, 15*8(3)
> +	ld	30, 16*8(3)
> +	ld	31, 17*8(3)
> +	blr
> +FUNC_END(load_gpr)
> +
> +FUNC_START(store_gpr)
> +	std	14, 0*8(3)
> +	std	15, 1*8(3)
> +	std	16, 2*8(3)
> +	std	17, 3*8(3)
> +	std	18, 4*8(3)
> +	std	19, 5*8(3)
> +	std	20, 6*8(3)
> +	std	21, 7*8(3)
> +	std	22, 8*8(3)
> +	std	23, 9*8(3)
> +	std	24, 10*8(3)
> +	std	25, 11*8(3)
> +	std	26, 12*8(3)
> +	std	27, 13*8(3)
> +	std	28, 14*8(3)
> +	std	29, 15*8(3)
> +	std	30, 16*8(3)
> +	std	31, 17*8(3)
> +	blr
> +FUNC_END(store_gpr)
> +
> +/* Single Precision Float - float buf[32] */
> +FUNC_START(load_fpr)
> +	lfs 0, 0*4(3)
> +	lfs 1, 1*4(3)
> +	lfs 2, 2*4(3)
> +	lfs 3, 3*4(3)
> +	lfs 4, 4*4(3)
> +	lfs 5, 5*4(3)
> +	lfs 6, 6*4(3)
> +	lfs 7, 7*4(3)
> +	lfs 8, 8*4(3)
> +	lfs 9, 9*4(3)
> +	lfs 10, 10*4(3)
> +	lfs 11, 11*4(3)
> +	lfs 12, 12*4(3)
> +	lfs 13, 13*4(3)
> +	lfs 14, 14*4(3)
> +	lfs 15, 15*4(3)
> +	lfs 16, 16*4(3)
> +	lfs 17, 17*4(3)
> +	lfs 18, 18*4(3)
> +	lfs 19, 19*4(3)
> +	lfs 20, 20*4(3)
> +	lfs 21, 21*4(3)
> +	lfs 22, 22*4(3)
> +	lfs 23, 23*4(3)
> +	lfs 24, 24*4(3)
> +	lfs 25, 25*4(3)
> +	lfs 26, 26*4(3)
> +	lfs 27, 27*4(3)
> +	lfs 28, 28*4(3)
> +	lfs 29, 29*4(3)
> +	lfs 30, 30*4(3)
> +	lfs 31, 31*4(3)
> +	blr
> +FUNC_END(load_fpr)
> +
> +FUNC_START(store_fpr)
> +	stfs 0, 0*4(3)
> +	stfs 1, 1*4(3)
> +	stfs 2, 2*4(3)
> +	stfs 3, 3*4(3)
> +	stfs 4, 4*4(3)
> +	stfs 5, 5*4(3)
> +	stfs 6, 6*4(3)
> +	stfs 7, 7*4(3)
> +	stfs 8, 8*4(3)
> +	stfs 9, 9*4(3)
> +	stfs 10, 10*4(3)
> +	stfs 11, 11*4(3)
> +	stfs 12, 12*4(3)
> +	stfs 13, 13*4(3)
> +	stfs 14, 14*4(3)
> +	stfs 15, 15*4(3)
> +	stfs 16, 16*4(3)
> +	stfs 17, 17*4(3)
> +	stfs 18, 18*4(3)
> +	stfs 19, 19*4(3)
> +	stfs 20, 20*4(3)
> +	stfs 21, 21*4(3)
> +	stfs 22, 22*4(3)
> +	stfs 23, 23*4(3)
> +	stfs 24, 24*4(3)
> +	stfs 25, 25*4(3)
> +	stfs 26, 26*4(3)
> +	stfs 27, 27*4(3)
> +	stfs 28, 28*4(3)
> +	stfs 29, 29*4(3)
> +	stfs 30, 30*4(3)
> +	stfs 31, 31*4(3)
> +	blr
> +FUNC_END(store_fpr)
> diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace.h b/tools/testing/selftests/powerpc/ptrace/ptrace.h
> index 44256d2..439fb65 100644
> --- a/tools/testing/selftests/powerpc/ptrace/ptrace.h
> +++ b/tools/testing/selftests/powerpc/ptrace/ptrace.h
> @@ -157,6 +157,214 @@ fail:
>  	return TEST_FAIL;
>  }
>  
> +/* FPR */
> +int show_fpr(pid_t child, unsigned long *fpr)
> +{
> +	struct fpr_regs *regs;
> +	int ret, i;
> +
> +	regs = (struct fpr_regs *) malloc(sizeof(struct fpr_regs));
> +	ret = ptrace(PTRACE_GETFPREGS, child, NULL, regs);
> +	if (ret) {
> +		perror("ptrace(PTRACE_GETREGSET) failed");
> +		return TEST_FAIL;
> +	}
> +
> +	if (fpr) {
> +		for (i = 0; i < 32; i++)
> +			fpr[i] = regs->fpr[i];
> +	}
> +	return TEST_PASS;
> +}
> +
> +int write_fpr(pid_t child, unsigned long val)
> +{
> +	struct fpr_regs *regs;
> +	int ret, i;
> +
> +	regs = (struct fpr_regs *) malloc(sizeof(struct fpr_regs));
> +	ret = ptrace(PTRACE_GETFPREGS, child, NULL, regs);
> +	if (ret) {
> +		perror("ptrace(PTRACE_GETREGSET) failed");
> +		return TEST_FAIL;
> +	}
> +
> +	for (i = 0; i < 32; i++)
> +		regs->fpr[i] = val;
> +
> +	ret = ptrace(PTRACE_SETFPREGS, child, NULL, regs);
> +	if (ret) {
> +		perror("ptrace(PTRACE_GETREGSET) failed");
> +		return TEST_FAIL;
> +	}
> +	return TEST_PASS;
> +}
> +
> +int show_ckpt_fpr(pid_t child, unsigned long *fpr)
> +{
> +	struct fpr_regs *regs;
> +	struct iovec iov;
> +	int ret, i;
> +
> +	regs = (struct fpr_regs *) malloc(sizeof(struct fpr_regs));
> +	iov.iov_base = regs;
> +	iov.iov_len = sizeof(struct fpr_regs);
> +
> +	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_CFPR, &iov);
> +	if (ret) {
> +		perror("ptrace(PTRACE_GETREGSET) failed");
> +		return TEST_FAIL;
> +	}
> +
> +	if (fpr) {
> +		for (i = 0; i < 32; i++)
> +			fpr[i] = regs->fpr[i];
> +	}
> +
> +	return TEST_PASS;
> +}
> +
> +int write_ckpt_fpr(pid_t child, unsigned long val)
> +{
> +	struct fpr_regs *regs;
> +	struct iovec iov;
> +	int ret, i;
> +
> +	regs = (struct fpr_regs *) malloc(sizeof(struct fpr_regs));
> +	iov.iov_base = regs;
> +	iov.iov_len = sizeof(struct fpr_regs);
> +
> +	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_CFPR, &iov);
> +	if (ret) {
> +		perror("ptrace(PTRACE_GETREGSET) failed");
> +		return TEST_FAIL;
> +	}
> +
> +	for (i = 0; i < 32; i++)
> +		regs->fpr[i] = val;
> +
> +	ret = ptrace(PTRACE_SETREGSET, child, NT_PPC_TM_CFPR, &iov);
> +	if (ret) {
> +		perror("ptrace(PTRACE_GETREGSET) failed");
> +		return TEST_FAIL;
> +	}
> +	return TEST_PASS;
> +}
> +
> +/* GPR */
> +int show_gpr(pid_t child, unsigned long *gpr)
> +{
> +	struct pt_regs *regs;
> +	int ret, i;
> +
> +	regs = (struct pt_regs *) malloc(sizeof(struct pt_regs));
> +	if (!regs) {
> +		perror("malloc() failed");
> +		return TEST_FAIL;
> +	}
> +
> +	ret = ptrace(PTRACE_GETREGS, child, NULL, regs);
> +	if (ret) {
> +		perror("ptrace(PTRACE_GETREGSET) failed");
> +		return TEST_FAIL;
> +	}
> +
> +	if (gpr) {
> +		for (i = 14; i < 32; i++)
> +			gpr[i-14] = regs->gpr[i];
> +	}
> +
> +	return TEST_PASS;
> +}
> +
> +int write_gpr(pid_t child, unsigned long val)
> +{
> +	struct pt_regs *regs;
> +	int i, ret;
> +
> +	regs = (struct pt_regs *) malloc(sizeof(struct pt_regs));
> +	if (!regs) {
> +		perror("malloc() failed");
> +		return TEST_FAIL;
> +	}
> +
> +	ret = ptrace(PTRACE_GETREGS, child, NULL, regs);
> +	if (ret) {
> +		perror("ptrace(PTRACE_GETREGSET) failed");
> +		return TEST_FAIL;
> +	}
> +
> +	for (i = 14; i < 32; i++)
> +		regs->gpr[i] = val;
> +
> +	ret = ptrace(PTRACE_SETREGS, child, NULL, regs);
> +	if (ret) {
> +		perror("ptrace(PTRACE_GETREGSET) failed");
> +		return TEST_FAIL;
> +	}
> +	return TEST_PASS;
> +}
> +
> +int show_ckpt_gpr(pid_t child, unsigned long *gpr)
> +{
> +	struct pt_regs *regs;
> +	struct iovec iov;
> +	int ret, i;
> +
> +	regs = (struct pt_regs *) malloc(sizeof(struct pt_regs));
> +	if (!regs) {
> +		perror("malloc() failed");
> +		return TEST_FAIL;
> +	}
> +
> +	iov.iov_base = (u64 *) regs;
> +	iov.iov_len = sizeof(struct pt_regs);
> +
> +	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_CGPR, &iov);
> +	if (ret) {
> +		perror("ptrace(PTRACE_GETREGSET) failed");
> +		return TEST_FAIL;
> +	}
> +
> +	if (gpr) {
> +		for (i = 14; i < 32; i++)
> +			gpr[i-14] = regs->gpr[i];
> +	}
> +
> +	return TEST_PASS;
> +}
> +
> +int write_ckpt_gpr(pid_t child, unsigned long val)
> +{
> +	struct pt_regs *regs;
> +	struct iovec iov;
> +	int ret, i;
> +
> +	regs = (struct pt_regs *) malloc(sizeof(struct pt_regs));
> +	if (!regs) {
> +		perror("malloc() failed\n");
> +		return TEST_FAIL;
> +	}
> +	iov.iov_base = (u64 *) regs;
> +	iov.iov_len = sizeof(struct pt_regs);
> +
> +	ret = ptrace(PTRACE_GETREGSET, child, NT_PPC_TM_CGPR, &iov);
> +	if (ret) {
> +		perror("ptrace(PTRACE_GETREGSET) failed");
> +		return TEST_FAIL;
> +	}
> +
> +	for (i = 14; i < 32; i++)
> +		regs->gpr[i] = val;
> +
> +	ret = ptrace(PTRACE_SETREGSET, child, NT_PPC_TM_CGPR, &iov);
> +	if (ret) {
> +		perror("ptrace(PTRACE_GETREGSET) failed");
> +		return TEST_FAIL;
> +	}
> +	return TEST_PASS;
> +}
> +
>  /* Analyse TEXASR after TM failure */
>  inline unsigned long get_tfiar(void)
>  {

Re: [PATCH V10 02/28] powerpc, process: Add the function flush_tmregs_to_thread

[Anshuman Khandual]

On 03/02/2016 05:45 AM, Cyril Bur wrote:
> On Tue, 16 Feb 2016 14:29:32 +0530
> Anshuman Khandual <khandual@linux.vnet.ibm.com> wrote:
> 
>> This patch creates a function flush_tmregs_to_thread which
>> will then be used by subsequent patches in this series. The
>> function checks for self tracing ptrace interface attempts
>> while in the TM context and logs appropriate warning message.
>>
> 
> Hi Anshuman,
> 
> You'll have to bare with me, my ptrace knowledge is non existent so you might
> have to walk me though some aspects.
> 
> I have been playing with FPU/VMX and VSX saving so I thought I'd take a look.

Sure.


> 
>> Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
>> ---
>>  arch/powerpc/include/asm/switch_to.h |  8 ++++++++
>>  arch/powerpc/kernel/process.c        | 20 ++++++++++++++++++++
>>  2 files changed, 28 insertions(+)
>>
>> diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h
>> index 5b268b6..7b297bf 100644
>> --- a/arch/powerpc/include/asm/switch_to.h
>> +++ b/arch/powerpc/include/asm/switch_to.h
>> @@ -70,6 +70,14 @@ static inline void disable_kernel_spe(void)
>>  }
>>  #endif
>>  
>> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
>> +extern void flush_tmregs_to_thread(struct task_struct *);
>> +#else
>> +static inline void flush_tmregs_to_thread(struct task_struct *t)
>> +{
>> +}
>> +#endif
>> +
>>  static inline void clear_task_ebb(struct task_struct *t)
>>  {
>>  #ifdef CONFIG_PPC_BOOK3S_64
>> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
>> index dccc87e..2c4fa7f 100644
>> --- a/arch/powerpc/kernel/process.c
>> +++ b/arch/powerpc/kernel/process.c
>> @@ -918,6 +918,26 @@ static inline void restore_sprs(struct thread_struct *old_thread,
>>  #endif
>>  }
>>  
> 
> 
> 
>> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
>> +void flush_tmregs_to_thread(struct task_struct *tsk)
>> +{
>> +	/*
>> +	 * Process self tracing is not yet supported through
>> +	 * ptrace interface. Ptrace generic code should have
>> +	 * prevented this from happening in the first place.
>> +	 * Warn once here with the message, if some how it
>> +	 * is attempted.
>> +	 */
>> +	WARN_ONCE(tsk == current,
>> +		"Not expecting ptrace on self: TM regs may be incorrect\n");
>> +
>> +	/*
>> +	 * If task is not current, it should have been flushed
>> +	 * already to it's thread_struct during __switch_to().
>> +	 */
> 
> I totally agree except this highlights something that I notice in subsequent
> patches, and existing code. All the *_{get,set}() functions call
> flush_*_to_thread() when, as per your comment (and my understanding of task
> switching) there really shouldn't be a need to do that. My only thought is that
> this could be a relic of uniprocessor days when it would have been necessary but
> Anton recently stripped that out. Are you able to shed some light here?

Its been sometime I had looked into this aspect of the series. I remember
Michael Neuling and myself discussed about this and settled on a single
WARN_ON here as nothing else was required to be done in the function. It
may be possible that all the flush_*_to_thread() functions used else where
are because of uniprocessor concerns. I dont understand completely our
context save/restore paths including the lazy ones. I believed that these
flush_*_to_thread() routines just made sure task struct has the latest
values of the thread context in case of some complicated save/restore
paths might not have done the complete save at that point in time.

If you think that all these flush_*_to_thread() functions used through
out POWER ptrace need review to see whether they are required or not
anymore I would suggest we should do it as a separate patch after this
series and I am willing to work with you on that.

> 
> The reason I ask is that if the flush_*_to_thread() calls ARE actually
> important then I worry that this function is inadequate...

I guess we went through that and finally settled on WARN_ON once but dont
remember the exact context now. Will look into all previous discussions
on this and get back.

Re: [PATCH V10 02/28] powerpc, process: Add the function flush_tmregs_to_thread

[Cyril Bur]

On Wed, 02 Mar 2016 09:59:06 +0530
Anshuman Khandual <khandual@linux.vnet.ibm.com> wrote:

> On 03/02/2016 05:45 AM, Cyril Bur wrote:
> > On Tue, 16 Feb 2016 14:29:32 +0530
> > Anshuman Khandual <khandual@linux.vnet.ibm.com> wrote:
> >   
> >> This patch creates a function flush_tmregs_to_thread which
> >> will then be used by subsequent patches in this series. The
> >> function checks for self tracing ptrace interface attempts
> >> while in the TM context and logs appropriate warning message.
> >>  
> > 
> > Hi Anshuman,
> > 
> > You'll have to bare with me, my ptrace knowledge is non existent so you might
> > have to walk me though some aspects.
> > 
> > I have been playing with FPU/VMX and VSX saving so I thought I'd take a look.  
> 
> Sure.
> 
> 
> >   
> >> Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
> >> ---
> >>  arch/powerpc/include/asm/switch_to.h |  8 ++++++++
> >>  arch/powerpc/kernel/process.c        | 20 ++++++++++++++++++++
> >>  2 files changed, 28 insertions(+)
> >>
> >> diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h
> >> index 5b268b6..7b297bf 100644
> >> --- a/arch/powerpc/include/asm/switch_to.h
> >> +++ b/arch/powerpc/include/asm/switch_to.h
> >> @@ -70,6 +70,14 @@ static inline void disable_kernel_spe(void)
> >>  }
> >>  #endif
> >>  
> >> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> >> +extern void flush_tmregs_to_thread(struct task_struct *);
> >> +#else
> >> +static inline void flush_tmregs_to_thread(struct task_struct *t)
> >> +{
> >> +}
> >> +#endif
> >> +
> >>  static inline void clear_task_ebb(struct task_struct *t)
> >>  {
> >>  #ifdef CONFIG_PPC_BOOK3S_64
> >> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
> >> index dccc87e..2c4fa7f 100644
> >> --- a/arch/powerpc/kernel/process.c
> >> +++ b/arch/powerpc/kernel/process.c
> >> @@ -918,6 +918,26 @@ static inline void restore_sprs(struct thread_struct *old_thread,
> >>  #endif
> >>  }
> >>    
> > 
> > 
> >   
> >> +#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
> >> +void flush_tmregs_to_thread(struct task_struct *tsk)
> >> +{
> >> +	/*
> >> +	 * Process self tracing is not yet supported through
> >> +	 * ptrace interface. Ptrace generic code should have
> >> +	 * prevented this from happening in the first place.
> >> +	 * Warn once here with the message, if some how it
> >> +	 * is attempted.
> >> +	 */
> >> +	WARN_ONCE(tsk == current,
> >> +		"Not expecting ptrace on self: TM regs may be incorrect\n");
> >> +
> >> +	/*
> >> +	 * If task is not current, it should have been flushed
> >> +	 * already to it's thread_struct during __switch_to().
> >> +	 */  
> > 
> > I totally agree except this highlights something that I notice in subsequent
> > patches, and existing code. All the *_{get,set}() functions call
> > flush_*_to_thread() when, as per your comment (and my understanding of task
> > switching) there really shouldn't be a need to do that. My only thought is that
> > this could be a relic of uniprocessor days when it would have been necessary but
> > Anton recently stripped that out. Are you able to shed some light here?  
> 
> Its been sometime I had looked into this aspect of the series. I remember
> Michael Neuling and myself discussed about this and settled on a single
> WARN_ON here as nothing else was required to be done in the function. It
> may be possible that all the flush_*_to_thread() functions used else where
> are because of uniprocessor concerns. I dont understand completely our
> context save/restore paths including the lazy ones. I believed that these
> flush_*_to_thread() routines just made sure task struct has the latest
> values of the thread context in case of some complicated save/restore
> paths might not have done the complete save at that point in time.
> 

Well as you note in the comment though, it should be done since we've gone
through __switch_to()...

> If you think that all these flush_*_to_thread() functions used through
> out POWER ptrace need review to see whether they are required or not
> anymore I would suggest we should do it as a separate patch after this
> series and I am willing to work with you on that.

I THINK your patches are correct and we're just performing needless
flush_*_to_thread() calls now in which case its fine and we can review laster,
my concern is that I've been wrong before so having flush_tmregs_to_thread() do
nothing worries me. I wonder if Mr Neuling or Mr Ellerman have anything to say
on the subject...

> 
> > 
> > The reason I ask is that if the flush_*_to_thread() calls ARE actually
> > important then I worry that this function is inadequate...  
> 
> I guess we went through that and finally settled on WARN_ON once but dont
> remember the exact context now. Will look into all previous discussions
> on this and get back.

Thanks,

Cyril
> 

Re: [PATCH V10 17/28] selftests, powerpc: Add ptrace tests for EBB

[Anshuman Khandual]

On 03/02/2016 06:02 AM, Cyril Bur wrote:
> On Tue, 16 Feb 2016 14:29:47 +0530
> Anshuman Khandual <khandual@linux.vnet.ibm.com> wrote:
> 
>> This patch adds ptrace interface test for EBB specific
>> registers. This also adds some generic ptrace interface
>> based helper functions to be used by other patches later
>> on in the series.
>>
>> Signed-off-by: Anshuman Khandual <khandual@linux.vnet.ibm.com>
>> ---
>>  tools/testing/selftests/powerpc/Makefile           |   3 +-
>>  tools/testing/selftests/powerpc/ptrace/Makefile    |   7 +
>>  .../testing/selftests/powerpc/ptrace/ptrace-ebb.c  | 150 ++++++++++++++
>>  .../testing/selftests/powerpc/ptrace/ptrace-ebb.h  | 103 ++++++++++
>>  tools/testing/selftests/powerpc/ptrace/ptrace.h    | 225 +++++++++++++++++++++
>>  5 files changed, 487 insertions(+), 1 deletion(-)
>>  create mode 100644 tools/testing/selftests/powerpc/ptrace/Makefile
>>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c
>>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-ebb.h
>>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace.h
>>
>> diff --git a/tools/testing/selftests/powerpc/Makefile b/tools/testing/selftests/powerpc/Makefile
>> index 0c2706b..5b3c62c 100644
>> --- a/tools/testing/selftests/powerpc/Makefile
>> +++ b/tools/testing/selftests/powerpc/Makefile
>> @@ -22,7 +22,8 @@ SUB_DIRS = benchmarks 		\
>>  	   switch_endian	\
>>  	   syscalls		\
>>  	   tm			\
>> -	   vphn
>> +	   vphn			\
>> +	   ptrace
>>  
>>  endif
>>  
>> diff --git a/tools/testing/selftests/powerpc/ptrace/Makefile b/tools/testing/selftests/powerpc/ptrace/Makefile
>> new file mode 100644
>> index 0000000..8666ac0
>> --- /dev/null
>> +++ b/tools/testing/selftests/powerpc/ptrace/Makefile
>> @@ -0,0 +1,7 @@
>> +TEST_PROGS := ptrace-ebb
>> +all: $(TEST_PROGS)
>> +
>> +$(TEST_PROGS): ../harness.c ptrace.S ../utils.c
>> +ptrace-ebb: ../pmu/event.c ../pmu/lib.c ../pmu/ebb/ebb_handler.S ../pmu/ebb/busy_loop.S
>> +clean:
>> +	rm -f $(TEST_PROGS) *.o
> 
> If you:
> include ../../lib.mk
> 
> Then this Makefile just works with run_tests and install targets from the
> base Makefile

Sure, will do that.

> 
>> diff --git a/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c b/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c
>> new file mode 100644
>> index 0000000..e1ca608
>> --- /dev/null
>> +++ b/tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c
>> @@ -0,0 +1,150 @@
>> +/*
>> + * Ptrace interface test for EBB
>> + *
>> + * Copyright (C) 2015 Anshuman Khandual, IBM Corporation.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License
>> + * as published by the Free Software Foundation; either version
>> + * 2 of the License, or (at your option) any later version.
>> + */
>> +#include "../pmu/ebb/ebb.h"
>> +#include "ptrace.h"
>> +#include "ptrace-ebb.h"
>> +
> 
> Check out tools/testing/selftests/powerpc/utils.h which provides a nice (and
> super hacky) FAIL_IF() macro.

Sure, will check it out and see where all it can be used.

Re: [PATCH V10 18/28] selftests, powerpc: Add ptrace tests for GPR/FPR registers

[Anshuman Khandual]

On 03/02/2016 06:10 AM, Cyril Bur wrote:
> On Tue, 16 Feb 2016 14:29:48 +0530
> Anshuman Khandual <khandual@linux.vnet.ibm.com> wrote:
> 
>> > This patch adds ptrace interface test for GPR/FPR registers.
>> > This adds ptrace interface based helper functions related to
>> > GPR/FPR access and some assembly helper functions related to
>> > GPR/FPR registers.
>> > 
> I wonder if with a bit of thought we could share our assembly helper
> functions... https://patchwork.ozlabs.org/patch/589703/
> 
> Let me know, happy to meet in the middle and augment my series if needed.

Let me look into this in detail, will need some time.

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Laurent Dufour]

On 16/02/2016 09:59, Anshuman Khandual wrote:
> 	This patch series adds twelve new ELF core note sections which can
> be used with existing ptrace request PTRACE_GETREGSET-SETREGSET for accessing
> various transactional memory and other miscellaneous debug register sets on
> powerpc platform.

Hi Michael,

This series is required to handle TM state in CRIU.
Is there a chance to get it upstream soon ?

Thanks,
Laurent.

> 
> Test Result (All tests pass on both BE and LE)
> ----------------------------------------------
> ptrace-ebb		PASS
> ptrace-gpr		PASS
> ptrace-tm-gpr		PASS
> ptrace-tm-spd-gpr	PASS
> ptrace-tar		PASS
> ptrace-tm-tar		PASS
> ptrace-tm-spd-tar	PASS
> ptrace-vsx		PASS
> ptrace-tm-vsx		PASS
> ptrace-tm-spd-vsx	PASS
> ptrace-tm-spr		PASS
> 
> Previous versions:
> ==================
> RFC: https://lkml.org/lkml/2014/4/1/292
> V1:  https://lkml.org/lkml/2014/4/2/43
> V2:  https://lkml.org/lkml/2014/5/5/88
> V3:  https://lkml.org/lkml/2014/5/23/486
> V4:  https://lkml.org/lkml/2014/11/11/6
> V5:  https://lkml.org/lkml/2014/11/25/134
> V6:  https://lkml.org/lkml/2014/12/2/98
> V7:  https://lkml.org/lkml/2015/1/14/19
> V8:  https://lkml.org/lkml/2015/5/19/700
> V9:  https://lkml.org/lkml/2015/10/8/522
> 
> Changes in V10:
> ---------------
> - Rebased against the latest mainline
> - Fixed couple of build failures in the test cases related to aux vector
> 
> Changes in V9:
> --------------
> - Fixed static build check failure after tm_orig_msr got dropped
> - Fixed asm volatile construct for used registers set
> - Fixed EBB, VSX, VMX tests for LE
> - Fixed TAR test which was failing because of system calls
> - Added checks for PPC_FEATURE2_HTM aux feature in the tests
> - Fixed copyright statements
> 
> Changes in V8:
> --------------
> - Split the misc register set into individual ELF core notes
> - Implemented support for VSX register set (on and off TM)
> - Implemented support for EBB register set
> - Implemented review comments on previous versions
> - Some code re-arrangements, re-writes and documentation
> - Added comprehensive list of test cases into selftests
> 
> Changes in V7:
> --------------
> - Fixed a config directive in the MISC code
> - Merged the two gitignore patches into a single one
> 
> Changes in V6:
> --------------
> - Added two git ignore patches for powerpc selftests
> - Re-formatted all in-code function definitions in kernel-doc format
> 
> Changes in V5:
> --------------
> - Changed flush_tmregs_to_thread, so not to take into account self tracing
> - Dropped the 3rd patch in the series which had merged two functions
> - Fixed one build problem for the misc debug register patch
> - Accommodated almost all the review comments from Suka on the 6th patch
> - Minor changes to the self test program
> - Changed commit messages for some of the patches
> 
> Changes in V4:
> --------------
> - Added one test program into the powerpc selftest bucket in this regard
> - Split the 2nd patch in the previous series into four different patches
> - Accommodated most of the review comments on the previous patch series
> - Added a patch to merge functions __switch_to_tm and tm_reclaim_task
> 
> Changes in V3:
> --------------
> - Added two new error paths in every TM related get/set functions when regset
>   support is not present on the system (ENODEV) or when the process does not
>   have any transaction active (ENODATA) in the context
> - Installed the active hooks for all the newly added regset core note types
> 
> Changes in V2:
> --------------
> - Removed all the power specific ptrace requests corresponding to new NT_PPC_*
>   elf core note types. Now all the register sets can be accessed from ptrace
>   through PTRACE_GETREGSET/PTRACE_SETREGSET using the individual NT_PPC* core
>   note type instead
> - Fixed couple of attribute values for REGSET_TM_CGPR register set
> - Renamed flush_tmreg_to_thread as flush_tmregs_to_thread
> - Fixed 32 bit checkpointed GPR support
> - Changed commit messages accordingly
> 
> 
> Anshuman Khandual (28):
>   elf: Add powerpc specific core note sections
>   powerpc, process: Add the function flush_tmregs_to_thread
>   powerpc, ptrace: Enable in transaction NT_PRFPREG ptrace requests
>   powerpc, ptrace: Enable in transaction NT_PPC_VMX ptrace requests
>   powerpc, ptrace: Enable in transaction NT_PPC_VSX ptrace requests
>   powerpc, ptrace: Adapt gpr32_get, gpr32_set functions for transaction
>   powerpc, ptrace: Enable support for NT_PPC_CGPR
>   powerpc, ptrace: Enable support for NT_PPC_CFPR
>   powerpc, ptrace: Enable support for NT_PPC_CVMX
>   powerpc, ptrace: Enable support for NT_PPC_CVSX
>   powerpc, ptrace: Enable support for TM SPR state
>   powerpc, ptrace: Enable NT_PPC_TM_CTAR, NT_PPC_TM_CPPR, NT_PPC_TM_CDSCR
>   powerpc, ptrace: Enable support for NT_PPPC_TAR, NT_PPC_PPR, NT_PPC_DSCR
>   powerpc, ptrace: Enable support for EBB registers
>   selftests, powerpc: Move 'reg.h' file outside of 'ebb' sub directory
>   selftests, powerpc: Add more SPR numbers, TM & VMX instructions to 'reg.h'
>   selftests, powerpc: Add ptrace tests for EBB
>   selftests, powerpc: Add ptrace tests for GPR/FPR registers
>   selftests, powerpc: Add ptrace tests for GPR/FPR registers in TM
>   selftests, powerpc: Add ptrace tests for GPR/FPR registers in suspended TM
>   selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR registers
>   selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR in TM
>   selftests, powerpc: Add ptrace tests for TAR, PPR, DSCR in suspended TM
>   selftests, powerpc: Add ptrace tests for VSX, VMX registers
>   selftests, powerpc: Add ptrace tests for VSX, VMX registers in TM
>   selftests, powerpc: Add ptrace tests for VSX, VMX registers in suspended TM
>   selftests, powerpc: Add ptrace tests for TM SPR registers
>   selftests, powerpc: Add .gitignore file for ptrace executables
> 
>  arch/powerpc/include/asm/switch_to.h               |    8 +
>  arch/powerpc/include/uapi/asm/elf.h                |    6 +
>  arch/powerpc/kernel/process.c                      |   20 +
>  arch/powerpc/kernel/ptrace.c                       | 1737 ++++++++++++++++++--
>  include/uapi/linux/elf.h                           |   12 +
>  tools/testing/selftests/powerpc/Makefile           |    3 +-
>  tools/testing/selftests/powerpc/pmu/ebb/ebb.c      |    2 +-
>  tools/testing/selftests/powerpc/pmu/ebb/ebb.h      |    2 +-
>  .../selftests/powerpc/pmu/ebb/ebb_handler.S        |    2 +-
>  tools/testing/selftests/powerpc/pmu/ebb/reg.h      |   49 -
>  .../selftests/powerpc/pmu/ebb/reg_access_test.c    |    2 +-
>  tools/testing/selftests/powerpc/ptrace/.gitignore  |   11 +
>  tools/testing/selftests/powerpc/ptrace/Makefile    |   12 +
>  .../testing/selftests/powerpc/ptrace/ptrace-ebb.c  |  150 ++
>  .../testing/selftests/powerpc/ptrace/ptrace-ebb.h  |  103 ++
>  .../testing/selftests/powerpc/ptrace/ptrace-gpr.c  |  191 +++
>  .../testing/selftests/powerpc/ptrace/ptrace-gpr.h  |   73 +
>  .../testing/selftests/powerpc/ptrace/ptrace-tar.c  |  151 ++
>  .../testing/selftests/powerpc/ptrace/ptrace-tar.h  |   50 +
>  .../selftests/powerpc/ptrace/ptrace-tm-gpr.c       |  288 ++++
>  .../selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c   |  319 ++++
>  .../selftests/powerpc/ptrace/ptrace-tm-spd-tar.c   |  184 +++
>  .../selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c   |  212 +++
>  .../selftests/powerpc/ptrace/ptrace-tm-spr.c       |  157 ++
>  .../selftests/powerpc/ptrace/ptrace-tm-tar.c       |  170 ++
>  .../selftests/powerpc/ptrace/ptrace-tm-vsx.c       |  196 +++
>  .../testing/selftests/powerpc/ptrace/ptrace-vsx.c  |  138 ++
>  .../testing/selftests/powerpc/ptrace/ptrace-vsx.h  |  104 ++
>  tools/testing/selftests/powerpc/ptrace/ptrace.S    |  396 +++++
>  tools/testing/selftests/powerpc/ptrace/ptrace.h    |  766 +++++++++
>  tools/testing/selftests/powerpc/reg.h              |   70 +
>  31 files changed, 5406 insertions(+), 178 deletions(-)
>  delete mode 100644 tools/testing/selftests/powerpc/pmu/ebb/reg.h
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/.gitignore
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/Makefile
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-ebb.c
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-ebb.h
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.c
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-gpr.h
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tar.c
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tar.h
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-gpr.c
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-gpr.c
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-tar.c
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spd-vsx.c
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-spr.c
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-tar.c
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-tm-vsx.c
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-vsx.c
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace-vsx.h
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace.S
>  create mode 100644 tools/testing/selftests/powerpc/ptrace/ptrace.h
>  create mode 100644 tools/testing/selftests/powerpc/reg.h
> 

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Michael Ellerman]

On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <ldufour@linux.vnet.ibm.com> wrote:
>On 16/02/2016 09:59, Anshuman Khandual wrote:
>> 	This patch series adds twelve new ELF core note sections which can
>> be used with existing ptrace request PTRACE_GETREGSET-SETREGSET for
>accessing
>> various transactional memory and other miscellaneous debug register
>sets on
>> powerpc platform.
>
>Hi Michael,
>
>This series is required to handle TM state in CRIU.
>Is there a chance to get it upstream soon ?

We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?

cheers
-- 
Sent from my Android phone with K-9 Mail. Please excuse my brevity.

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Edjunior Barbosa Machado]

On 04/07/2016 06:49 PM, Michael Ellerman wrote:
> 
> 
> On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <ldufour@linux.vnet.ibm.com> wrote:
>> On 16/02/2016 09:59, Anshuman Khandual wrote:
>>> 	This patch series adds twelve new ELF core note sections which can
>>> be used with existing ptrace request PTRACE_GETREGSET-SETREGSET for
>> accessing
>>> various transactional memory and other miscellaneous debug register
>> sets on
>>> powerpc platform.
>>
>> Hi Michael,
>>
>> This series is required to handle TM state in CRIU.
>> Is there a chance to get it upstream soon ?
> 
> We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?
> 
> cheers
> 

Hi Michael, Anshuman,

I've managed to implement the GDB support for the new regsets and test
on Power8 (BE and LE). The following is an example of GDB 'info
registers all' partial output showing the new registers when inside a
suspended transaction on Power8 LE using this patchset. Please let me
know if you need any additional information or tests from GDB side.

(gdb) info registers all
...
dscr           0x0      0
ppr            0xc000000000000  3377699720527872
tar            0x0      0
ebbrr          <unavailable>
ebbhr          <unavailable>
bescr          <unavailable>
siar           <unavailable>
sdar           <unavailable>
sier           <unavailable>
mmcr2          <unavailable>
mmcr0          <unavailable>
tfhar          0x10002b30       268446512
texasr         0x110000098000001        76561196215435265
tfiar          0x10002ad9       268446425
cr0            0x10002b2c       268446508
cr1            0x3fffffffeb20   70368744172320
cr2            0x10027f00       268599040
cr3            0x10020278       268567160
cr4            0x1000339c       268448668
cr5            0x42000488       1107297416
cr6            0x4000   16384
cr7            0x3fffb7ea0f28   70367534780200
cr8            0x800000010280f033       9223372041191747635
cr9            0x10020178       268566904
cr10           0x10020278       268567160
cr11           0x0      0
cr12           0x0      0
cr13           0x3fffb7ffc350   70367536202576
cr14           0x0      0
cr15           0x0      0
cr16           0x0      0
cr17           0x0      0
cr18           0x0      0
cr19           0x0      0
cr20           0x0      0
cr21           0x0      0
cr22           0x0      0
cr23           0x0      0
cr24           0x0      0
cr25           0x0      0
cr26           0x0      0
cr27           0x3fffb7fef718   70367536150296
cr28           0x0      0
cr29           0x3fffb7fef720   70367536150304
cr30           0x0      0
cr31           0x3fffffffeb20   70368744172320
cf0            0.30000001192092896      (raw 0x3fd3333340000000)
cf1            0.30000001192092896      (raw 0x3fd3333340000000)
cf2            0.30000001192092896      (raw 0x3fd3333340000000)
cf3            0.30000001192092896      (raw 0x3fd3333340000000)
cf4            0.30000001192092896      (raw 0x3fd3333340000000)
cf5            0.30000001192092896      (raw 0x3fd3333340000000)
cf6            0.30000001192092896      (raw 0x3fd3333340000000)
cf7            0.30000001192092896      (raw 0x3fd3333340000000)
cf8            0.30000001192092896      (raw 0x3fd3333340000000)
cf9            0.30000001192092896      (raw 0x3fd3333340000000)
cf10           0.30000001192092896      (raw 0x3fd3333340000000)
cf11           0.30000001192092896      (raw 0x3fd3333340000000)
cf12           0.30000001192092896      (raw 0x3fd3333340000000)
cf13           0.30000001192092896      (raw 0x3fd3333340000000)
cf14           0.30000001192092896      (raw 0x3fd3333340000000)
cf15           0.30000001192092896      (raw 0x3fd3333340000000)
cf16           0.30000001192092896      (raw 0x3fd3333340000000)
cf17           0.30000001192092896      (raw 0x3fd3333340000000)
cf18           0.30000001192092896      (raw 0x3fd3333340000000)
cf19           0.30000001192092896      (raw 0x3fd3333340000000)
cf20           0.30000001192092896      (raw 0x3fd3333340000000)
cf21           0.30000001192092896      (raw 0x3fd3333340000000)
cf22           0.30000001192092896      (raw 0x3fd3333340000000)
cf23           0.30000001192092896      (raw 0x3fd3333340000000)
cf24           0.30000001192092896      (raw 0x3fd3333340000000)
cf25           0.30000001192092896      (raw 0x3fd3333340000000)
cf26           0.30000001192092896      (raw 0x3fd3333340000000)
cf27           0.30000001192092896      (raw 0x3fd3333340000000)
cf28           0.30000001192092896      (raw 0x3fd3333340000000)
cf29           0.30000001192092896      (raw 0x3fd3333340000000)
cf30           0.30000001192092896      (raw 0x3fd3333340000000)
cf31           0.30000001192092896      (raw 0x3fd3333340000000)
cfpscr         0x0      0
cvr0           {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr1           {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr2           {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr3           {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr4           {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr5           {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr6           {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr7           {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr8           {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr9           {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr10          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr11          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr12          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr13          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr14          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr15          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr16          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr17          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr18          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr19          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr20          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr21          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr22          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr23          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr24          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr25          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr26          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr27          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr28          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr29          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr30          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvr31          {uint128 = 0x00000000000000000000000000000000, v4_float =
{0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0, 0x0, 0x0}, v8_int16 = {0x0,
0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8 = {0x0 <repeats 16 times>}}
cvscr          0x0      0
cvrsave        0xffffffff       -1
cdscr          0x0      0
cppr           0xc000000000000  3377699720527872
ctar           0x0      0
cvs0           {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs1           {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs2           {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs3           {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs4           {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs5           {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs6           {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs7           {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs8           {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs9           {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs10          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs11          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs12          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs13          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs14          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs15          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs16          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs17          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs18          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs19          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs20          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs21          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs22          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs23          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs24          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs25          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs26          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs27          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs28          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs29          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs30          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs31          {uint128 = 0x3fd33333400000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x2, 0x1}, v4_int32 = {0x0, 0x0,
0x40000000, 0x3fd33333}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x4000,
0x3333, 0x3fd3}, v16_int8 = {0x0 <repeats 11 times>, 0x40, 0x33, 0x33,
0xd3, 0x3f}}
cvs32          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs33          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs34          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs35          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs36          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs37          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs38          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs39          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs40          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs41          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs42          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs43          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs44          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs45          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs46          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs47          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs48          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs49          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs50          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs51          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs52          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs53          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs54          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs55          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs56          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs57          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs58          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs59          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs60          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs61          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs62          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cvs63          {uint128 = 0x00000000000000000000000000000000, v2_double
= {0x0, 0x0}, v4_float = {0x0, 0x0, 0x0, 0x0}, v4_int32 = {0x0, 0x0,
0x0, 0x0}, v8_int16 = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}, v16_int8
= {0x0 <repeats 16 times>}}
cf32           0        (raw 0x0000000000000000)
cf33           0        (raw 0x0000000000000000)
cf34           0        (raw 0x0000000000000000)
cf35           0        (raw 0x0000000000000000)
cf36           0        (raw 0x0000000000000000)
cf37           0        (raw 0x0000000000000000)
cf38           0        (raw 0x0000000000000000)
cf39           0        (raw 0x0000000000000000)
cf40           0        (raw 0x0000000000000000)
cf41           0        (raw 0x0000000000000000)
cf42           0        (raw 0x0000000000000000)
cf43           0        (raw 0x0000000000000000)
cf44           0        (raw 0x0000000000000000)
cf45           0        (raw 0x0000000000000000)
cf46           0        (raw 0x0000000000000000)
cf47           0        (raw 0x0000000000000000)
cf48           0        (raw 0x0000000000000000)
cf49           0        (raw 0x0000000000000000)
cf50           0        (raw 0x0000000000000000)
cf51           0        (raw 0x0000000000000000)
cf52           0        (raw 0x0000000000000000)
cf53           0        (raw 0x0000000000000000)
cf54           0        (raw 0x0000000000000000)
cf55           0        (raw 0x0000000000000000)
cf56           0        (raw 0x0000000000000000)
cf57           0        (raw 0x0000000000000000)
cf58           0        (raw 0x0000000000000000)
cf59           0        (raw 0x0000000000000000)
cf60           0        (raw 0x0000000000000000)
cf61           0        (raw 0x0000000000000000)
cf62           0        (raw 0x0000000000000000)
cf63           0        (raw 0x0000000000000000)

Thanks and regards,
--
Edjunior Barbosa Machado

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Laurent Dufour]

On 07/04/2016 23:49, Michael Ellerman wrote:
> 
> 
> On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <ldufour@linux.vnet.ibm.com> wrote:
>> On 16/02/2016 09:59, Anshuman Khandual wrote:
>>> 	This patch series adds twelve new ELF core note sections which can
>>> be used with existing ptrace request PTRACE_GETREGSET-SETREGSET for
>> accessing
>>> various transactional memory and other miscellaneous debug register
>> sets on
>>> powerpc platform.
>>
>> Hi Michael,
>>
>> This series is required to handle TM state in CRIU.
>> Is there a chance to get it upstream soon ?
> 
> We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?

I just started integrating it in CRIU, my basic tests didn't report any
issue with the new ptrace API, but I can't state that it is bug free ;)

Cheers,
Laurent.

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Michael Ellerman]

On Mon, 2016-04-11 at 09:40 +0200, Laurent Dufour wrote:
> On 07/04/2016 23:49, Michael Ellerman wrote:
> > On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <ldufour@linux.vnet.ibm.com> wrote:
> > > This series is required to handle TM state in CRIU.
> > > Is there a chance to get it upstream soon ?
> > 
> > We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?
> 
> I just started integrating it in CRIU, my basic tests didn't report any
> issue with the new ptrace API, but I can't state that it is bug free ;)

Sure. But if it's working for CRIU that's at least postive :)

cheers

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Michael Ellerman]

On Mon, 2016-04-11 at 03:32 -0300, Edjunior Barbosa Machado wrote:
> Hi Michael, Anshuman,
> 
> I've managed to implement the GDB support for the new regsets and test
> on Power8 (BE and LE).

Great work thanks!

> The following is an example of GDB 'info
> registers all' partial output showing the new registers when inside a
> suspended transaction on Power8 LE using this patchset. Please let me
> know if you need any additional information or tests from GDB side.

What's the plan for merging the gdb changes?

> (gdb) info registers all
> ...
> dscr           0x0      0
> ppr            0xc000000000000  3377699720527872
> tar            0x0      0
> ebbrr          <unavailable>
> ebbhr          <unavailable>
> bescr          <unavailable>
> siar           <unavailable>
> sdar           <unavailable>
> sier           <unavailable>
> mmcr2          <unavailable>
> mmcr0          <unavailable>
> tfhar          0x10002b30       268446512
> texasr         0x110000098000001        76561196215435265
> tfiar          0x10002ad9       268446425
> cr0            0x10002b2c       268446508

Using 'c' as the prefix is a bit confusing here, as 'cr0' is usually used to
refer to the CR0 field of CR.

Speaking of which, I don't see CR here? Or is it somewhere above in the ... ?

Maybe the prefix could be 'c_' ?

Or do other arches already use 'c' as the prefix?

Otherwise looks good.

cheers

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Michael Ellerman]

On Mon, 2016-04-11 at 03:32 -0300, Edjunior Barbosa Machado wrote:
> Hi Michael, Anshuman,
> 
> I've managed to implement the GDB support for the new regsets and test
> on Power8 (BE and LE).

Great work thanks!

> The following is an example of GDB 'info
> registers all' partial output showing the new registers when inside a
> suspended transaction on Power8 LE using this patchset. Please let me
> know if you need any additional information or tests from GDB side.

What's the plan for merging the gdb changes?

> (gdb) info registers all
> ...
> dscr           0x0      0
> ppr            0xc000000000000  3377699720527872
> tar            0x0      0
> ebbrr          <unavailable>
> ebbhr          <unavailable>
> bescr          <unavailable>
> siar           <unavailable>
> sdar           <unavailable>
> sier           <unavailable>
> mmcr2          <unavailable>
> mmcr0          <unavailable>
> tfhar          0x10002b30       268446512
> texasr         0x110000098000001        76561196215435265
> tfiar          0x10002ad9       268446425
> cr0            0x10002b2c       268446508

Using 'c' as the prefix is a bit confusing here, as 'cr0' is usually used to
refer to the CR0 field of CR.

Speaking of which, I don't see CR here? Or is it somewhere above in the ... ?

Maybe the prefix could be 'c_' ?

Or do other arches already use 'c' as the prefix?

Otherwise looks good.

cheers

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Laurent Dufour]

[-- Attachment #1: Type: text/plain, Size: 961 bytes --]

On 13/04/2016 07:14, Michael Ellerman wrote:
> On Mon, 2016-04-11 at 09:40 +0200, Laurent Dufour wrote:
>> On 07/04/2016 23:49, Michael Ellerman wrote:
>>> On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <ldufour@linux.vnet.ibm.com> wrote:
>>>> This series is required to handle TM state in CRIU.
>>>> Is there a chance to get it upstream soon ?
>>>
>>> We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?
>>
>> I just started integrating it in CRIU, my basic tests didn't report any
>> issue with the new ptrace API, but I can't state that it is bug free ;)
> 
> Sure. But if it's working for CRIU that's at least postive :)

I did additional tests and the Anshuman's series is working fine for
CRIU's support with the attached patch applied.

Michael, could you please applied the attached patch among the
Anshuman's series ?

Thanks,
Laurent.


[-- Attachment #2: ppc64-allow-ptrace-to-set-TM-bits.patch --]
[-- Type: text/x-patch, Size: 2081 bytes --]

>From 7a4f07c54afdbe7bef84d1f700ab9262f449513a Mon Sep 17 00:00:00 2001
From: Laurent Dufour <ldufour@linux.vnet.ibm.com>
Date: Mon, 11 Apr 2016 18:59:16 +0200
Subject: [PATCH] ppc64: allow ptrace to set TM bits

This patch allows the MSR bits relative to the Transactional memory
state to be manipulated through the ptrace API.

However, in the case the TM available bit is not set in the
manipulated MSR, the changes are ignored.

When dealing with the checkpointed MSR, we must be sure that the TM
state bits will not be set since the checkpointed state can't be a
transactional one.

Signed-off-by: Laurent Dufour <ldufour@linux.vnet.ibm.com>
---
 arch/powerpc/kernel/ptrace.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index b063fc499c1d..5c792f0bf1ca 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -161,8 +161,12 @@ const char *regs_query_register_name(unsigned int offset)
 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 #define MSR_DEBUGCHANGE	0
 #else
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+#define MSR_DEBUGCHANGE	(MSR_TS_MASK | MSR_SE | MSR_BE)
+#else
 #define MSR_DEBUGCHANGE	(MSR_SE | MSR_BE)
 #endif
+#endif
 
 /*
  * Max register writeable via put_reg
@@ -180,6 +184,12 @@ static unsigned long get_user_msr(struct task_struct *task)
 
 static int set_user_msr(struct task_struct *task, unsigned long msr)
 {
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+	if (!(task->thread.regs->msr & MSR_TM)) {
+		/* If TM is not available, discard TM bits changes */
+		msr &= ~(MSR_TM | MSR_TS_MASK);
+	}
+#endif
 	task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
 	task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
 	return 0;
@@ -193,6 +203,7 @@ static unsigned long get_user_ckpt_msr(struct task_struct *task)
 
 static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr)
 {
+	msr &= ~MSR_TS_MASK;	/* Checkpoint state can't be in transaction */
 	task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE;
 	task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE;
 	return 0;
-- 
1.9.1

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Edjunior Barbosa Machado]

On 04/13/2016 02:36 AM, Michael Ellerman wrote:
> On Mon, 2016-04-11 at 03:32 -0300, Edjunior Barbosa Machado wrote:
>> Hi Michael, Anshuman,
>>
>> I've managed to implement the GDB support for the new regsets and test
>> on Power8 (BE and LE).
> 
> Great work thanks!
> 
>> The following is an example of GDB 'info
>> registers all' partial output showing the new registers when inside a
>> suspended transaction on Power8 LE using this patchset. Please let me
>> know if you need any additional information or tests from GDB side.
> 
> What's the plan for merging the gdb changes?

Thanks for the feedback, Michael. I intend to submit the patches to the
gdb mailing list for review right after the kernel patchset is checked in.

> 
>> (gdb) info registers all
>> ...
>> dscr           0x0      0
>> ppr            0xc000000000000  3377699720527872
>> tar            0x0      0
>> ebbrr          <unavailable>
>> ebbhr          <unavailable>
>> bescr          <unavailable>
>> siar           <unavailable>
>> sdar           <unavailable>
>> sier           <unavailable>
>> mmcr2          <unavailable>
>> mmcr0          <unavailable>
>> tfhar          0x10002b30       268446512
>> texasr         0x110000098000001        76561196215435265
>> tfiar          0x10002ad9       268446425
>> cr0            0x10002b2c       268446508
> 
> Using 'c' as the prefix is a bit confusing here, as 'cr0' is usually used to
> refer to the CR0 field of CR.
> 
> Speaking of which, I don't see CR here? Or is it somewhere above in the ... ?
> 
> Maybe the prefix could be 'c_' ?
> 
> Or do other arches already use 'c' as the prefix?

Good point, I hadn't thought about the possible confusion with CR
register (CR doesn't appear in the excerpt because it is just a partial
output of 'info registers all', reduced to the new registers only). As
far as I am aware, we don't have other arches that use 'c' as prefix
(Are there other arches that provide checkpointed registers? s390 gdb
uses 't' as prefix, but for the transactional regs, which would be the
"opposite" of our checkpointed ones here, if I'm not mistaken), but this
can be changed with no difficult in gdb code.

Thanks and regards,
--
Edjunior Barbosa Machado

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Michael Ellerman]

On Tue, 2016-02-16 at 14:29 +0530, Anshuman Khandual wrote:

> 	This patch series adds twelve new ELF core note sections which can
> be used with existing ptrace request PTRACE_GETREGSET-SETREGSET for accessing
> various transactional memory and other miscellaneous debug register sets on
> powerpc platform.
> 
> Test Result (All tests pass on both BE and LE)
> ----------------------------------------------
> ptrace-ebb		PASS
> ptrace-gpr		PASS
> ptrace-tm-gpr		PASS
> ptrace-tm-spd-gpr	PASS
> ptrace-tar		PASS
> ptrace-tm-tar		PASS
> ptrace-tm-spd-tar	PASS
> ptrace-vsx		PASS
> ptrace-tm-vsx		PASS
> ptrace-tm-spd-vsx	PASS
> ptrace-tm-spr		PASS

How are you building the tests? On BE I get:


  In file included from ptrace-tm-gpr.c:12:0:
  ptrace-tm-gpr.c: In function ‘trace_tm_gpr’:
  In file included from ptrace.h:31:0,
                   from ptrace-tm-vsx.c:11:
  ptrace-tm-vsx.c: In function ‘ptrace_tm_vsx’:
  ptrace-gpr.h:20:19: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define FPR_2_REP 0x3f60624de0000000
                     ^
  ptrace-tm-gpr.c:209:26: note: in expansion of macro ‘FPR_2_REP’
    ret = validate_fpr(fpr, FPR_2_REP);
                            ^
  ptrace-tm-vsx.c:150:46: error: ‘PPC_FEATURE2_HTM’ undeclared (first use in this function)
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  ptrace-gpr.h:19:19: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define FPR_1_REP 0x3f50624de0000000
                     ^
  ptrace-tm-gpr.c:217:26: note: in expansion of macro ‘FPR_1_REP’
    ret = validate_fpr(fpr, FPR_1_REP);
                            ^
  ptrace-tm-vsx.c:150:46: note: each undeclared identifier is reported only once for each function it appears in
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  ptrace-gpr.h:21:19: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define FPR_3_REP 0x3f689374c0000000
                     ^
  ptrace-tm-gpr.c:233:30: note: in expansion of macro ‘FPR_3_REP’
    ret = write_ckpt_fpr(child, FPR_3_REP);
                                ^
  In file included from ptrace.h:31:0,
                   from ptrace-tm-gpr.c:11:
  ptrace-tm-gpr.c: In function ‘ptrace_tm_gpr’:
  ptrace-tm-gpr.c:249:46: error: ‘PPC_FEATURE2_HTM’ undeclared (first use in this function)
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  ptrace-tm-gpr.c:249:46: note: each undeclared identifier is reported only once for each function it appears in
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  cc1: all warnings being treated as errors
  In file included from ../pmu/ebb/ebb.h:12:0,
                   from ptrace-ebb.c:11:
  ptrace-ebb.h: In function ‘reset_ebb_with_clear_mask’:
  ../pmu/ebb/../../reg.h:49:31: error: left shift count >= width of type [-Werror=shift-count-overflow]
   #define BESCR_PME      (0x1ul << 32) /* PMU Event-based exception Enable */
                                 ^
  ../pmu/ebb/../../reg.h:16:60: note: in definition of macro ‘mtspr’
                                       : "r" ((unsigned long)(v)) \
                                                              ^
  ptrace-ebb.h:73:28: note: in expansion of macro ‘BESCR_PME’
           mtspr(SPRN_BESCRS, BESCR_PME);
                              ^
  In file included from ptrace-tm-tar.c:12:0:
  ptrace-tm-tar.c: In function ‘tm_tar’:
  ptrace-tar.h:24:17: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define PPR_4   0x10000000000000        /* or 2,2,2 */
                   ^
  ptrace-tm-tar.c:78:45: note: in expansion of macro ‘PPR_4’
     ret = validate_tar_registers(regs, TAR_4, PPR_4, DSCR_4);
                                               ^
  In file included from ptrace-tm-spd-tar.c:12:0:
  ptrace-tm-spd-tar.c: In function ‘tm_spd_tar’:
  ptrace-tm-tar.c: In function ‘trace_tm_tar’:
  ptrace-tar.h:22:17: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define PPR_2   0x8000000000000         /* or 1,1,1 */
                   ^
  ptrace-tm-tar.c:103:44: note: in expansion of macro ‘PPR_2’
    ret = validate_tar_registers(regs, TAR_2, PPR_2, DSCR_2);
                                              ^
  In file included from ptrace-gpr.c:12:0:
  ptrace-gpr.c: In function ‘trace_gpr’:
  ptrace-tar.h:21:17: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define PPR_1   0x4000000000000         /* or 31,31,31*/
                   ^
  ptrace-tm-tar.c:113:44: note: in expansion of macro ‘PPR_1’
    ret = validate_tar_registers(regs, TAR_1, PPR_1, DSCR_1);
                                              ^
  ptrace-tar.h:24:17: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define PPR_4   0x10000000000000        /* or 2,2,2 */
                   ^
  ptrace-tm-spd-tar.c:89:45: note: in expansion of macro ‘PPR_4’
     ret = validate_tar_registers(regs, TAR_4, PPR_4, DSCR_4);
                                               ^
  ptrace-tar.h:24:17: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define PPR_4   0x10000000000000        /* or 2,2,2 */
                   ^
  ptrace-tm-tar.c:117:47: note: in expansion of macro ‘PPR_4’
    ret = write_ckpt_tar_registers(child, TAR_4, PPR_4, DSCR_4);
                                                 ^
  ptrace-tm-tar.c:121:9: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 4 has type ‘long long int’ [-Werror=format=]
    printf("%-30s TAR: %u PPR: %lx DSCR: %u\n", ptrace_write_ckpt, TAR_4, PPR_4, DSCR_4);
           ^
  ptrace-gpr.h:19:19: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define FPR_1_REP 0x3f50624de0000000
                     ^
  ptrace-gpr.c:129:26: note: in expansion of macro ‘FPR_1_REP’
    ret = validate_fpr(fpr, FPR_1_REP);
                            ^
  ptrace-tm-spd-tar.c: In function ‘trace_tm_spd_tar’:
  ptrace-tar.h:23:17: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define PPR_3   0xc000000000000         /* or 6,6,6 */
                   ^
  ptrace-tm-spd-tar.c:114:44: note: in expansion of macro ‘PPR_3’
    ret = validate_tar_registers(regs, TAR_3, PPR_3, DSCR_3);
                                              ^
  In file included from ptrace.h:31:0,
                   from ptrace-tm-tar.c:11:
  ptrace-tm-tar.c: In function ‘ptrace_tm_tar’:
  ptrace-gpr.h:21:19: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define FPR_3_REP 0x3f689374c0000000
                     ^
  ptrace-gpr.c:137:25: note: in expansion of macro ‘FPR_3_REP’
    ret = write_fpr(child, FPR_3_REP);
                           ^
  ptrace-tm-tar.c:134:46: error: ‘PPC_FEATURE2_HTM’ undeclared (first use in this function)
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  ptrace-tm-tar.c:134:46: note: each undeclared identifier is reported only once for each function it appears in
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  ptrace-tar.h:21:17: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define PPR_1   0x4000000000000         /* or 31,31,31*/
                   ^
  ptrace-tm-spd-tar.c:124:44: note: in expansion of macro ‘PPR_1’
    ret = validate_tar_registers(regs, TAR_1, PPR_1, DSCR_1);
                                              ^
  In file included from ptrace-tm-spd-gpr.c:12:0:
  ptrace-tm-spd-gpr.c: In function ‘trace_tm_spd_gpr’:
  ptrace-tar.h:24:17: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define PPR_4   0x10000000000000        /* or 2,2,2 */
                   ^
  ptrace-tm-spd-tar.c:128:47: note: in expansion of macro ‘PPR_4’
    ret = write_ckpt_tar_registers(child, TAR_4, PPR_4, DSCR_4);
                                                 ^
  ptrace-tm-spd-tar.c:132:9: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 4 has type ‘long long int’ [-Werror=format=]
    printf("%-30s TAR: %u PPR: %lx DSCR: %u\n", ptrace_write_ckpt, TAR_4, PPR_4, DSCR_4);
           ^
  ptrace-gpr.h:22:19: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define FPR_4_REP 0x3f70624de0000000
                     ^
  ptrace-tm-spd-gpr.c:235:26: note: in expansion of macro ‘FPR_4_REP’
    ret = validate_fpr(fpr, FPR_4_REP);
                            ^
  In file included from ptrace.h:31:0,
                   from ptrace-tm-spd-tar.c:11:
  ptrace-tm-spd-tar.c: In function ‘ptrace_tm_spd_tar’:
  ptrace-gpr.h:19:19: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define FPR_1_REP 0x3f50624de0000000
                     ^
  ptrace-tm-spd-gpr.c:243:26: note: in expansion of macro ‘FPR_1_REP’
    ret = validate_fpr(fpr, FPR_1_REP);
                            ^
  ptrace-tm-spd-tar.c:145:46: error: ‘PPC_FEATURE2_HTM’ undeclared (first use in this function)
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  ptrace-tm-spd-tar.c:145:46: note: each undeclared identifier is reported only once for each function it appears in
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  ptrace-gpr.h:21:19: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define FPR_3_REP 0x3f689374c0000000
                     ^
  ptrace-tm-spd-gpr.c:259:30: note: in expansion of macro ‘FPR_3_REP’
    ret = write_ckpt_fpr(child, FPR_3_REP);
                                ^
  In file included from ptrace.h:31:0,
                   from ptrace-tm-spd-vsx.c:11:
  ptrace-tm-spd-vsx.c: In function ‘ptrace_tm_spd_vsx’:
  In file included from ptrace.h:31:0,
                   from ptrace-tm-spd-gpr.c:11:
  ptrace-tm-spd-gpr.c: In function ‘ptrace_tm_spd_gpr’:
  ptrace-tm-spd-gpr.c:275:46: error: ‘PPC_FEATURE2_HTM’ undeclared (first use in this function)
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  ptrace-tm-spd-gpr.c:275:46: note: each undeclared identifier is reported only once for each function it appears in
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  ptrace-tm-spd-vsx.c:164:46: error: ‘PPC_FEATURE2_HTM’ undeclared (first use in this function)
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  ptrace-tm-spd-vsx.c:164:46: note: each undeclared identifier is reported only once for each function it appears in
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  cc1: all warnings being treated as errors
  cc1: all warnings being treated as errors
  cc1: all warnings being treated as errors
  In file included from ptrace.h:31:0,
                   from ptrace-tm-spr.c:11:
  ptrace-tm-spr.c: In function ‘ptrace_tm_spr’:
  ptrace-tm-spr.c:118:46: error: ‘PPC_FEATURE2_HTM’ undeclared (first use in this function)
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  ptrace-tm-spr.c:118:46: note: each undeclared identifier is reported only once for each function it appears in
    SKIP_IF(!((long)get_auxv_entry(AT_HWCAP2) & PPC_FEATURE2_HTM));
                                                ^
  /home/kerkins/workspace/kernel-build-selftests/arch/powerpc/compiler/gcc_ubuntu_be/linux/tools/testing/selftests/powerpc/utils.h:49:7: note: in definition of macro ‘SKIP_IF’
    if ((x)) {      \
         ^
  ptrace-tar.c: In function ‘tar’:
  ptrace-tar.c:25:9: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 4 has type ‘long long int’ [-Werror=format=]
    printf("%-30s TAR: %u PPR: %lx DSCR: %u\n", user_write, TAR_1, PPR_1, DSCR_1);
           ^
  In file included from ptrace-tar.c:12:0:
  ptrace-tar.h:22:17: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define PPR_2   0x8000000000000         /* or 1,1,1 */
                   ^
  ptrace-tar.c:44:43: note: in expansion of macro ‘PPR_2’
    ret = validate_tar_registers(reg, TAR_2, PPR_2, DSCR_2);
                                             ^
  ptrace-tar.c: In function ‘trace_tar’:
  ptrace-tar.h:21:17: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define PPR_1   0x4000000000000         /* or 31,31,31*/
                   ^
  ptrace-tar.c:66:43: note: in expansion of macro ‘PPR_1’
    ret = validate_tar_registers(reg, TAR_1, PPR_1, DSCR_1);
                                             ^
  ptrace-tar.c: In function ‘trace_tar_write’:
  ptrace-tar.h:22:17: error: large integer implicitly truncated to unsigned type [-Werror=overflow]
   #define PPR_2   0x8000000000000         /* or 1,1,1 */
                   ^
  ptrace-tar.c:85:42: note: in expansion of macro ‘PPR_2’
    ret = write_tar_registers(child, TAR_2, PPR_2, DSCR_2);
                                            ^
  ptrace-tar.c:89:9: error: format ‘%lx’ expects argument of type ‘long unsigned int’, but argument 4 has type ‘long long int’ [-Werror=format=]
    printf("%-30s TAR: %u PPR: %lx DSCR: %u\n", ptrace_write_running, TAR_2, PPR_2, DSCR_2);
           ^
  cc1: all warnings being treated as errors
  cc1: all warnings being treated as errors
  cc1: all warnings being treated as errors
  <builtin>: recipe for target 'ptrace-tm-spd-tar' failed
  make[1]: *** [ptrace-tm-spd-tar] Error 1
  <builtin>: recipe for target 'ptrace-tm-tar' failed
  make[1]: *** [ptrace-tm-tar] Error 1
  <builtin>: recipe for target 'ptrace-tm-vsx' failed
  make[1]: *** [ptrace-tm-vsx] Error 1
  <builtin>: recipe for target 'ptrace-tm-spd-gpr' failed
  make[1]: *** [ptrace-tm-spd-gpr] Error 1
  <builtin>: recipe for target 'ptrace-tm-spr' failed
  make[1]: *** [ptrace-tm-spr] Error 1
  <builtin>: recipe for target 'ptrace-tm-gpr' failed
  make[1]: *** [ptrace-tm-gpr] Error 1
  <builtin>: recipe for target 'ptrace-tm-spd-vsx' failed
  make[1]: *** [ptrace-tm-spd-vsx] Error 1
  <builtin>: recipe for target 'ptrace-tar' failed
  make[1]: *** [ptrace-tar] Error 1
  <builtin>: recipe for target 'ptrace-gpr' failed
  make[1]: *** [ptrace-gpr] Error 1
  ../pmu/ebb/ebb_handler.S: Assembler messages:
  ../pmu/ebb/ebb_handler.S:242: Error: syntax error; found `@', expected `,'
  ../pmu/ebb/ebb_handler.S:242: Error: junk at end of line: `@highest'
  ../pmu/ebb/ebb_handler.S:242: Error: syntax error; found `@', expected `,'
  ../pmu/ebb/ebb_handler.S:242: Error: junk at end of line: `@higher'
  <builtin>: recipe for target 'ptrace-ebb' failed

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Anshuman Khandual]

On 05/06/2016 05:19 PM, Michael Ellerman wrote:
> On Tue, 2016-02-16 at 14:29 +0530, Anshuman Khandual wrote:
> 
>> > 	This patch series adds twelve new ELF core note sections which can
>> > be used with existing ptrace request PTRACE_GETREGSET-SETREGSET for accessing
>> > various transactional memory and other miscellaneous debug register sets on
>> > powerpc platform.
>> > 
>> > Test Result (All tests pass on both BE and LE)
>> > ----------------------------------------------
>> > ptrace-ebb		PASS
>> > ptrace-gpr		PASS
>> > ptrace-tm-gpr		PASS
>> > ptrace-tm-spd-gpr	PASS
>> > ptrace-tar		PASS
>> > ptrace-tm-tar		PASS
>> > ptrace-tm-spd-tar	PASS
>> > ptrace-vsx		PASS
>> > ptrace-tm-vsx		PASS
>> > ptrace-tm-spd-vsx	PASS
>> > ptrace-tm-spr		PASS
> How are you building the tests? On BE I get:

Yeah, it fails to compile on 32 bit BE. Will make it explicit -m64 next time around.

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Laurent Dufour]

On 21/04/2016 18:00, Laurent Dufour wrote:
> On 13/04/2016 07:14, Michael Ellerman wrote:
>> On Mon, 2016-04-11 at 09:40 +0200, Laurent Dufour wrote:
>>> On 07/04/2016 23:49, Michael Ellerman wrote:
>>>> On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <ldufour@linux.vnet.ibm.com> wrote:
>>>>> This series is required to handle TM state in CRIU.
>>>>> Is there a chance to get it upstream soon ?
>>>>
>>>> We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?
>>>
>>> I just started integrating it in CRIU, my basic tests didn't report any
>>> issue with the new ptrace API, but I can't state that it is bug free ;)
>>
>> Sure. But if it's working for CRIU that's at least postive :)
> 
> I did additional tests and the Anshuman's series is working fine for
> CRIU's support with the attached patch applied.
> 
> Michael, could you please applied the attached patch among the
> Anshuman's series ?

Hi Michael,

Is there any chance we get this series pushed in 4.7 ?

Thanks,
Laurent.

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Michael Ellerman]

On Fri, 2016-05-27 at 10:07 +0200, Laurent Dufour wrote:

> On 21/04/2016 18:00, Laurent Dufour wrote:

> > On 13/04/2016 07:14, Michael Ellerman wrote:

> > > On Mon, 2016-04-11 at 09:40 +0200, Laurent Dufour wrote:

> > > > On 07/04/2016 23:49, Michael Ellerman wrote:

> > > > > On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <ldufour@linux.vnet.ibm.com> wrote:

> > > > > > This series is required to handle TM state in CRIU.
> > > > > > Is there a chance to get it upstream soon ?
> > > > > 
> > > > > We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?
> > > > 
> > > > I just started integrating it in CRIU, my basic tests didn't report any
> > > > issue with the new ptrace API, but I can't state that it is bug free ;)
> > > 
> > > Sure. But if it's working for CRIU that's at least postive :)
> > 
> > I did additional tests and the Anshuman's series is working fine for
> > CRIU's support with the attached patch applied.
> > 
> > Michael, could you please applied the attached patch among the
> > Anshuman's series ?
> 
> Hi Michael,
> 
> Is there any chance we get this series pushed in 4.7 ?

Hi Laurent,

Sorry no. My next branch closed for 4.7 about 3 weeks ago.

This series has been blocked for a long time on the gdb support, but that is
now working. However it still doesn't pass its own selftests, and I had some
disagreements with the implementation - it duplicates a lot of code rather
than refactoring things.

I'm waiting on a patch from Cyril which will rework how the TM FP state is
handled, and that should make this series easier to implement.

The plan is that both should go into 4.8.

cheers

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Michael Ellerman]

On Fri, 2016-05-27 at 10:07 +0200, Laurent Dufour wrote:

> On 21/04/2016 18:00, Laurent Dufour wrote:

> > On 13/04/2016 07:14, Michael Ellerman wrote:

> > > On Mon, 2016-04-11 at 09:40 +0200, Laurent Dufour wrote:

> > > > On 07/04/2016 23:49, Michael Ellerman wrote:

> > > > > On 7 April 2016 7:23:46 pm AEST, Laurent Dufour <ldufour@linux.vnet.ibm.com> wrote:

> > > > > > This series is required to handle TM state in CRIU.
> > > > > > Is there a chance to get it upstream soon ?
> > > > > 
> > > > > We were waiting on the gdb support to make sure it had some testing. If it's working for CRIU that would be a good data point, have you actually tested it with CRIU?
> > > > 
> > > > I just started integrating it in CRIU, my basic tests didn't report any
> > > > issue with the new ptrace API, but I can't state that it is bug free ;)
> > > 
> > > Sure. But if it's working for CRIU that's at least postive :)
> > 
> > I did additional tests and the Anshuman's series is working fine for
> > CRIU's support with the attached patch applied.
> > 
> > Michael, could you please applied the attached patch among the
> > Anshuman's series ?
> 
> Hi Michael,
> 
> Is there any chance we get this series pushed in 4.7 ?

Hi Laurent,

Sorry no. My next branch closed for 4.7 about 3 weeks ago.

This series has been blocked for a long time on the gdb support, but that is
now working. However it still doesn't pass its own selftests, and I had some
disagreements with the implementation - it duplicates a lot of code rather
than refactoring things.

I'm waiting on a patch from Cyril which will rework how the TM FP state is
handled, and that should make this series easier to implement.

The plan is that both should go into 4.8.

cheers

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Anshuman Khandual]

On 05/31/2016 04:42 AM, Michael Ellerman wrote:
> Hi Laurent,
> 
> Sorry no. My next branch closed for 4.7 about 3 weeks ago.
> 
> This series has been blocked for a long time on the gdb support, but that is
> now working. However it still doesn't pass its own selftests, and I had some

This series was clearing all of the selftests at the time it was posted.
But yes, it has some assumptions from timing and sync perspective which
gets broken some times as the kernel changes. Its been bit difficult to
perfect the sync requirements as we can do only some much inside the
transaction once it gets started. There are scopes here to improve these
selftests but not clearing them today does not really mean the patches are
now functionally broken.

> disagreements with the implementation - it duplicates a lot of code rather
> than refactoring things.

hmm, sorry, I dont remember the context here. Can you please point to the
discussion in this regard ?

> 
> I'm waiting on a patch from Cyril which will rework how the TM FP state is
> handled, and that should make this series easier to implement.

Can you please elaborate on this ? Has this patch been posted in the mailing
list ? How does this make it easier for us to implement these ELF notes ?

> 
> The plan is that both should go into 4.8.

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Anshuman Khandual]

On 05/31/2016 04:42 AM, Michael Ellerman wrote:
> Hi Laurent,
> 
> Sorry no. My next branch closed for 4.7 about 3 weeks ago.
> 
> This series has been blocked for a long time on the gdb support, but that is
> now working. However it still doesn't pass its own selftests, and I had some

This series was clearing all of the selftests at the time it was posted.
But yes, it has some assumptions from timing and sync perspective which
gets broken some times as the kernel changes. Its been bit difficult to
perfect the sync requirements as we can do only some much inside the
transaction once it gets started. There are scopes here to improve these
selftests but not clearing them today does not really mean the patches are
now functionally broken.

> disagreements with the implementation - it duplicates a lot of code rather
> than refactoring things.

hmm, sorry, I dont remember the context here. Can you please point to the
discussion in this regard ?

> 
> I'm waiting on a patch from Cyril which will rework how the TM FP state is
> handled, and that should make this series easier to implement.

Can you please elaborate on this ? Has this patch been posted in the mailing
list ? How does this make it easier for us to implement these ELF notes ?

> 
> The plan is that both should go into 4.8.

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Cyril Bur]

[-- Attachment #1: Type: text/plain, Size: 2358 bytes --]

On 1 June 2016 at 18:26, Anshuman Khandual <khandual@linux.vnet.ibm.com>
wrote:

> On 05/31/2016 04:42 AM, Michael Ellerman wrote:
> > Hi Laurent,
> >
> > Sorry no. My next branch closed for 4.7 about 3 weeks ago.
> >
> > This series has been blocked for a long time on the gdb support, but
> that is
> > now working. However it still doesn't pass its own selftests, and I had
> some
>
> This series was clearing all of the selftests at the time it was posted.
> But yes, it has some assumptions from timing and sync perspective which
> gets broken some times as the kernel changes. Its been bit difficult to
> perfect the sync requirements as we can do only some much inside the
> transaction once it gets started. There are scopes here to improve these
> selftests but not clearing them today does not really mean the patches are
> now functionally broken.
>
> > disagreements with the implementation - it duplicates a lot of code
> rather
> > than refactoring things.
>
> hmm, sorry, I dont remember the context here. Can you please point to the
> discussion in this regard ?
>
> >
> > I'm waiting on a patch from Cyril which will rework how the TM FP state
> is
> > handled, and that should make this series easier to implement.
>
> Can you please elaborate on this ? Has this patch been posted in the
> mailing
> list ? How does this make it easier for us to implement these ELF notes ?


Hi Anshuman,

I'm doing a bit of a rewrite of the TM handling of the FP/VMX/VSX state.

At the moment is is rather confusing since pt_regs is the always the 'live'
state
and theres a ckpt_regs that is the pt_regs for the checkpointed state.
FPU/VMX/VSX
is done differently which is really only creating confusion so I'm changing
it to do the
same at for pt_regs/ckpt_regs. Ultimately this is part of more work from me
but
Michael has told me that at least this bit is useful now so I'm splitting
it off from
the bigger picture and sending asap. At the very least it will make it
easier to know
what and where the transactional state it and where the checkpointed state
is.

It isn't on the list but I hope I'll get it out today.

Cyril


> >
> > The plan is that both should go into 4.8.
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/linuxppc-dev
>



-- 
Cyril

[-- Attachment #2: Type: text/html, Size: 3527 bytes --]

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Anshuman Khandual]

On 06/03/2016 03:56 AM, Cyril Bur wrote:
> On 1 June 2016 at 18:26, Anshuman Khandual <khandual@linux.vnet.ibm.com>
> wrote:
> 
>> On 05/31/2016 04:42 AM, Michael Ellerman wrote:
>>> Hi Laurent,
>>>
>>> Sorry no. My next branch closed for 4.7 about 3 weeks ago.
>>>
>>> This series has been blocked for a long time on the gdb support, but
>> that is
>>> now working. However it still doesn't pass its own selftests, and I had
>> some
>>
>> This series was clearing all of the selftests at the time it was posted.
>> But yes, it has some assumptions from timing and sync perspective which
>> gets broken some times as the kernel changes. Its been bit difficult to
>> perfect the sync requirements as we can do only some much inside the
>> transaction once it gets started. There are scopes here to improve these
>> selftests but not clearing them today does not really mean the patches are
>> now functionally broken.
>>
>>> disagreements with the implementation - it duplicates a lot of code
>> rather
>>> than refactoring things.
>>
>> hmm, sorry, I dont remember the context here. Can you please point to the
>> discussion in this regard ?
>>
>>>
>>> I'm waiting on a patch from Cyril which will rework how the TM FP state
>> is
>>> handled, and that should make this series easier to implement.
>>
>> Can you please elaborate on this ? Has this patch been posted in the
>> mailing
>> list ? How does this make it easier for us to implement these ELF notes ?
> 
> 
> Hi Anshuman,
> 
> I'm doing a bit of a rewrite of the TM handling of the FP/VMX/VSX state.
> 
> At the moment is is rather confusing since pt_regs is the always the 'live'
> state
> and theres a ckpt_regs that is the pt_regs for the checkpointed state.
> FPU/VMX/VSX
> is done differently which is really only creating confusion so I'm changing
> it to do the
> same at for pt_regs/ckpt_regs. Ultimately this is part of more work from me

But that changes the basic semantics on which this ptrace series is written.
With this change, a significant part of the ptrace series has to be changed.
Its just an improvement on how we store running and check pointed values for
FP/VSX/VMX registers inside the kernel. How does it improve ptrace interface
from the user point of view ? If not, then why this change is necessary for
the acceptance of this patch series ? This change should be implemented as
an independent work and then necessary ptrace change can be incorporated
there after.

> but
> Michael has told me that at least this bit is useful now so I'm splitting
> it off from
> the bigger picture and sending asap. At the very least it will make it
> easier to know
> what and where the transactional state it and where the checkpointed state
> is.
> 
> It isn't on the list but I hope I'll get it out today.

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Michael Ellerman]

On Mon, 2016-06-06 at 14:27 +0530, Anshuman Khandual wrote:
> On 06/03/2016 03:56 AM, Cyril Bur wrote:
> > 
> > At the moment is is rather confusing since pt_regs is the always the 'live'
> > state and theres a ckpt_regs that is the pt_regs for the checkpointed state.
> > FPU/VMX/VSX is done differently which is really only creating confusion so I'm changing
> > it to do the same at for pt_regs/ckpt_regs. Ultimately this is part of more work from me
> 
> But that changes the basic semantics on which this ptrace series is written.
> With this change, a significant part of the ptrace series has to be changed.

Yes, that's the whole point.

In fact half of the code should vanish, because the only difference between
copying the live or checkpointed state out to userspace should be which regs
struct you pass to the function.

> Its just an improvement on how we store running and check pointed values for
> FP/VSX/VMX registers inside the kernel. How does it improve ptrace interface
> from the user point of view ? If not, then why this change is necessary for
> the acceptance of this patch series ?

Because the clean-ups never happen once a series is merged, and I'm left to deal
with it.

cheers

Re: [PATCH V10 00/28] Add new powerpc specific ELF core notes

[Michael Ellerman]

On Mon, 2016-06-06 at 14:27 +0530, Anshuman Khandual wrote:
> On 06/03/2016 03:56 AM, Cyril Bur wrote:
> > 
> > At the moment is is rather confusing since pt_regs is the always the 'live'
> > state and theres a ckpt_regs that is the pt_regs for the checkpointed state.
> > FPU/VMX/VSX is done differently which is really only creating confusion so I'm changing
> > it to do the same at for pt_regs/ckpt_regs. Ultimately this is part of more work from me
> 
> But that changes the basic semantics on which this ptrace series is written.
> With this change, a significant part of the ptrace series has to be changed.

Yes, that's the whole point.

In fact half of the code should vanish, because the only difference between
copying the live or checkpointed state out to userspace should be which regs
struct you pass to the function.

> Its just an improvement on how we store running and check pointed values for
> FP/VSX/VMX registers inside the kernel. How does it improve ptrace interface
> from the user point of view ? If not, then why this change is necessary for
> the acceptance of this patch series ?

Because the clean-ups never happen once a series is merged, and I'm left to deal
with it.

cheers