* [RFC i-g-t 0/9] Remove compile time depencencies on libdrm_intel.
@ 2016-05-20 22:59 robert.foss
2016-05-20 22:59 ` [RFC i-g-t 1/9] configure.ac: Test for libdrm_intel and build for it if present robert.foss
` (8 more replies)
0 siblings, 9 replies; 29+ messages in thread
From: robert.foss @ 2016-05-20 22:59 UTC (permalink / raw)
To: daniel.vetter, daniel.stone, marius.c.vlad, tomeu.vizoso, emil.velikov
Cc: intel-gfx
From: Robert Foss <robert.foss@collabora.com>
Hey,
I've been looking at the possibilty of removing the compile time depency on
libdrm_intel. There are two technical solutions to this problem as far as
I can see; stubs and conditional compilation.
I'd like to compare the two approaches to provide an overview.
Conditional compilation:
+ Programs that will not work on a given platform are not built.
+ Faster compilation (especially helpful on slow platforms like the RPi2).
- Combinatorial complexity of different environments (what to build if we
have libpciaccess and libdrm_vc4 but no libintel_drm for example), that
that quickly will get worse with more configurations.
- Currently some sources like igt_aux/igt_kms partially depend on
libdrm_intel, to avoid #ifdef hell, configuraiton specific functionality
should have to be extracted into new files.
Stubs:
+ Relatively straight forward to implement, as can be seen from these
patches.
+ Can easily be extended for any depency.
- Duplicating defines/structs/functions is a maintenance burden.
- Some built binaries will always skip, and are essentially useless.
- Little compilation speedup.
Robert Foss (9):
configure.ac: Test for libdrm_intel and build for it if present.
benchmarks/Makefile: Don't build benchmarks that depend on
libdrm_intel.
tools/Makefile: Don't build tools that depend on libdrm_intel.
demos/Makefile: Don't build tools that depend on libdrm_intel.
tests/gem_ppgtt: Switched to new aliases of intel specific functions.
tests/gem_render_tiled_blits: Switched to new aliases of intel
specific functions.
lib/intel_drm_stubs: Add stubs for functionality from libdrm_intel.
lib: Replace intel specific header includes with intel_drm_stubs.h.
tests: Replace intel specific header includes with intel_drm_stubs.h.
benchmarks/Makefile.sources | 15 +-
configure.ac | 14 +-
demos/Makefile.am | 5 +-
demos/Makefile.sources | 7 +
lib/Makefile.sources | 2 +
lib/drmtest.c | 2 +-
lib/gpgpu_fill.c | 7 +-
lib/igt_aux.c | 2 +-
lib/igt_aux.h | 3 +-
lib/igt_debugfs.c | 4 +-
lib/igt_draw.h | 3 +-
lib/igt_fb.h | 3 +-
lib/igt_kms.c | 3 +-
lib/intel_batchbuffer.c | 4 -
lib/intel_batchbuffer.h | 3 +-
lib/intel_chipset.c | 2 +-
lib/intel_drm_stubs.c | 258 +++++++++
lib/intel_drm_stubs.h | 999 +++++++++++++++++++++++++++++++++
lib/ioctl_wrappers.c | 1 -
lib/ioctl_wrappers.h | 4 +-
lib/media_fill_gen7.c | 3 +-
lib/media_fill_gen8.c | 4 +-
lib/media_fill_gen8lp.c | 6 +-
lib/media_fill_gen9.c | 4 +-
lib/media_spin.c | 2 -
lib/rendercopy_gen6.c | 5 +-
lib/rendercopy_gen7.c | 4 +-
lib/rendercopy_gen8.c | 4 +-
lib/rendercopy_gen9.c | 5 +-
lib/rendercopy_i830.c | 5 +-
lib/rendercopy_i915.c | 9 +-
tests/core_auth.c | 2 +-
tests/core_get_client_auth.c | 2 +-
tests/core_getclient.c | 3 +-
tests/drm_import_export.c | 7 +-
tests/drm_read.c | 5 +-
tests/drm_vma_limiter.c | 6 +-
tests/drm_vma_limiter_cached.c | 6 +-
tests/drm_vma_limiter_cpu.c | 6 +-
tests/drm_vma_limiter_gtt.c | 6 +-
tests/drv_getparams_basic.c | 6 +-
tests/gem_alive.c | 4 +-
tests/gem_bad_address.c | 6 +-
tests/gem_bad_batch.c | 6 +-
tests/gem_bad_blit.c | 6 +-
tests/gem_bad_length.c | 2 +-
tests/gem_bad_reloc.c | 2 +-
tests/gem_basic.c | 2 +-
tests/gem_caching.c | 5 +-
tests/gem_close_race.c | 2 +-
tests/gem_concurrent_all.c | 5 +-
tests/gem_cpu_reloc.c | 4 +-
tests/gem_create.c | 8 +-
tests/gem_ctx_bad_exec.c | 3 +-
tests/gem_ctx_basic.c | 8 +-
tests/gem_double_irq_loop.c | 7 +-
tests/gem_evict_everything.c | 2 +-
tests/gem_exec_bad_domains.c | 7 +-
tests/gem_exec_big.c | 2 +-
tests/gem_exec_blt.c | 2 +-
tests/gem_exec_faulting_reloc.c | 2 +-
tests/gem_exec_lut_handle.c | 2 +-
tests/gem_exec_nop.c | 2 +-
tests/gem_exec_params.c | 2 +-
tests/gem_fence_thrash.c | 2 +-
tests/gem_fence_upload.c | 7 +-
tests/gem_flink_basic.c | 2 +-
tests/gem_flink_race.c | 4 +-
tests/gem_gpgpu_fill.c | 7 +-
tests/gem_gtt_cpu_tlb.c | 2 +-
tests/gem_gtt_speed.c | 2 +-
tests/gem_hang.c | 6 +-
tests/gem_hangcheck_forcewake.c | 7 +-
tests/gem_largeobject.c | 2 +-
tests/gem_lut_handle.c | 2 +-
tests/gem_madvise.c | 3 +-
tests/gem_media_fill.c | 7 +-
tests/gem_mmap.c | 2 +-
tests/gem_mmap_gtt.c | 2 +-
tests/gem_mmap_offset_exhaustion.c | 2 +-
tests/gem_mmap_wc.c | 2 +-
tests/gem_non_secure_batch.c | 5 +-
tests/gem_partial_pwrite_pread.c | 1 -
tests/gem_persistent_relocs.c | 1 -
tests/gem_pin.c | 1 -
tests/gem_pipe_control_store_loop.c | 7 +-
tests/gem_ppgtt.c | 24 +-
tests/gem_pread.c | 2 +-
tests/gem_pread_after_blit.c | 1 -
tests/gem_pwrite.c | 2 +-
tests/gem_pwrite_pread.c | 7 +-
tests/gem_pwrite_snooped.c | 2 +-
tests/gem_read_read_speed.c | 5 +-
tests/gem_readwrite.c | 2 +-
tests/gem_reloc_overflow.c | 2 +-
tests/gem_reloc_vs_gpu.c | 1 -
tests/gem_render_copy.c | 5 +-
tests/gem_render_copy_redux.c | 7 +-
tests/gem_render_linear_blits.c | 5 +-
tests/gem_render_tiled_blits.c | 9 +-
tests/gem_request_retire.c | 8 +-
tests/gem_seqno_wrap.c | 4 +-
tests/gem_set_tiling_vs_blt.c | 7 +-
tests/gem_set_tiling_vs_gtt.c | 2 +-
tests/gem_set_tiling_vs_pwrite.c | 2 +-
tests/gem_stolen.c | 14 +-
tests/gem_storedw_batches_loop.c | 7 +-
tests/gem_storedw_loop.c | 2 +-
tests/gem_streaming_writes.c | 2 +-
tests/gem_stress.c | 6 +-
tests/gem_threaded_access_tiled.c | 4 +-
tests/gem_tiled_blits.c | 1 -
tests/gem_tiled_fence_blits.c | 5 +-
tests/gem_tiled_partial_pwrite_pread.c | 1 -
tests/gem_tiled_pread_basic.c | 2 +-
tests/gem_tiled_pread_pwrite.c | 1 -
tests/gem_tiled_swapping.c | 1 -
tests/gem_tiled_wb.c | 2 +-
tests/gem_tiled_wc.c | 2 +-
tests/gem_tiling_max_stride.c | 2 +-
tests/gem_unfence_active_buffers.c | 7 +-
tests/gem_unref_active_buffers.c | 7 +-
tests/gem_userptr_blits.c | 8 +-
tests/gem_wait.c | 5 +-
tests/gem_write_read_ring_switch.c | 1 -
tests/gen3_mixed_blits.c | 2 +-
tests/gen3_render_linear_blits.c | 2 +-
tests/gen3_render_mixed_blits.c | 2 +-
tests/gen3_render_tiledx_blits.c | 2 +-
tests/gen3_render_tiledy_blits.c | 2 +-
tests/gen7_forcewake_mt.c | 3 +-
tests/kms_addfb_basic.c | 3 +-
tests/kms_atomic.c | 5 +-
tests/kms_mmap_write_crc.c | 2 +-
tests/kms_psr_sink_crc.c | 4 +-
tests/kms_render.c | 4 +-
tests/kms_setmode.c | 4 +-
tests/kms_vblank.c | 5 +-
tests/pm_rpm.c | 1 -
tests/pm_rps.c | 4 +-
tests/pm_sseu.c | 6 +-
tests/prime_mmap.c | 5 +-
tests/prime_nv_api.c | 4 +-
tests/prime_nv_pcopy.c | 4 +-
tests/prime_nv_test.c | 4 +-
tests/prime_self_import.c | 3 +-
tests/prime_udl.c | 7 +-
tests/vc4_create_bo.c | 5 +-
tests/vc4_wait_bo.c | 5 +-
tests/vc4_wait_seqno.c | 3 +-
tools/Makefile.sources | 50 +-
151 files changed, 1588 insertions(+), 338 deletions(-)
create mode 100644 demos/Makefile.sources
create mode 100644 lib/intel_drm_stubs.c
create mode 100644 lib/intel_drm_stubs.h
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* [RFC i-g-t 1/9] configure.ac: Test for libdrm_intel and build for it if present.
2016-05-20 22:59 [RFC i-g-t 0/9] Remove compile time depencencies on libdrm_intel robert.foss
@ 2016-05-20 22:59 ` robert.foss
2016-05-21 7:55 ` Chris Wilson
2016-05-20 22:59 ` [RFC i-g-t 2/9] benchmarks/Makefile: Don't build benchmarks that depend on libdrm_intel robert.foss
` (7 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: robert.foss @ 2016-05-20 22:59 UTC (permalink / raw)
To: daniel.vetter, daniel.stone, marius.c.vlad, tomeu.vizoso, emil.velikov
Cc: intel-gfx
From: Robert Foss <robert.foss@collabora.com>
Test for libdrm_intel and build for it if present.
Also expose the HAVE_INTEL #define to allow code to be conditionally
compiled.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
---
configure.ac | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/configure.ac b/configure.ac
index 0589782..b6fc168 100644
--- a/configure.ac
+++ b/configure.ac
@@ -100,7 +100,7 @@ if test "x$GCC" = "xyes"; then
fi
AC_SUBST(ASSEMBLER_WARN_CFLAGS)
-PKG_CHECK_MODULES(DRM, [libdrm_intel >= 2.4.64 libdrm])
+PKG_CHECK_MODULES(DRM, [libdrm])
PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10])
case "$target_cpu" in
@@ -150,6 +150,18 @@ PKG_CHECK_MODULES(GLIB, glib-2.0)
# -----------------------------------------------------------------------------
# Configuration options
# -----------------------------------------------------------------------------
+AC_ARG_ENABLE(intel, AS_HELP_STRING([--disable-intel],
+ [Enable building of intel specific parts (default: auto)]),
+ [INTEL=$enableval], [INTEL=auto])
+if test "x$INTEL" = xauto; then
+ PKG_CHECK_EXISTS([libdrm_intel >= 2.4.64], [INTEL=yes], [INTEL=no])
+fi
+if test "x$INTEL" = xyes; then
+ PKG_CHECK_MODULES(DRM_INTEL, [libdrm_intel >= 2.4.64])
+ AC_DEFINE(HAVE_INTEL, 1, [Have intel support])
+fi
+AM_CONDITIONAL(HAVE_INTEL, [test "x$INTEL" = xyes])
+
# for dma-buf tests
AC_ARG_ENABLE(nouveau, AS_HELP_STRING([--disable-nouveau],
[Enable use of nouveau API for prime tests (default: auto)]),
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [RFC i-g-t 2/9] benchmarks/Makefile: Don't build benchmarks that depend on libdrm_intel.
2016-05-20 22:59 [RFC i-g-t 0/9] Remove compile time depencencies on libdrm_intel robert.foss
2016-05-20 22:59 ` [RFC i-g-t 1/9] configure.ac: Test for libdrm_intel and build for it if present robert.foss
@ 2016-05-20 22:59 ` robert.foss
2016-05-23 14:04 ` ?==?utf-8?q? " Emil Velikov
2016-05-20 22:59 ` [RFC i-g-t 3/9] tools/Makefile: Don't build tools " robert.foss
` (6 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: robert.foss @ 2016-05-20 22:59 UTC (permalink / raw)
To: daniel.vetter, daniel.stone, marius.c.vlad, tomeu.vizoso, emil.velikov
Cc: intel-gfx
From: Robert Foss <robert.foss@collabora.com>
Use the HAS_INTEL automake flag to avoid building benchmarks that won't
compile unless libdrm_intel is available in the build system.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
---
benchmarks/Makefile.sources | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/benchmarks/Makefile.sources b/benchmarks/Makefile.sources
index 81607a5..26ee3ea 100644
--- a/benchmarks/Makefile.sources
+++ b/benchmarks/Makefile.sources
@@ -1,10 +1,6 @@
benchmarksdir=$(libexecdir)/intel-gpu-tools/benchmarks
benchmarks_PROGRAMS = \
- intel_upload_blit_large \
- intel_upload_blit_large_gtt \
- intel_upload_blit_large_map \
- intel_upload_blit_small \
gem_blt \
gem_create \
gem_exec_ctx \
@@ -16,6 +12,15 @@ benchmarks_PROGRAMS = \
gem_prw \
gem_set_domain \
gem_syslatency \
- gem_userptr_benchmark \
kms_vblank \
$(NULL)
+
+if HAVE_INTEL
+ benchmarks_PROGRAMS += \
+ intel_upload_blit_large \
+ intel_upload_blit_large_gtt \
+ intel_upload_blit_large_map \
+ intel_upload_blit_small \
+ gem_userptr_benchmark \
+ $(NULL)
+endif
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [RFC i-g-t 3/9] tools/Makefile: Don't build tools that depend on libdrm_intel.
2016-05-20 22:59 [RFC i-g-t 0/9] Remove compile time depencencies on libdrm_intel robert.foss
2016-05-20 22:59 ` [RFC i-g-t 1/9] configure.ac: Test for libdrm_intel and build for it if present robert.foss
2016-05-20 22:59 ` [RFC i-g-t 2/9] benchmarks/Makefile: Don't build benchmarks that depend on libdrm_intel robert.foss
@ 2016-05-20 22:59 ` robert.foss
2016-05-23 14:09 ` ?==?utf-8?q? " Emil Velikov
2016-05-20 22:59 ` [RFC i-g-t 4/9] demos/Makefile: " robert.foss
` (5 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: robert.foss @ 2016-05-20 22:59 UTC (permalink / raw)
To: daniel.vetter, daniel.stone, marius.c.vlad, tomeu.vizoso, emil.velikov
Cc: intel-gfx
From: Robert Foss <robert.foss@collabora.com>
Use the HAS_INTEL automake flag to avoid building tools that won't
compile unless libdrm_intel is available in the build system.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
---
tools/Makefile.sources | 50 +++++++++++++++++++++++++++++---------------------
1 file changed, 29 insertions(+), 21 deletions(-)
diff --git a/tools/Makefile.sources b/tools/Makefile.sources
index 5d5958d..c2dab8e 100644
--- a/tools/Makefile.sources
+++ b/tools/Makefile.sources
@@ -1,42 +1,54 @@
-noinst_PROGRAMS = \
- hsw_compute_wrpll \
- skl_compute_wrpll \
- skl_ddb_allocation \
+noinst_PROGRAMS = \
+ hsw_compute_wrpll \
+ skl_compute_wrpll \
+ skl_ddb_allocation \
$(NULL)
-bin_PROGRAMS = \
+bin_PROGRAMS = \
igt_stats \
- intel_audio_dump \
+ intel_audio_dump \
intel_reg \
intel_backlight \
intel_bios_dumper \
intel_bios_reader \
intel_display_crc \
intel_display_poller \
- intel_dump_decode \
- intel_error_decode \
intel_forcewaked \
intel_gpu_frequency \
- intel_framebuffer_dump \
intel_firmware_decode \
- intel_gpu_time \
- intel_gpu_top \
- intel_gtt \
+ intel_gpu_time \
+ intel_gpu_top \
+ intel_gtt \
intel_infoframes \
intel_l3_parity \
intel_lid \
intel_opregion_decode \
intel_panel_fitter \
- intel_perf_counters \
- intel_reg_checker \
+ intel_reg_checker \
intel_residency \
- intel_stepping \
+ intel_stepping \
intel_watermark
dist_bin_SCRIPTS = intel_gpu_abrt
-intel_dump_decode_SOURCES = \
- intel_dump_decode.c
+if HAVE_INTEL
+ bin_PROGRAMS += \
+ intel_dump_decode \
+ intel_error_decode \
+ intel_framebuffer_dump \
+ intel_perf_counters \
+ $(NULL)
+
+ intel_dump_decode_SOURCES = \
+ intel_dump_decode.c \
+ $(NULL)
+
+ intel_error_decode_SOURCES = \
+ intel_error_decode.c \
+ $(NULL)
+
+ intel_error_decode_LDFLAGS = -lz
+endif
intel_reg_SOURCES = \
intel_reg.c \
@@ -44,10 +56,6 @@ intel_reg_SOURCES = \
intel_reg_spec.c \
intel_reg_spec.h
-intel_error_decode_SOURCES = \
- intel_error_decode.c
-intel_error_decode_LDFLAGS = -lz
-
intel_bios_reader_SOURCES = \
intel_bios_reader.c \
intel_bios.h
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [RFC i-g-t 4/9] demos/Makefile: Don't build tools that depend on libdrm_intel.
2016-05-20 22:59 [RFC i-g-t 0/9] Remove compile time depencencies on libdrm_intel robert.foss
` (2 preceding siblings ...)
2016-05-20 22:59 ` [RFC i-g-t 3/9] tools/Makefile: Don't build tools " robert.foss
@ 2016-05-20 22:59 ` robert.foss
2016-05-20 22:59 ` [RFC i-g-t 5/9] tests/gem_ppgtt: Switched to new aliases of intel specific functions robert.foss
` (4 subsequent siblings)
8 siblings, 0 replies; 29+ messages in thread
From: robert.foss @ 2016-05-20 22:59 UTC (permalink / raw)
To: daniel.vetter, daniel.stone, marius.c.vlad, tomeu.vizoso, emil.velikov
Cc: intel-gfx
From: Robert Foss <robert.foss@collabora.com>
Use the HAS_INTEL automake flag to avoid building tools that won't
compile unless libdrm_intel is available in the build system.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
---
demos/Makefile.am | 5 ++---
demos/Makefile.sources | 7 +++++++
2 files changed, 9 insertions(+), 3 deletions(-)
create mode 100644 demos/Makefile.sources
diff --git a/demos/Makefile.am b/demos/Makefile.am
index e6fbb3b..02409fe 100644
--- a/demos/Makefile.am
+++ b/demos/Makefile.am
@@ -1,6 +1,5 @@
-bin_PROGRAMS = \
- intel_sprite_on \
- $(NULL)
+
+include Makefile.sources
AM_CPPFLAGS = -I$(top_srcdir) -I$(top_srcdir)/lib
AM_CFLAGS = $(DRM_CFLAGS) $(PCIACCESS_CFLAGS) $(CWARNFLAGS) $(CAIRO_CFLAGS) $(LIBUNWIND_CFLAGS)
diff --git a/demos/Makefile.sources b/demos/Makefile.sources
new file mode 100644
index 0000000..98da30d
--- /dev/null
+++ b/demos/Makefile.sources
@@ -0,0 +1,7 @@
+bin_PROGRAMS = \
+ $(NULL)
+
+if HAVE_INTEL
+ bin_PROGRAMS += \
+ intel_sprite_on \
+endif
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [RFC i-g-t 5/9] tests/gem_ppgtt: Switched to new aliases of intel specific functions.
2016-05-20 22:59 [RFC i-g-t 0/9] Remove compile time depencencies on libdrm_intel robert.foss
` (3 preceding siblings ...)
2016-05-20 22:59 ` [RFC i-g-t 4/9] demos/Makefile: " robert.foss
@ 2016-05-20 22:59 ` robert.foss
2016-05-23 14:14 ` ?==?utf-8?q? " Emil Velikov
2016-05-23 14:15 ` Emil Velikov
2016-05-20 22:59 ` [RFC i-g-t 6/9] tests/gem_render_tiled_blits: " robert.foss
` (3 subsequent siblings)
8 siblings, 2 replies; 29+ messages in thread
From: robert.foss @ 2016-05-20 22:59 UTC (permalink / raw)
To: daniel.vetter, daniel.stone, marius.c.vlad, tomeu.vizoso, emil.velikov
Cc: intel-gfx
From: Robert Foss <robert.foss@collabora.com>
Switched from drm_XXX aliases drm_intel_XXX aliases for symbols where that
switch is possible.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
---
tests/gem_ppgtt.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/tests/gem_ppgtt.c b/tests/gem_ppgtt.c
index 1a620ad..eb15ca5 100644
--- a/tests/gem_ppgtt.c
+++ b/tests/gem_ppgtt.c
@@ -74,11 +74,11 @@ static void scratch_buf_init(struct igt_buf *buf,
static void scratch_buf_fini(struct igt_buf *buf)
{
- dri_bo_unreference(buf->bo);
+ drm_intel_bo_unreference(buf->bo);
memset(buf, 0, sizeof(*buf));
}
-static void fork_rcs_copy(int target, dri_bo **dst, int count, unsigned flags)
+static void fork_rcs_copy(int target, drm_intel_bo **dst, int count, unsigned flags)
#define CREATE_CONTEXT 0x1
{
igt_render_copyfunc_t render_copy;
@@ -143,7 +143,7 @@ static void fork_rcs_copy(int target, dri_bo **dst, int count, unsigned flags)
}
}
-static void fork_bcs_copy(int target, dri_bo **dst, int count)
+static void fork_bcs_copy(int target, drm_intel_bo **dst, int count)
{
int devid;
@@ -167,7 +167,7 @@ static void fork_bcs_copy(int target, dri_bo **dst, int count)
igt_assert(batch);
for (int i = 0; i <= target; i++) {
- dri_bo *src[2];
+ drm_intel_bo *src[2];
src[0] = create_bo(dst[child]->bufmgr,
~0);
@@ -177,13 +177,13 @@ static void fork_bcs_copy(int target, dri_bo **dst, int count)
intel_copy_bo(batch, src[0], src[1], SIZE);
intel_copy_bo(batch, dst[child], src[0], SIZE);
- dri_bo_unreference(src[1]);
- dri_bo_unreference(src[0]);
+ drm_intel_bo_unreference(src[1]);
+ drm_intel_bo_unreference(src[0]);
}
}
}
-static void surfaces_check(dri_bo **bo, int count, uint32_t expected)
+static void surfaces_check(drm_intel_bo **bo, int count, uint32_t expected)
{
for (int child = 0; child < count; child++) {
uint32_t *ptr;
@@ -322,7 +322,7 @@ int main(int argc, char **argv)
igt_subtest_init(argc, argv);
igt_subtest("blt-vs-render-ctx0") {
- dri_bo *bcs[1], *rcs[N_CHILD];
+ drm_intel_bo *bcs[1], *rcs[N_CHILD];
fork_bcs_copy(0x4000, bcs, 1);
fork_rcs_copy(0x8000 / N_CHILD, rcs, N_CHILD, 0);
@@ -334,7 +334,7 @@ int main(int argc, char **argv)
}
igt_subtest("blt-vs-render-ctxN") {
- dri_bo *bcs[1], *rcs[N_CHILD];
+ drm_intel_bo *bcs[1], *rcs[N_CHILD];
fork_rcs_copy(0x8000 / N_CHILD, rcs, N_CHILD, CREATE_CONTEXT);
fork_bcs_copy(0x4000, bcs, 1);
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [RFC i-g-t 6/9] tests/gem_render_tiled_blits: Switched to new aliases of intel specific functions.
2016-05-20 22:59 [RFC i-g-t 0/9] Remove compile time depencencies on libdrm_intel robert.foss
` (4 preceding siblings ...)
2016-05-20 22:59 ` [RFC i-g-t 5/9] tests/gem_ppgtt: Switched to new aliases of intel specific functions robert.foss
@ 2016-05-20 22:59 ` robert.foss
2016-05-23 14:39 ` ?==?utf-8?q? " Emil Velikov
2016-05-20 22:59 ` [RFC i-g-t 7/9] lib/intel_drm_stubs: Add stubs for functionality from libdrm_intel robert.foss
` (2 subsequent siblings)
8 siblings, 1 reply; 29+ messages in thread
From: robert.foss @ 2016-05-20 22:59 UTC (permalink / raw)
To: daniel.vetter, daniel.stone, marius.c.vlad, tomeu.vizoso, emil.velikov
Cc: intel-gfx
From: Robert Foss <robert.foss@collabora.com>
Switched from drm_XXX aliases drm_intel_XXX aliases for symbols where that
switch is possible.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
---
tests/gem_render_tiled_blits.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/gem_render_tiled_blits.c b/tests/gem_render_tiled_blits.c
index fb2f39d..9f0e588 100644
--- a/tests/gem_render_tiled_blits.c
+++ b/tests/gem_render_tiled_blits.c
@@ -72,7 +72,7 @@ check_bo(struct intel_batchbuffer *batch, struct igt_buf *buf, uint32_t val)
render_copy(batch, NULL, buf, 0, 0, WIDTH, HEIGHT, &tmp, 0, 0);
if (snoop) {
- do_or_die(dri_bo_map(linear, 0));
+ do_or_die(drm_intel_bo_map(linear, 0));
ptr = linear->virtual;
} else {
do_or_die(drm_intel_bo_get_subdata(linear, 0, sizeof(data), data));
@@ -86,7 +86,7 @@ check_bo(struct intel_batchbuffer *batch, struct igt_buf *buf, uint32_t val)
val++;
}
if (ptr != data)
- dri_bo_unmap(linear);
+ drm_intel_bo_unmap(linear);
}
static void run_test (int fd, int count)
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [RFC i-g-t 7/9] lib/intel_drm_stubs: Add stubs for functionality from libdrm_intel.
2016-05-20 22:59 [RFC i-g-t 0/9] Remove compile time depencencies on libdrm_intel robert.foss
` (5 preceding siblings ...)
2016-05-20 22:59 ` [RFC i-g-t 6/9] tests/gem_render_tiled_blits: " robert.foss
@ 2016-05-20 22:59 ` robert.foss
2016-05-23 14:53 ` ?==?utf-8?q? " Emil Velikov
2016-05-24 8:05 ` Daniel Vetter
2016-05-20 22:59 ` [RFC i-g-t 8/9] lib: Replace intel specific header includes with intel_drm_stubs.h robert.foss
2016-05-20 22:59 ` [RFC i-g-t 9/9] tests: " robert.foss
8 siblings, 2 replies; 29+ messages in thread
From: robert.foss @ 2016-05-20 22:59 UTC (permalink / raw)
To: daniel.vetter, daniel.stone, marius.c.vlad, tomeu.vizoso, emil.velikov
Cc: intel-gfx
From: Robert Foss <robert.foss@collabora.com>
This patch provides stubs for functionality otherwise provided by libdrm_intel.
The stubbed functions all fail with a call to igt_require(false).
Defines and enums have been copied from libdrm_intel.
Due to the stubbed tests failing with an igt_require() call, these stubs are
not well suited for non-tests, since tools/benchmarks/etc 'skipping'
execution is unhelpful.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
---
lib/Makefile.sources | 2 +
lib/intel_drm_stubs.c | 258 +++++++++++++
lib/intel_drm_stubs.h | 999 ++++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1259 insertions(+)
create mode 100644 lib/intel_drm_stubs.c
create mode 100644 lib/intel_drm_stubs.h
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 1316fd2..c0f9f6d 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -21,6 +21,8 @@ libintel_tools_la_SOURCES = \
intel_batchbuffer.c \
intel_batchbuffer.h \
intel_chipset.h \
+ intel_drm_stubs.c \
+ intel_drm_stubs.h \
intel_os.c \
intel_io.h \
intel_mmio.c \
diff --git a/lib/intel_drm_stubs.c b/lib/intel_drm_stubs.c
new file mode 100644
index 0000000..d46a9b3
--- /dev/null
+++ b/lib/intel_drm_stubs.c
@@ -0,0 +1,258 @@
+#ifndef HAVE_INTEL
+
+#include "intel_drm_stubs.h"
+
+drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size)
+{
+ igt_require(false);
+ return (drm_intel_bufmgr *) NULL;
+}
+
+void drm_intel_bo_unreference(drm_intel_bo *bo)
+{
+ igt_require(false);
+}
+
+drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
+ unsigned long size, unsigned int alignment)
+{
+ igt_require(false);
+ return (drm_intel_bo *) NULL;
+}
+
+int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
+ unsigned long size, const void *data)
+{
+ igt_require(false);
+ return 0;
+}
+
+int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
+ int used, unsigned int flags)
+{
+ igt_require(false);
+ return 0;
+}
+
+int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
+ drm_intel_bo *target_bo, uint32_t target_offset,
+ uint32_t read_domains, uint32_t write_domain)
+{
+ igt_require(false);
+ return 0;
+}
+
+int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
+ drm_intel_bo *target_bo,
+ uint32_t target_offset,
+ uint32_t read_domains, uint32_t write_domain)
+{
+ igt_require(false);
+ return 0;
+}
+
+int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
+ uint32_t * swizzle_mode)
+{
+ igt_require(false);
+ return 0;
+}
+
+int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
+ struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
+ unsigned int flags)
+{
+ igt_require(false);
+ return 0;
+}
+
+void drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
+ drm_intel_aub_annotation *annotations,
+ unsigned count)
+{
+ igt_require(false);
+}
+
+void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
+{
+ igt_require(false);
+}
+
+int drm_intel_bo_exec(drm_intel_bo *bo, int used,
+ struct drm_clip_rect *cliprects, int num_cliprects, int DR4)
+{
+ igt_require(false);
+ return 0;
+}
+
+void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
+{
+ igt_require(false);
+}
+
+void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
+{
+ igt_require(false);
+}
+
+int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
+ unsigned long size, void *data)
+{
+ igt_require(false);
+ return 0;
+}
+
+int drm_intel_bo_map(drm_intel_bo *bo, int write_enable)
+{
+ igt_require(false);
+ return 0;
+}
+
+int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
+{
+ igt_require(false);
+ return 0;
+}
+
+void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
+{
+ igt_require(false);
+}
+
+int drm_intel_bo_unmap(drm_intel_bo *bo)
+{
+ igt_require(false);
+ return 0;
+}
+
+int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
+{
+ igt_require(false);
+ return 0;
+}
+
+drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
+ const char *name,
+ unsigned int handle)
+{
+ igt_require(false);
+ return (drm_intel_bo *) NULL;
+}
+
+int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
+{
+ igt_require(false);
+ return 0;
+}
+
+drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
+ int prime_fd, int size)
+{
+ igt_require(false);
+ return (drm_intel_bo *) NULL;
+}
+
+void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
+ int limit)
+{
+ igt_require(false);
+}
+
+int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
+{
+ igt_require(false);
+ return 0;
+}
+
+drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
+{
+ igt_require(false);
+ return (drm_intel_bo *) NULL;
+}
+
+void drm_intel_gem_context_destroy(drm_intel_context *ctx)
+{
+ igt_require(false);
+}
+
+drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
+ const char *name,
+ int x, int y, int cpp,
+ uint32_t *tiling_mode,
+ unsigned long *pitch,
+ unsigned long flags)
+{
+ igt_require(false);
+ return (drm_intel_bo *) NULL;
+}
+
+void drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
+ const char *filename)
+{
+ igt_require(false);
+}
+
+void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
+{
+ igt_require(false);
+}
+
+void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
+ int x1, int y1, int width, int height,
+ enum aub_dump_bmp_format format,
+ int pitch, int offset)
+{
+ igt_require(false);
+}
+
+void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
+{
+ igt_require(false);
+}
+
+int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
+ uint32_t stride)
+{
+ igt_require(false);
+ return 0;
+}
+
+int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
+{
+ igt_require(false);
+ return 0;
+}
+
+void drm_intel_bo_reference(drm_intel_bo *bo)
+{
+ igt_require(false);
+}
+
+int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
+{
+ igt_require(false);
+ return 0;
+}
+
+drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
+ const char *name,
+ unsigned long size,
+ unsigned int alignment)
+{
+ igt_require(false);
+ return (drm_intel_bo *) NULL;
+}
+
+int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
+{
+ igt_require(false);
+ return 0;
+}
+
+int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
+{
+ igt_require(false);
+ return 0;
+}
+
+#endif//HAVE_INTEL
diff --git a/lib/intel_drm_stubs.h b/lib/intel_drm_stubs.h
new file mode 100644
index 0000000..fdfaaeb
--- /dev/null
+++ b/lib/intel_drm_stubs.h
@@ -0,0 +1,999 @@
+#ifndef INTEL_DRM_STUBS_H
+#define INTEL_DRM_STUBS_H
+
+#include <xf86drm.h>
+
+#include "igt_core.h"
+
+#ifdef HAVE_INTEL
+#include <i915_drm.h>
+#include <intel_bufmgr.h>
+#include <drm.h>
+
+
+#else
+#define i915_execbuffer2_set_context_id(eb2, context) igt_require(false);
+#define i915_execbuffer2_get_context_id(eb2) igt_require(false);
+
+#define I915_EXEC_GEN7_SOL_RESET (1<<8)
+#define I915_EXEC_SECURE (1<<9)
+#define I915_EXEC_IS_PINNED (1<<10)
+#define I915_EXEC_NO_RELOC (1<<11)
+#define I915_EXEC_HANDLE_LUT (1<<12)
+#define I915_EXEC_BSD_MASK (3<<13)
+#define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */
+#define I915_EXEC_BSD_RING1 (1<<13)
+#define I915_EXEC_BSD_RING2 (2<<13)
+
+#define I915_MADV_WILLNEED 0
+#define I915_MADV_DONTNEED 1
+
+#define I915_TILING_NONE 0
+#define I915_TILING_X 1
+#define I915_TILING_Y 2
+
+#define I915_CACHING_NONE 0
+#define I915_CACHING_CACHED 1
+#define I915_CACHING_DISPLAY 2
+
+#define I915_BIT_6_SWIZZLE_NONE 0
+#define I915_BIT_6_SWIZZLE_9 1
+#define I915_BIT_6_SWIZZLE_9_10 2
+#define I915_BIT_6_SWIZZLE_9_11 3
+#define I915_BIT_6_SWIZZLE_9_10_11 4
+#define I915_BIT_6_SWIZZLE_UNKNOWN 5
+#define I915_BIT_6_SWIZZLE_9_17 6
+#define I915_BIT_6_SWIZZLE_9_10_17 7
+
+#define I915_PARAM_CHIPSET_ID 4
+
+#define I915_PARAM_IRQ_ACTIVE 1
+#define I915_PARAM_ALLOW_BATCHBUFFER 2
+#define I915_PARAM_LAST_DISPATCH 3
+#define I915_PARAM_CHIPSET_ID 4
+#define I915_PARAM_HAS_GEM 5
+#define I915_PARAM_NUM_FENCES_AVAIL 6
+#define I915_PARAM_HAS_OVERLAY 7
+#define I915_PARAM_HAS_PAGEFLIPPING 8
+#define I915_PARAM_HAS_EXECBUF2 9
+#define I915_PARAM_HAS_BSD 10
+#define I915_PARAM_HAS_BLT 11
+#define I915_PARAM_HAS_RELAXED_FENCING 12
+#define I915_PARAM_HAS_COHERENT_RINGS 13
+#define I915_PARAM_HAS_EXEC_CONSTANTS 14
+#define I915_PARAM_HAS_RELAXED_DELTA 15
+#define I915_PARAM_HAS_GEN7_SOL_RESET 16
+#define I915_PARAM_HAS_LLC 17
+#define I915_PARAM_HAS_ALIASING_PPGTT 18
+#define I915_PARAM_HAS_WAIT_TIMEOUT 19
+#define I915_PARAM_HAS_SEMAPHORES 20
+#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
+#define I915_PARAM_HAS_VEBOX 22
+#define I915_PARAM_HAS_SECURE_BATCHES 23
+#define I915_PARAM_HAS_PINNED_BATCHES 24
+#define I915_PARAM_HAS_EXEC_NO_RELOC 25
+#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
+#define I915_PARAM_HAS_WT 27
+#define I915_PARAM_CMD_PARSER_VERSION 28
+#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
+#define I915_PARAM_MMAP_VERSION 30
+#define I915_PARAM_HAS_BSD2 31
+#define I915_PARAM_REVISION 32
+#define I915_PARAM_SUBSLICE_TOTAL 33
+#define I915_PARAM_EU_TOTAL 34
+#define I915_PARAM_HAS_GPU_RESET 35
+#define I915_PARAM_HAS_RESOURCE_STREAMER 36
+#define I915_PARAM_HAS_EXEC_SOFTPIN 37
+
+#define I915_GEM_DOMAIN_CPU 0x00000001
+#define I915_GEM_DOMAIN_RENDER 0x00000002
+#define I915_GEM_DOMAIN_SAMPLER 0x00000004
+#define I915_GEM_DOMAIN_COMMAND 0x00000008
+#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
+#define I915_GEM_DOMAIN_VERTEX 0x00000020
+#define I915_GEM_DOMAIN_GTT 0x00000040
+
+#define DRM_I915_INIT 0x00
+#define DRM_I915_FLUSH 0x01
+#define DRM_I915_FLIP 0x02
+#define DRM_I915_BATCHBUFFER 0x03
+#define DRM_I915_IRQ_EMIT 0x04
+#define DRM_I915_IRQ_WAIT 0x05
+#define DRM_I915_GETPARAM 0x06
+#define DRM_I915_SETPARAM 0x07
+#define DRM_I915_ALLOC 0x08
+#define DRM_I915_FREE 0x09
+#define DRM_I915_INIT_HEAP 0x0a
+#define DRM_I915_CMDBUFFER 0x0b
+#define DRM_I915_DESTROY_HEAP 0x0c
+#define DRM_I915_SET_VBLANK_PIPE 0x0d
+#define DRM_I915_GET_VBLANK_PIPE 0x0e
+#define DRM_I915_VBLANK_SWAP 0x0f
+#define DRM_I915_HWS_ADDR 0x11
+#define DRM_I915_GEM_INIT 0x13
+#define DRM_I915_GEM_EXECBUFFER 0x14
+#define DRM_I915_GEM_PIN 0x15
+#define DRM_I915_GEM_UNPIN 0x16
+#define DRM_I915_GEM_BUSY 0x17
+#define DRM_I915_GEM_THROTTLE 0x18
+#define DRM_I915_GEM_ENTERVT 0x19
+#define DRM_I915_GEM_LEAVEVT 0x1a
+#define DRM_I915_GEM_CREATE 0x1b
+#define DRM_I915_GEM_PREAD 0x1c
+#define DRM_I915_GEM_PWRITE 0x1d
+#define DRM_I915_GEM_MMAP 0x1e
+#define DRM_I915_GEM_SET_DOMAIN 0x1f
+#define DRM_I915_GEM_SW_FINISH 0x20
+#define DRM_I915_GEM_SET_TILING 0x21
+#define DRM_I915_GEM_GET_TILING 0x22
+#define DRM_I915_GEM_GET_APERTURE 0x23
+#define DRM_I915_GEM_MMAP_GTT 0x24
+#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
+#define DRM_I915_GEM_MADVISE 0x26
+#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
+#define DRM_I915_OVERLAY_ATTRS 0x28
+#define DRM_I915_GEM_EXECBUFFER2 0x29
+#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
+#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
+#define DRM_I915_GEM_WAIT 0x2c
+#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
+#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
+#define DRM_I915_GEM_SET_CACHING 0x2f
+#define DRM_I915_GEM_GET_CACHING 0x30
+#define DRM_I915_REG_READ 0x31
+#define DRM_I915_GET_RESET_STATS 0x32
+#define DRM_I915_GEM_USERPTR 0x33
+#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
+#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
+
+#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
+#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
+#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
+#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
+#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
+#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
+#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
+#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
+#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
+#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
+#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
+#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
+#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
+#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
+#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
+#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
+#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
+#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
+#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
+#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
+#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
+#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
+#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
+#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
+#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
+#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
+#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
+#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
+#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
+#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
+#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
+#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
+#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
+#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
+#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
+#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
+#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
+#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
+#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
+#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
+#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
+#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
+#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
+#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
+#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
+#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
+#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
+#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
+#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
+#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
+#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
+
+enum aub_dump_bmp_format {
+ AUB_DUMP_BMP_FORMAT_8BIT = 1,
+ AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4,
+ AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6,
+ AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7,
+};
+
+typedef struct _drm_intel_bo drm_intel_bo;
+typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
+typedef struct _drm_intel_context drm_intel_context;
+
+struct _drm_intel_context {
+ unsigned int ctx_id;
+ struct _drm_intel_bufmgr *bufmgr;
+};
+
+struct _drm_intel_bufmgr {
+ /**
+ * Allocate a buffer object.
+ *
+ * Buffer objects are not necessarily initially mapped into CPU virtual
+ * address space or graphics device aperture. They must be mapped
+ * using bo_map() or drm_intel_gem_bo_map_gtt() to be used by the CPU.
+ */
+ drm_intel_bo *(*bo_alloc) (drm_intel_bufmgr *bufmgr, const char *name,
+ unsigned long size, unsigned int alignment);
+
+ /**
+ * Allocate a buffer object, hinting that it will be used as a
+ * render target.
+ *
+ * This is otherwise the same as bo_alloc.
+ */
+ drm_intel_bo *(*bo_alloc_for_render) (drm_intel_bufmgr *bufmgr,
+ const char *name,
+ unsigned long size,
+ unsigned int alignment);
+
+ /**
+ * Allocate a buffer object from an existing user accessible
+ * address malloc'd with the provided size.
+ * Alignment is used when mapping to the gtt.
+ * Flags may be I915_VMAP_READ_ONLY or I915_USERPTR_UNSYNCHRONIZED
+ */
+ drm_intel_bo *(*bo_alloc_userptr)(drm_intel_bufmgr *bufmgr,
+ const char *name, void *addr,
+ uint32_t tiling_mode, uint32_t stride,
+ unsigned long size,
+ unsigned long flags);
+
+ /**
+ * Allocate a tiled buffer object.
+ *
+ * Alignment for tiled objects is set automatically; the 'flags'
+ * argument provides a hint about how the object will be used initially.
+ *
+ * Valid tiling formats are:
+ * I915_TILING_NONE
+ * I915_TILING_X
+ * I915_TILING_Y
+ *
+ * Note the tiling format may be rejected; callers should check the
+ * 'tiling_mode' field on return, as well as the pitch value, which
+ * may have been rounded up to accommodate for tiling restrictions.
+ */
+ drm_intel_bo *(*bo_alloc_tiled) (drm_intel_bufmgr *bufmgr,
+ const char *name,
+ int x, int y, int cpp,
+ uint32_t *tiling_mode,
+ unsigned long *pitch,
+ unsigned long flags);
+
+ /** Takes a reference on a buffer object */
+ void (*bo_reference) (drm_intel_bo *bo);
+
+ /**
+ * Releases a reference on a buffer object, freeing the data if
+ * no references remain.
+ */
+ void (*bo_unreference) (drm_intel_bo *bo);
+
+ /**
+ * Maps the buffer into userspace.
+ *
+ * This function will block waiting for any existing execution on the
+ * buffer to complete, first. The resulting mapping is available at
+ * buf->virtual.
+ */
+ int (*bo_map) (drm_intel_bo *bo, int write_enable);
+
+ /**
+ * Reduces the refcount on the userspace mapping of the buffer
+ * object.
+ */
+ int (*bo_unmap) (drm_intel_bo *bo);
+
+ /**
+ * Write data into an object.
+ *
+ * This is an optional function, if missing,
+ * drm_intel_bo will map/memcpy/unmap.
+ */
+ int (*bo_subdata) (drm_intel_bo *bo, unsigned long offset,
+ unsigned long size, const void *data);
+
+ /**
+ * Read data from an object
+ *
+ * This is an optional function, if missing,
+ * drm_intel_bo will map/memcpy/unmap.
+ */
+ int (*bo_get_subdata) (drm_intel_bo *bo, unsigned long offset,
+ unsigned long size, void *data);
+
+ /**
+ * Waits for rendering to an object by the GPU to have completed.
+ *
+ * This is not required for any access to the BO by bo_map,
+ * bo_subdata, etc. It is merely a way for the driver to implement
+ * glFinish.
+ */
+ void (*bo_wait_rendering) (drm_intel_bo *bo);
+
+ /**
+ * Tears down the buffer manager instance.
+ */
+ void (*destroy) (drm_intel_bufmgr *bufmgr);
+
+ /**
+ * Indicate if the buffer can be placed anywhere in the full ppgtt
+ * address range (2^48).
+ *
+ * Any resource used with flat/heapless (0x00000000-0xfffff000)
+ * General State Heap (GSH) or Intructions State Heap (ISH) must
+ * be in a 32-bit range. 48-bit range will only be used when explicitly
+ * requested.
+ *
+ * \param bo Buffer to set the use_48b_address_range flag.
+ * \param enable The flag value.
+ */
+ void (*bo_use_48b_address_range) (drm_intel_bo *bo, uint32_t enable);
+
+ /**
+ * Add relocation entry in reloc_buf, which will be updated with the
+ * target buffer's real offset on on command submission.
+ *
+ * Relocations remain in place for the lifetime of the buffer object.
+ *
+ * \param bo Buffer to write the relocation into.
+ * \param offset Byte offset within reloc_bo of the pointer to
+ * target_bo.
+ * \param target_bo Buffer whose offset should be written into the
+ * relocation entry.
+ * \param target_offset Constant value to be added to target_bo's
+ * offset in relocation entry.
+ * \param read_domains GEM read domains which the buffer will be
+ * read into by the command that this relocation
+ * is part of.
+ * \param write_domains GEM read domains which the buffer will be
+ * dirtied in by the command that this
+ * relocation is part of.
+ */
+ int (*bo_emit_reloc) (drm_intel_bo *bo, uint32_t offset,
+ drm_intel_bo *target_bo, uint32_t target_offset,
+ uint32_t read_domains, uint32_t write_domain);
+ int (*bo_emit_reloc_fence)(drm_intel_bo *bo, uint32_t offset,
+ drm_intel_bo *target_bo,
+ uint32_t target_offset,
+ uint32_t read_domains,
+ uint32_t write_domain);
+
+ /** Executes the command buffer pointed to by bo. */
+ int (*bo_exec) (drm_intel_bo *bo, int used,
+ drm_clip_rect_t *cliprects, int num_cliprects,
+ int DR4);
+
+ /** Executes the command buffer pointed to by bo on the selected
+ * ring buffer
+ */
+ int (*bo_mrb_exec) (drm_intel_bo *bo, int used,
+ drm_clip_rect_t *cliprects, int num_cliprects,
+ int DR4, unsigned flags);
+
+ /**
+ * Pin a buffer to the aperture and fix the offset until unpinned
+ *
+ * \param buf Buffer to pin
+ * \param alignment Required alignment for aperture, in bytes
+ */
+ int (*bo_pin) (drm_intel_bo *bo, uint32_t alignment);
+
+ /**
+ * Unpin a buffer from the aperture, allowing it to be removed
+ *
+ * \param buf Buffer to unpin
+ */
+ int (*bo_unpin) (drm_intel_bo *bo);
+
+ /**
+ * Ask that the buffer be placed in tiling mode
+ *
+ * \param buf Buffer to set tiling mode for
+ * \param tiling_mode desired, and returned tiling mode
+ */
+ int (*bo_set_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode,
+ uint32_t stride);
+
+ /**
+ * Get the current tiling (and resulting swizzling) mode for the bo.
+ *
+ * \param buf Buffer to get tiling mode for
+ * \param tiling_mode returned tiling mode
+ * \param swizzle_mode returned swizzling mode
+ */
+ int (*bo_get_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode,
+ uint32_t * swizzle_mode);
+
+ /**
+ * Set the offset at which this buffer will be softpinned
+ * \param bo Buffer to set the softpin offset for
+ * \param offset Softpin offset
+ */
+ int (*bo_set_softpin_offset) (drm_intel_bo *bo, uint64_t offset);
+
+ /**
+ * Create a visible name for a buffer which can be used by other apps
+ *
+ * \param buf Buffer to create a name for
+ * \param name Returned name
+ */
+ int (*bo_flink) (drm_intel_bo *bo, uint32_t * name);
+
+ /**
+ * Returns 1 if mapping the buffer for write could cause the process
+ * to block, due to the object being active in the GPU.
+ */
+ int (*bo_busy) (drm_intel_bo *bo);
+
+ /**
+ * Specify the volatility of the buffer.
+ * \param bo Buffer to create a name for
+ * \param madv The purgeable status
+ *
+ * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
+ * reclaimed under memory pressure. If you subsequently require the buffer,
+ * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
+ *
+ * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
+ * marked as I915_MADV_DONTNEED.
+ */
+ int (*bo_madvise) (drm_intel_bo *bo, int madv);
+
+ int (*check_aperture_space) (drm_intel_bo ** bo_array, int count);
+
+ /**
+ * Disable buffer reuse for buffers which will be shared in some way,
+ * as with scanout buffers. When the buffer reference count goes to
+ * zero, it will be freed and not placed in the reuse list.
+ *
+ * \param bo Buffer to disable reuse for
+ */
+ int (*bo_disable_reuse) (drm_intel_bo *bo);
+
+ /**
+ * Query whether a buffer is reusable.
+ *
+ * \param bo Buffer to query
+ */
+ int (*bo_is_reusable) (drm_intel_bo *bo);
+
+ /**
+ *
+ * Return the pipe associated with a crtc_id so that vblank
+ * synchronization can use the correct data in the request.
+ * This is only supported for KMS and gem at this point, when
+ * unsupported, this function returns -1 and leaves the decision
+ * of what to do in that case to the caller
+ *
+ * \param bufmgr the associated buffer manager
+ * \param crtc_id the crtc identifier
+ */
+ int (*get_pipe_from_crtc_id) (drm_intel_bufmgr *bufmgr, int crtc_id);
+
+ /** Returns true if target_bo is in the relocation tree rooted at bo. */
+ int (*bo_references) (drm_intel_bo *bo, drm_intel_bo *target_bo);
+
+ /**< Enables verbose debugging printouts */
+ int debug;
+};
+
+struct _drm_intel_bo {
+ /**
+ * Size in bytes of the buffer object.
+ *
+ * The size may be larger than the size originally requested for the
+ * allocation, such as being aligned to page size.
+ */
+ unsigned long size;
+
+ /**
+ * Alignment requirement for object
+ *
+ * Used for GTT mapping & pinning the object.
+ */
+ unsigned long align;
+
+ /**
+ * Deprecated field containing (possibly the low 32-bits of) the last
+ * seen virtual card address. Use offset64 instead.
+ */
+ unsigned long offset;
+
+ /**
+ * Virtual address for accessing the buffer data. Only valid while
+ * mapped.
+ */
+#ifdef __cplusplus
+ void *virt;
+#else
+ void *virtual;
+#endif
+
+ /** Buffer manager context associated with this buffer object */
+ drm_intel_bufmgr *bufmgr;
+
+ /**
+ * MM-specific handle for accessing object
+ */
+ int handle;
+
+ /**
+ * Last seen card virtual address (offset from the beginning of the
+ * aperture) for the object. This should be used to fill relocation
+ * entries when calling drm_intel_bo_emit_reloc()
+ */
+ uint64_t offset64;
+};
+
+typedef struct drm_i915_getparam {
+ __s32 param;
+ /*
+ * WARNING: Using pointers instead of fixed-size u64 means we need to write
+ * compat32 code. Don't repeat this mistake.
+ */
+ int *value;
+} drm_i915_getparam_t;
+
+struct drm_i915_gem_execbuffer2 {
+ /**
+ * List of gem_exec_object2 structs
+ */
+ __u64 buffers_ptr;
+ __u32 buffer_count;
+
+ /** Offset in the batchbuffer to start execution from. */
+ __u32 batch_start_offset;
+ /** Bytes used in batchbuffer from batch_start_offset */
+ __u32 batch_len;
+ __u32 DR1;
+ __u32 DR4;
+ __u32 num_cliprects;
+ /** This is a struct drm_clip_rect *cliprects */
+ __u64 cliprects_ptr;
+#define I915_EXEC_RING_MASK (7<<0)
+#define I915_EXEC_DEFAULT (0<<0)
+#define I915_EXEC_RENDER (1<<0)
+#define I915_EXEC_BSD (2<<0)
+#define I915_EXEC_BLT (3<<0)
+#define I915_EXEC_VEBOX (4<<0)
+
+/* Used for switching the constants addressing mode on gen4+ RENDER ring.
+ * Gen6+ only supports relative addressing to dynamic state (default) and
+ * absolute addressing.
+ *
+ * These flags are ignored for the BSD and BLT rings.
+ */
+#define I915_EXEC_CONSTANTS_MASK (3<<6)
+#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
+#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
+#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
+ __u64 flags;
+ __u64 rsvd1; /* now used for context info */
+ __u64 rsvd2;
+};
+
+struct drm_i915_gem_exec_object2 {
+ /**
+ * User's handle for a buffer to be bound into the GTT for this
+ * operation.
+ */
+ __u32 handle;
+
+ /** Number of relocations to be performed on this buffer */
+ __u32 relocation_count;
+ /**
+ * Pointer to array of struct drm_i915_gem_relocation_entry containing
+ * the relocations to be performed in this buffer.
+ */
+ __u64 relocs_ptr;
+
+ /** Required alignment in graphics aperture */
+ __u64 alignment;
+
+ /**
+ * When the EXEC_OBJECT_PINNED flag is specified this is populated by
+ * the user with the GTT offset at which this object will be pinned.
+ * When the I915_EXEC_NO_RELOC flag is specified this must contain the
+ * presumed_offset of the object.
+ * During execbuffer2 the kernel populates it with the value of the
+ * current GTT offset of the object, for future presumed_offset writes.
+ */
+ __u64 offset;
+
+#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
+#define EXEC_OBJECT_NEEDS_GTT (1<<1)
+#define EXEC_OBJECT_WRITE (1<<2)
+#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
+#define EXEC_OBJECT_PINNED (1<<4)
+#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1)
+ __u64 flags;
+
+ __u64 rsvd1;
+ __u64 rsvd2;
+};
+
+struct drm_i915_gem_relocation_entry {
+ /**
+ * Handle of the buffer being pointed to by this relocation entry.
+ *
+ * It's appealing to make this be an index into the mm_validate_entry
+ * list to refer to the buffer, but this allows the driver to create
+ * a relocation list for state buffers and not re-write it per
+ * exec using the buffer.
+ */
+ __u32 target_handle;
+
+ /**
+ * Value to be added to the offset of the target buffer to make up
+ * the relocation entry.
+ */
+ __u32 delta;
+
+ /** Offset in the buffer the relocation entry will be written into */
+ __u64 offset;
+
+ /**
+ * Offset value of the target buffer that the relocation entry was last
+ * written as.
+ *
+ * If the buffer has the same offset as last time, we can skip syncing
+ * and writing the relocation. This value is written back out by
+ * the execbuffer ioctl when the relocation is written.
+ */
+ __u64 presumed_offset;
+
+ /**
+ * Target memory domains read by this operation.
+ */
+ __u32 read_domains;
+
+ /**
+ * Target memory domains written by this operation.
+ *
+ * Note that only one domain may be written by the whole
+ * execbuffer operation, so that where there are conflicts,
+ * the application will get -EINVAL back.
+ */
+ __u32 write_domain;
+};
+
+struct drm_i915_gem_get_tiling {
+ /** Handle of the buffer to get tiling state for. */
+ __u32 handle;
+
+ /**
+ * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
+ * I915_TILING_Y).
+ */
+ __u32 tiling_mode;
+
+ /**
+ * Returned address bit 6 swizzling required for CPU access through
+ * mmap mapping.
+ */
+ __u32 swizzle_mode;
+
+ /**
+ * Returned address bit 6 swizzling required for CPU access through
+ * mmap mapping whilst bound.
+ */
+ __u32 phys_swizzle_mode;
+};
+
+struct drm_i915_gem_set_tiling {
+ /** Handle of the buffer to have its tiling state updated */
+ __u32 handle;
+
+ /**
+ * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
+ * I915_TILING_Y).
+ *
+ * This value is to be set on request, and will be updated by the
+ * kernel on successful return with the actual chosen tiling layout.
+ *
+ * The tiling mode may be demoted to I915_TILING_NONE when the system
+ * has bit 6 swizzling that can't be managed correctly by GEM.
+ *
+ * Buffer contents become undefined when changing tiling_mode.
+ */
+ __u32 tiling_mode;
+
+ /**
+ * Stride in bytes for the object when in I915_TILING_X or
+ * I915_TILING_Y.
+ */
+ __u32 stride;
+
+ /**
+ * Returned address bit 6 swizzling required for CPU access through
+ * mmap mapping.
+ */
+ __u32 swizzle_mode;
+};
+
+struct drm_i915_gem_pwrite {
+ /** Handle for the object being written to. */
+ __u32 handle;
+ __u32 pad;
+ /** Offset into the object to write to */
+ __u64 offset;
+ /** Length of data to write */
+ __u64 size;
+ /**
+ * Pointer to read the data from.
+ *
+ * This is a fixed-size type for 32/64 compatibility.
+ */
+ __u64 data_ptr;
+};
+
+struct drm_i915_gem_pread {
+ /** Handle for the object being read. */
+ __u32 handle;
+ __u32 pad;
+ /** Offset into the object to read from */
+ __u64 offset;
+ /** Length of data to read */
+ __u64 size;
+ /**
+ * Pointer to write the data into.
+ *
+ * This is a fixed-size type for 32/64 compatibility.
+ */
+ __u64 data_ptr;
+};
+
+struct drm_i915_gem_set_domain {
+ /** Handle for the object */
+ __u32 handle;
+
+ /** New read domains */
+ __u32 read_domains;
+
+ /** New write domain */
+ __u32 write_domain;
+};
+
+struct drm_i915_gem_wait {
+ /** Handle of BO we shall wait on */
+ __u32 bo_handle;
+ __u32 flags;
+ /** Number of nanoseconds to wait, Returns time remaining. */
+ __s64 timeout_ns;
+};
+
+struct drm_i915_gem_busy {
+ /** Handle of the buffer to check for busy */
+ __u32 handle;
+
+ /** Return busy status (1 if busy, 0 if idle).
+ * The high word is used to indicate on which rings the object
+ * currently resides:
+ * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
+ */
+ __u32 busy;
+};
+
+struct drm_i915_gem_get_aperture {
+ /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
+ __u64 aper_size;
+
+ /**
+ * Available space in the aperture used by i915_gem_execbuffer, in
+ * bytes
+ */
+ __u64 aper_available_size;
+};
+
+struct drm_i915_gem_create {
+ /**
+ * Requested size for the object.
+ *
+ * The (page-aligned) allocated size for the object will be returned.
+ */
+ __u64 size;
+ /**
+ * Returned handle for the object.
+ *
+ * Object handles are nonzero.
+ */
+ __u32 handle;
+ __u32 pad;
+};
+
+struct drm_i915_gem_mmap_gtt {
+ /** Handle for the object being mapped. */
+ __u32 handle;
+ __u32 pad;
+ /**
+ * Fake offset to use for subsequent mmap call
+ *
+ * This is a fixed-size type for 32/64 compatibility.
+ */
+ __u64 offset;
+};
+
+struct drm_i915_gem_sw_finish {
+ /** Handle for the object */
+ __u32 handle;
+};
+
+struct drm_i915_gem_mmap {
+ /** Handle for the object being mapped. */
+ __u32 handle;
+ __u32 pad;
+ /** Offset in the object to map. */
+ __u64 offset;
+ /**
+ * Length of data to map.
+ *
+ * The value will be page-aligned.
+ */
+ __u64 size;
+ /**
+ * Returned pointer the data was mapped at.
+ *
+ * This is a fixed-size type for 32/64 compatibility.
+ */
+ __u64 addr_ptr;
+
+ /**
+ * Flags for extended behaviour.
+ *
+ * Added in version 2.
+ */
+ __u64 flags;
+#define I915_MMAP_WC 0x1
+};
+
+struct drm_i915_gem_madvise {
+ /** Handle of the buffer to change the backing store advice */
+ __u32 handle;
+
+ /* Advice: either the buffer will be needed again in the near future,
+ * or wont be and could be discarded under memory pressure.
+ */
+ __u32 madv;
+
+ /** Whether the backing store still exists. */
+ __u32 retained;
+};
+
+struct drm_i915_gem_context_create {
+ /* output: id of new context*/
+ __u32 ctx_id;
+ __u32 pad;
+};
+
+struct drm_i915_gem_context_destroy {
+ __u32 ctx_id;
+ __u32 pad;
+};
+
+typedef struct _drm_intel_aub_annotation {
+ uint32_t type;
+ uint32_t subtype;
+ uint32_t ending_offset;
+} drm_intel_aub_annotation;
+
+struct drm_i915_gem_pin {
+ /** Handle of the buffer to be pinned. */
+ __u32 handle;
+ __u32 pad;
+
+ /** alignment required within the aperture */
+ __u64 alignment;
+
+ /** Returned GTT offset of the buffer. */
+ __u64 offset;
+};
+
+#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
+#define I915_SET_COLORKEY_DESTINATION (1<<1)
+#define I915_SET_COLORKEY_SOURCE (1<<2)
+struct drm_intel_sprite_colorkey {
+ __u32 plane_id;
+ __u32 min_value;
+ __u32 channel_mask;
+ __u32 max_value;
+ __u32 flags;
+};
+
+struct drm_i915_reg_read {
+ /*
+ * Register offset.
+ * For 64bit wide registers where the upper 32bits don't immediately
+ * follow the lower 32bits, the offset of the lower 32bits must
+ * be specified
+ */
+ __u64 offset;
+ __u64 val; /* Return value */
+};
+
+drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
+void drm_intel_bo_unreference(drm_intel_bo *bo);
+drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
+ unsigned long size, unsigned int alignment);
+int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
+ unsigned long size, const void *data);
+int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
+ int used, unsigned int flags);
+int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
+ drm_intel_bo *target_bo, uint32_t target_offset,
+ uint32_t read_domains, uint32_t write_domain);
+int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
+ drm_intel_bo *target_bo,
+ uint32_t target_offset,
+ uint32_t read_domains, uint32_t write_domain);
+int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
+ uint32_t * swizzle_mode);
+int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
+ struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
+ unsigned int flags);
+void drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
+ drm_intel_aub_annotation *annotations,
+ unsigned count);
+void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
+int drm_intel_bo_exec(drm_intel_bo *bo, int used,
+ struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
+void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
+void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
+int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
+ unsigned long size, void *data);
+int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
+int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
+void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr);
+int drm_intel_bo_unmap(drm_intel_bo *bo);
+int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
+drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
+ const char *name,
+ unsigned int handle);
+int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
+drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
+ int prime_fd, int size);
+void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
+ int limit);
+int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
+drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr);
+void drm_intel_gem_context_destroy(drm_intel_context *ctx);
+drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
+ const char *name,
+ int x, int y, int cpp,
+ uint32_t *tiling_mode,
+ unsigned long *pitch,
+ unsigned long flags);
+void drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
+ const char *filename);
+void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
+void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
+ int x1, int y1, int width, int height,
+ enum aub_dump_bmp_format format,
+ int pitch, int offset);
+void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
+int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
+ uint32_t stride);
+int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
+void drm_intel_bo_reference(drm_intel_bo *bo);
+int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
+drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
+ const char *name,
+ unsigned long size,
+ unsigned int alignment);
+int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
+int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns);
+
+#endif
+
+#endif//INTEL_DRM_STUBS_H
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [RFC i-g-t 8/9] lib: Replace intel specific header includes with intel_drm_stubs.h.
2016-05-20 22:59 [RFC i-g-t 0/9] Remove compile time depencencies on libdrm_intel robert.foss
` (6 preceding siblings ...)
2016-05-20 22:59 ` [RFC i-g-t 7/9] lib/intel_drm_stubs: Add stubs for functionality from libdrm_intel robert.foss
@ 2016-05-20 22:59 ` robert.foss
2016-05-23 14:57 ` ?==?utf-8?q? " Emil Velikov
2016-05-24 8:07 ` Daniel Vetter
2016-05-20 22:59 ` [RFC i-g-t 9/9] tests: " robert.foss
8 siblings, 2 replies; 29+ messages in thread
From: robert.foss @ 2016-05-20 22:59 UTC (permalink / raw)
To: daniel.vetter, daniel.stone, marius.c.vlad, tomeu.vizoso, emil.velikov
Cc: intel-gfx
From: Robert Foss <robert.foss@collabora.com>
Replace intel specific header includes with intel_drm_stubs.h.
The stubbed functions will all call igt_require(false) and cause a skip.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
---
lib/drmtest.c | 2 +-
lib/gpgpu_fill.c | 7 +++----
lib/igt_aux.c | 2 +-
lib/igt_aux.h | 3 ++-
lib/igt_debugfs.c | 4 ++--
lib/igt_draw.h | 3 +--
lib/igt_fb.h | 3 ++-
lib/igt_kms.c | 3 +--
lib/intel_batchbuffer.c | 4 ----
lib/intel_batchbuffer.h | 3 +--
lib/intel_chipset.c | 2 +-
lib/ioctl_wrappers.c | 1 -
lib/ioctl_wrappers.h | 4 ++--
lib/media_fill_gen7.c | 3 +--
lib/media_fill_gen8.c | 4 +---
lib/media_fill_gen8lp.c | 6 ++----
lib/media_fill_gen9.c | 4 +---
lib/media_spin.c | 2 --
lib/rendercopy_gen6.c | 5 ++---
lib/rendercopy_gen7.c | 4 +---
lib/rendercopy_gen8.c | 4 +---
lib/rendercopy_gen9.c | 5 +----
lib/rendercopy_i830.c | 5 +----
lib/rendercopy_i915.c | 9 +++------
24 files changed, 31 insertions(+), 61 deletions(-)
diff --git a/lib/drmtest.c b/lib/drmtest.c
index 7d6b74a..f043607 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -48,13 +48,13 @@
#include <termios.h>
#include "drmtest.h"
-#include "i915_drm.h"
#include "intel_chipset.h"
#include "intel_io.h"
#include "igt_gt.h"
#include "igt_debugfs.h"
#include "version.h"
#include "config.h"
+#include "intel_drm_stubs.h"
#include "intel_reg.h"
#include "ioctl_wrappers.h"
diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
index 4d98643..62b1161 100644
--- a/lib/gpgpu_fill.c
+++ b/lib/gpgpu_fill.c
@@ -25,15 +25,14 @@
* Dominik Zeromski <dominik.zeromski@intel.com>
*/
-#include <intel_bufmgr.h>
-#include <i915_drm.h>
-#include "intel_reg.h"
#include "drmtest.h"
-#include "intel_batchbuffer.h"
#include "gen7_media.h"
#include "gen8_media.h"
#include "gpgpu_fill.h"
+#include "intel_batchbuffer.h"
+#include "intel_drm_stubs.h"
+#include "intel_reg.h"
/* shaders/gpgpu/gpgpu_fill.gxa */
static const uint32_t gen7_gpgpu_kernel[][4] = {
diff --git a/lib/igt_aux.c b/lib/igt_aux.c
index fe18365..772c902 100644
--- a/lib/igt_aux.c
+++ b/lib/igt_aux.c
@@ -52,12 +52,12 @@
#include <assert.h>
#include "drmtest.h"
-#include "i915_drm.h"
#include "intel_chipset.h"
#include "igt_aux.h"
#include "igt_debugfs.h"
#include "igt_gt.h"
#include "config.h"
+#include "intel_drm_stubs.h"
#include "intel_reg.h"
#include "ioctl_wrappers.h"
#include "igt_kms.h"
diff --git a/lib/igt_aux.h b/lib/igt_aux.h
index f66de72..c66121b 100644
--- a/lib/igt_aux.h
+++ b/lib/igt_aux.h
@@ -28,10 +28,11 @@
#ifndef IGT_AUX_H
#define IGT_AUX_H
-#include <intel_bufmgr.h>
#include <stdbool.h>
#include <sys/time.h>
+#include "intel_drm_stubs.h"
+
extern drm_intel_bo **trash_bos;
extern int num_trash_bos;
diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
index a32ed78..d9f371f 100644
--- a/lib/igt_debugfs.c
+++ b/lib/igt_debugfs.c
@@ -32,12 +32,12 @@
#include <string.h>
#include <fcntl.h>
#include <unistd.h>
-#include <i915_drm.h>
#include "drmtest.h"
+#include "intel_drm_stubs.h"
#include "igt_aux.h"
-#include "igt_kms.h"
#include "igt_debugfs.h"
+#include "igt_kms.h"
/**
* SECTION:igt_debugfs
diff --git a/lib/igt_draw.h b/lib/igt_draw.h
index b030131..c0e95ca 100644
--- a/lib/igt_draw.h
+++ b/lib/igt_draw.h
@@ -25,9 +25,8 @@
#ifndef __IGT_DRAW_H__
#define __IGT_DRAW_H__
-#include <intel_bufmgr.h>
#include "igt_fb.h"
-
+#include "intel_drm_stubs.h"
/**
* igt_draw_method:
* @IGT_DRAW_MMAP_CPU: draw using a CPU mmap.
diff --git a/lib/igt_fb.h b/lib/igt_fb.h
index ce2cc0f..82dbacb 100644
--- a/lib/igt_fb.h
+++ b/lib/igt_fb.h
@@ -38,10 +38,11 @@ typedef struct _cairo cairo_t;
#include <stddef.h>
#include <stdbool.h>
+#include <stdint.h>
#include <drm_fourcc.h>
#include <xf86drmMode.h>
-#include <i915_drm.h>
+#include "intel_drm_stubs.h"
/* helpers to create nice-looking framebuffers */
struct igt_fb {
diff --git a/lib/igt_kms.c b/lib/igt_kms.c
index f85be1e..7afee53 100644
--- a/lib/igt_kms.c
+++ b/lib/igt_kms.c
@@ -41,12 +41,11 @@
#include <errno.h>
#include <time.h>
-#include <i915_drm.h>
-
#include "drmtest.h"
#include "igt_kms.h"
#include "igt_aux.h"
#include "intel_chipset.h"
+#include "intel_drm_stubs.h"
#include "igt_debugfs.h"
/* list of connectors that need resetting on exit */
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 692521f..a28eb33 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -31,10 +31,8 @@
#include <string.h>
#include <assert.h>
-#include "drm.h"
#include "drmtest.h"
#include "intel_batchbuffer.h"
-#include "intel_bufmgr.h"
#include "intel_chipset.h"
#include "intel_reg.h"
#include "rendercopy.h"
@@ -43,8 +41,6 @@
#include "media_spin.h"
#include "gpgpu_fill.h"
-#include <i915_drm.h>
-
/**
* SECTION:intel_batchbuffer
* @short_description: Batchbuffer and blitter support
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 869747d..bd365db 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -2,10 +2,9 @@
#define INTEL_BATCHBUFFER_H
#include <stdint.h>
-#include <intel_bufmgr.h>
-#include <i915_drm.h>
#include "igt_core.h"
+#include "intel_drm_stubs.h"
#include "intel_reg.h"
#define BATCH_SZ 4096
diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
index 56746b0..6ac74e9 100644
--- a/lib/intel_chipset.c
+++ b/lib/intel_chipset.c
@@ -36,9 +36,9 @@
#include <fcntl.h>
#include <sys/stat.h>
#include <sys/mman.h>
-#include "i915_drm.h"
#include "drmtest.h"
+#include "intel_drm_stubs.h"
#include "intel_chipset.h"
#include "igt_core.h"
diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
index f224091..e46811a 100644
--- a/lib/ioctl_wrappers.c
+++ b/lib/ioctl_wrappers.c
@@ -50,7 +50,6 @@
#include <errno.h>
#include "drmtest.h"
-#include "i915_drm.h"
#include "intel_chipset.h"
#include "intel_io.h"
#include "igt_debugfs.h"
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 8fe35b0..aa8c60f 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -32,8 +32,8 @@
#include <stdint.h>
#include <stdbool.h>
-#include <intel_bufmgr.h>
-#include <i915_drm.h>
+
+#include "intel_drm_stubs.h"
extern int (*igt_ioctl)(int fd, unsigned long request, void *arg);
diff --git a/lib/media_fill_gen7.c b/lib/media_fill_gen7.c
index 6fb4479..5ec8502 100644
--- a/lib/media_fill_gen7.c
+++ b/lib/media_fill_gen7.c
@@ -1,9 +1,8 @@
-#include <intel_bufmgr.h>
-#include <i915_drm.h>
#include "media_fill.h"
#include "gen7_media.h"
#include "intel_reg.h"
+#include "intel_drm_stubs.h"
#include "drmtest.h"
#include <assert.h>
diff --git a/lib/media_fill_gen8.c b/lib/media_fill_gen8.c
index 4a8fe5a..a1e1fe4 100644
--- a/lib/media_fill_gen8.c
+++ b/lib/media_fill_gen8.c
@@ -1,8 +1,6 @@
-#include <intel_bufmgr.h>
-#include <i915_drm.h>
-
#include "media_fill.h"
#include "gen8_media.h"
+#include "intel_drm_stubs.h"
#include "intel_reg.h"
#include "drmtest.h"
diff --git a/lib/media_fill_gen8lp.c b/lib/media_fill_gen8lp.c
index 1f8a4ad..eed26ee 100644
--- a/lib/media_fill_gen8lp.c
+++ b/lib/media_fill_gen8lp.c
@@ -1,13 +1,11 @@
-#include <intel_bufmgr.h>
-#include <i915_drm.h>
+#include <assert.h>
#include "media_fill.h"
#include "gen8_media.h"
+#include "intel_drm_stubs.h"
#include "intel_reg.h"
#include "drmtest.h"
-#include <assert.h>
-
static const uint32_t media_kernel[][4] = {
{ 0x00400001, 0x20202288, 0x00000020, 0x00000000 },
diff --git a/lib/media_fill_gen9.c b/lib/media_fill_gen9.c
index 3fd2181..902b28b 100644
--- a/lib/media_fill_gen9.c
+++ b/lib/media_fill_gen9.c
@@ -1,8 +1,6 @@
-#include <intel_bufmgr.h>
-#include <i915_drm.h>
-
#include "media_fill.h"
#include "gen8_media.h"
+#include "intel_drm_stubs.h"
#include "intel_reg.h"
#include <assert.h>
diff --git a/lib/media_spin.c b/lib/media_spin.c
index 580c109..f4a432a 100644
--- a/lib/media_spin.c
+++ b/lib/media_spin.c
@@ -24,8 +24,6 @@
* Jeff McGee <jeff.mcgee@intel.com>
*/
-#include <intel_bufmgr.h>
-#include <i915_drm.h>
#include "intel_reg.h"
#include "drmtest.h"
#include "intel_batchbuffer.h"
diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c
index 8c24cf8..d5207d5 100644
--- a/lib/rendercopy_gen6.c
+++ b/lib/rendercopy_gen6.c
@@ -9,11 +9,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "i915_drm.h"
+
#include "drmtest.h"
-#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
+#include "intel_drm_stubs.h"
#include "intel_io.h"
#include "rendercopy.h"
#include "gen6_render.h"
diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c
index 3b92406..dc48a99 100644
--- a/lib/rendercopy_gen7.c
+++ b/lib/rendercopy_gen7.c
@@ -9,10 +9,8 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "i915_drm.h"
+
#include "drmtest.h"
-#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
#include "intel_io.h"
#include "intel_chipset.h"
diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c
index a7fc2c4..6fbb680 100644
--- a/lib/rendercopy_gen8.c
+++ b/lib/rendercopy_gen8.c
@@ -10,12 +10,10 @@
#include <sys/stat.h>
#include <sys/time.h>
-#include <drm.h>
-#include <i915_drm.h>
#include "drmtest.h"
-#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
+#include "intel_drm_stubs.h"
#include "intel_io.h"
#include "rendercopy.h"
#include "gen8_render.h"
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 9537480..d575ddf 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -11,12 +11,9 @@
#include <sys/time.h>
#include <getopt.h>
-#include <drm.h>
-#include <i915_drm.h>
-
#include "drmtest.h"
-#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
+#include "intel_drm_stubs.h"
#include "intel_io.h"
#include "rendercopy.h"
#include "gen9_render.h"
diff --git a/lib/rendercopy_i830.c b/lib/rendercopy_i830.c
index 04215b1..738d4d2 100644
--- a/lib/rendercopy_i830.c
+++ b/lib/rendercopy_i830.c
@@ -8,13 +8,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "i915_drm.h"
+
#include "drmtest.h"
-#include "intel_bufmgr.h"
#include "intel_batchbuffer.h"
#include "intel_io.h"
-
#include "i830_reg.h"
#include "rendercopy.h"
diff --git a/lib/rendercopy_i915.c b/lib/rendercopy_i915.c
index fc9583c..8846fdc 100644
--- a/lib/rendercopy_i915.c
+++ b/lib/rendercopy_i915.c
@@ -8,15 +8,12 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "i915_drm.h"
-#include "drmtest.h"
-#include "intel_bufmgr.h"
-#include "intel_batchbuffer.h"
-#include "intel_io.h"
+#include "drmtest.h"
#include "i915_reg.h"
#include "i915_3d.h"
+#include "intel_batchbuffer.h"
+#include "intel_io.h"
#include "rendercopy.h"
void gen3_render_copyfunc(struct intel_batchbuffer *batch,
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [RFC i-g-t 9/9] tests: Replace intel specific header includes with intel_drm_stubs.h.
2016-05-20 22:59 [RFC i-g-t 0/9] Remove compile time depencencies on libdrm_intel robert.foss
` (7 preceding siblings ...)
2016-05-20 22:59 ` [RFC i-g-t 8/9] lib: Replace intel specific header includes with intel_drm_stubs.h robert.foss
@ 2016-05-20 22:59 ` robert.foss
8 siblings, 0 replies; 29+ messages in thread
From: robert.foss @ 2016-05-20 22:59 UTC (permalink / raw)
To: daniel.vetter, daniel.stone, marius.c.vlad, tomeu.vizoso, emil.velikov
Cc: intel-gfx
From: Robert Foss <robert.foss@collabora.com>
Replace intel specific header includes with intel_drm_stubs.h.
The stubbed functions will all call igt_require(false) and cause a skip.
Additionally there a small amount of reformatting of the #includes was
perfomed. "XXX" was fixed to <XXX> where approptiate, spacing and alphabetical
ordering was also enforced.
Signed-off-by: Robert Foss <robert.foss@collabora.com>
---
tests/core_auth.c | 2 +-
tests/core_get_client_auth.c | 2 +-
tests/core_getclient.c | 3 ++-
tests/drm_import_export.c | 7 +++----
tests/drm_read.c | 5 +++--
tests/drm_vma_limiter.c | 6 +++---
tests/drm_vma_limiter_cached.c | 6 +++---
tests/drm_vma_limiter_cpu.c | 6 +++---
tests/drm_vma_limiter_gtt.c | 6 +++---
tests/drv_getparams_basic.c | 6 +++---
tests/gem_alive.c | 4 ++--
tests/gem_bad_address.c | 6 +++---
tests/gem_bad_batch.c | 6 +++---
tests/gem_bad_blit.c | 6 +++---
tests/gem_bad_length.c | 2 +-
tests/gem_bad_reloc.c | 2 +-
tests/gem_basic.c | 2 +-
tests/gem_caching.c | 5 ++---
tests/gem_close_race.c | 2 +-
tests/gem_concurrent_all.c | 5 ++---
tests/gem_cpu_reloc.c | 4 ++--
tests/gem_create.c | 8 ++++----
tests/gem_ctx_bad_exec.c | 3 ++-
tests/gem_ctx_basic.c | 8 +++++---
tests/gem_double_irq_loop.c | 7 ++++---
tests/gem_evict_everything.c | 2 +-
tests/gem_exec_bad_domains.c | 7 ++++---
tests/gem_exec_big.c | 2 +-
tests/gem_exec_blt.c | 2 +-
tests/gem_exec_faulting_reloc.c | 2 +-
tests/gem_exec_lut_handle.c | 2 +-
tests/gem_exec_nop.c | 2 +-
tests/gem_exec_params.c | 2 +-
tests/gem_fence_thrash.c | 2 +-
tests/gem_fence_upload.c | 7 ++++---
tests/gem_flink_basic.c | 2 +-
tests/gem_flink_race.c | 4 ++--
tests/gem_gpgpu_fill.c | 7 ++++---
tests/gem_gtt_cpu_tlb.c | 2 +-
tests/gem_gtt_speed.c | 2 +-
tests/gem_hang.c | 6 +++---
tests/gem_hangcheck_forcewake.c | 7 ++++---
tests/gem_largeobject.c | 2 +-
tests/gem_lut_handle.c | 2 +-
tests/gem_madvise.c | 3 +--
tests/gem_media_fill.c | 7 ++++---
tests/gem_mmap.c | 2 +-
tests/gem_mmap_gtt.c | 2 +-
tests/gem_mmap_offset_exhaustion.c | 2 +-
tests/gem_mmap_wc.c | 2 +-
tests/gem_non_secure_batch.c | 5 +++--
tests/gem_partial_pwrite_pread.c | 1 -
tests/gem_persistent_relocs.c | 1 -
tests/gem_pin.c | 1 -
tests/gem_pipe_control_store_loop.c | 7 ++++---
tests/gem_ppgtt.c | 6 +++---
tests/gem_pread.c | 2 +-
tests/gem_pread_after_blit.c | 1 -
tests/gem_pwrite.c | 2 +-
tests/gem_pwrite_pread.c | 7 ++++---
tests/gem_pwrite_snooped.c | 2 +-
tests/gem_read_read_speed.c | 5 ++---
tests/gem_readwrite.c | 2 +-
tests/gem_reloc_overflow.c | 2 +-
tests/gem_reloc_vs_gpu.c | 1 -
tests/gem_render_copy.c | 5 ++---
tests/gem_render_copy_redux.c | 7 +++----
tests/gem_render_linear_blits.c | 5 ++---
tests/gem_render_tiled_blits.c | 5 ++---
tests/gem_request_retire.c | 8 +++-----
tests/gem_seqno_wrap.c | 4 ++--
tests/gem_set_tiling_vs_blt.c | 7 ++++---
tests/gem_set_tiling_vs_gtt.c | 2 +-
tests/gem_set_tiling_vs_pwrite.c | 2 +-
tests/gem_stolen.c | 14 ++++++--------
tests/gem_storedw_batches_loop.c | 7 ++++---
tests/gem_storedw_loop.c | 2 +-
tests/gem_streaming_writes.c | 2 +-
tests/gem_stress.c | 6 ++----
tests/gem_threaded_access_tiled.c | 4 ++--
tests/gem_tiled_blits.c | 1 -
tests/gem_tiled_fence_blits.c | 5 ++---
tests/gem_tiled_partial_pwrite_pread.c | 1 -
tests/gem_tiled_pread_basic.c | 2 +-
tests/gem_tiled_pread_pwrite.c | 1 -
tests/gem_tiled_swapping.c | 1 -
tests/gem_tiled_wb.c | 2 +-
tests/gem_tiled_wc.c | 2 +-
tests/gem_tiling_max_stride.c | 2 +-
tests/gem_unfence_active_buffers.c | 7 ++++---
tests/gem_unref_active_buffers.c | 7 ++++---
tests/gem_userptr_blits.c | 8 +++-----
tests/gem_wait.c | 5 ++---
tests/gem_write_read_ring_switch.c | 1 -
tests/gen3_mixed_blits.c | 2 +-
tests/gen3_render_linear_blits.c | 2 +-
tests/gen3_render_mixed_blits.c | 2 +-
tests/gen3_render_tiledx_blits.c | 2 +-
tests/gen3_render_tiledy_blits.c | 2 +-
tests/gen7_forcewake_mt.c | 3 +--
tests/kms_addfb_basic.c | 3 ++-
tests/kms_atomic.c | 5 +++--
tests/kms_mmap_write_crc.c | 2 +-
tests/kms_psr_sink_crc.c | 4 ++--
tests/kms_render.c | 4 ++--
tests/kms_setmode.c | 4 ++--
tests/kms_vblank.c | 5 ++---
tests/pm_rpm.c | 1 -
tests/pm_rps.c | 4 ++--
tests/pm_sseu.c | 6 +++---
tests/prime_mmap.c | 5 +++--
tests/prime_nv_api.c | 4 ++--
tests/prime_nv_pcopy.c | 4 ++--
tests/prime_nv_test.c | 4 ++--
tests/prime_self_import.c | 3 +--
tests/prime_udl.c | 7 +++----
tests/vc4_create_bo.c | 5 +++--
tests/vc4_wait_bo.c | 5 +++--
tests/vc4_wait_seqno.c | 3 ++-
119 files changed, 226 insertions(+), 236 deletions(-)
diff --git a/tests/core_auth.c b/tests/core_auth.c
index 79bd587..8281172 100644
--- a/tests/core_auth.c
+++ b/tests/core_auth.c
@@ -39,7 +39,7 @@
#include <sys/ioctl.h>
#include <sys/time.h>
#include <sys/poll.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Call drmGetMagic() and drmAuthMagic() and see if it behaves.");
diff --git a/tests/core_get_client_auth.c b/tests/core_get_client_auth.c
index 50e87fa..a2ee293 100644
--- a/tests/core_get_client_auth.c
+++ b/tests/core_get_client_auth.c
@@ -44,7 +44,7 @@
# include <pthread.h>
#endif
-#include "drm.h"
+#include <drm.h>
/* Checks whether the thread id is the current thread */
static bool
diff --git a/tests/core_getclient.c b/tests/core_getclient.c
index 40a1c19..94f1b2f 100644
--- a/tests/core_getclient.c
+++ b/tests/core_getclient.c
@@ -25,12 +25,13 @@
*
*/
-#include "igt.h"
#include <limits.h>
#include <sys/ioctl.h>
#include <stdlib.h>
#include <errno.h>
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Tests the DRM_IOCTL_GET_CLIENT ioctl.");
diff --git a/tests/drm_import_export.c b/tests/drm_import_export.c
index cfe5f6d..0f8475b 100644
--- a/tests/drm_import_export.c
+++ b/tests/drm_import_export.c
@@ -25,22 +25,21 @@
*/
#define _GNU_SOURCE
-#include "igt.h"
#include <stdio.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdlib.h>
#include <string.h>
-#include <libdrm/drm.h>
-#include <libdrm/i915_drm.h>
#include <xf86drm.h>
-#include <intel_bufmgr.h>
#include <errno.h>
#include <pthread.h>
#include <unistd.h>
#include <sys/syscall.h>
+#include "igt.h"
+#include "intel_drm_stubs.h"
+
int fd;
drm_intel_bufmgr *bufmgr;
diff --git a/tests/drm_read.c b/tests/drm_read.c
index 7df36e9..45e51dd 100644
--- a/tests/drm_read.c
+++ b/tests/drm_read.c
@@ -29,7 +29,6 @@
* Testcase: boundary testing of read(drm_fd)
*/
-#include "igt.h"
#include <unistd.h>
#include <stdlib.h>
#include <stdint.h>
@@ -43,7 +42,9 @@
#include <sys/ioctl.h>
#include <sys/time.h>
#include <sys/poll.h>
-#include "drm.h"
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Call read(drm) and see if it behaves.");
diff --git a/tests/drm_vma_limiter.c b/tests/drm_vma_limiter.c
index fc853f3..d3797e6 100644
--- a/tests/drm_vma_limiter.c
+++ b/tests/drm_vma_limiter.c
@@ -24,7 +24,6 @@
* Daniel Vetter <daniel.vetter@ffwll.ch>
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -33,8 +32,9 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
diff --git a/tests/drm_vma_limiter_cached.c b/tests/drm_vma_limiter_cached.c
index a47c797..9a23c51 100644
--- a/tests/drm_vma_limiter_cached.c
+++ b/tests/drm_vma_limiter_cached.c
@@ -24,7 +24,6 @@
* Daniel Vetter <daniel.vetter@ffwll.ch>
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -33,8 +32,9 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
diff --git a/tests/drm_vma_limiter_cpu.c b/tests/drm_vma_limiter_cpu.c
index 5ea7491..e41ec9c 100644
--- a/tests/drm_vma_limiter_cpu.c
+++ b/tests/drm_vma_limiter_cpu.c
@@ -24,7 +24,6 @@
* Daniel Vetter <daniel.vetter@ffwll.ch>
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -33,8 +32,9 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
diff --git a/tests/drm_vma_limiter_gtt.c b/tests/drm_vma_limiter_gtt.c
index 5202823..210aea8 100644
--- a/tests/drm_vma_limiter_gtt.c
+++ b/tests/drm_vma_limiter_gtt.c
@@ -24,7 +24,6 @@
* Daniel Vetter <daniel.vetter@ffwll.ch>
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -33,8 +32,9 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
diff --git a/tests/drv_getparams_basic.c b/tests/drv_getparams_basic.c
index 7cb210d..7b2d771 100644
--- a/tests/drv_getparams_basic.c
+++ b/tests/drv_getparams_basic.c
@@ -25,12 +25,12 @@
*
*/
-#include "igt.h"
#include <unistd.h>
#include <errno.h>
#include <xf86drm.h>
-#include <i915_drm.h>
-#include "intel_bufmgr.h"
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Tests the export of parameters via DRM_IOCTL_I915_GETPARAM\n");
diff --git a/tests/gem_alive.c b/tests/gem_alive.c
index 7544443..c1e6243 100644
--- a/tests/gem_alive.c
+++ b/tests/gem_alive.c
@@ -1,11 +1,11 @@
-#include "igt.h"
#include <sys/ioctl.h>
#include <fcntl.h>
#include <errno.h>
#include <string.h>
#include <signal.h>
-#include <i915_drm.h>
+#include "igt.h"
+#include "intel_drm_stubs.h"
int main(void)
{
diff --git a/tests/gem_bad_address.c b/tests/gem_bad_address.c
index a970dfa..a42ab29 100644
--- a/tests/gem_bad_address.c
+++ b/tests/gem_bad_address.c
@@ -26,7 +26,6 @@
*
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -35,8 +34,9 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
diff --git a/tests/gem_bad_batch.c b/tests/gem_bad_batch.c
index a11e191..a014608 100644
--- a/tests/gem_bad_batch.c
+++ b/tests/gem_bad_batch.c
@@ -26,7 +26,6 @@
*
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -35,8 +34,9 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
diff --git a/tests/gem_bad_blit.c b/tests/gem_bad_blit.c
index 47e6e90..030aba8 100644
--- a/tests/gem_bad_blit.c
+++ b/tests/gem_bad_blit.c
@@ -41,7 +41,6 @@
* resulted.
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -50,8 +49,9 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
diff --git a/tests/gem_bad_length.c b/tests/gem_bad_length.c
index cca0145..18862b1 100644
--- a/tests/gem_bad_length.c
+++ b/tests/gem_bad_length.c
@@ -35,7 +35,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Test minimal bo_create and batchbuffer exec.");
diff --git a/tests/gem_bad_reloc.c b/tests/gem_bad_reloc.c
index 2351ce9..d76286e 100644
--- a/tests/gem_bad_reloc.c
+++ b/tests/gem_bad_reloc.c
@@ -37,7 +37,7 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Simulates SNA behaviour using negative self-relocations"
" for STATE_BASE_ADDRESS command packets.");
diff --git a/tests/gem_basic.c b/tests/gem_basic.c
index 9f7412f..a15dcb0 100644
--- a/tests/gem_basic.c
+++ b/tests/gem_basic.c
@@ -35,7 +35,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
static void
test_bad_close(int fd)
diff --git a/tests/gem_caching.c b/tests/gem_caching.c
index 2ef364d..decabd8 100644
--- a/tests/gem_caching.c
+++ b/tests/gem_caching.c
@@ -26,7 +26,6 @@
*
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -35,10 +34,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Test snoop consistency when touching partial"
" cachelines.");
diff --git a/tests/gem_close_race.c b/tests/gem_close_race.c
index 1c97076..7fc3c18 100644
--- a/tests/gem_close_race.c
+++ b/tests/gem_close_race.c
@@ -40,7 +40,7 @@
#include <sys/ioctl.h>
#include <sys/time.h>
#include <sys/syscall.h>
-#include "drm.h"
+#include <drm.h>
#define OBJECT_SIZE (256 * 1024)
diff --git a/tests/gem_concurrent_all.c b/tests/gem_concurrent_all.c
index c0af60d..763b1d7 100644
--- a/tests/gem_concurrent_all.c
+++ b/tests/gem_concurrent_all.c
@@ -35,7 +35,6 @@
* Based on gem_gtt_concurrent_blt.
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -46,10 +45,10 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/wait.h>
-
#include <drm.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Test of pread/pwrite/mmap behavior when writing to active"
" buffers.");
diff --git a/tests/gem_cpu_reloc.c b/tests/gem_cpu_reloc.c
index 520030a..56f0af7 100644
--- a/tests/gem_cpu_reloc.c
+++ b/tests/gem_cpu_reloc.c
@@ -45,7 +45,6 @@
* GPU will hang.
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -57,7 +56,8 @@
#include <drm.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Test the relocations through the CPU domain.");
diff --git a/tests/gem_create.c b/tests/gem_create.c
index 25f75d4..3954d20 100644
--- a/tests/gem_create.c
+++ b/tests/gem_create.c
@@ -47,15 +47,15 @@
#include <drm.h>
+
+#include "igt.h"
#include "ioctl_wrappers.h"
-#include "intel_bufmgr.h"
-#include "intel_batchbuffer.h"
+#include "intel_drm_stubs.h"
#include "intel_io.h"
#include "intel_chipset.h"
#include "igt_aux.h"
#include "drmtest.h"
-#include "drm.h"
-#include "i915_drm.h"
+
IGT_TEST_DESCRIPTION("This is a test for the extended & old gem_create ioctl,"
" that includes allocation of object from stolen memory"
diff --git a/tests/gem_ctx_bad_exec.c b/tests/gem_ctx_bad_exec.c
index 5b3577f..6118322 100644
--- a/tests/gem_ctx_bad_exec.c
+++ b/tests/gem_ctx_bad_exec.c
@@ -42,7 +42,8 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/time.h>
-#include "drm.h"
+
+#include <drm.h>
IGT_TEST_DESCRIPTION("Test that context cannot be submitted to unsupported"
" rings.");
diff --git a/tests/gem_ctx_basic.c b/tests/gem_ctx_basic.c
index c18a9ef..5a33f3d 100644
--- a/tests/gem_ctx_basic.c
+++ b/tests/gem_ctx_basic.c
@@ -29,7 +29,6 @@
* This test is useful for finding memory and refcount leaks.
*/
-#include "igt.h"
#include <pthread.h>
#include <stdlib.h>
#include <sys/ioctl.h>
@@ -40,8 +39,11 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
+
IGT_TEST_DESCRIPTION("Basic test for memory and refcount leaks.");
diff --git a/tests/gem_double_irq_loop.c b/tests/gem_double_irq_loop.c
index 71ed3b0..2a75c99 100644
--- a/tests/gem_double_irq_loop.c
+++ b/tests/gem_double_irq_loop.c
@@ -25,7 +25,6 @@
*
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -34,8 +33,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
#include "i830_reg.h"
static drm_intel_bufmgr *bufmgr;
diff --git a/tests/gem_evict_everything.c b/tests/gem_evict_everything.c
index 2e7b33a..9f4b9af 100644
--- a/tests/gem_evict_everything.c
+++ b/tests/gem_evict_everything.c
@@ -42,7 +42,7 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
#include "eviction_common.c"
diff --git a/tests/gem_exec_bad_domains.c b/tests/gem_exec_bad_domains.c
index 1c18461..6421649 100644
--- a/tests/gem_exec_bad_domains.c
+++ b/tests/gem_exec_bad_domains.c
@@ -25,7 +25,6 @@
*
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -34,8 +33,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
/* Testcase: Test whether the kernel rejects relocations with non-gpu domains
*
diff --git a/tests/gem_exec_big.c b/tests/gem_exec_big.c
index 4ea1943..3bab44f 100644
--- a/tests/gem_exec_big.c
+++ b/tests/gem_exec_big.c
@@ -44,7 +44,7 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Run a large nop batch to stress test the error capture"
" code.");
diff --git a/tests/gem_exec_blt.c b/tests/gem_exec_blt.c
index 677708d..1b29ff7 100644
--- a/tests/gem_exec_blt.c
+++ b/tests/gem_exec_blt.c
@@ -37,7 +37,7 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
#define OBJECT_SIZE 16384
diff --git a/tests/gem_exec_faulting_reloc.c b/tests/gem_exec_faulting_reloc.c
index dcd3734..9739bbc 100644
--- a/tests/gem_exec_faulting_reloc.c
+++ b/tests/gem_exec_faulting_reloc.c
@@ -37,7 +37,7 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
/* Testcase: Submit patches with relocations in memory that will fault
*
diff --git a/tests/gem_exec_lut_handle.c b/tests/gem_exec_lut_handle.c
index a1aa694..78531c9 100644
--- a/tests/gem_exec_lut_handle.c
+++ b/tests/gem_exec_lut_handle.c
@@ -36,7 +36,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Exercises the basic execbuffer using the handle LUT"
" interface.");
diff --git a/tests/gem_exec_nop.c b/tests/gem_exec_nop.c
index e90d5eb..4eca246 100644
--- a/tests/gem_exec_nop.c
+++ b/tests/gem_exec_nop.c
@@ -38,7 +38,7 @@
#include <sys/ioctl.h>
#include <sys/time.h>
#include <time.h>
-#include "drm.h"
+#include <drm.h>
#define LOCAL_I915_EXEC_NO_RELOC (1<<11)
#define LOCAL_I915_EXEC_HANDLE_LUT (1<<12)
diff --git a/tests/gem_exec_params.c b/tests/gem_exec_params.c
index e192150..1999a14 100644
--- a/tests/gem_exec_params.c
+++ b/tests/gem_exec_params.c
@@ -37,7 +37,7 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
#define LOCAL_I915_EXEC_VEBOX (4<<0)
diff --git a/tests/gem_fence_thrash.c b/tests/gem_fence_thrash.c
index 52095f2..2aee957 100644
--- a/tests/gem_fence_thrash.c
+++ b/tests/gem_fence_thrash.c
@@ -41,7 +41,7 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <pthread.h>
-#include "drm.h"
+#include <drm.h>
#define OBJECT_SIZE (128*1024) /* restricted to 1MiB alignment on i915 fences */
diff --git a/tests/gem_fence_upload.c b/tests/gem_fence_upload.c
index 7d9acdc..b2f41a8 100644
--- a/tests/gem_fence_upload.c
+++ b/tests/gem_fence_upload.c
@@ -29,7 +29,6 @@
#include "config.h"
#endif
-#include "igt.h"
#include <unistd.h>
#include <stdlib.h>
#include <stdio.h>
@@ -39,8 +38,10 @@
#include <errno.h>
#include <sys/time.h>
#include <pthread.h>
-#include "drm.h"
-#include "i915_drm.h"
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
#define OBJECT_SIZE (1024*1024) /* restricted to 1MiB alignment on i915 fences */
diff --git a/tests/gem_flink_basic.c b/tests/gem_flink_basic.c
index 26ae7d6..2ece2a6 100644
--- a/tests/gem_flink_basic.c
+++ b/tests/gem_flink_basic.c
@@ -34,7 +34,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
static void
test_flink(int fd)
diff --git a/tests/gem_flink_race.c b/tests/gem_flink_race.c
index 30e33f6..44501ef 100644
--- a/tests/gem_flink_race.c
+++ b/tests/gem_flink_race.c
@@ -25,7 +25,6 @@
*/
#define _GNU_SOURCE
-#include "igt.h"
#include <sys/ioctl.h>
#include <stdlib.h>
#include <string.h>
@@ -34,7 +33,8 @@
#include <pthread.h>
#include <errno.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Check for flink/open vs. gem close races.");
diff --git a/tests/gem_gpgpu_fill.c b/tests/gem_gpgpu_fill.c
index df9e86f..a4cc59a 100644
--- a/tests/gem_gpgpu_fill.c
+++ b/tests/gem_gpgpu_fill.c
@@ -30,7 +30,6 @@
* workload for the GPGPU pipeline.
*/
-#include "igt.h"
#include <stdbool.h>
#include <unistd.h>
#include <stdlib.h>
@@ -42,8 +41,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
#define WIDTH 64
#define HEIGHT 64
diff --git a/tests/gem_gtt_cpu_tlb.c b/tests/gem_gtt_cpu_tlb.c
index 8ceef44..77a7802 100644
--- a/tests/gem_gtt_cpu_tlb.c
+++ b/tests/gem_gtt_cpu_tlb.c
@@ -40,7 +40,7 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Check whether gtt tlbs for cpu access are correctly"
" invalidated.");
diff --git a/tests/gem_gtt_speed.c b/tests/gem_gtt_speed.c
index 1b222ca..a6c3767 100644
--- a/tests/gem_gtt_speed.c
+++ b/tests/gem_gtt_speed.c
@@ -38,7 +38,7 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
#define OBJECT_SIZE 16384
diff --git a/tests/gem_hang.c b/tests/gem_hang.c
index f506fc7..274d05d 100644
--- a/tests/gem_hang.c
+++ b/tests/gem_hang.c
@@ -26,7 +26,6 @@
*
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -35,8 +34,9 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
diff --git a/tests/gem_hangcheck_forcewake.c b/tests/gem_hangcheck_forcewake.c
index 16f2167..4a4ae4a 100644
--- a/tests/gem_hangcheck_forcewake.c
+++ b/tests/gem_hangcheck_forcewake.c
@@ -25,7 +25,6 @@
*
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -34,8 +33,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Provoke the hangcheck timer on an otherwise idle"
" system.");
diff --git a/tests/gem_largeobject.c b/tests/gem_largeobject.c
index c001c17..11a74ad 100644
--- a/tests/gem_largeobject.c
+++ b/tests/gem_largeobject.c
@@ -34,7 +34,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
/* Should take 64 pages to store the page pointers on 64 bit */
#define OBJ_SIZE (128 * 1024 * 1024)
diff --git a/tests/gem_lut_handle.c b/tests/gem_lut_handle.c
index 11dc141..1fede03 100644
--- a/tests/gem_lut_handle.c
+++ b/tests/gem_lut_handle.c
@@ -36,7 +36,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Exercises the basic execbuffer using the handle LUT"
" interface.");
diff --git a/tests/gem_madvise.c b/tests/gem_madvise.c
index 36408fe..82d9f4c 100644
--- a/tests/gem_madvise.c
+++ b/tests/gem_madvise.c
@@ -35,8 +35,7 @@
#include <errno.h>
#include <setjmp.h>
#include <signal.h>
-
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Checks that the kernel reports EFAULT when trying to use"
" purged bo.");
diff --git a/tests/gem_media_fill.c b/tests/gem_media_fill.c
index 2c52260..6395732 100644
--- a/tests/gem_media_fill.c
+++ b/tests/gem_media_fill.c
@@ -30,7 +30,6 @@
* workload for the Media pipeline.
*/
-#include "igt.h"
#include <stdbool.h>
#include <unistd.h>
#include <stdlib.h>
@@ -42,8 +41,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Basic test for the media_fill() function, a very simple"
" workload for the Media pipeline.");
diff --git a/tests/gem_mmap.c b/tests/gem_mmap.c
index 2e0d725..00dcf2a 100644
--- a/tests/gem_mmap.c
+++ b/tests/gem_mmap.c
@@ -35,7 +35,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
#define OBJECT_SIZE 16384
#define PAGE_SIZE 4096
diff --git a/tests/gem_mmap_gtt.c b/tests/gem_mmap_gtt.c
index 984ad72..ccb8871 100644
--- a/tests/gem_mmap_gtt.c
+++ b/tests/gem_mmap_gtt.c
@@ -37,7 +37,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
#ifndef PAGE_SIZE
#define PAGE_SIZE 4096
diff --git a/tests/gem_mmap_offset_exhaustion.c b/tests/gem_mmap_offset_exhaustion.c
index 8c8e3fa..f091eec 100644
--- a/tests/gem_mmap_offset_exhaustion.c
+++ b/tests/gem_mmap_offset_exhaustion.c
@@ -35,7 +35,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Checks whether the kernel handles mmap offset exhaustion"
" correctly.");
diff --git a/tests/gem_mmap_wc.c b/tests/gem_mmap_wc.c
index 8ecb9cc..ee9f86d 100644
--- a/tests/gem_mmap_wc.c
+++ b/tests/gem_mmap_wc.c
@@ -37,7 +37,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
struct local_i915_gem_mmap_v2 {
uint32_t handle;
diff --git a/tests/gem_non_secure_batch.c b/tests/gem_non_secure_batch.c
index 5f33991..e411a8e 100644
--- a/tests/gem_non_secure_batch.c
+++ b/tests/gem_non_secure_batch.c
@@ -34,9 +34,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+
#include "i830_reg.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Basic check of non-secure batches.");
diff --git a/tests/gem_partial_pwrite_pread.c b/tests/gem_partial_pwrite_pread.c
index bc63910..f991fd3 100644
--- a/tests/gem_partial_pwrite_pread.c
+++ b/tests/gem_partial_pwrite_pread.c
@@ -34,7 +34,6 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
diff --git a/tests/gem_persistent_relocs.c b/tests/gem_persistent_relocs.c
index 509c812..111629d 100644
--- a/tests/gem_persistent_relocs.c
+++ b/tests/gem_persistent_relocs.c
@@ -37,7 +37,6 @@
#include <sys/time.h>
#include <signal.h>
#include <sys/wait.h>
-
#include <drm.h>
diff --git a/tests/gem_pin.c b/tests/gem_pin.c
index 8da75c5..4f5db9a 100644
--- a/tests/gem_pin.c
+++ b/tests/gem_pin.c
@@ -36,7 +36,6 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
diff --git a/tests/gem_pipe_control_store_loop.c b/tests/gem_pipe_control_store_loop.c
index a155ad1..7dd1e70 100644
--- a/tests/gem_pipe_control_store_loop.c
+++ b/tests/gem_pipe_control_store_loop.c
@@ -31,7 +31,6 @@
* Writes a counter-value into an always newly allocated target bo (by disabling
* buffer reuse). Decently trashes on tlb inconsistencies, too.
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -40,8 +39,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control QW writes.");
diff --git a/tests/gem_ppgtt.c b/tests/gem_ppgtt.c
index eb15ca5..7c9b492 100644
--- a/tests/gem_ppgtt.c
+++ b/tests/gem_ppgtt.c
@@ -21,7 +21,6 @@
* IN THE SOFTWARE.
*/
-#include "igt.h"
#include <stdbool.h>
#include <unistd.h>
#include <stdlib.h>
@@ -33,11 +32,12 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
#include "igt_debugfs.h"
+#include "intel_drm_stubs.h"
+
#define WIDTH 512
#define STRIDE (WIDTH*4)
diff --git a/tests/gem_pread.c b/tests/gem_pread.c
index afa072d..b0f05f7 100644
--- a/tests/gem_pread.c
+++ b/tests/gem_pread.c
@@ -37,7 +37,7 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
#define OBJECT_SIZE 16384
#define LARGE_OBJECT_SIZE 1024 * 1024
diff --git a/tests/gem_pread_after_blit.c b/tests/gem_pread_after_blit.c
index a85bab1..ea828f3 100644
--- a/tests/gem_pread_after_blit.c
+++ b/tests/gem_pread_after_blit.c
@@ -43,7 +43,6 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
diff --git a/tests/gem_pwrite.c b/tests/gem_pwrite.c
index a322f91..f46f5a7 100644
--- a/tests/gem_pwrite.c
+++ b/tests/gem_pwrite.c
@@ -37,7 +37,7 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
#define OBJECT_SIZE 16384
diff --git a/tests/gem_pwrite_pread.c b/tests/gem_pwrite_pread.c
index fe136d3..d5862ae 100644
--- a/tests/gem_pwrite_pread.c
+++ b/tests/gem_pwrite_pread.c
@@ -25,7 +25,6 @@
*
*/
-#include "igt.h"
#include <unistd.h>
#include <stdlib.h>
#include <stdint.h>
@@ -37,8 +36,10 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
#define OBJECT_SIZE 16384
diff --git a/tests/gem_pwrite_snooped.c b/tests/gem_pwrite_snooped.c
index b193395..9a3670e 100644
--- a/tests/gem_pwrite_snooped.c
+++ b/tests/gem_pwrite_snooped.c
@@ -34,7 +34,7 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION(
"pwrite to a snooped bo then make it uncached and check that the GPU sees the data.");
diff --git a/tests/gem_read_read_speed.c b/tests/gem_read_read_speed.c
index c01e4c2..72bcc3f 100644
--- a/tests/gem_read_read_speed.c
+++ b/tests/gem_read_read_speed.c
@@ -26,7 +26,6 @@
* This is a test of performance with multiple readers from the same source.
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -37,10 +36,10 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/wait.h>
-
#include <drm.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Test speed of concurrent reads between engines.");
diff --git a/tests/gem_readwrite.c b/tests/gem_readwrite.c
index f5dd9ab..0b31f02 100644
--- a/tests/gem_readwrite.c
+++ b/tests/gem_readwrite.c
@@ -35,7 +35,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
#define OBJECT_SIZE 16384
diff --git a/tests/gem_reloc_overflow.c b/tests/gem_reloc_overflow.c
index d60bec9..2e8a47e 100644
--- a/tests/gem_reloc_overflow.c
+++ b/tests/gem_reloc_overflow.c
@@ -43,7 +43,7 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/types.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Check that kernel relocation overflows are caught.");
diff --git a/tests/gem_reloc_vs_gpu.c b/tests/gem_reloc_vs_gpu.c
index b11b428..77e709e 100644
--- a/tests/gem_reloc_vs_gpu.c
+++ b/tests/gem_reloc_vs_gpu.c
@@ -37,7 +37,6 @@
#include <sys/time.h>
#include <signal.h>
#include <sys/wait.h>
-
#include <drm.h>
diff --git a/tests/gem_render_copy.c b/tests/gem_render_copy.c
index a036a92..ed236c3 100644
--- a/tests/gem_render_copy.c
+++ b/tests/gem_render_copy.c
@@ -29,7 +29,6 @@
* workload for the 3D engine.
*/
-#include "igt.h"
#include <stdbool.h>
#include <unistd.h>
#include <cairo.h>
@@ -42,10 +41,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Basic test for the render_copy() function.");
diff --git a/tests/gem_render_copy_redux.c b/tests/gem_render_copy_redux.c
index 95d1f97..f9fecd2 100644
--- a/tests/gem_render_copy_redux.c
+++ b/tests/gem_render_copy_redux.c
@@ -32,7 +32,6 @@
* the execbuffer interface with a simple render workload.
*/
-#include "igt.h"
#include <stdbool.h>
#include <unistd.h>
#include <stdlib.h>
@@ -44,10 +43,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Advanced test for the render_copy() function.");
@@ -111,7 +110,7 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf,
static void scratch_buf_fini(data_t *data, struct igt_buf *buf)
{
- dri_bo_unreference(buf->bo);
+ drm_intel_bo_unreference(buf->bo);
memset(buf, 0, sizeof(*buf));
}
diff --git a/tests/gem_render_linear_blits.c b/tests/gem_render_linear_blits.c
index 13f76a5..67413db 100644
--- a/tests/gem_render_linear_blits.c
+++ b/tests/gem_render_linear_blits.c
@@ -37,7 +37,6 @@
#include "config.h"
#endif
-#include "igt.h"
#include <stdlib.h>
#include <sys/ioctl.h>
#include <stdio.h>
@@ -47,10 +46,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
#define WIDTH 512
#define STRIDE (WIDTH*4)
diff --git a/tests/gem_render_tiled_blits.c b/tests/gem_render_tiled_blits.c
index 9f0e588..a5700e3 100644
--- a/tests/gem_render_tiled_blits.c
+++ b/tests/gem_render_tiled_blits.c
@@ -33,7 +33,6 @@
* The goal is to simply ensure the basics work.
*/
-#include "igt.h"
#include <stdlib.h>
#include <sys/ioctl.h>
#include <stdio.h>
@@ -43,10 +42,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
#define WIDTH 512
#define STRIDE (WIDTH*4)
diff --git a/tests/gem_request_retire.c b/tests/gem_request_retire.c
index 545a245..38e5f8e 100644
--- a/tests/gem_request_retire.c
+++ b/tests/gem_request_retire.c
@@ -30,7 +30,6 @@
* Collection of tests targeting request retirement code paths.
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -43,11 +42,10 @@
#include <signal.h>
#include <pthread.h>
#include <time.h>
+#include <drm.h>
-#include "drm.h"
-#include "i915_drm.h"
-
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Collection of tests targeting request retirement code"
" paths.");
diff --git a/tests/gem_seqno_wrap.c b/tests/gem_seqno_wrap.c
index f6320f4..6d2ac92 100644
--- a/tests/gem_seqno_wrap.c
+++ b/tests/gem_seqno_wrap.c
@@ -30,7 +30,6 @@
* boundary.
*/
-#include "igt.h"
#include <stdlib.h>
#include <string.h>
#include <time.h>
@@ -42,7 +41,8 @@
#include <signal.h>
#include <errno.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Runs blitcopy -> rendercopy with multiple buffers over"
" wrap boundary.");
diff --git a/tests/gem_set_tiling_vs_blt.c b/tests/gem_set_tiling_vs_blt.c
index f6cd5b9..2995c05 100644
--- a/tests/gem_set_tiling_vs_blt.c
+++ b/tests/gem_set_tiling_vs_blt.c
@@ -44,7 +44,6 @@
* transitions (i.e. changing stride).
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -54,8 +53,10 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <stdbool.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Check for proper synchronization of tiling changes vs."
" tiled gpu access.");
diff --git a/tests/gem_set_tiling_vs_gtt.c b/tests/gem_set_tiling_vs_gtt.c
index 2611ec5..ae715cf 100644
--- a/tests/gem_set_tiling_vs_gtt.c
+++ b/tests/gem_set_tiling_vs_gtt.c
@@ -35,7 +35,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Check set_tiling vs gtt mmap coherency.");
diff --git a/tests/gem_set_tiling_vs_pwrite.c b/tests/gem_set_tiling_vs_pwrite.c
index 006edfe..7b19b5a 100644
--- a/tests/gem_set_tiling_vs_pwrite.c
+++ b/tests/gem_set_tiling_vs_pwrite.c
@@ -35,7 +35,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Check set_tiling vs pwrite coherency.");
diff --git a/tests/gem_stolen.c b/tests/gem_stolen.c
index 07fdd39..7753b2e 100644
--- a/tests/gem_stolen.c
+++ b/tests/gem_stolen.c
@@ -44,18 +44,16 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <getopt.h>
-
#include <drm.h>
-#include "ioctl_wrappers.h"
-#include "intel_bufmgr.h"
-#include "intel_batchbuffer.h"
+#include "drmtest.h"
+#include "igt.h"
+#include "igt_aux.h"
+#include "intel_drm_stubs.h"
#include "intel_io.h"
#include "intel_chipset.h"
-#include "igt_aux.h"
-#include "drmtest.h"
-#include "drm.h"
-#include "i915_drm.h"
+#include "ioctl_wrappers.h"
+
IGT_TEST_DESCRIPTION("This test verifies the exetended gem_create ioctl,"
" that includes allocation of obj from stolen region");
diff --git a/tests/gem_storedw_batches_loop.c b/tests/gem_storedw_batches_loop.c
index 4b0249a..51dc1e0 100644
--- a/tests/gem_storedw_batches_loop.c
+++ b/tests/gem_storedw_batches_loop.c
@@ -26,7 +26,6 @@
*
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -35,8 +34,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
static drm_intel_bufmgr *bufmgr;
static drm_intel_bo *target_bo;
diff --git a/tests/gem_storedw_loop.c b/tests/gem_storedw_loop.c
index 317b8c6..4490a36 100644
--- a/tests/gem_storedw_loop.c
+++ b/tests/gem_storedw_loop.c
@@ -35,7 +35,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Basic CS check using MI_STORE_DATA_IMM.");
diff --git a/tests/gem_streaming_writes.c b/tests/gem_streaming_writes.c
index 5d0014a..2269b3c 100644
--- a/tests/gem_streaming_writes.c
+++ b/tests/gem_streaming_writes.c
@@ -37,7 +37,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
#define OBJECT_SIZE 1024*1024
#define CHUNK_SIZE 32
diff --git a/tests/gem_stress.c b/tests/gem_stress.c
index 4d0de5c..8efbd43 100644
--- a/tests/gem_stress.c
+++ b/tests/gem_stress.c
@@ -49,7 +49,6 @@
* In short: designed for maximum evilness.
*/
-#include "igt.h"
#include <stdlib.h>
#include <sys/ioctl.h>
#include <stdio.h>
@@ -60,9 +59,8 @@
#include <sys/stat.h>
#include <sys/time.h>
-#include <drm.h>
-
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("General gem coherency test.");
diff --git a/tests/gem_threaded_access_tiled.c b/tests/gem_threaded_access_tiled.c
index 288324d..b959d00 100644
--- a/tests/gem_threaded_access_tiled.c
+++ b/tests/gem_threaded_access_tiled.c
@@ -24,14 +24,14 @@
* Mika Kuoppala <mika.kuoppala@intel.com>
*/
-#include "igt.h"
#include <stdlib.h>
#include <string.h>
#include <fcntl.h>
#include <unistd.h>
#include <pthread.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Check parallel access to tiled memory.");
diff --git a/tests/gem_tiled_blits.c b/tests/gem_tiled_blits.c
index 10e30df..50ece22 100644
--- a/tests/gem_tiled_blits.c
+++ b/tests/gem_tiled_blits.c
@@ -50,7 +50,6 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
diff --git a/tests/gem_tiled_fence_blits.c b/tests/gem_tiled_fence_blits.c
index d4bcf20..ad40c05 100644
--- a/tests/gem_tiled_fence_blits.c
+++ b/tests/gem_tiled_fence_blits.c
@@ -41,7 +41,6 @@
* resulted.
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -50,10 +49,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
diff --git a/tests/gem_tiled_partial_pwrite_pread.c b/tests/gem_tiled_partial_pwrite_pread.c
index fe573c3..46036db 100644
--- a/tests/gem_tiled_partial_pwrite_pread.c
+++ b/tests/gem_tiled_partial_pwrite_pread.c
@@ -34,7 +34,6 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
diff --git a/tests/gem_tiled_pread_basic.c b/tests/gem_tiled_pread_basic.c
index 1dfd87c..780093a 100644
--- a/tests/gem_tiled_pread_basic.c
+++ b/tests/gem_tiled_pread_basic.c
@@ -45,7 +45,7 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Test pread behavior on tiled objects with respect to the"
diff --git a/tests/gem_tiled_pread_pwrite.c b/tests/gem_tiled_pread_pwrite.c
index a1d6ed5..7cf4d6b 100644
--- a/tests/gem_tiled_pread_pwrite.c
+++ b/tests/gem_tiled_pread_pwrite.c
@@ -54,7 +54,6 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/ioctl.h>
-
#include <drm.h>
diff --git a/tests/gem_tiled_swapping.c b/tests/gem_tiled_swapping.c
index b5849bc..772bc66 100644
--- a/tests/gem_tiled_swapping.c
+++ b/tests/gem_tiled_swapping.c
@@ -55,7 +55,6 @@
#include <sys/time.h>
#include <sys/ioctl.h>
#include <pthread.h>
-
#include <drm.h>
diff --git a/tests/gem_tiled_wb.c b/tests/gem_tiled_wb.c
index 67d54bd..803d1f6 100644
--- a/tests/gem_tiled_wb.c
+++ b/tests/gem_tiled_wb.c
@@ -42,7 +42,7 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("This is a test of write-combining mmap's behavior on"
" tiled objects with respect to the reported swizzling"
diff --git a/tests/gem_tiled_wc.c b/tests/gem_tiled_wc.c
index 65ac385..74519c8 100644
--- a/tests/gem_tiled_wc.c
+++ b/tests/gem_tiled_wc.c
@@ -42,7 +42,7 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
#define WIDTH 512
#define HEIGHT 512
diff --git a/tests/gem_tiling_max_stride.c b/tests/gem_tiling_max_stride.c
index a6f97a9..f60a038 100644
--- a/tests/gem_tiling_max_stride.c
+++ b/tests/gem_tiling_max_stride.c
@@ -36,7 +36,7 @@
#include <limits.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Check that max fence stride works.");
diff --git a/tests/gem_unfence_active_buffers.c b/tests/gem_unfence_active_buffers.c
index 6df23cc..227924a 100644
--- a/tests/gem_unfence_active_buffers.c
+++ b/tests/gem_unfence_active_buffers.c
@@ -38,7 +38,6 @@
* problem - the race window is too small.
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -48,8 +47,10 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <stdbool.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Check for use-after-free in the fence stealing code.");
diff --git a/tests/gem_unref_active_buffers.c b/tests/gem_unref_active_buffers.c
index 353b40a..a9a4fa6 100644
--- a/tests/gem_unref_active_buffers.c
+++ b/tests/gem_unref_active_buffers.c
@@ -32,7 +32,6 @@
* will be the last one to hold a reference on them. Usually libdrm bo caching
* prevents that by keeping another reference.
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -41,8 +40,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
+#include <drm.h>
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Test unreferencing of active buffers.");
diff --git a/tests/gem_userptr_blits.c b/tests/gem_userptr_blits.c
index d154657..602f04e 100644
--- a/tests/gem_userptr_blits.c
+++ b/tests/gem_userptr_blits.c
@@ -36,7 +36,6 @@
* The goal is to simply ensure the basics work.
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -49,11 +48,10 @@
#include <signal.h>
#include <pthread.h>
#include <time.h>
+#include <drm.h>
-#include "drm.h"
-#include "i915_drm.h"
-
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
#include "eviction_common.c"
diff --git a/tests/gem_wait.c b/tests/gem_wait.c
index 461efdb..03deb77 100644
--- a/tests/gem_wait.c
+++ b/tests/gem_wait.c
@@ -25,7 +25,6 @@
*
*/
-#include "igt.h"
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
@@ -37,10 +36,10 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
#define MSEC_PER_SEC 1000L
#define USEC_PER_MSEC 1000L
diff --git a/tests/gem_write_read_ring_switch.c b/tests/gem_write_read_ring_switch.c
index d00d4f9..178ca9d 100644
--- a/tests/gem_write_read_ring_switch.c
+++ b/tests/gem_write_read_ring_switch.c
@@ -34,7 +34,6 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-
#include <drm.h>
#include "i830_reg.h"
diff --git a/tests/gen3_mixed_blits.c b/tests/gen3_mixed_blits.c
index dce92b0..31045da 100644
--- a/tests/gen3_mixed_blits.c
+++ b/tests/gen3_mixed_blits.c
@@ -43,7 +43,7 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
#include "i915_reg.h"
diff --git a/tests/gen3_render_linear_blits.c b/tests/gen3_render_linear_blits.c
index e56bff9..0838152 100644
--- a/tests/gen3_render_linear_blits.c
+++ b/tests/gen3_render_linear_blits.c
@@ -42,7 +42,7 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/time.h>
-#include "drm.h"
+#include <drm.h>
#include "i915_reg.h"
diff --git a/tests/gen3_render_mixed_blits.c b/tests/gen3_render_mixed_blits.c
index 6cc8d05..a9fc21e 100644
--- a/tests/gen3_render_mixed_blits.c
+++ b/tests/gen3_render_mixed_blits.c
@@ -43,7 +43,7 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
#include "i915_reg.h"
diff --git a/tests/gen3_render_tiledx_blits.c b/tests/gen3_render_tiledx_blits.c
index 6706d3a..30360b4 100644
--- a/tests/gen3_render_tiledx_blits.c
+++ b/tests/gen3_render_tiledx_blits.c
@@ -43,7 +43,7 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
#include "i915_reg.h"
diff --git a/tests/gen3_render_tiledy_blits.c b/tests/gen3_render_tiledy_blits.c
index 44e88d4..41965a5 100644
--- a/tests/gen3_render_tiledy_blits.c
+++ b/tests/gen3_render_tiledy_blits.c
@@ -43,7 +43,7 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
#include "i915_reg.h"
diff --git a/tests/gen7_forcewake_mt.c b/tests/gen7_forcewake_mt.c
index dea1e8a..5bdb732 100644
--- a/tests/gen7_forcewake_mt.c
+++ b/tests/gen7_forcewake_mt.c
@@ -34,8 +34,7 @@
#include <sys/types.h>
#include <pthread.h>
#include <string.h>
-
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Exercise a suspect workaround required for"
" FORCEWAKE_MT.");
diff --git a/tests/kms_addfb_basic.c b/tests/kms_addfb_basic.c
index 6404730..5b0b69a 100644
--- a/tests/kms_addfb_basic.c
+++ b/tests/kms_addfb_basic.c
@@ -35,7 +35,8 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "drm.h"
+#include <drm.h>
+
#include "drm_fourcc.h"
uint32_t gem_bo;
diff --git a/tests/kms_atomic.c b/tests/kms_atomic.c
index 4fb3cb0..95e0ed9 100644
--- a/tests/kms_atomic.c
+++ b/tests/kms_atomic.c
@@ -39,11 +39,12 @@
#include <errno.h>
#include <xf86drmMode.h>
#include <cairo.h>
-#include "drm.h"
-#include "ioctl_wrappers.h"
+#include <drm.h>
+
#include "drmtest.h"
#include "igt.h"
#include "igt_aux.h"
+#include "ioctl_wrappers.h"
#ifndef DRM_CLIENT_CAP_ATOMIC
#define DRM_CLIENT_CAP_ATOMIC 3
diff --git a/tests/kms_mmap_write_crc.c b/tests/kms_mmap_write_crc.c
index fce0471..51fd308 100644
--- a/tests/kms_mmap_write_crc.c
+++ b/tests/kms_mmap_write_crc.c
@@ -31,11 +31,11 @@
#include <string.h>
#include "drmtest.h"
+#include "igt_aux.h"
#include "igt_debugfs.h"
#include "igt_kms.h"
#include "intel_chipset.h"
#include "ioctl_wrappers.h"
-#include "igt_aux.h"
IGT_TEST_DESCRIPTION(
"Use the display CRC support to validate mmap write to an already uncached future scanout buffer.");
diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
index b18e426..75e4557 100644
--- a/tests/kms_psr_sink_crc.c
+++ b/tests/kms_psr_sink_crc.c
@@ -22,13 +22,13 @@
*
*/
-#include "igt.h"
#include <errno.h>
#include <stdbool.h>
#include <stdio.h>
#include <string.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
bool running_with_psr_disabled;
diff --git a/tests/kms_render.c b/tests/kms_render.c
index 72da87f..ef286de 100644
--- a/tests/kms_render.c
+++ b/tests/kms_render.c
@@ -24,14 +24,14 @@
#include "config.h"
#endif
-#include "igt.h"
#include <cairo.h>
#include <errno.h>
#include <stdint.h>
#include <unistd.h>
#include <sys/time.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
drmModeRes *resources;
int drm_fd;
diff --git a/tests/kms_setmode.c b/tests/kms_setmode.c
index 24fb34c..8544036 100644
--- a/tests/kms_setmode.c
+++ b/tests/kms_setmode.c
@@ -24,7 +24,6 @@
#include "config.h"
#endif
-#include "igt.h"
#include <cairo.h>
#include <errno.h>
#include <stdint.h>
@@ -32,7 +31,8 @@
#include <string.h>
#include <sys/time.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
#define MAX_CONNECTORS 10
#define MAX_CRTCS 3
diff --git a/tests/kms_vblank.c b/tests/kms_vblank.c
index 40ab6fd..0aa400a 100644
--- a/tests/kms_vblank.c
+++ b/tests/kms_vblank.c
@@ -26,7 +26,6 @@
* This is a test of performance of drmWaitVblank.
*/
-#include "igt.h"
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
@@ -37,10 +36,10 @@
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/wait.h>
-
#include <drm.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Test speed of WaitVblank.");
diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
index 03ef2eb..a1dcde2 100644
--- a/tests/pm_rpm.c
+++ b/tests/pm_rpm.c
@@ -40,7 +40,6 @@
#include <sys/stat.h>
#include <linux/i2c.h>
#include <linux/i2c-dev.h>
-
#include <drm.h>
diff --git a/tests/pm_rps.c b/tests/pm_rps.c
index c3d4417..39e1552 100644
--- a/tests/pm_rps.c
+++ b/tests/pm_rps.c
@@ -27,7 +27,6 @@
*/
#define _GNU_SOURCE
-#include "igt.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
@@ -38,7 +37,8 @@
#include <time.h>
#include <sys/wait.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
static int drm_fd;
diff --git a/tests/pm_sseu.c b/tests/pm_sseu.c
index 3e60a5f..cc4962b 100644
--- a/tests/pm_sseu.c
+++ b/tests/pm_sseu.c
@@ -24,14 +24,14 @@
* Jeff McGee <jeff.mcgee@intel.com>
*/
-#include "igt.h"
#include <fcntl.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <time.h>
-#include "i915_drm.h"
-#include "intel_bufmgr.h"
+
+#include "igt.h"
+#include "intel_drm_stubs.h"
IGT_TEST_DESCRIPTION("Tests slice/subslice/EU power gating functionality.\n");
diff --git a/tests/prime_mmap.c b/tests/prime_mmap.c
index 1ea61c2..32e76ef 100644
--- a/tests/prime_mmap.c
+++ b/tests/prime_mmap.c
@@ -40,11 +40,12 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <pthread.h>
+#include <drm.h>
-#include "drm.h"
-#include "i915_drm.h"
#include "drmtest.h"
+#include "igt.h"
#include "igt_debugfs.h"
+#include "intel_drm_stubs.h"
#include "ioctl_wrappers.h"
#define BO_SIZE (16*1024)
diff --git a/tests/prime_nv_api.c b/tests/prime_nv_api.c
index 054a1ec..bb5f6a2 100644
--- a/tests/prime_nv_api.c
+++ b/tests/prime_nv_api.c
@@ -8,14 +8,14 @@
test4 - export handle twice from intel, import into nouveau twice, check handle is the same
*/
-#include "igt.h"
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/stat.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
#include "nouveau.h"
#define BO_SIZE (256*1024)
diff --git a/tests/prime_nv_pcopy.c b/tests/prime_nv_pcopy.c
index b5ceabf..996bed9 100644
--- a/tests/prime_nv_pcopy.c
+++ b/tests/prime_nv_pcopy.c
@@ -14,7 +14,6 @@
*/
-#include "igt.h"
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
@@ -24,7 +23,8 @@
#include <sys/ioctl.h>
#include <errno.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
#include "nouveau.h"
static int intel_fd = -1, nouveau_fd = -1;
diff --git a/tests/prime_nv_test.c b/tests/prime_nv_test.c
index b4714dc..37759a2 100644
--- a/tests/prime_nv_test.c
+++ b/tests/prime_nv_test.c
@@ -14,7 +14,6 @@
*/
-#include "igt.h"
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
@@ -23,7 +22,8 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
#include "nouveau.h"
int intel_fd = -1, nouveau_fd = -1;
diff --git a/tests/prime_self_import.c b/tests/prime_self_import.c
index 992334d..bc92ede 100644
--- a/tests/prime_self_import.c
+++ b/tests/prime_self_import.c
@@ -43,8 +43,7 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <pthread.h>
-
-#include "drm.h"
+#include <drm.h>
IGT_TEST_DESCRIPTION("Check whether prime import/export works on the same"
" device... but with different fds.");
diff --git a/tests/prime_udl.c b/tests/prime_udl.c
index 59f478f..06d75f3 100644
--- a/tests/prime_udl.c
+++ b/tests/prime_udl.c
@@ -14,7 +14,6 @@
*/
-#include "igt.h"
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
@@ -23,11 +22,11 @@
#include <sys/stat.h>
#include <sys/ioctl.h>
#include <errno.h>
-
-#include "xf86drm.h"
+#include <xf86drm.h>
#include <xf86drmMode.h>
-#include "intel_bufmgr.h"
+#include "igt.h"
+#include "intel_drm_stubs.h"
int intel_fd = -1, udl_fd = -1;
drm_intel_bufmgr *bufmgr;
diff --git a/tests/vc4_create_bo.c b/tests/vc4_create_bo.c
index 99d180a..b3ae89b 100644
--- a/tests/vc4_create_bo.c
+++ b/tests/vc4_create_bo.c
@@ -21,8 +21,6 @@
* IN THE SOFTWARE.
*/
-#include "igt.h"
-#include "igt_vc4.h"
#include <unistd.h>
#include <stdlib.h>
#include <stdio.h>
@@ -32,6 +30,9 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
+
+#include "igt.h"
+#include "igt_vc4.h"
#include "vc4_drm.h"
igt_main
diff --git a/tests/vc4_wait_bo.c b/tests/vc4_wait_bo.c
index 65a085a..c372b82 100644
--- a/tests/vc4_wait_bo.c
+++ b/tests/vc4_wait_bo.c
@@ -21,8 +21,6 @@
* IN THE SOFTWARE.
*/
-#include "igt.h"
-#include "igt_vc4.h"
#include <unistd.h>
#include <stdlib.h>
#include <stdio.h>
@@ -32,6 +30,9 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
+
+#include "igt.h"
+#include "igt_vc4.h"
#include "vc4_drm.h"
static void
diff --git a/tests/vc4_wait_seqno.c b/tests/vc4_wait_seqno.c
index bcc263c..689d5a2 100644
--- a/tests/vc4_wait_seqno.c
+++ b/tests/vc4_wait_seqno.c
@@ -21,7 +21,6 @@
* IN THE SOFTWARE.
*/
-#include "igt.h"
#include <unistd.h>
#include <stdlib.h>
#include <stdio.h>
@@ -31,6 +30,8 @@
#include <errno.h>
#include <sys/stat.h>
#include <sys/ioctl.h>
+
+#include "igt.h"
#include "vc4_drm.h"
igt_main
--
2.7.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [RFC i-g-t 1/9] configure.ac: Test for libdrm_intel and build for it if present.
2016-05-20 22:59 ` [RFC i-g-t 1/9] configure.ac: Test for libdrm_intel and build for it if present robert.foss
@ 2016-05-21 7:55 ` Chris Wilson
2016-05-21 13:15 ` Robert Foss
2016-05-23 15:03 ` ?==?utf-8?q? ?==?utf-8?q? [RFC i-g-t 1/9]?==?utf-8?q? " Emil Velikov
0 siblings, 2 replies; 29+ messages in thread
From: Chris Wilson @ 2016-05-21 7:55 UTC (permalink / raw)
To: robert.foss
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On Fri, May 20, 2016 at 06:59:25PM -0400, robert.foss@collabora.com wrote:
> From: Robert Foss <robert.foss@collabora.com>
>
> Test for libdrm_intel and build for it if present.
> Also expose the HAVE_INTEL #define to allow code to be conditionally
> compiled.
>
> Signed-off-by: Robert Foss <robert.foss@collabora.com>
> ---
> configure.ac | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/configure.ac b/configure.ac
> index 0589782..b6fc168 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -100,7 +100,7 @@ if test "x$GCC" = "xyes"; then
> fi
> AC_SUBST(ASSEMBLER_WARN_CFLAGS)
>
> -PKG_CHECK_MODULES(DRM, [libdrm_intel >= 2.4.64 libdrm])
> +PKG_CHECK_MODULES(DRM, [libdrm])
> PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10])
>
> case "$target_cpu" in
> @@ -150,6 +150,18 @@ PKG_CHECK_MODULES(GLIB, glib-2.0)
> # -----------------------------------------------------------------------------
> # Configuration options
> # -----------------------------------------------------------------------------
> +AC_ARG_ENABLE(intel, AS_HELP_STRING([--disable-intel],
> + [Enable building of intel specific parts (default: auto)]),
> + [INTEL=$enableval], [INTEL=auto])
> +if test "x$INTEL" = xauto; then
> + PKG_CHECK_EXISTS([libdrm_intel >= 2.4.64], [INTEL=yes], [INTEL=no])
> +fi
> +if test "x$INTEL" = xyes; then
> + PKG_CHECK_MODULES(DRM_INTEL, [libdrm_intel >= 2.4.64])
> + AC_DEFINE(HAVE_INTEL, 1, [Have intel support])
> +fi
> +AM_CONDITIONAL(HAVE_INTEL, [test "x$INTEL" = xyes])
HAVE_INTEL caused quite a bit of confusion when reading the later build
patches.
Please use HAVE_LIBDRM_INTEL instead
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [RFC i-g-t 1/9] configure.ac: Test for libdrm_intel and build for it if present.
2016-05-21 7:55 ` Chris Wilson
@ 2016-05-21 13:15 ` Robert Foss
2016-05-23 15:03 ` ?==?utf-8?q? ?==?utf-8?q? [RFC i-g-t 1/9]?==?utf-8?q? " Emil Velikov
1 sibling, 0 replies; 29+ messages in thread
From: Robert Foss @ 2016-05-21 13:15 UTC (permalink / raw)
To: Chris Wilson, daniel.vetter, daniel.stone, marius.c.vlad,
tomeu.vizoso, emil.velikov, intel-gfx
On 2016-05-21 03:55 AM, Chris Wilson wrote:
> On Fri, May 20, 2016 at 06:59:25PM -0400, robert.foss@collabora.com wrote:
>> From: Robert Foss <robert.foss@collabora.com>
>>
>> Test for libdrm_intel and build for it if present.
>> Also expose the HAVE_INTEL #define to allow code to be conditionally
>> compiled.
>>
>> Signed-off-by: Robert Foss <robert.foss@collabora.com>
>> ---
>> configure.ac | 14 +++++++++++++-
>> 1 file changed, 13 insertions(+), 1 deletion(-)
>>
>> diff --git a/configure.ac b/configure.ac
>> index 0589782..b6fc168 100644
>> --- a/configure.ac
>> +++ b/configure.ac
>> @@ -100,7 +100,7 @@ if test "x$GCC" = "xyes"; then
>> fi
>> AC_SUBST(ASSEMBLER_WARN_CFLAGS)
>>
>> -PKG_CHECK_MODULES(DRM, [libdrm_intel >= 2.4.64 libdrm])
>> +PKG_CHECK_MODULES(DRM, [libdrm])
>> PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10])
>>
>> case "$target_cpu" in
>> @@ -150,6 +150,18 @@ PKG_CHECK_MODULES(GLIB, glib-2.0)
>> # -----------------------------------------------------------------------------
>> # Configuration options
>> # -----------------------------------------------------------------------------
>> +AC_ARG_ENABLE(intel, AS_HELP_STRING([--disable-intel],
>> + [Enable building of intel specific parts (default: auto)]),
>> + [INTEL=$enableval], [INTEL=auto])
>> +if test "x$INTEL" = xauto; then
>> + PKG_CHECK_EXISTS([libdrm_intel >= 2.4.64], [INTEL=yes], [INTEL=no])
>> +fi
>> +if test "x$INTEL" = xyes; then
>> + PKG_CHECK_MODULES(DRM_INTEL, [libdrm_intel >= 2.4.64])
>> + AC_DEFINE(HAVE_INTEL, 1, [Have intel support])
>> +fi
>> +AM_CONDITIONAL(HAVE_INTEL, [test "x$INTEL" = xyes])
>
> HAVE_INTEL caused quite a bit of confusion when reading the later build
> patches.
>
> Please use HAVE_LIBDRM_INTEL instead
> -Chris
>
That is definitely better, I've added it to v2.
Thanks for the suggestion.
Rob.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: ?==?utf-8?q? [RFC i-g-t 2/9] benchmarks/Makefile: Don't build benchmarks that depend on libdrm_intel.
2016-05-20 22:59 ` [RFC i-g-t 2/9] benchmarks/Makefile: Don't build benchmarks that depend on libdrm_intel robert.foss
@ 2016-05-23 14:04 ` Emil Velikov
2016-05-24 8:01 ` Daniel Vetter
0 siblings, 1 reply; 29+ messages in thread
From: Emil Velikov @ 2016-05-23 14:04 UTC (permalink / raw)
To: robert.foss
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On Friday, May 20, 2016 23:59 BST, robert.foss@collabora.com wrote:
> From: Robert Foss <robert.foss@collabora.com>
>
> Use the HAS_INTEL automake flag to avoid building benchmarks that won't
> compile unless libdrm_intel is available in the build system.
>
> Signed-off-by: Robert Foss <robert.foss@collabora.com>
> ---
> benchmarks/Makefile.sources | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/benchmarks/Makefile.sources b/benchmarks/Makefile.sources
> index 81607a5..26ee3ea 100644
> --- a/benchmarks/Makefile.sources
> +++ b/benchmarks/Makefile.sources
> @@ -1,10 +1,6 @@
> benchmarksdir=$(libexecdir)/intel-gpu-tools/benchmarks
>
> benchmarks_PROGRAMS = \
> - intel_upload_blit_large \
> - intel_upload_blit_large_gtt \
> - intel_upload_blit_large_map \
> - intel_upload_blit_small \
> gem_blt \
> gem_create \
> gem_exec_ctx \
> @@ -16,6 +12,15 @@ benchmarks_PROGRAMS = \
> gem_prw \
> gem_set_domain \
> gem_syslatency \
> - gem_userptr_benchmark \
> kms_vblank \
> $(NULL)
> +
> +if HAVE_INTEL
> + benchmarks_PROGRAMS += \
> + intel_upload_blit_large \
> + intel_upload_blit_large_gtt \
> + intel_upload_blit_large_map \
> + intel_upload_blit_small \
> + gem_userptr_benchmark \
> + $(NULL)
> +endif
Some suggestions:
- Please don't use conditionals in the Makefile.sources - you'll break the other build (Android)
- instead of ^^ use separate variable and combine them in the Makefile.am/Android.mk
- Don't double-indent, don't think any other place does so.
Thanks
Emil
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: ?==?utf-8?q? [RFC i-g-t 3/9] tools/Makefile: Don't build tools that depend on libdrm_intel.
2016-05-20 22:59 ` [RFC i-g-t 3/9] tools/Makefile: Don't build tools " robert.foss
@ 2016-05-23 14:09 ` Emil Velikov
0 siblings, 0 replies; 29+ messages in thread
From: Emil Velikov @ 2016-05-23 14:09 UTC (permalink / raw)
To: robert.foss
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On Friday, May 20, 2016 23:59 BST, robert.foss@collabora.com wrote:
> From: Robert Foss <robert.foss@collabora.com>
>
> Use the HAS_INTEL automake flag to avoid building tools that won't
> compile unless libdrm_intel is available in the build system.
>
> Signed-off-by: Robert Foss <robert.foss@collabora.com>
> ---
> tools/Makefile.sources | 50 +++++++++++++++++++++++++++++---------------------
> 1 file changed, 29 insertions(+), 21 deletions(-)
>
> diff --git a/tools/Makefile.sources b/tools/Makefile.sources
> index 5d5958d..c2dab8e 100644
> --- a/tools/Makefile.sources
> +++ b/tools/Makefile.sources
> @@ -1,42 +1,54 @@
> -noinst_PROGRAMS = \
> - hsw_compute_wrpll \
> - skl_compute_wrpll \
> - skl_ddb_allocation \
> +noinst_PROGRAMS = \
> + hsw_compute_wrpll \
> + skl_compute_wrpll \
> + skl_ddb_allocation \
> $(NULL)
>
> -bin_PROGRAMS = \
> +bin_PROGRAMS = \
> igt_stats \
> - intel_audio_dump \
> + intel_audio_dump \
> intel_reg \
> intel_backlight \
> intel_bios_dumper \
> intel_bios_reader \
> intel_display_crc \
> intel_display_poller \
> - intel_dump_decode \
> - intel_error_decode \
> intel_forcewaked \
> intel_gpu_frequency \
> - intel_framebuffer_dump \
> intel_firmware_decode \
> - intel_gpu_time \
> - intel_gpu_top \
> - intel_gtt \
> + intel_gpu_time \
> + intel_gpu_top \
> + intel_gtt \
> intel_infoframes \
> intel_l3_parity \
> intel_lid \
> intel_opregion_decode \
> intel_panel_fitter \
> - intel_perf_counters \
> - intel_reg_checker \
> + intel_reg_checker \
> intel_residency \
> - intel_stepping \
> + intel_stepping \
Please don't mix functionality and cosmetic changes. Apply the whitespace polish as a separate patch ?
> intel_watermark
>
> dist_bin_SCRIPTS = intel_gpu_abrt
>
> -intel_dump_decode_SOURCES = \
> - intel_dump_decode.c
> +if HAVE_INTEL
> + bin_PROGRAMS += \
> + intel_dump_decode \
> + intel_error_decode \
> + intel_framebuffer_dump \
> + intel_perf_counters \
> + $(NULL)
> +
> + intel_dump_decode_SOURCES = \
> + intel_dump_decode.c \
> + $(NULL)
> +
> + intel_error_decode_SOURCES = \
> + intel_error_decode.c \
> + $(NULL)
> +
> + intel_error_decode_LDFLAGS = -lz
Apart from than my earlier comments, LDFLAGS variables should not live in this file. Please move it to Makefile.am.
Thanks
Emil
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: ?==?utf-8?q? [RFC i-g-t 5/9] tests/gem_ppgtt: Switched to new aliases of intel specific functions.
2016-05-20 22:59 ` [RFC i-g-t 5/9] tests/gem_ppgtt: Switched to new aliases of intel specific functions robert.foss
@ 2016-05-23 14:14 ` Emil Velikov
2016-05-23 14:15 ` Emil Velikov
1 sibling, 0 replies; 29+ messages in thread
From: Emil Velikov @ 2016-05-23 14:14 UTC (permalink / raw)
To: robert.foss
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On Friday, May 20, 2016 23:59 BST, robert.foss@collabora.com wrote:
> From: Robert Foss <robert.foss@collabora.com>
>
> Switched from drm_XXX aliases drm_intel_XXX aliases for symbols where that
> switch is possible.
>
> Signed-off-by: Robert Foss <robert.foss@collabora.com>
> ---
> tests/gem_ppgtt.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
I could swear I've sent a similar looking patch... actually I have it only locally.
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
-Emil
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: ?==?utf-8?q? [RFC i-g-t 5/9] tests/gem_ppgtt: Switched to new aliases of intel specific functions.
2016-05-20 22:59 ` [RFC i-g-t 5/9] tests/gem_ppgtt: Switched to new aliases of intel specific functions robert.foss
2016-05-23 14:14 ` ?==?utf-8?q? " Emil Velikov
@ 2016-05-23 14:15 ` Emil Velikov
2016-05-24 8:03 ` Daniel Vetter
1 sibling, 1 reply; 29+ messages in thread
From: Emil Velikov @ 2016-05-23 14:15 UTC (permalink / raw)
To: robert.foss
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On Friday, May 20, 2016 23:59 BST, robert.foss@collabora.com wrote:
> From: Robert Foss <robert.foss@collabora.com>
>
> Switched from drm_XXX aliases drm_intel_XXX aliases for symbols where that
> switch is possible.
>
> Signed-off-by: Robert Foss <robert.foss@collabora.com>
> ---
> tests/gem_ppgtt.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
-Emil
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: ?==?utf-8?q? [RFC i-g-t 6/9] tests/gem_render_tiled_blits: Switched to new aliases of intel specific functions.
2016-05-20 22:59 ` [RFC i-g-t 6/9] tests/gem_render_tiled_blits: " robert.foss
@ 2016-05-23 14:39 ` Emil Velikov
2016-05-24 8:04 ` Daniel Vetter
0 siblings, 1 reply; 29+ messages in thread
From: Emil Velikov @ 2016-05-23 14:39 UTC (permalink / raw)
To: robert.foss
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On Friday, May 20, 2016 23:59 BST, robert.foss@collabora.com wrote:
> From: Robert Foss <robert.foss@collabora.com>
>
> Switched from drm_XXX aliases drm_intel_XXX aliases for symbols where that
> switch is possible.
>
> Signed-off-by: Robert Foss <robert.foss@collabora.com>
> ---
> tests/gem_render_tiled_blits.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Looks like I've replied to 5/9 twice instead of here :-\
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
-Emil
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: ?==?utf-8?q? [RFC i-g-t 7/9] lib/intel_drm_stubs: Add stubs for functionality from libdrm_intel.
2016-05-20 22:59 ` [RFC i-g-t 7/9] lib/intel_drm_stubs: Add stubs for functionality from libdrm_intel robert.foss
@ 2016-05-23 14:53 ` Emil Velikov
2016-05-24 8:05 ` Daniel Vetter
1 sibling, 0 replies; 29+ messages in thread
From: Emil Velikov @ 2016-05-23 14:53 UTC (permalink / raw)
To: robert.foss
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On Friday, May 20, 2016 23:59 BST, robert.foss@collabora.com wrote:
> --- /dev/null
> +++ b/lib/intel_drm_stubs.c
Since this and the header file are stubs around intel_bufmgr, it might be better to call them intel_bufmgr_stubs.[ch]. In case "_stubs" in the name brings any confusion one could use _implementation/_internal and/or other.
> --- /dev/null
> +++ b/lib/intel_drm_stubs.h
> @@ -0,0 +1,999 @@
> +#ifndef INTEL_DRM_STUBS_H
> +#define INTEL_DRM_STUBS_H
> +
> +#include <xf86drm.h>
> +
> +#include "igt_core.h"
> +
Please don't. There is nothing here that requires either of these includes. As-is this makes the already convoluted header inclusion worse.
> +#ifdef HAVE_INTEL
> +#include <i915_drm.h>
> +#include <intel_bufmgr.h>
> +#include <drm.h>
> +
Similarly, please drop the drm headers. They are provided by libdrm itself (as opposed to libdrm_intel) and thus they should be available everywhere.
> +
> +#else
> +#define i915_execbuffer2_set_context_id(eb2, context) igt_require(false);
> +#define i915_execbuffer2_get_context_id(eb2) igt_require(false);
> +
Do we have (m)any test that don't any intel_bufmgr functionality and/or don't explicitly require intel drm device ? Afaict those will take precedense over the above two execbuf macros, thus one can omit the above.
For the rest of the patch you seems to be inlining i915_drm.h and intel_bufmgr.h which is a very bad idea imho. As-is it's fragile and hard to maintain.
If we drop the i915_drm.h changes, as suggested above, and copy/import the latter header as local_intel_bufmgr.h things will be better imho. It might be worth adding a note in the releasing document to sync the file with the latest libdrm_intel release.
Regards,
Emil
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: ?==?utf-8?q? [RFC i-g-t 8/9] lib: Replace intel specific header includes with intel_drm_stubs.h.
2016-05-20 22:59 ` [RFC i-g-t 8/9] lib: Replace intel specific header includes with intel_drm_stubs.h robert.foss
@ 2016-05-23 14:57 ` Emil Velikov
2016-05-24 8:07 ` Daniel Vetter
1 sibling, 0 replies; 29+ messages in thread
From: Emil Velikov @ 2016-05-23 14:57 UTC (permalink / raw)
To: robert.foss
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On Friday, May 20, 2016 23:59 BST, robert.foss@collabora.com wrote:
> From: Robert Foss <robert.foss@collabora.com>
>
> Replace intel specific header includes with intel_drm_stubs.h.
>
> The stubbed functions will all call igt_require(false) and cause a skip.
>
> Signed-off-by: Robert Foss <robert.foss@collabora.com>
> ---
> lib/drmtest.c | 2 +-
> lib/gpgpu_fill.c | 7 +++----
> lib/igt_aux.c | 2 +-
> lib/igt_aux.h | 3 ++-
> lib/igt_debugfs.c | 4 ++--
> lib/igt_draw.h | 3 +--
> lib/igt_fb.h | 3 ++-
> lib/igt_kms.c | 3 +--
> lib/intel_batchbuffer.c | 4 ----
> lib/intel_batchbuffer.h | 3 +--
> lib/intel_chipset.c | 2 +-
> lib/ioctl_wrappers.c | 1 -
> lib/ioctl_wrappers.h | 4 ++--
> lib/media_fill_gen7.c | 3 +--
> lib/media_fill_gen8.c | 4 +---
> lib/media_fill_gen8lp.c | 6 ++----
> lib/media_fill_gen9.c | 4 +---
> lib/media_spin.c | 2 --
> lib/rendercopy_gen6.c | 5 ++---
> lib/rendercopy_gen7.c | 4 +---
> lib/rendercopy_gen8.c | 4 +---
> lib/rendercopy_gen9.c | 5 +----
> lib/rendercopy_i830.c | 5 +----
> lib/rendercopy_i915.c | 9 +++------
> 24 files changed, 31 insertions(+), 61 deletions(-)
>
This and next patch should be a simple sed job. Untangling the header inclusion(s) is a worthy goal imho, although it's not something that should be mixed in here.
The usual disclaimer... I've got little-to-no say when it comes to IGT so take all the above with a grain (truckload) of salt. That said, I'm fairly confident I haven't gone off the rocker this time and the reasoning is sound ;-)
Thanks
Emil
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: ?==?utf-8?q? ?==?utf-8?q? [RFC i-g-t 1/9]?==?utf-8?q? configure.ac: Test for libdrm_intel and build for it if present.
2016-05-21 7:55 ` Chris Wilson
2016-05-21 13:15 ` Robert Foss
@ 2016-05-23 15:03 ` Emil Velikov
2016-05-24 14:58 ` [RFC i-g-t 1/9] " Robert Foss
1 sibling, 1 reply; 29+ messages in thread
From: Emil Velikov @ 2016-05-23 15:03 UTC (permalink / raw)
To: Chris Wilson
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On Saturday, May 21, 2016 08:55 BST, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Fri, May 20, 2016 at 06:59:25PM -0400, robert.foss@collabora.com wrote:
> > From: Robert Foss <robert.foss@collabora.com>
> >
> > Test for libdrm_intel and build for it if present.
> > Also expose the HAVE_INTEL #define to allow code to be conditionally
> > compiled.
> >
> > Signed-off-by: Robert Foss <robert.foss@collabora.com>
> > ---
> > configure.ac | 14 +++++++++++++-
> > 1 file changed, 13 insertions(+), 1 deletion(-)
> >
> > diff --git a/configure.ac b/configure.ac
> > index 0589782..b6fc168 100644
> > --- a/configure.ac
> > +++ b/configure.ac
> > @@ -100,7 +100,7 @@ if test "x$GCC" = "xyes"; then
> > fi
> > AC_SUBST(ASSEMBLER_WARN_CFLAGS)
> >
> > -PKG_CHECK_MODULES(DRM, [libdrm_intel >= 2.4.64 libdrm])
> > +PKG_CHECK_MODULES(DRM, [libdrm])
> > PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10])
> >
> > case "$target_cpu" in
> > @@ -150,6 +150,18 @@ PKG_CHECK_MODULES(GLIB, glib-2.0)
> > # -----------------------------------------------------------------------------
> > # Configuration options
> > # -----------------------------------------------------------------------------
> > +AC_ARG_ENABLE(intel, AS_HELP_STRING([--disable-intel],
> > + [Enable building of intel specific parts (default: auto)]),
> > + [INTEL=$enableval], [INTEL=auto])
> > +if test "x$INTEL" = xauto; then
> > + PKG_CHECK_EXISTS([libdrm_intel >= 2.4.64], [INTEL=yes], [INTEL=no])
> > +fi
> > +if test "x$INTEL" = xyes; then
> > + PKG_CHECK_MODULES(DRM_INTEL, [libdrm_intel >= 2.4.64])
> > + AC_DEFINE(HAVE_INTEL, 1, [Have intel support])
> > +fi
> > +AM_CONDITIONAL(HAVE_INTEL, [test "x$INTEL" = xyes])
>
> HAVE_INTEL caused quite a bit of confusion when reading the later build
> patches.
>
> Please use HAVE_LIBDRM_INTEL instead
As a counter argument, one could, should really, use --enable-intel to replace the 'x86' parts in commit bccc0ec6a3fdae880e14770c2ff5770fb86ea6fc. Perhaps HAVE_INTEL isn't that bad when we take that into consideration ?
Regards,
Emil
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [RFC i-g-t 2/9] benchmarks/Makefile: Don't build benchmarks that depend on libdrm_intel.
2016-05-23 14:04 ` ?==?utf-8?q? " Emil Velikov
@ 2016-05-24 8:01 ` Daniel Vetter
2016-05-25 17:47 ` Robert Foss
0 siblings, 1 reply; 29+ messages in thread
From: Daniel Vetter @ 2016-05-24 8:01 UTC (permalink / raw)
To: Emil Velikov
Cc: tomeu.vizoso, daniel.stone, daniel.vetter, intel-gfx, emil.velikov
On Mon, May 23, 2016 at 03:04:16PM +0100, Emil Velikov wrote:
> On Friday, May 20, 2016 23:59 BST, robert.foss@collabora.com wrote:
> > From: Robert Foss <robert.foss@collabora.com>
> >
> > Use the HAS_INTEL automake flag to avoid building benchmarks that won't
> > compile unless libdrm_intel is available in the build system.
> >
> > Signed-off-by: Robert Foss <robert.foss@collabora.com>
> > ---
> > benchmarks/Makefile.sources | 15 ++++++++++-----
> > 1 file changed, 10 insertions(+), 5 deletions(-)
> >
> > diff --git a/benchmarks/Makefile.sources b/benchmarks/Makefile.sources
> > index 81607a5..26ee3ea 100644
> > --- a/benchmarks/Makefile.sources
> > +++ b/benchmarks/Makefile.sources
> > @@ -1,10 +1,6 @@
> > benchmarksdir=$(libexecdir)/intel-gpu-tools/benchmarks
> >
> > benchmarks_PROGRAMS = \
> > - intel_upload_blit_large \
> > - intel_upload_blit_large_gtt \
> > - intel_upload_blit_large_map \
> > - intel_upload_blit_small \
> > gem_blt \
> > gem_create \
> > gem_exec_ctx \
> > @@ -16,6 +12,15 @@ benchmarks_PROGRAMS = \
> > gem_prw \
> > gem_set_domain \
> > gem_syslatency \
> > - gem_userptr_benchmark \
> > kms_vblank \
> > $(NULL)
> > +
> > +if HAVE_INTEL
> > + benchmarks_PROGRAMS += \
> > + intel_upload_blit_large \
> > + intel_upload_blit_large_gtt \
> > + intel_upload_blit_large_map \
> > + intel_upload_blit_small \
> > + gem_userptr_benchmark \
> > + $(NULL)
> > +endif
> Some suggestions:
> - Please don't use conditionals in the Makefile.sources - you'll break the other build (Android)
> - instead of ^^ use separate variable and combine them in the Makefile.am/Android.mk
> - Don't double-indent, don't think any other place does so.
Atm the other build is Intel-only, so I don't think it's that bad really -
if we add a #define HAVE_INTEL there before including Makefile.sources (or
whatever the make magic for this is). If someone wants to build igt on
other Android machines that needs some extensions, but hey not my problem
when Android wants to reinvent half of autoconf ;-)
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [RFC i-g-t 5/9] tests/gem_ppgtt: Switched to new aliases of intel specific functions.
2016-05-23 14:15 ` Emil Velikov
@ 2016-05-24 8:03 ` Daniel Vetter
0 siblings, 0 replies; 29+ messages in thread
From: Daniel Vetter @ 2016-05-24 8:03 UTC (permalink / raw)
To: Emil Velikov
Cc: tomeu.vizoso, daniel.stone, daniel.vetter, intel-gfx, emil.velikov
On Mon, May 23, 2016 at 03:15:26PM +0100, Emil Velikov wrote:
> On Friday, May 20, 2016 23:59 BST, robert.foss@collabora.com wrote:
> > From: Robert Foss <robert.foss@collabora.com>
> >
> > Switched from drm_XXX aliases drm_intel_XXX aliases for symbols where that
> > switch is possible.
> >
> > Signed-off-by: Robert Foss <robert.foss@collabora.com>
> > ---
> > tests/gem_ppgtt.c | 18 +++++++++---------
> > 1 file changed, 9 insertions(+), 9 deletions(-)
> >
> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Applied, thanks.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [RFC i-g-t 6/9] tests/gem_render_tiled_blits: Switched to new aliases of intel specific functions.
2016-05-23 14:39 ` ?==?utf-8?q? " Emil Velikov
@ 2016-05-24 8:04 ` Daniel Vetter
0 siblings, 0 replies; 29+ messages in thread
From: Daniel Vetter @ 2016-05-24 8:04 UTC (permalink / raw)
To: Emil Velikov
Cc: tomeu.vizoso, daniel.stone, daniel.vetter, intel-gfx, emil.velikov
On Mon, May 23, 2016 at 03:39:12PM +0100, Emil Velikov wrote:
> On Friday, May 20, 2016 23:59 BST, robert.foss@collabora.com wrote:
> > From: Robert Foss <robert.foss@collabora.com>
> >
> > Switched from drm_XXX aliases drm_intel_XXX aliases for symbols where that
> > switch is possible.
> >
> > Signed-off-by: Robert Foss <robert.foss@collabora.com>
> > ---
> > tests/gem_render_tiled_blits.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> Looks like I've replied to 5/9 twice instead of here :-\
>
> Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Also applied, thanks.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [RFC i-g-t 7/9] lib/intel_drm_stubs: Add stubs for functionality from libdrm_intel.
2016-05-20 22:59 ` [RFC i-g-t 7/9] lib/intel_drm_stubs: Add stubs for functionality from libdrm_intel robert.foss
2016-05-23 14:53 ` ?==?utf-8?q? " Emil Velikov
@ 2016-05-24 8:05 ` Daniel Vetter
2016-05-25 17:48 ` Robert Foss
1 sibling, 1 reply; 29+ messages in thread
From: Daniel Vetter @ 2016-05-24 8:05 UTC (permalink / raw)
To: robert.foss
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On Fri, May 20, 2016 at 06:59:31PM -0400, robert.foss@collabora.com wrote:
> From: Robert Foss <robert.foss@collabora.com>
>
> This patch provides stubs for functionality otherwise provided by libdrm_intel.
>
> The stubbed functions all fail with a call to igt_require(false).
> Defines and enums have been copied from libdrm_intel.
For prettiness mayb igt_require_f(false, "Not compiled with libdrm_intel
support\n"); or something similar.
-Daniel
>
> Due to the stubbed tests failing with an igt_require() call, these stubs are
> not well suited for non-tests, since tools/benchmarks/etc 'skipping'
> execution is unhelpful.
>
> Signed-off-by: Robert Foss <robert.foss@collabora.com>
> ---
> lib/Makefile.sources | 2 +
> lib/intel_drm_stubs.c | 258 +++++++++++++
> lib/intel_drm_stubs.h | 999 ++++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1259 insertions(+)
> create mode 100644 lib/intel_drm_stubs.c
> create mode 100644 lib/intel_drm_stubs.h
>
> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
> index 1316fd2..c0f9f6d 100644
> --- a/lib/Makefile.sources
> +++ b/lib/Makefile.sources
> @@ -21,6 +21,8 @@ libintel_tools_la_SOURCES = \
> intel_batchbuffer.c \
> intel_batchbuffer.h \
> intel_chipset.h \
> + intel_drm_stubs.c \
> + intel_drm_stubs.h \
> intel_os.c \
> intel_io.h \
> intel_mmio.c \
> diff --git a/lib/intel_drm_stubs.c b/lib/intel_drm_stubs.c
> new file mode 100644
> index 0000000..d46a9b3
> --- /dev/null
> +++ b/lib/intel_drm_stubs.c
> @@ -0,0 +1,258 @@
> +#ifndef HAVE_INTEL
> +
> +#include "intel_drm_stubs.h"
> +
> +drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size)
> +{
> + igt_require(false);
> + return (drm_intel_bufmgr *) NULL;
> +}
> +
> +void drm_intel_bo_unreference(drm_intel_bo *bo)
> +{
> + igt_require(false);
> +}
> +
> +drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
> + unsigned long size, unsigned int alignment)
> +{
> + igt_require(false);
> + return (drm_intel_bo *) NULL;
> +}
> +
> +int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
> + unsigned long size, const void *data)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
> + int used, unsigned int flags)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
> + drm_intel_bo *target_bo, uint32_t target_offset,
> + uint32_t read_domains, uint32_t write_domain)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
> + drm_intel_bo *target_bo,
> + uint32_t target_offset,
> + uint32_t read_domains, uint32_t write_domain)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
> + uint32_t * swizzle_mode)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
> + struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
> + unsigned int flags)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +void drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
> + drm_intel_aub_annotation *annotations,
> + unsigned count)
> +{
> + igt_require(false);
> +}
> +
> +void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
> +{
> + igt_require(false);
> +}
> +
> +int drm_intel_bo_exec(drm_intel_bo *bo, int used,
> + struct drm_clip_rect *cliprects, int num_cliprects, int DR4)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
> +{
> + igt_require(false);
> +}
> +
> +void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
> +{
> + igt_require(false);
> +}
> +
> +int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
> + unsigned long size, void *data)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +int drm_intel_bo_map(drm_intel_bo *bo, int write_enable)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
> +{
> + igt_require(false);
> +}
> +
> +int drm_intel_bo_unmap(drm_intel_bo *bo)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
> + const char *name,
> + unsigned int handle)
> +{
> + igt_require(false);
> + return (drm_intel_bo *) NULL;
> +}
> +
> +int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
> + int prime_fd, int size)
> +{
> + igt_require(false);
> + return (drm_intel_bo *) NULL;
> +}
> +
> +void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
> + int limit)
> +{
> + igt_require(false);
> +}
> +
> +int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
> +{
> + igt_require(false);
> + return (drm_intel_bo *) NULL;
> +}
> +
> +void drm_intel_gem_context_destroy(drm_intel_context *ctx)
> +{
> + igt_require(false);
> +}
> +
> +drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
> + const char *name,
> + int x, int y, int cpp,
> + uint32_t *tiling_mode,
> + unsigned long *pitch,
> + unsigned long flags)
> +{
> + igt_require(false);
> + return (drm_intel_bo *) NULL;
> +}
> +
> +void drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
> + const char *filename)
> +{
> + igt_require(false);
> +}
> +
> +void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
> +{
> + igt_require(false);
> +}
> +
> +void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
> + int x1, int y1, int width, int height,
> + enum aub_dump_bmp_format format,
> + int pitch, int offset)
> +{
> + igt_require(false);
> +}
> +
> +void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
> +{
> + igt_require(false);
> +}
> +
> +int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
> + uint32_t stride)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +void drm_intel_bo_reference(drm_intel_bo *bo)
> +{
> + igt_require(false);
> +}
> +
> +int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
> + const char *name,
> + unsigned long size,
> + unsigned int alignment)
> +{
> + igt_require(false);
> + return (drm_intel_bo *) NULL;
> +}
> +
> +int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
> +{
> + igt_require(false);
> + return 0;
> +}
> +
> +#endif//HAVE_INTEL
> diff --git a/lib/intel_drm_stubs.h b/lib/intel_drm_stubs.h
> new file mode 100644
> index 0000000..fdfaaeb
> --- /dev/null
> +++ b/lib/intel_drm_stubs.h
> @@ -0,0 +1,999 @@
> +#ifndef INTEL_DRM_STUBS_H
> +#define INTEL_DRM_STUBS_H
> +
> +#include <xf86drm.h>
> +
> +#include "igt_core.h"
> +
> +#ifdef HAVE_INTEL
> +#include <i915_drm.h>
> +#include <intel_bufmgr.h>
> +#include <drm.h>
> +
> +
> +#else
> +#define i915_execbuffer2_set_context_id(eb2, context) igt_require(false);
> +#define i915_execbuffer2_get_context_id(eb2) igt_require(false);
> +
> +#define I915_EXEC_GEN7_SOL_RESET (1<<8)
> +#define I915_EXEC_SECURE (1<<9)
> +#define I915_EXEC_IS_PINNED (1<<10)
> +#define I915_EXEC_NO_RELOC (1<<11)
> +#define I915_EXEC_HANDLE_LUT (1<<12)
> +#define I915_EXEC_BSD_MASK (3<<13)
> +#define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */
> +#define I915_EXEC_BSD_RING1 (1<<13)
> +#define I915_EXEC_BSD_RING2 (2<<13)
> +
> +#define I915_MADV_WILLNEED 0
> +#define I915_MADV_DONTNEED 1
> +
> +#define I915_TILING_NONE 0
> +#define I915_TILING_X 1
> +#define I915_TILING_Y 2
> +
> +#define I915_CACHING_NONE 0
> +#define I915_CACHING_CACHED 1
> +#define I915_CACHING_DISPLAY 2
> +
> +#define I915_BIT_6_SWIZZLE_NONE 0
> +#define I915_BIT_6_SWIZZLE_9 1
> +#define I915_BIT_6_SWIZZLE_9_10 2
> +#define I915_BIT_6_SWIZZLE_9_11 3
> +#define I915_BIT_6_SWIZZLE_9_10_11 4
> +#define I915_BIT_6_SWIZZLE_UNKNOWN 5
> +#define I915_BIT_6_SWIZZLE_9_17 6
> +#define I915_BIT_6_SWIZZLE_9_10_17 7
> +
> +#define I915_PARAM_CHIPSET_ID 4
> +
> +#define I915_PARAM_IRQ_ACTIVE 1
> +#define I915_PARAM_ALLOW_BATCHBUFFER 2
> +#define I915_PARAM_LAST_DISPATCH 3
> +#define I915_PARAM_CHIPSET_ID 4
> +#define I915_PARAM_HAS_GEM 5
> +#define I915_PARAM_NUM_FENCES_AVAIL 6
> +#define I915_PARAM_HAS_OVERLAY 7
> +#define I915_PARAM_HAS_PAGEFLIPPING 8
> +#define I915_PARAM_HAS_EXECBUF2 9
> +#define I915_PARAM_HAS_BSD 10
> +#define I915_PARAM_HAS_BLT 11
> +#define I915_PARAM_HAS_RELAXED_FENCING 12
> +#define I915_PARAM_HAS_COHERENT_RINGS 13
> +#define I915_PARAM_HAS_EXEC_CONSTANTS 14
> +#define I915_PARAM_HAS_RELAXED_DELTA 15
> +#define I915_PARAM_HAS_GEN7_SOL_RESET 16
> +#define I915_PARAM_HAS_LLC 17
> +#define I915_PARAM_HAS_ALIASING_PPGTT 18
> +#define I915_PARAM_HAS_WAIT_TIMEOUT 19
> +#define I915_PARAM_HAS_SEMAPHORES 20
> +#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
> +#define I915_PARAM_HAS_VEBOX 22
> +#define I915_PARAM_HAS_SECURE_BATCHES 23
> +#define I915_PARAM_HAS_PINNED_BATCHES 24
> +#define I915_PARAM_HAS_EXEC_NO_RELOC 25
> +#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
> +#define I915_PARAM_HAS_WT 27
> +#define I915_PARAM_CMD_PARSER_VERSION 28
> +#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
> +#define I915_PARAM_MMAP_VERSION 30
> +#define I915_PARAM_HAS_BSD2 31
> +#define I915_PARAM_REVISION 32
> +#define I915_PARAM_SUBSLICE_TOTAL 33
> +#define I915_PARAM_EU_TOTAL 34
> +#define I915_PARAM_HAS_GPU_RESET 35
> +#define I915_PARAM_HAS_RESOURCE_STREAMER 36
> +#define I915_PARAM_HAS_EXEC_SOFTPIN 37
> +
> +#define I915_GEM_DOMAIN_CPU 0x00000001
> +#define I915_GEM_DOMAIN_RENDER 0x00000002
> +#define I915_GEM_DOMAIN_SAMPLER 0x00000004
> +#define I915_GEM_DOMAIN_COMMAND 0x00000008
> +#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
> +#define I915_GEM_DOMAIN_VERTEX 0x00000020
> +#define I915_GEM_DOMAIN_GTT 0x00000040
> +
> +#define DRM_I915_INIT 0x00
> +#define DRM_I915_FLUSH 0x01
> +#define DRM_I915_FLIP 0x02
> +#define DRM_I915_BATCHBUFFER 0x03
> +#define DRM_I915_IRQ_EMIT 0x04
> +#define DRM_I915_IRQ_WAIT 0x05
> +#define DRM_I915_GETPARAM 0x06
> +#define DRM_I915_SETPARAM 0x07
> +#define DRM_I915_ALLOC 0x08
> +#define DRM_I915_FREE 0x09
> +#define DRM_I915_INIT_HEAP 0x0a
> +#define DRM_I915_CMDBUFFER 0x0b
> +#define DRM_I915_DESTROY_HEAP 0x0c
> +#define DRM_I915_SET_VBLANK_PIPE 0x0d
> +#define DRM_I915_GET_VBLANK_PIPE 0x0e
> +#define DRM_I915_VBLANK_SWAP 0x0f
> +#define DRM_I915_HWS_ADDR 0x11
> +#define DRM_I915_GEM_INIT 0x13
> +#define DRM_I915_GEM_EXECBUFFER 0x14
> +#define DRM_I915_GEM_PIN 0x15
> +#define DRM_I915_GEM_UNPIN 0x16
> +#define DRM_I915_GEM_BUSY 0x17
> +#define DRM_I915_GEM_THROTTLE 0x18
> +#define DRM_I915_GEM_ENTERVT 0x19
> +#define DRM_I915_GEM_LEAVEVT 0x1a
> +#define DRM_I915_GEM_CREATE 0x1b
> +#define DRM_I915_GEM_PREAD 0x1c
> +#define DRM_I915_GEM_PWRITE 0x1d
> +#define DRM_I915_GEM_MMAP 0x1e
> +#define DRM_I915_GEM_SET_DOMAIN 0x1f
> +#define DRM_I915_GEM_SW_FINISH 0x20
> +#define DRM_I915_GEM_SET_TILING 0x21
> +#define DRM_I915_GEM_GET_TILING 0x22
> +#define DRM_I915_GEM_GET_APERTURE 0x23
> +#define DRM_I915_GEM_MMAP_GTT 0x24
> +#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
> +#define DRM_I915_GEM_MADVISE 0x26
> +#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
> +#define DRM_I915_OVERLAY_ATTRS 0x28
> +#define DRM_I915_GEM_EXECBUFFER2 0x29
> +#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
> +#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
> +#define DRM_I915_GEM_WAIT 0x2c
> +#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
> +#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
> +#define DRM_I915_GEM_SET_CACHING 0x2f
> +#define DRM_I915_GEM_GET_CACHING 0x30
> +#define DRM_I915_REG_READ 0x31
> +#define DRM_I915_GET_RESET_STATS 0x32
> +#define DRM_I915_GEM_USERPTR 0x33
> +#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
> +#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
> +
> +#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
> +#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
> +#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
> +#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
> +#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
> +#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
> +#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
> +#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
> +#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
> +#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
> +#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
> +#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
> +#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
> +#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
> +#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
> +#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
> +#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
> +#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
> +#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
> +#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
> +#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
> +#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
> +#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
> +#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
> +#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
> +#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
> +#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
> +#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
> +#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
> +#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
> +#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
> +#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
> +#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
> +#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
> +#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
> +#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
> +#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
> +#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
> +#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
> +#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
> +#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
> +#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
> +#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
> +#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
> +#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
> +#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
> +#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
> +#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
> +#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
> +#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
> +#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
> +#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
> +
> +enum aub_dump_bmp_format {
> + AUB_DUMP_BMP_FORMAT_8BIT = 1,
> + AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4,
> + AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6,
> + AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7,
> +};
> +
> +typedef struct _drm_intel_bo drm_intel_bo;
> +typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
> +typedef struct _drm_intel_context drm_intel_context;
> +
> +struct _drm_intel_context {
> + unsigned int ctx_id;
> + struct _drm_intel_bufmgr *bufmgr;
> +};
> +
> +struct _drm_intel_bufmgr {
> + /**
> + * Allocate a buffer object.
> + *
> + * Buffer objects are not necessarily initially mapped into CPU virtual
> + * address space or graphics device aperture. They must be mapped
> + * using bo_map() or drm_intel_gem_bo_map_gtt() to be used by the CPU.
> + */
> + drm_intel_bo *(*bo_alloc) (drm_intel_bufmgr *bufmgr, const char *name,
> + unsigned long size, unsigned int alignment);
> +
> + /**
> + * Allocate a buffer object, hinting that it will be used as a
> + * render target.
> + *
> + * This is otherwise the same as bo_alloc.
> + */
> + drm_intel_bo *(*bo_alloc_for_render) (drm_intel_bufmgr *bufmgr,
> + const char *name,
> + unsigned long size,
> + unsigned int alignment);
> +
> + /**
> + * Allocate a buffer object from an existing user accessible
> + * address malloc'd with the provided size.
> + * Alignment is used when mapping to the gtt.
> + * Flags may be I915_VMAP_READ_ONLY or I915_USERPTR_UNSYNCHRONIZED
> + */
> + drm_intel_bo *(*bo_alloc_userptr)(drm_intel_bufmgr *bufmgr,
> + const char *name, void *addr,
> + uint32_t tiling_mode, uint32_t stride,
> + unsigned long size,
> + unsigned long flags);
> +
> + /**
> + * Allocate a tiled buffer object.
> + *
> + * Alignment for tiled objects is set automatically; the 'flags'
> + * argument provides a hint about how the object will be used initially.
> + *
> + * Valid tiling formats are:
> + * I915_TILING_NONE
> + * I915_TILING_X
> + * I915_TILING_Y
> + *
> + * Note the tiling format may be rejected; callers should check the
> + * 'tiling_mode' field on return, as well as the pitch value, which
> + * may have been rounded up to accommodate for tiling restrictions.
> + */
> + drm_intel_bo *(*bo_alloc_tiled) (drm_intel_bufmgr *bufmgr,
> + const char *name,
> + int x, int y, int cpp,
> + uint32_t *tiling_mode,
> + unsigned long *pitch,
> + unsigned long flags);
> +
> + /** Takes a reference on a buffer object */
> + void (*bo_reference) (drm_intel_bo *bo);
> +
> + /**
> + * Releases a reference on a buffer object, freeing the data if
> + * no references remain.
> + */
> + void (*bo_unreference) (drm_intel_bo *bo);
> +
> + /**
> + * Maps the buffer into userspace.
> + *
> + * This function will block waiting for any existing execution on the
> + * buffer to complete, first. The resulting mapping is available at
> + * buf->virtual.
> + */
> + int (*bo_map) (drm_intel_bo *bo, int write_enable);
> +
> + /**
> + * Reduces the refcount on the userspace mapping of the buffer
> + * object.
> + */
> + int (*bo_unmap) (drm_intel_bo *bo);
> +
> + /**
> + * Write data into an object.
> + *
> + * This is an optional function, if missing,
> + * drm_intel_bo will map/memcpy/unmap.
> + */
> + int (*bo_subdata) (drm_intel_bo *bo, unsigned long offset,
> + unsigned long size, const void *data);
> +
> + /**
> + * Read data from an object
> + *
> + * This is an optional function, if missing,
> + * drm_intel_bo will map/memcpy/unmap.
> + */
> + int (*bo_get_subdata) (drm_intel_bo *bo, unsigned long offset,
> + unsigned long size, void *data);
> +
> + /**
> + * Waits for rendering to an object by the GPU to have completed.
> + *
> + * This is not required for any access to the BO by bo_map,
> + * bo_subdata, etc. It is merely a way for the driver to implement
> + * glFinish.
> + */
> + void (*bo_wait_rendering) (drm_intel_bo *bo);
> +
> + /**
> + * Tears down the buffer manager instance.
> + */
> + void (*destroy) (drm_intel_bufmgr *bufmgr);
> +
> + /**
> + * Indicate if the buffer can be placed anywhere in the full ppgtt
> + * address range (2^48).
> + *
> + * Any resource used with flat/heapless (0x00000000-0xfffff000)
> + * General State Heap (GSH) or Intructions State Heap (ISH) must
> + * be in a 32-bit range. 48-bit range will only be used when explicitly
> + * requested.
> + *
> + * \param bo Buffer to set the use_48b_address_range flag.
> + * \param enable The flag value.
> + */
> + void (*bo_use_48b_address_range) (drm_intel_bo *bo, uint32_t enable);
> +
> + /**
> + * Add relocation entry in reloc_buf, which will be updated with the
> + * target buffer's real offset on on command submission.
> + *
> + * Relocations remain in place for the lifetime of the buffer object.
> + *
> + * \param bo Buffer to write the relocation into.
> + * \param offset Byte offset within reloc_bo of the pointer to
> + * target_bo.
> + * \param target_bo Buffer whose offset should be written into the
> + * relocation entry.
> + * \param target_offset Constant value to be added to target_bo's
> + * offset in relocation entry.
> + * \param read_domains GEM read domains which the buffer will be
> + * read into by the command that this relocation
> + * is part of.
> + * \param write_domains GEM read domains which the buffer will be
> + * dirtied in by the command that this
> + * relocation is part of.
> + */
> + int (*bo_emit_reloc) (drm_intel_bo *bo, uint32_t offset,
> + drm_intel_bo *target_bo, uint32_t target_offset,
> + uint32_t read_domains, uint32_t write_domain);
> + int (*bo_emit_reloc_fence)(drm_intel_bo *bo, uint32_t offset,
> + drm_intel_bo *target_bo,
> + uint32_t target_offset,
> + uint32_t read_domains,
> + uint32_t write_domain);
> +
> + /** Executes the command buffer pointed to by bo. */
> + int (*bo_exec) (drm_intel_bo *bo, int used,
> + drm_clip_rect_t *cliprects, int num_cliprects,
> + int DR4);
> +
> + /** Executes the command buffer pointed to by bo on the selected
> + * ring buffer
> + */
> + int (*bo_mrb_exec) (drm_intel_bo *bo, int used,
> + drm_clip_rect_t *cliprects, int num_cliprects,
> + int DR4, unsigned flags);
> +
> + /**
> + * Pin a buffer to the aperture and fix the offset until unpinned
> + *
> + * \param buf Buffer to pin
> + * \param alignment Required alignment for aperture, in bytes
> + */
> + int (*bo_pin) (drm_intel_bo *bo, uint32_t alignment);
> +
> + /**
> + * Unpin a buffer from the aperture, allowing it to be removed
> + *
> + * \param buf Buffer to unpin
> + */
> + int (*bo_unpin) (drm_intel_bo *bo);
> +
> + /**
> + * Ask that the buffer be placed in tiling mode
> + *
> + * \param buf Buffer to set tiling mode for
> + * \param tiling_mode desired, and returned tiling mode
> + */
> + int (*bo_set_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode,
> + uint32_t stride);
> +
> + /**
> + * Get the current tiling (and resulting swizzling) mode for the bo.
> + *
> + * \param buf Buffer to get tiling mode for
> + * \param tiling_mode returned tiling mode
> + * \param swizzle_mode returned swizzling mode
> + */
> + int (*bo_get_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode,
> + uint32_t * swizzle_mode);
> +
> + /**
> + * Set the offset at which this buffer will be softpinned
> + * \param bo Buffer to set the softpin offset for
> + * \param offset Softpin offset
> + */
> + int (*bo_set_softpin_offset) (drm_intel_bo *bo, uint64_t offset);
> +
> + /**
> + * Create a visible name for a buffer which can be used by other apps
> + *
> + * \param buf Buffer to create a name for
> + * \param name Returned name
> + */
> + int (*bo_flink) (drm_intel_bo *bo, uint32_t * name);
> +
> + /**
> + * Returns 1 if mapping the buffer for write could cause the process
> + * to block, due to the object being active in the GPU.
> + */
> + int (*bo_busy) (drm_intel_bo *bo);
> +
> + /**
> + * Specify the volatility of the buffer.
> + * \param bo Buffer to create a name for
> + * \param madv The purgeable status
> + *
> + * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
> + * reclaimed under memory pressure. If you subsequently require the buffer,
> + * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
> + *
> + * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
> + * marked as I915_MADV_DONTNEED.
> + */
> + int (*bo_madvise) (drm_intel_bo *bo, int madv);
> +
> + int (*check_aperture_space) (drm_intel_bo ** bo_array, int count);
> +
> + /**
> + * Disable buffer reuse for buffers which will be shared in some way,
> + * as with scanout buffers. When the buffer reference count goes to
> + * zero, it will be freed and not placed in the reuse list.
> + *
> + * \param bo Buffer to disable reuse for
> + */
> + int (*bo_disable_reuse) (drm_intel_bo *bo);
> +
> + /**
> + * Query whether a buffer is reusable.
> + *
> + * \param bo Buffer to query
> + */
> + int (*bo_is_reusable) (drm_intel_bo *bo);
> +
> + /**
> + *
> + * Return the pipe associated with a crtc_id so that vblank
> + * synchronization can use the correct data in the request.
> + * This is only supported for KMS and gem at this point, when
> + * unsupported, this function returns -1 and leaves the decision
> + * of what to do in that case to the caller
> + *
> + * \param bufmgr the associated buffer manager
> + * \param crtc_id the crtc identifier
> + */
> + int (*get_pipe_from_crtc_id) (drm_intel_bufmgr *bufmgr, int crtc_id);
> +
> + /** Returns true if target_bo is in the relocation tree rooted at bo. */
> + int (*bo_references) (drm_intel_bo *bo, drm_intel_bo *target_bo);
> +
> + /**< Enables verbose debugging printouts */
> + int debug;
> +};
> +
> +struct _drm_intel_bo {
> + /**
> + * Size in bytes of the buffer object.
> + *
> + * The size may be larger than the size originally requested for the
> + * allocation, such as being aligned to page size.
> + */
> + unsigned long size;
> +
> + /**
> + * Alignment requirement for object
> + *
> + * Used for GTT mapping & pinning the object.
> + */
> + unsigned long align;
> +
> + /**
> + * Deprecated field containing (possibly the low 32-bits of) the last
> + * seen virtual card address. Use offset64 instead.
> + */
> + unsigned long offset;
> +
> + /**
> + * Virtual address for accessing the buffer data. Only valid while
> + * mapped.
> + */
> +#ifdef __cplusplus
> + void *virt;
> +#else
> + void *virtual;
> +#endif
> +
> + /** Buffer manager context associated with this buffer object */
> + drm_intel_bufmgr *bufmgr;
> +
> + /**
> + * MM-specific handle for accessing object
> + */
> + int handle;
> +
> + /**
> + * Last seen card virtual address (offset from the beginning of the
> + * aperture) for the object. This should be used to fill relocation
> + * entries when calling drm_intel_bo_emit_reloc()
> + */
> + uint64_t offset64;
> +};
> +
> +typedef struct drm_i915_getparam {
> + __s32 param;
> + /*
> + * WARNING: Using pointers instead of fixed-size u64 means we need to write
> + * compat32 code. Don't repeat this mistake.
> + */
> + int *value;
> +} drm_i915_getparam_t;
> +
> +struct drm_i915_gem_execbuffer2 {
> + /**
> + * List of gem_exec_object2 structs
> + */
> + __u64 buffers_ptr;
> + __u32 buffer_count;
> +
> + /** Offset in the batchbuffer to start execution from. */
> + __u32 batch_start_offset;
> + /** Bytes used in batchbuffer from batch_start_offset */
> + __u32 batch_len;
> + __u32 DR1;
> + __u32 DR4;
> + __u32 num_cliprects;
> + /** This is a struct drm_clip_rect *cliprects */
> + __u64 cliprects_ptr;
> +#define I915_EXEC_RING_MASK (7<<0)
> +#define I915_EXEC_DEFAULT (0<<0)
> +#define I915_EXEC_RENDER (1<<0)
> +#define I915_EXEC_BSD (2<<0)
> +#define I915_EXEC_BLT (3<<0)
> +#define I915_EXEC_VEBOX (4<<0)
> +
> +/* Used for switching the constants addressing mode on gen4+ RENDER ring.
> + * Gen6+ only supports relative addressing to dynamic state (default) and
> + * absolute addressing.
> + *
> + * These flags are ignored for the BSD and BLT rings.
> + */
> +#define I915_EXEC_CONSTANTS_MASK (3<<6)
> +#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
> +#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
> +#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
> + __u64 flags;
> + __u64 rsvd1; /* now used for context info */
> + __u64 rsvd2;
> +};
> +
> +struct drm_i915_gem_exec_object2 {
> + /**
> + * User's handle for a buffer to be bound into the GTT for this
> + * operation.
> + */
> + __u32 handle;
> +
> + /** Number of relocations to be performed on this buffer */
> + __u32 relocation_count;
> + /**
> + * Pointer to array of struct drm_i915_gem_relocation_entry containing
> + * the relocations to be performed in this buffer.
> + */
> + __u64 relocs_ptr;
> +
> + /** Required alignment in graphics aperture */
> + __u64 alignment;
> +
> + /**
> + * When the EXEC_OBJECT_PINNED flag is specified this is populated by
> + * the user with the GTT offset at which this object will be pinned.
> + * When the I915_EXEC_NO_RELOC flag is specified this must contain the
> + * presumed_offset of the object.
> + * During execbuffer2 the kernel populates it with the value of the
> + * current GTT offset of the object, for future presumed_offset writes.
> + */
> + __u64 offset;
> +
> +#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
> +#define EXEC_OBJECT_NEEDS_GTT (1<<1)
> +#define EXEC_OBJECT_WRITE (1<<2)
> +#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
> +#define EXEC_OBJECT_PINNED (1<<4)
> +#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1)
> + __u64 flags;
> +
> + __u64 rsvd1;
> + __u64 rsvd2;
> +};
> +
> +struct drm_i915_gem_relocation_entry {
> + /**
> + * Handle of the buffer being pointed to by this relocation entry.
> + *
> + * It's appealing to make this be an index into the mm_validate_entry
> + * list to refer to the buffer, but this allows the driver to create
> + * a relocation list for state buffers and not re-write it per
> + * exec using the buffer.
> + */
> + __u32 target_handle;
> +
> + /**
> + * Value to be added to the offset of the target buffer to make up
> + * the relocation entry.
> + */
> + __u32 delta;
> +
> + /** Offset in the buffer the relocation entry will be written into */
> + __u64 offset;
> +
> + /**
> + * Offset value of the target buffer that the relocation entry was last
> + * written as.
> + *
> + * If the buffer has the same offset as last time, we can skip syncing
> + * and writing the relocation. This value is written back out by
> + * the execbuffer ioctl when the relocation is written.
> + */
> + __u64 presumed_offset;
> +
> + /**
> + * Target memory domains read by this operation.
> + */
> + __u32 read_domains;
> +
> + /**
> + * Target memory domains written by this operation.
> + *
> + * Note that only one domain may be written by the whole
> + * execbuffer operation, so that where there are conflicts,
> + * the application will get -EINVAL back.
> + */
> + __u32 write_domain;
> +};
> +
> +struct drm_i915_gem_get_tiling {
> + /** Handle of the buffer to get tiling state for. */
> + __u32 handle;
> +
> + /**
> + * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
> + * I915_TILING_Y).
> + */
> + __u32 tiling_mode;
> +
> + /**
> + * Returned address bit 6 swizzling required for CPU access through
> + * mmap mapping.
> + */
> + __u32 swizzle_mode;
> +
> + /**
> + * Returned address bit 6 swizzling required for CPU access through
> + * mmap mapping whilst bound.
> + */
> + __u32 phys_swizzle_mode;
> +};
> +
> +struct drm_i915_gem_set_tiling {
> + /** Handle of the buffer to have its tiling state updated */
> + __u32 handle;
> +
> + /**
> + * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
> + * I915_TILING_Y).
> + *
> + * This value is to be set on request, and will be updated by the
> + * kernel on successful return with the actual chosen tiling layout.
> + *
> + * The tiling mode may be demoted to I915_TILING_NONE when the system
> + * has bit 6 swizzling that can't be managed correctly by GEM.
> + *
> + * Buffer contents become undefined when changing tiling_mode.
> + */
> + __u32 tiling_mode;
> +
> + /**
> + * Stride in bytes for the object when in I915_TILING_X or
> + * I915_TILING_Y.
> + */
> + __u32 stride;
> +
> + /**
> + * Returned address bit 6 swizzling required for CPU access through
> + * mmap mapping.
> + */
> + __u32 swizzle_mode;
> +};
> +
> +struct drm_i915_gem_pwrite {
> + /** Handle for the object being written to. */
> + __u32 handle;
> + __u32 pad;
> + /** Offset into the object to write to */
> + __u64 offset;
> + /** Length of data to write */
> + __u64 size;
> + /**
> + * Pointer to read the data from.
> + *
> + * This is a fixed-size type for 32/64 compatibility.
> + */
> + __u64 data_ptr;
> +};
> +
> +struct drm_i915_gem_pread {
> + /** Handle for the object being read. */
> + __u32 handle;
> + __u32 pad;
> + /** Offset into the object to read from */
> + __u64 offset;
> + /** Length of data to read */
> + __u64 size;
> + /**
> + * Pointer to write the data into.
> + *
> + * This is a fixed-size type for 32/64 compatibility.
> + */
> + __u64 data_ptr;
> +};
> +
> +struct drm_i915_gem_set_domain {
> + /** Handle for the object */
> + __u32 handle;
> +
> + /** New read domains */
> + __u32 read_domains;
> +
> + /** New write domain */
> + __u32 write_domain;
> +};
> +
> +struct drm_i915_gem_wait {
> + /** Handle of BO we shall wait on */
> + __u32 bo_handle;
> + __u32 flags;
> + /** Number of nanoseconds to wait, Returns time remaining. */
> + __s64 timeout_ns;
> +};
> +
> +struct drm_i915_gem_busy {
> + /** Handle of the buffer to check for busy */
> + __u32 handle;
> +
> + /** Return busy status (1 if busy, 0 if idle).
> + * The high word is used to indicate on which rings the object
> + * currently resides:
> + * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
> + */
> + __u32 busy;
> +};
> +
> +struct drm_i915_gem_get_aperture {
> + /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
> + __u64 aper_size;
> +
> + /**
> + * Available space in the aperture used by i915_gem_execbuffer, in
> + * bytes
> + */
> + __u64 aper_available_size;
> +};
> +
> +struct drm_i915_gem_create {
> + /**
> + * Requested size for the object.
> + *
> + * The (page-aligned) allocated size for the object will be returned.
> + */
> + __u64 size;
> + /**
> + * Returned handle for the object.
> + *
> + * Object handles are nonzero.
> + */
> + __u32 handle;
> + __u32 pad;
> +};
> +
> +struct drm_i915_gem_mmap_gtt {
> + /** Handle for the object being mapped. */
> + __u32 handle;
> + __u32 pad;
> + /**
> + * Fake offset to use for subsequent mmap call
> + *
> + * This is a fixed-size type for 32/64 compatibility.
> + */
> + __u64 offset;
> +};
> +
> +struct drm_i915_gem_sw_finish {
> + /** Handle for the object */
> + __u32 handle;
> +};
> +
> +struct drm_i915_gem_mmap {
> + /** Handle for the object being mapped. */
> + __u32 handle;
> + __u32 pad;
> + /** Offset in the object to map. */
> + __u64 offset;
> + /**
> + * Length of data to map.
> + *
> + * The value will be page-aligned.
> + */
> + __u64 size;
> + /**
> + * Returned pointer the data was mapped at.
> + *
> + * This is a fixed-size type for 32/64 compatibility.
> + */
> + __u64 addr_ptr;
> +
> + /**
> + * Flags for extended behaviour.
> + *
> + * Added in version 2.
> + */
> + __u64 flags;
> +#define I915_MMAP_WC 0x1
> +};
> +
> +struct drm_i915_gem_madvise {
> + /** Handle of the buffer to change the backing store advice */
> + __u32 handle;
> +
> + /* Advice: either the buffer will be needed again in the near future,
> + * or wont be and could be discarded under memory pressure.
> + */
> + __u32 madv;
> +
> + /** Whether the backing store still exists. */
> + __u32 retained;
> +};
> +
> +struct drm_i915_gem_context_create {
> + /* output: id of new context*/
> + __u32 ctx_id;
> + __u32 pad;
> +};
> +
> +struct drm_i915_gem_context_destroy {
> + __u32 ctx_id;
> + __u32 pad;
> +};
> +
> +typedef struct _drm_intel_aub_annotation {
> + uint32_t type;
> + uint32_t subtype;
> + uint32_t ending_offset;
> +} drm_intel_aub_annotation;
> +
> +struct drm_i915_gem_pin {
> + /** Handle of the buffer to be pinned. */
> + __u32 handle;
> + __u32 pad;
> +
> + /** alignment required within the aperture */
> + __u64 alignment;
> +
> + /** Returned GTT offset of the buffer. */
> + __u64 offset;
> +};
> +
> +#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
> +#define I915_SET_COLORKEY_DESTINATION (1<<1)
> +#define I915_SET_COLORKEY_SOURCE (1<<2)
> +struct drm_intel_sprite_colorkey {
> + __u32 plane_id;
> + __u32 min_value;
> + __u32 channel_mask;
> + __u32 max_value;
> + __u32 flags;
> +};
> +
> +struct drm_i915_reg_read {
> + /*
> + * Register offset.
> + * For 64bit wide registers where the upper 32bits don't immediately
> + * follow the lower 32bits, the offset of the lower 32bits must
> + * be specified
> + */
> + __u64 offset;
> + __u64 val; /* Return value */
> +};
> +
> +drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
> +void drm_intel_bo_unreference(drm_intel_bo *bo);
> +drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
> + unsigned long size, unsigned int alignment);
> +int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
> + unsigned long size, const void *data);
> +int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
> + int used, unsigned int flags);
> +int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
> + drm_intel_bo *target_bo, uint32_t target_offset,
> + uint32_t read_domains, uint32_t write_domain);
> +int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
> + drm_intel_bo *target_bo,
> + uint32_t target_offset,
> + uint32_t read_domains, uint32_t write_domain);
> +int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
> + uint32_t * swizzle_mode);
> +int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
> + struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
> + unsigned int flags);
> +void drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
> + drm_intel_aub_annotation *annotations,
> + unsigned count);
> +void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
> +int drm_intel_bo_exec(drm_intel_bo *bo, int used,
> + struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
> +void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
> +void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
> +int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
> + unsigned long size, void *data);
> +int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
> +int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
> +void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr);
> +int drm_intel_bo_unmap(drm_intel_bo *bo);
> +int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
> +drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
> + const char *name,
> + unsigned int handle);
> +int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
> +drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
> + int prime_fd, int size);
> +void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
> + int limit);
> +int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
> +drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr);
> +void drm_intel_gem_context_destroy(drm_intel_context *ctx);
> +drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
> + const char *name,
> + int x, int y, int cpp,
> + uint32_t *tiling_mode,
> + unsigned long *pitch,
> + unsigned long flags);
> +void drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
> + const char *filename);
> +void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
> +void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
> + int x1, int y1, int width, int height,
> + enum aub_dump_bmp_format format,
> + int pitch, int offset);
> +void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
> +int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
> + uint32_t stride);
> +int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
> +void drm_intel_bo_reference(drm_intel_bo *bo);
> +int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
> +drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
> + const char *name,
> + unsigned long size,
> + unsigned int alignment);
> +int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
> +int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns);
> +
> +#endif
> +
> +#endif//INTEL_DRM_STUBS_H
> --
> 2.7.4
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [RFC i-g-t 8/9] lib: Replace intel specific header includes with intel_drm_stubs.h.
2016-05-20 22:59 ` [RFC i-g-t 8/9] lib: Replace intel specific header includes with intel_drm_stubs.h robert.foss
2016-05-23 14:57 ` ?==?utf-8?q? " Emil Velikov
@ 2016-05-24 8:07 ` Daniel Vetter
2016-05-25 18:00 ` Robert Foss
1 sibling, 1 reply; 29+ messages in thread
From: Daniel Vetter @ 2016-05-24 8:07 UTC (permalink / raw)
To: robert.foss
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On Fri, May 20, 2016 at 06:59:32PM -0400, robert.foss@collabora.com wrote:
> From: Robert Foss <robert.foss@collabora.com>
>
> Replace intel specific header includes with intel_drm_stubs.h.
>
> The stubbed functions will all call igt_require(false) and cause a skip.
>
> Signed-off-by: Robert Foss <robert.foss@collabora.com>
Do we need this sed job really? I kinda hoped we could have a dummy header
somewhere, like lib/stubs/drm/i915_drm.h and similar (instead of your
intel_drm_stubs.h), and then add lib/stubs/ to the include path when
!HAVE_LIBDRM_INTEL? That way 0 changes to tests/lib itself should be
needed.
-Daniel
> ---
> lib/drmtest.c | 2 +-
> lib/gpgpu_fill.c | 7 +++----
> lib/igt_aux.c | 2 +-
> lib/igt_aux.h | 3 ++-
> lib/igt_debugfs.c | 4 ++--
> lib/igt_draw.h | 3 +--
> lib/igt_fb.h | 3 ++-
> lib/igt_kms.c | 3 +--
> lib/intel_batchbuffer.c | 4 ----
> lib/intel_batchbuffer.h | 3 +--
> lib/intel_chipset.c | 2 +-
> lib/ioctl_wrappers.c | 1 -
> lib/ioctl_wrappers.h | 4 ++--
> lib/media_fill_gen7.c | 3 +--
> lib/media_fill_gen8.c | 4 +---
> lib/media_fill_gen8lp.c | 6 ++----
> lib/media_fill_gen9.c | 4 +---
> lib/media_spin.c | 2 --
> lib/rendercopy_gen6.c | 5 ++---
> lib/rendercopy_gen7.c | 4 +---
> lib/rendercopy_gen8.c | 4 +---
> lib/rendercopy_gen9.c | 5 +----
> lib/rendercopy_i830.c | 5 +----
> lib/rendercopy_i915.c | 9 +++------
> 24 files changed, 31 insertions(+), 61 deletions(-)
>
> diff --git a/lib/drmtest.c b/lib/drmtest.c
> index 7d6b74a..f043607 100644
> --- a/lib/drmtest.c
> +++ b/lib/drmtest.c
> @@ -48,13 +48,13 @@
> #include <termios.h>
>
> #include "drmtest.h"
> -#include "i915_drm.h"
> #include "intel_chipset.h"
> #include "intel_io.h"
> #include "igt_gt.h"
> #include "igt_debugfs.h"
> #include "version.h"
> #include "config.h"
> +#include "intel_drm_stubs.h"
> #include "intel_reg.h"
> #include "ioctl_wrappers.h"
>
> diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
> index 4d98643..62b1161 100644
> --- a/lib/gpgpu_fill.c
> +++ b/lib/gpgpu_fill.c
> @@ -25,15 +25,14 @@
> * Dominik Zeromski <dominik.zeromski@intel.com>
> */
>
> -#include <intel_bufmgr.h>
> -#include <i915_drm.h>
>
> -#include "intel_reg.h"
> #include "drmtest.h"
> -#include "intel_batchbuffer.h"
> #include "gen7_media.h"
> #include "gen8_media.h"
> #include "gpgpu_fill.h"
> +#include "intel_batchbuffer.h"
> +#include "intel_drm_stubs.h"
> +#include "intel_reg.h"
>
> /* shaders/gpgpu/gpgpu_fill.gxa */
> static const uint32_t gen7_gpgpu_kernel[][4] = {
> diff --git a/lib/igt_aux.c b/lib/igt_aux.c
> index fe18365..772c902 100644
> --- a/lib/igt_aux.c
> +++ b/lib/igt_aux.c
> @@ -52,12 +52,12 @@
> #include <assert.h>
>
> #include "drmtest.h"
> -#include "i915_drm.h"
> #include "intel_chipset.h"
> #include "igt_aux.h"
> #include "igt_debugfs.h"
> #include "igt_gt.h"
> #include "config.h"
> +#include "intel_drm_stubs.h"
> #include "intel_reg.h"
> #include "ioctl_wrappers.h"
> #include "igt_kms.h"
> diff --git a/lib/igt_aux.h b/lib/igt_aux.h
> index f66de72..c66121b 100644
> --- a/lib/igt_aux.h
> +++ b/lib/igt_aux.h
> @@ -28,10 +28,11 @@
> #ifndef IGT_AUX_H
> #define IGT_AUX_H
>
> -#include <intel_bufmgr.h>
> #include <stdbool.h>
> #include <sys/time.h>
>
> +#include "intel_drm_stubs.h"
> +
> extern drm_intel_bo **trash_bos;
> extern int num_trash_bos;
>
> diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
> index a32ed78..d9f371f 100644
> --- a/lib/igt_debugfs.c
> +++ b/lib/igt_debugfs.c
> @@ -32,12 +32,12 @@
> #include <string.h>
> #include <fcntl.h>
> #include <unistd.h>
> -#include <i915_drm.h>
>
> #include "drmtest.h"
> +#include "intel_drm_stubs.h"
> #include "igt_aux.h"
> -#include "igt_kms.h"
> #include "igt_debugfs.h"
> +#include "igt_kms.h"
>
> /**
> * SECTION:igt_debugfs
> diff --git a/lib/igt_draw.h b/lib/igt_draw.h
> index b030131..c0e95ca 100644
> --- a/lib/igt_draw.h
> +++ b/lib/igt_draw.h
> @@ -25,9 +25,8 @@
> #ifndef __IGT_DRAW_H__
> #define __IGT_DRAW_H__
>
> -#include <intel_bufmgr.h>
> #include "igt_fb.h"
> -
> +#include "intel_drm_stubs.h"
> /**
> * igt_draw_method:
> * @IGT_DRAW_MMAP_CPU: draw using a CPU mmap.
> diff --git a/lib/igt_fb.h b/lib/igt_fb.h
> index ce2cc0f..82dbacb 100644
> --- a/lib/igt_fb.h
> +++ b/lib/igt_fb.h
> @@ -38,10 +38,11 @@ typedef struct _cairo cairo_t;
>
> #include <stddef.h>
> #include <stdbool.h>
> +#include <stdint.h>
> #include <drm_fourcc.h>
> #include <xf86drmMode.h>
>
> -#include <i915_drm.h>
> +#include "intel_drm_stubs.h"
>
> /* helpers to create nice-looking framebuffers */
> struct igt_fb {
> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
> index f85be1e..7afee53 100644
> --- a/lib/igt_kms.c
> +++ b/lib/igt_kms.c
> @@ -41,12 +41,11 @@
> #include <errno.h>
> #include <time.h>
>
> -#include <i915_drm.h>
> -
> #include "drmtest.h"
> #include "igt_kms.h"
> #include "igt_aux.h"
> #include "intel_chipset.h"
> +#include "intel_drm_stubs.h"
> #include "igt_debugfs.h"
>
> /* list of connectors that need resetting on exit */
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index 692521f..a28eb33 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -31,10 +31,8 @@
> #include <string.h>
> #include <assert.h>
>
> -#include "drm.h"
> #include "drmtest.h"
> #include "intel_batchbuffer.h"
> -#include "intel_bufmgr.h"
> #include "intel_chipset.h"
> #include "intel_reg.h"
> #include "rendercopy.h"
> @@ -43,8 +41,6 @@
> #include "media_spin.h"
> #include "gpgpu_fill.h"
>
> -#include <i915_drm.h>
> -
> /**
> * SECTION:intel_batchbuffer
> * @short_description: Batchbuffer and blitter support
> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
> index 869747d..bd365db 100644
> --- a/lib/intel_batchbuffer.h
> +++ b/lib/intel_batchbuffer.h
> @@ -2,10 +2,9 @@
> #define INTEL_BATCHBUFFER_H
>
> #include <stdint.h>
> -#include <intel_bufmgr.h>
> -#include <i915_drm.h>
>
> #include "igt_core.h"
> +#include "intel_drm_stubs.h"
> #include "intel_reg.h"
>
> #define BATCH_SZ 4096
> diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
> index 56746b0..6ac74e9 100644
> --- a/lib/intel_chipset.c
> +++ b/lib/intel_chipset.c
> @@ -36,9 +36,9 @@
> #include <fcntl.h>
> #include <sys/stat.h>
> #include <sys/mman.h>
> -#include "i915_drm.h"
>
> #include "drmtest.h"
> +#include "intel_drm_stubs.h"
> #include "intel_chipset.h"
> #include "igt_core.h"
>
> diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
> index f224091..e46811a 100644
> --- a/lib/ioctl_wrappers.c
> +++ b/lib/ioctl_wrappers.c
> @@ -50,7 +50,6 @@
> #include <errno.h>
>
> #include "drmtest.h"
> -#include "i915_drm.h"
> #include "intel_chipset.h"
> #include "intel_io.h"
> #include "igt_debugfs.h"
> diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
> index 8fe35b0..aa8c60f 100644
> --- a/lib/ioctl_wrappers.h
> +++ b/lib/ioctl_wrappers.h
> @@ -32,8 +32,8 @@
>
> #include <stdint.h>
> #include <stdbool.h>
> -#include <intel_bufmgr.h>
> -#include <i915_drm.h>
> +
> +#include "intel_drm_stubs.h"
>
> extern int (*igt_ioctl)(int fd, unsigned long request, void *arg);
>
> diff --git a/lib/media_fill_gen7.c b/lib/media_fill_gen7.c
> index 6fb4479..5ec8502 100644
> --- a/lib/media_fill_gen7.c
> +++ b/lib/media_fill_gen7.c
> @@ -1,9 +1,8 @@
> -#include <intel_bufmgr.h>
> -#include <i915_drm.h>
>
> #include "media_fill.h"
> #include "gen7_media.h"
> #include "intel_reg.h"
> +#include "intel_drm_stubs.h"
> #include "drmtest.h"
>
> #include <assert.h>
> diff --git a/lib/media_fill_gen8.c b/lib/media_fill_gen8.c
> index 4a8fe5a..a1e1fe4 100644
> --- a/lib/media_fill_gen8.c
> +++ b/lib/media_fill_gen8.c
> @@ -1,8 +1,6 @@
> -#include <intel_bufmgr.h>
> -#include <i915_drm.h>
> -
> #include "media_fill.h"
> #include "gen8_media.h"
> +#include "intel_drm_stubs.h"
> #include "intel_reg.h"
> #include "drmtest.h"
>
> diff --git a/lib/media_fill_gen8lp.c b/lib/media_fill_gen8lp.c
> index 1f8a4ad..eed26ee 100644
> --- a/lib/media_fill_gen8lp.c
> +++ b/lib/media_fill_gen8lp.c
> @@ -1,13 +1,11 @@
> -#include <intel_bufmgr.h>
> -#include <i915_drm.h>
> +#include <assert.h>
>
> #include "media_fill.h"
> #include "gen8_media.h"
> +#include "intel_drm_stubs.h"
> #include "intel_reg.h"
> #include "drmtest.h"
>
> -#include <assert.h>
> -
>
> static const uint32_t media_kernel[][4] = {
> { 0x00400001, 0x20202288, 0x00000020, 0x00000000 },
> diff --git a/lib/media_fill_gen9.c b/lib/media_fill_gen9.c
> index 3fd2181..902b28b 100644
> --- a/lib/media_fill_gen9.c
> +++ b/lib/media_fill_gen9.c
> @@ -1,8 +1,6 @@
> -#include <intel_bufmgr.h>
> -#include <i915_drm.h>
> -
> #include "media_fill.h"
> #include "gen8_media.h"
> +#include "intel_drm_stubs.h"
> #include "intel_reg.h"
>
> #include <assert.h>
> diff --git a/lib/media_spin.c b/lib/media_spin.c
> index 580c109..f4a432a 100644
> --- a/lib/media_spin.c
> +++ b/lib/media_spin.c
> @@ -24,8 +24,6 @@
> * Jeff McGee <jeff.mcgee@intel.com>
> */
>
> -#include <intel_bufmgr.h>
> -#include <i915_drm.h>
> #include "intel_reg.h"
> #include "drmtest.h"
> #include "intel_batchbuffer.h"
> diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c
> index 8c24cf8..d5207d5 100644
> --- a/lib/rendercopy_gen6.c
> +++ b/lib/rendercopy_gen6.c
> @@ -9,11 +9,10 @@
> #include <errno.h>
> #include <sys/stat.h>
> #include <sys/time.h>
> -#include "drm.h"
> -#include "i915_drm.h"
> +
> #include "drmtest.h"
> -#include "intel_bufmgr.h"
> #include "intel_batchbuffer.h"
> +#include "intel_drm_stubs.h"
> #include "intel_io.h"
> #include "rendercopy.h"
> #include "gen6_render.h"
> diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c
> index 3b92406..dc48a99 100644
> --- a/lib/rendercopy_gen7.c
> +++ b/lib/rendercopy_gen7.c
> @@ -9,10 +9,8 @@
> #include <errno.h>
> #include <sys/stat.h>
> #include <sys/time.h>
> -#include "drm.h"
> -#include "i915_drm.h"
> +
> #include "drmtest.h"
> -#include "intel_bufmgr.h"
> #include "intel_batchbuffer.h"
> #include "intel_io.h"
> #include "intel_chipset.h"
> diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c
> index a7fc2c4..6fbb680 100644
> --- a/lib/rendercopy_gen8.c
> +++ b/lib/rendercopy_gen8.c
> @@ -10,12 +10,10 @@
> #include <sys/stat.h>
> #include <sys/time.h>
>
> -#include <drm.h>
> -#include <i915_drm.h>
>
> #include "drmtest.h"
> -#include "intel_bufmgr.h"
> #include "intel_batchbuffer.h"
> +#include "intel_drm_stubs.h"
> #include "intel_io.h"
> #include "rendercopy.h"
> #include "gen8_render.h"
> diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
> index 9537480..d575ddf 100644
> --- a/lib/rendercopy_gen9.c
> +++ b/lib/rendercopy_gen9.c
> @@ -11,12 +11,9 @@
> #include <sys/time.h>
> #include <getopt.h>
>
> -#include <drm.h>
> -#include <i915_drm.h>
> -
> #include "drmtest.h"
> -#include "intel_bufmgr.h"
> #include "intel_batchbuffer.h"
> +#include "intel_drm_stubs.h"
> #include "intel_io.h"
> #include "rendercopy.h"
> #include "gen9_render.h"
> diff --git a/lib/rendercopy_i830.c b/lib/rendercopy_i830.c
> index 04215b1..738d4d2 100644
> --- a/lib/rendercopy_i830.c
> +++ b/lib/rendercopy_i830.c
> @@ -8,13 +8,10 @@
> #include <errno.h>
> #include <sys/stat.h>
> #include <sys/time.h>
> -#include "drm.h"
> -#include "i915_drm.h"
> +
> #include "drmtest.h"
> -#include "intel_bufmgr.h"
> #include "intel_batchbuffer.h"
> #include "intel_io.h"
> -
> #include "i830_reg.h"
> #include "rendercopy.h"
>
> diff --git a/lib/rendercopy_i915.c b/lib/rendercopy_i915.c
> index fc9583c..8846fdc 100644
> --- a/lib/rendercopy_i915.c
> +++ b/lib/rendercopy_i915.c
> @@ -8,15 +8,12 @@
> #include <errno.h>
> #include <sys/stat.h>
> #include <sys/time.h>
> -#include "drm.h"
> -#include "i915_drm.h"
> -#include "drmtest.h"
> -#include "intel_bufmgr.h"
> -#include "intel_batchbuffer.h"
> -#include "intel_io.h"
>
> +#include "drmtest.h"
> #include "i915_reg.h"
> #include "i915_3d.h"
> +#include "intel_batchbuffer.h"
> +#include "intel_io.h"
> #include "rendercopy.h"
>
> void gen3_render_copyfunc(struct intel_batchbuffer *batch,
> --
> 2.7.4
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [RFC i-g-t 1/9] configure.ac: Test for libdrm_intel and build for it if present.
2016-05-23 15:03 ` ?==?utf-8?q? ?==?utf-8?q? [RFC i-g-t 1/9]?==?utf-8?q? " Emil Velikov
@ 2016-05-24 14:58 ` Robert Foss
0 siblings, 0 replies; 29+ messages in thread
From: Robert Foss @ 2016-05-24 14:58 UTC (permalink / raw)
To: Emil Velikov, Chris Wilson
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On 2016-05-23 11:03 AM, Emil Velikov wrote:
> On Saturday, May 21, 2016 08:55 BST, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>> On Fri, May 20, 2016 at 06:59:25PM -0400, robert.foss@collabora.com wrote:
>>> From: Robert Foss <robert.foss@collabora.com>
>>>
>>> Test for libdrm_intel and build for it if present.
>>> Also expose the HAVE_INTEL #define to allow code to be conditionally
>>> compiled.
>>>
>>> Signed-off-by: Robert Foss <robert.foss@collabora.com>
>>> ---
>>> configure.ac | 14 +++++++++++++-
>>> 1 file changed, 13 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/configure.ac b/configure.ac
>>> index 0589782..b6fc168 100644
>>> --- a/configure.ac
>>> +++ b/configure.ac
>>> @@ -100,7 +100,7 @@ if test "x$GCC" = "xyes"; then
>>> fi
>>> AC_SUBST(ASSEMBLER_WARN_CFLAGS)
>>>
>>> -PKG_CHECK_MODULES(DRM, [libdrm_intel >= 2.4.64 libdrm])
>>> +PKG_CHECK_MODULES(DRM, [libdrm])
>>> PKG_CHECK_MODULES(PCIACCESS, [pciaccess >= 0.10])
>>>
>>> case "$target_cpu" in
>>> @@ -150,6 +150,18 @@ PKG_CHECK_MODULES(GLIB, glib-2.0)
>>> # -----------------------------------------------------------------------------
>>> # Configuration options
>>> # -----------------------------------------------------------------------------
>>> +AC_ARG_ENABLE(intel, AS_HELP_STRING([--disable-intel],
>>> + [Enable building of intel specific parts (default: auto)]),
>>> + [INTEL=$enableval], [INTEL=auto])
>>> +if test "x$INTEL" = xauto; then
>>> + PKG_CHECK_EXISTS([libdrm_intel >= 2.4.64], [INTEL=yes], [INTEL=no])
>>> +fi
>>> +if test "x$INTEL" = xyes; then
>>> + PKG_CHECK_MODULES(DRM_INTEL, [libdrm_intel >= 2.4.64])
>
>>> + AC_DEFINE(HAVE_INTEL, 1, [Have intel support])
>>> +fi
>>> +AM_CONDITIONAL(HAVE_INTEL, [test "x$INTEL" = xyes])
>>
>> HAVE_INTEL caused quite a bit of confusion when reading the later build
>> patches.
>>
>> Please use HAVE_LIBDRM_INTEL instead
> As a counter argument, one could, should really, use --enable-intel to replace the 'x86' parts in commit bccc0ec6a3fdae880e14770c2ff5770fb86ea6fc. Perhaps HAVE_INTEL isn't that bad when we take that into consideration ?
>
The purpose of HAVE_INTEL isn't really to avoid building x86 code on
non-x86 platforms, but rather to avoid a build dependency where it can
be avoided.
That being said using a BUILD_X86 or something like it to avoid building
irrelevant binaries would be very useful.
Either way, HAVE_LIBDRM_INTEL more clearly defines what the flag is about.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [RFC i-g-t 2/9] benchmarks/Makefile: Don't build benchmarks that depend on libdrm_intel.
2016-05-24 8:01 ` Daniel Vetter
@ 2016-05-25 17:47 ` Robert Foss
0 siblings, 0 replies; 29+ messages in thread
From: Robert Foss @ 2016-05-25 17:47 UTC (permalink / raw)
To: Daniel Vetter, Emil Velikov
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On 2016-05-24 04:01 AM, Daniel Vetter wrote:
> On Mon, May 23, 2016 at 03:04:16PM +0100, Emil Velikov wrote:
>> On Friday, May 20, 2016 23:59 BST, robert.foss@collabora.com wrote:
>>> From: Robert Foss <robert.foss@collabora.com>
>>>
>>> Use the HAS_INTEL automake flag to avoid building benchmarks that won't
>>> compile unless libdrm_intel is available in the build system.
>>>
>>> Signed-off-by: Robert Foss <robert.foss@collabora.com>
>>> ---
>>> benchmarks/Makefile.sources | 15 ++++++++++-----
>>> 1 file changed, 10 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/benchmarks/Makefile.sources b/benchmarks/Makefile.sources
>>> index 81607a5..26ee3ea 100644
>>> --- a/benchmarks/Makefile.sources
>>> +++ b/benchmarks/Makefile.sources
>>> @@ -1,10 +1,6 @@
>>> benchmarksdir=$(libexecdir)/intel-gpu-tools/benchmarks
>>>
>>> benchmarks_PROGRAMS = \
>>> - intel_upload_blit_large \
>>> - intel_upload_blit_large_gtt \
>>> - intel_upload_blit_large_map \
>>> - intel_upload_blit_small \
>>> gem_blt \
>>> gem_create \
>>> gem_exec_ctx \
>>> @@ -16,6 +12,15 @@ benchmarks_PROGRAMS = \
>>> gem_prw \
>>> gem_set_domain \
>>> gem_syslatency \
>>> - gem_userptr_benchmark \
>>> kms_vblank \
>>> $(NULL)
>>> +
>>> +if HAVE_INTEL
>>> + benchmarks_PROGRAMS += \
>>> + intel_upload_blit_large \
>>> + intel_upload_blit_large_gtt \
>>> + intel_upload_blit_large_map \
>>> + intel_upload_blit_small \
>>> + gem_userptr_benchmark \
>>> + $(NULL)
>>> +endif
>> Some suggestions:
>> - Please don't use conditionals in the Makefile.sources - you'll break the other build (Android)
>> - instead of ^^ use separate variable and combine them in the Makefile.am/Android.mk
>> - Don't double-indent, don't think any other place does so.
>
> Atm the other build is Intel-only, so I don't think it's that bad really -
> if we add a #define HAVE_INTEL there before including Makefile.sources (or
> whatever the make magic for this is). If someone wants to build igt on
> other Android machines that needs some extensions, but hey not my problem
> when Android wants to reinvent half of autoconf ;-)
> -Daniel
>
For v2 I've implemented the changes as suggested by Emil, I've also
added the (hopefully) equivalent changes to Arduino.mk.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [RFC i-g-t 7/9] lib/intel_drm_stubs: Add stubs for functionality from libdrm_intel.
2016-05-24 8:05 ` Daniel Vetter
@ 2016-05-25 17:48 ` Robert Foss
0 siblings, 0 replies; 29+ messages in thread
From: Robert Foss @ 2016-05-25 17:48 UTC (permalink / raw)
To: Daniel Vetter
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On 2016-05-24 04:05 AM, Daniel Vetter wrote:
> On Fri, May 20, 2016 at 06:59:31PM -0400, robert.foss@collabora.com wrote:
>> From: Robert Foss <robert.foss@collabora.com>
>>
>> This patch provides stubs for functionality otherwise provided by libdrm_intel.
>>
>> The stubbed functions all fail with a call to igt_require(false).
>> Defines and enums have been copied from libdrm_intel.
>
> For prettiness mayb igt_require_f(false, "Not compiled with libdrm_intel
> support\n"); or something similar.
> -Daniel
Ack, added in v2.
Rob.
>
>>
>> Due to the stubbed tests failing with an igt_require() call, these stubs are
>> not well suited for non-tests, since tools/benchmarks/etc 'skipping'
>> execution is unhelpful.
>>
>> Signed-off-by: Robert Foss <robert.foss@collabora.com>
>> ---
>> lib/Makefile.sources | 2 +
>> lib/intel_drm_stubs.c | 258 +++++++++++++
>> lib/intel_drm_stubs.h | 999 ++++++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 1259 insertions(+)
>> create mode 100644 lib/intel_drm_stubs.c
>> create mode 100644 lib/intel_drm_stubs.h
>>
>> diff --git a/lib/Makefile.sources b/lib/Makefile.sources
>> index 1316fd2..c0f9f6d 100644
>> --- a/lib/Makefile.sources
>> +++ b/lib/Makefile.sources
>> @@ -21,6 +21,8 @@ libintel_tools_la_SOURCES = \
>> intel_batchbuffer.c \
>> intel_batchbuffer.h \
>> intel_chipset.h \
>> + intel_drm_stubs.c \
>> + intel_drm_stubs.h \
>> intel_os.c \
>> intel_io.h \
>> intel_mmio.c \
>> diff --git a/lib/intel_drm_stubs.c b/lib/intel_drm_stubs.c
>> new file mode 100644
>> index 0000000..d46a9b3
>> --- /dev/null
>> +++ b/lib/intel_drm_stubs.c
>> @@ -0,0 +1,258 @@
>> +#ifndef HAVE_INTEL
>> +
>> +#include "intel_drm_stubs.h"
>> +
>> +drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size)
>> +{
>> + igt_require(false);
>> + return (drm_intel_bufmgr *) NULL;
>> +}
>> +
>> +void drm_intel_bo_unreference(drm_intel_bo *bo)
>> +{
>> + igt_require(false);
>> +}
>> +
>> +drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
>> + unsigned long size, unsigned int alignment)
>> +{
>> + igt_require(false);
>> + return (drm_intel_bo *) NULL;
>> +}
>> +
>> +int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
>> + unsigned long size, const void *data)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
>> + int used, unsigned int flags)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
>> + drm_intel_bo *target_bo, uint32_t target_offset,
>> + uint32_t read_domains, uint32_t write_domain)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
>> + drm_intel_bo *target_bo,
>> + uint32_t target_offset,
>> + uint32_t read_domains, uint32_t write_domain)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
>> + uint32_t * swizzle_mode)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
>> + struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
>> + unsigned int flags)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +void drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
>> + drm_intel_aub_annotation *annotations,
>> + unsigned count)
>> +{
>> + igt_require(false);
>> +}
>> +
>> +void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
>> +{
>> + igt_require(false);
>> +}
>> +
>> +int drm_intel_bo_exec(drm_intel_bo *bo, int used,
>> + struct drm_clip_rect *cliprects, int num_cliprects, int DR4)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr)
>> +{
>> + igt_require(false);
>> +}
>> +
>> +void drm_intel_bo_wait_rendering(drm_intel_bo *bo)
>> +{
>> + igt_require(false);
>> +}
>> +
>> +int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
>> + unsigned long size, void *data)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +int drm_intel_bo_map(drm_intel_bo *bo, int write_enable)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr)
>> +{
>> + igt_require(false);
>> +}
>> +
>> +int drm_intel_bo_unmap(drm_intel_bo *bo)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
>> + const char *name,
>> + unsigned int handle)
>> +{
>> + igt_require(false);
>> + return (drm_intel_bo *) NULL;
>> +}
>> +
>> +int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
>> + int prime_fd, int size)
>> +{
>> + igt_require(false);
>> + return (drm_intel_bo *) NULL;
>> +}
>> +
>> +void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
>> + int limit)
>> +{
>> + igt_require(false);
>> +}
>> +
>> +int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr)
>> +{
>> + igt_require(false);
>> + return (drm_intel_bo *) NULL;
>> +}
>> +
>> +void drm_intel_gem_context_destroy(drm_intel_context *ctx)
>> +{
>> + igt_require(false);
>> +}
>> +
>> +drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
>> + const char *name,
>> + int x, int y, int cpp,
>> + uint32_t *tiling_mode,
>> + unsigned long *pitch,
>> + unsigned long flags)
>> +{
>> + igt_require(false);
>> + return (drm_intel_bo *) NULL;
>> +}
>> +
>> +void drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
>> + const char *filename)
>> +{
>> + igt_require(false);
>> +}
>> +
>> +void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable)
>> +{
>> + igt_require(false);
>> +}
>> +
>> +void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
>> + int x1, int y1, int width, int height,
>> + enum aub_dump_bmp_format format,
>> + int pitch, int offset)
>> +{
>> + igt_require(false);
>> +}
>> +
>> +void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
>> +{
>> + igt_require(false);
>> +}
>> +
>> +int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
>> + uint32_t stride)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +int drm_intel_bo_disable_reuse(drm_intel_bo *bo)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +void drm_intel_bo_reference(drm_intel_bo *bo)
>> +{
>> + igt_require(false);
>> +}
>> +
>> +int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
>> + const char *name,
>> + unsigned long size,
>> + unsigned int alignment)
>> +{
>> + igt_require(false);
>> + return (drm_intel_bo *) NULL;
>> +}
>> +
>> +int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns)
>> +{
>> + igt_require(false);
>> + return 0;
>> +}
>> +
>> +#endif//HAVE_INTEL
>> diff --git a/lib/intel_drm_stubs.h b/lib/intel_drm_stubs.h
>> new file mode 100644
>> index 0000000..fdfaaeb
>> --- /dev/null
>> +++ b/lib/intel_drm_stubs.h
>> @@ -0,0 +1,999 @@
>> +#ifndef INTEL_DRM_STUBS_H
>> +#define INTEL_DRM_STUBS_H
>> +
>> +#include <xf86drm.h>
>> +
>> +#include "igt_core.h"
>> +
>> +#ifdef HAVE_INTEL
>> +#include <i915_drm.h>
>> +#include <intel_bufmgr.h>
>> +#include <drm.h>
>> +
>> +
>> +#else
>> +#define i915_execbuffer2_set_context_id(eb2, context) igt_require(false);
>> +#define i915_execbuffer2_get_context_id(eb2) igt_require(false);
>> +
>> +#define I915_EXEC_GEN7_SOL_RESET (1<<8)
>> +#define I915_EXEC_SECURE (1<<9)
>> +#define I915_EXEC_IS_PINNED (1<<10)
>> +#define I915_EXEC_NO_RELOC (1<<11)
>> +#define I915_EXEC_HANDLE_LUT (1<<12)
>> +#define I915_EXEC_BSD_MASK (3<<13)
>> +#define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */
>> +#define I915_EXEC_BSD_RING1 (1<<13)
>> +#define I915_EXEC_BSD_RING2 (2<<13)
>> +
>> +#define I915_MADV_WILLNEED 0
>> +#define I915_MADV_DONTNEED 1
>> +
>> +#define I915_TILING_NONE 0
>> +#define I915_TILING_X 1
>> +#define I915_TILING_Y 2
>> +
>> +#define I915_CACHING_NONE 0
>> +#define I915_CACHING_CACHED 1
>> +#define I915_CACHING_DISPLAY 2
>> +
>> +#define I915_BIT_6_SWIZZLE_NONE 0
>> +#define I915_BIT_6_SWIZZLE_9 1
>> +#define I915_BIT_6_SWIZZLE_9_10 2
>> +#define I915_BIT_6_SWIZZLE_9_11 3
>> +#define I915_BIT_6_SWIZZLE_9_10_11 4
>> +#define I915_BIT_6_SWIZZLE_UNKNOWN 5
>> +#define I915_BIT_6_SWIZZLE_9_17 6
>> +#define I915_BIT_6_SWIZZLE_9_10_17 7
>> +
>> +#define I915_PARAM_CHIPSET_ID 4
>> +
>> +#define I915_PARAM_IRQ_ACTIVE 1
>> +#define I915_PARAM_ALLOW_BATCHBUFFER 2
>> +#define I915_PARAM_LAST_DISPATCH 3
>> +#define I915_PARAM_CHIPSET_ID 4
>> +#define I915_PARAM_HAS_GEM 5
>> +#define I915_PARAM_NUM_FENCES_AVAIL 6
>> +#define I915_PARAM_HAS_OVERLAY 7
>> +#define I915_PARAM_HAS_PAGEFLIPPING 8
>> +#define I915_PARAM_HAS_EXECBUF2 9
>> +#define I915_PARAM_HAS_BSD 10
>> +#define I915_PARAM_HAS_BLT 11
>> +#define I915_PARAM_HAS_RELAXED_FENCING 12
>> +#define I915_PARAM_HAS_COHERENT_RINGS 13
>> +#define I915_PARAM_HAS_EXEC_CONSTANTS 14
>> +#define I915_PARAM_HAS_RELAXED_DELTA 15
>> +#define I915_PARAM_HAS_GEN7_SOL_RESET 16
>> +#define I915_PARAM_HAS_LLC 17
>> +#define I915_PARAM_HAS_ALIASING_PPGTT 18
>> +#define I915_PARAM_HAS_WAIT_TIMEOUT 19
>> +#define I915_PARAM_HAS_SEMAPHORES 20
>> +#define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
>> +#define I915_PARAM_HAS_VEBOX 22
>> +#define I915_PARAM_HAS_SECURE_BATCHES 23
>> +#define I915_PARAM_HAS_PINNED_BATCHES 24
>> +#define I915_PARAM_HAS_EXEC_NO_RELOC 25
>> +#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
>> +#define I915_PARAM_HAS_WT 27
>> +#define I915_PARAM_CMD_PARSER_VERSION 28
>> +#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
>> +#define I915_PARAM_MMAP_VERSION 30
>> +#define I915_PARAM_HAS_BSD2 31
>> +#define I915_PARAM_REVISION 32
>> +#define I915_PARAM_SUBSLICE_TOTAL 33
>> +#define I915_PARAM_EU_TOTAL 34
>> +#define I915_PARAM_HAS_GPU_RESET 35
>> +#define I915_PARAM_HAS_RESOURCE_STREAMER 36
>> +#define I915_PARAM_HAS_EXEC_SOFTPIN 37
>> +
>> +#define I915_GEM_DOMAIN_CPU 0x00000001
>> +#define I915_GEM_DOMAIN_RENDER 0x00000002
>> +#define I915_GEM_DOMAIN_SAMPLER 0x00000004
>> +#define I915_GEM_DOMAIN_COMMAND 0x00000008
>> +#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
>> +#define I915_GEM_DOMAIN_VERTEX 0x00000020
>> +#define I915_GEM_DOMAIN_GTT 0x00000040
>> +
>> +#define DRM_I915_INIT 0x00
>> +#define DRM_I915_FLUSH 0x01
>> +#define DRM_I915_FLIP 0x02
>> +#define DRM_I915_BATCHBUFFER 0x03
>> +#define DRM_I915_IRQ_EMIT 0x04
>> +#define DRM_I915_IRQ_WAIT 0x05
>> +#define DRM_I915_GETPARAM 0x06
>> +#define DRM_I915_SETPARAM 0x07
>> +#define DRM_I915_ALLOC 0x08
>> +#define DRM_I915_FREE 0x09
>> +#define DRM_I915_INIT_HEAP 0x0a
>> +#define DRM_I915_CMDBUFFER 0x0b
>> +#define DRM_I915_DESTROY_HEAP 0x0c
>> +#define DRM_I915_SET_VBLANK_PIPE 0x0d
>> +#define DRM_I915_GET_VBLANK_PIPE 0x0e
>> +#define DRM_I915_VBLANK_SWAP 0x0f
>> +#define DRM_I915_HWS_ADDR 0x11
>> +#define DRM_I915_GEM_INIT 0x13
>> +#define DRM_I915_GEM_EXECBUFFER 0x14
>> +#define DRM_I915_GEM_PIN 0x15
>> +#define DRM_I915_GEM_UNPIN 0x16
>> +#define DRM_I915_GEM_BUSY 0x17
>> +#define DRM_I915_GEM_THROTTLE 0x18
>> +#define DRM_I915_GEM_ENTERVT 0x19
>> +#define DRM_I915_GEM_LEAVEVT 0x1a
>> +#define DRM_I915_GEM_CREATE 0x1b
>> +#define DRM_I915_GEM_PREAD 0x1c
>> +#define DRM_I915_GEM_PWRITE 0x1d
>> +#define DRM_I915_GEM_MMAP 0x1e
>> +#define DRM_I915_GEM_SET_DOMAIN 0x1f
>> +#define DRM_I915_GEM_SW_FINISH 0x20
>> +#define DRM_I915_GEM_SET_TILING 0x21
>> +#define DRM_I915_GEM_GET_TILING 0x22
>> +#define DRM_I915_GEM_GET_APERTURE 0x23
>> +#define DRM_I915_GEM_MMAP_GTT 0x24
>> +#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
>> +#define DRM_I915_GEM_MADVISE 0x26
>> +#define DRM_I915_OVERLAY_PUT_IMAGE 0x27
>> +#define DRM_I915_OVERLAY_ATTRS 0x28
>> +#define DRM_I915_GEM_EXECBUFFER2 0x29
>> +#define DRM_I915_GET_SPRITE_COLORKEY 0x2a
>> +#define DRM_I915_SET_SPRITE_COLORKEY 0x2b
>> +#define DRM_I915_GEM_WAIT 0x2c
>> +#define DRM_I915_GEM_CONTEXT_CREATE 0x2d
>> +#define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
>> +#define DRM_I915_GEM_SET_CACHING 0x2f
>> +#define DRM_I915_GEM_GET_CACHING 0x30
>> +#define DRM_I915_REG_READ 0x31
>> +#define DRM_I915_GET_RESET_STATS 0x32
>> +#define DRM_I915_GEM_USERPTR 0x33
>> +#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
>> +#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
>> +
>> +#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
>> +#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
>> +#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
>> +#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
>> +#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
>> +#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
>> +#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
>> +#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
>> +#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
>> +#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
>> +#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
>> +#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
>> +#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
>> +#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
>> +#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
>> +#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
>> +#define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
>> +#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
>> +#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
>> +#define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
>> +#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
>> +#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
>> +#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
>> +#define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
>> +#define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
>> +#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
>> +#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
>> +#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
>> +#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
>> +#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
>> +#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
>> +#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
>> +#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
>> +#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
>> +#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
>> +#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
>> +#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
>> +#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
>> +#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
>> +#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
>> +#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
>> +#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
>> +#define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
>> +#define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
>> +#define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
>> +#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
>> +#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
>> +#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
>> +#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
>> +#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
>> +#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
>> +#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
>> +
>> +enum aub_dump_bmp_format {
>> + AUB_DUMP_BMP_FORMAT_8BIT = 1,
>> + AUB_DUMP_BMP_FORMAT_ARGB_4444 = 4,
>> + AUB_DUMP_BMP_FORMAT_ARGB_0888 = 6,
>> + AUB_DUMP_BMP_FORMAT_ARGB_8888 = 7,
>> +};
>> +
>> +typedef struct _drm_intel_bo drm_intel_bo;
>> +typedef struct _drm_intel_bufmgr drm_intel_bufmgr;
>> +typedef struct _drm_intel_context drm_intel_context;
>> +
>> +struct _drm_intel_context {
>> + unsigned int ctx_id;
>> + struct _drm_intel_bufmgr *bufmgr;
>> +};
>> +
>> +struct _drm_intel_bufmgr {
>> + /**
>> + * Allocate a buffer object.
>> + *
>> + * Buffer objects are not necessarily initially mapped into CPU virtual
>> + * address space or graphics device aperture. They must be mapped
>> + * using bo_map() or drm_intel_gem_bo_map_gtt() to be used by the CPU.
>> + */
>> + drm_intel_bo *(*bo_alloc) (drm_intel_bufmgr *bufmgr, const char *name,
>> + unsigned long size, unsigned int alignment);
>> +
>> + /**
>> + * Allocate a buffer object, hinting that it will be used as a
>> + * render target.
>> + *
>> + * This is otherwise the same as bo_alloc.
>> + */
>> + drm_intel_bo *(*bo_alloc_for_render) (drm_intel_bufmgr *bufmgr,
>> + const char *name,
>> + unsigned long size,
>> + unsigned int alignment);
>> +
>> + /**
>> + * Allocate a buffer object from an existing user accessible
>> + * address malloc'd with the provided size.
>> + * Alignment is used when mapping to the gtt.
>> + * Flags may be I915_VMAP_READ_ONLY or I915_USERPTR_UNSYNCHRONIZED
>> + */
>> + drm_intel_bo *(*bo_alloc_userptr)(drm_intel_bufmgr *bufmgr,
>> + const char *name, void *addr,
>> + uint32_t tiling_mode, uint32_t stride,
>> + unsigned long size,
>> + unsigned long flags);
>> +
>> + /**
>> + * Allocate a tiled buffer object.
>> + *
>> + * Alignment for tiled objects is set automatically; the 'flags'
>> + * argument provides a hint about how the object will be used initially.
>> + *
>> + * Valid tiling formats are:
>> + * I915_TILING_NONE
>> + * I915_TILING_X
>> + * I915_TILING_Y
>> + *
>> + * Note the tiling format may be rejected; callers should check the
>> + * 'tiling_mode' field on return, as well as the pitch value, which
>> + * may have been rounded up to accommodate for tiling restrictions.
>> + */
>> + drm_intel_bo *(*bo_alloc_tiled) (drm_intel_bufmgr *bufmgr,
>> + const char *name,
>> + int x, int y, int cpp,
>> + uint32_t *tiling_mode,
>> + unsigned long *pitch,
>> + unsigned long flags);
>> +
>> + /** Takes a reference on a buffer object */
>> + void (*bo_reference) (drm_intel_bo *bo);
>> +
>> + /**
>> + * Releases a reference on a buffer object, freeing the data if
>> + * no references remain.
>> + */
>> + void (*bo_unreference) (drm_intel_bo *bo);
>> +
>> + /**
>> + * Maps the buffer into userspace.
>> + *
>> + * This function will block waiting for any existing execution on the
>> + * buffer to complete, first. The resulting mapping is available at
>> + * buf->virtual.
>> + */
>> + int (*bo_map) (drm_intel_bo *bo, int write_enable);
>> +
>> + /**
>> + * Reduces the refcount on the userspace mapping of the buffer
>> + * object.
>> + */
>> + int (*bo_unmap) (drm_intel_bo *bo);
>> +
>> + /**
>> + * Write data into an object.
>> + *
>> + * This is an optional function, if missing,
>> + * drm_intel_bo will map/memcpy/unmap.
>> + */
>> + int (*bo_subdata) (drm_intel_bo *bo, unsigned long offset,
>> + unsigned long size, const void *data);
>> +
>> + /**
>> + * Read data from an object
>> + *
>> + * This is an optional function, if missing,
>> + * drm_intel_bo will map/memcpy/unmap.
>> + */
>> + int (*bo_get_subdata) (drm_intel_bo *bo, unsigned long offset,
>> + unsigned long size, void *data);
>> +
>> + /**
>> + * Waits for rendering to an object by the GPU to have completed.
>> + *
>> + * This is not required for any access to the BO by bo_map,
>> + * bo_subdata, etc. It is merely a way for the driver to implement
>> + * glFinish.
>> + */
>> + void (*bo_wait_rendering) (drm_intel_bo *bo);
>> +
>> + /**
>> + * Tears down the buffer manager instance.
>> + */
>> + void (*destroy) (drm_intel_bufmgr *bufmgr);
>> +
>> + /**
>> + * Indicate if the buffer can be placed anywhere in the full ppgtt
>> + * address range (2^48).
>> + *
>> + * Any resource used with flat/heapless (0x00000000-0xfffff000)
>> + * General State Heap (GSH) or Intructions State Heap (ISH) must
>> + * be in a 32-bit range. 48-bit range will only be used when explicitly
>> + * requested.
>> + *
>> + * \param bo Buffer to set the use_48b_address_range flag.
>> + * \param enable The flag value.
>> + */
>> + void (*bo_use_48b_address_range) (drm_intel_bo *bo, uint32_t enable);
>> +
>> + /**
>> + * Add relocation entry in reloc_buf, which will be updated with the
>> + * target buffer's real offset on on command submission.
>> + *
>> + * Relocations remain in place for the lifetime of the buffer object.
>> + *
>> + * \param bo Buffer to write the relocation into.
>> + * \param offset Byte offset within reloc_bo of the pointer to
>> + * target_bo.
>> + * \param target_bo Buffer whose offset should be written into the
>> + * relocation entry.
>> + * \param target_offset Constant value to be added to target_bo's
>> + * offset in relocation entry.
>> + * \param read_domains GEM read domains which the buffer will be
>> + * read into by the command that this relocation
>> + * is part of.
>> + * \param write_domains GEM read domains which the buffer will be
>> + * dirtied in by the command that this
>> + * relocation is part of.
>> + */
>> + int (*bo_emit_reloc) (drm_intel_bo *bo, uint32_t offset,
>> + drm_intel_bo *target_bo, uint32_t target_offset,
>> + uint32_t read_domains, uint32_t write_domain);
>> + int (*bo_emit_reloc_fence)(drm_intel_bo *bo, uint32_t offset,
>> + drm_intel_bo *target_bo,
>> + uint32_t target_offset,
>> + uint32_t read_domains,
>> + uint32_t write_domain);
>> +
>> + /** Executes the command buffer pointed to by bo. */
>> + int (*bo_exec) (drm_intel_bo *bo, int used,
>> + drm_clip_rect_t *cliprects, int num_cliprects,
>> + int DR4);
>> +
>> + /** Executes the command buffer pointed to by bo on the selected
>> + * ring buffer
>> + */
>> + int (*bo_mrb_exec) (drm_intel_bo *bo, int used,
>> + drm_clip_rect_t *cliprects, int num_cliprects,
>> + int DR4, unsigned flags);
>> +
>> + /**
>> + * Pin a buffer to the aperture and fix the offset until unpinned
>> + *
>> + * \param buf Buffer to pin
>> + * \param alignment Required alignment for aperture, in bytes
>> + */
>> + int (*bo_pin) (drm_intel_bo *bo, uint32_t alignment);
>> +
>> + /**
>> + * Unpin a buffer from the aperture, allowing it to be removed
>> + *
>> + * \param buf Buffer to unpin
>> + */
>> + int (*bo_unpin) (drm_intel_bo *bo);
>> +
>> + /**
>> + * Ask that the buffer be placed in tiling mode
>> + *
>> + * \param buf Buffer to set tiling mode for
>> + * \param tiling_mode desired, and returned tiling mode
>> + */
>> + int (*bo_set_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode,
>> + uint32_t stride);
>> +
>> + /**
>> + * Get the current tiling (and resulting swizzling) mode for the bo.
>> + *
>> + * \param buf Buffer to get tiling mode for
>> + * \param tiling_mode returned tiling mode
>> + * \param swizzle_mode returned swizzling mode
>> + */
>> + int (*bo_get_tiling) (drm_intel_bo *bo, uint32_t * tiling_mode,
>> + uint32_t * swizzle_mode);
>> +
>> + /**
>> + * Set the offset at which this buffer will be softpinned
>> + * \param bo Buffer to set the softpin offset for
>> + * \param offset Softpin offset
>> + */
>> + int (*bo_set_softpin_offset) (drm_intel_bo *bo, uint64_t offset);
>> +
>> + /**
>> + * Create a visible name for a buffer which can be used by other apps
>> + *
>> + * \param buf Buffer to create a name for
>> + * \param name Returned name
>> + */
>> + int (*bo_flink) (drm_intel_bo *bo, uint32_t * name);
>> +
>> + /**
>> + * Returns 1 if mapping the buffer for write could cause the process
>> + * to block, due to the object being active in the GPU.
>> + */
>> + int (*bo_busy) (drm_intel_bo *bo);
>> +
>> + /**
>> + * Specify the volatility of the buffer.
>> + * \param bo Buffer to create a name for
>> + * \param madv The purgeable status
>> + *
>> + * Use I915_MADV_DONTNEED to mark the buffer as purgeable, and it will be
>> + * reclaimed under memory pressure. If you subsequently require the buffer,
>> + * then you must pass I915_MADV_WILLNEED to mark the buffer as required.
>> + *
>> + * Returns 1 if the buffer was retained, or 0 if it was discarded whilst
>> + * marked as I915_MADV_DONTNEED.
>> + */
>> + int (*bo_madvise) (drm_intel_bo *bo, int madv);
>> +
>> + int (*check_aperture_space) (drm_intel_bo ** bo_array, int count);
>> +
>> + /**
>> + * Disable buffer reuse for buffers which will be shared in some way,
>> + * as with scanout buffers. When the buffer reference count goes to
>> + * zero, it will be freed and not placed in the reuse list.
>> + *
>> + * \param bo Buffer to disable reuse for
>> + */
>> + int (*bo_disable_reuse) (drm_intel_bo *bo);
>> +
>> + /**
>> + * Query whether a buffer is reusable.
>> + *
>> + * \param bo Buffer to query
>> + */
>> + int (*bo_is_reusable) (drm_intel_bo *bo);
>> +
>> + /**
>> + *
>> + * Return the pipe associated with a crtc_id so that vblank
>> + * synchronization can use the correct data in the request.
>> + * This is only supported for KMS and gem at this point, when
>> + * unsupported, this function returns -1 and leaves the decision
>> + * of what to do in that case to the caller
>> + *
>> + * \param bufmgr the associated buffer manager
>> + * \param crtc_id the crtc identifier
>> + */
>> + int (*get_pipe_from_crtc_id) (drm_intel_bufmgr *bufmgr, int crtc_id);
>> +
>> + /** Returns true if target_bo is in the relocation tree rooted at bo. */
>> + int (*bo_references) (drm_intel_bo *bo, drm_intel_bo *target_bo);
>> +
>> + /**< Enables verbose debugging printouts */
>> + int debug;
>> +};
>> +
>> +struct _drm_intel_bo {
>> + /**
>> + * Size in bytes of the buffer object.
>> + *
>> + * The size may be larger than the size originally requested for the
>> + * allocation, such as being aligned to page size.
>> + */
>> + unsigned long size;
>> +
>> + /**
>> + * Alignment requirement for object
>> + *
>> + * Used for GTT mapping & pinning the object.
>> + */
>> + unsigned long align;
>> +
>> + /**
>> + * Deprecated field containing (possibly the low 32-bits of) the last
>> + * seen virtual card address. Use offset64 instead.
>> + */
>> + unsigned long offset;
>> +
>> + /**
>> + * Virtual address for accessing the buffer data. Only valid while
>> + * mapped.
>> + */
>> +#ifdef __cplusplus
>> + void *virt;
>> +#else
>> + void *virtual;
>> +#endif
>> +
>> + /** Buffer manager context associated with this buffer object */
>> + drm_intel_bufmgr *bufmgr;
>> +
>> + /**
>> + * MM-specific handle for accessing object
>> + */
>> + int handle;
>> +
>> + /**
>> + * Last seen card virtual address (offset from the beginning of the
>> + * aperture) for the object. This should be used to fill relocation
>> + * entries when calling drm_intel_bo_emit_reloc()
>> + */
>> + uint64_t offset64;
>> +};
>> +
>> +typedef struct drm_i915_getparam {
>> + __s32 param;
>> + /*
>> + * WARNING: Using pointers instead of fixed-size u64 means we need to write
>> + * compat32 code. Don't repeat this mistake.
>> + */
>> + int *value;
>> +} drm_i915_getparam_t;
>> +
>> +struct drm_i915_gem_execbuffer2 {
>> + /**
>> + * List of gem_exec_object2 structs
>> + */
>> + __u64 buffers_ptr;
>> + __u32 buffer_count;
>> +
>> + /** Offset in the batchbuffer to start execution from. */
>> + __u32 batch_start_offset;
>> + /** Bytes used in batchbuffer from batch_start_offset */
>> + __u32 batch_len;
>> + __u32 DR1;
>> + __u32 DR4;
>> + __u32 num_cliprects;
>> + /** This is a struct drm_clip_rect *cliprects */
>> + __u64 cliprects_ptr;
>> +#define I915_EXEC_RING_MASK (7<<0)
>> +#define I915_EXEC_DEFAULT (0<<0)
>> +#define I915_EXEC_RENDER (1<<0)
>> +#define I915_EXEC_BSD (2<<0)
>> +#define I915_EXEC_BLT (3<<0)
>> +#define I915_EXEC_VEBOX (4<<0)
>> +
>> +/* Used for switching the constants addressing mode on gen4+ RENDER ring.
>> + * Gen6+ only supports relative addressing to dynamic state (default) and
>> + * absolute addressing.
>> + *
>> + * These flags are ignored for the BSD and BLT rings.
>> + */
>> +#define I915_EXEC_CONSTANTS_MASK (3<<6)
>> +#define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
>> +#define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
>> +#define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
>> + __u64 flags;
>> + __u64 rsvd1; /* now used for context info */
>> + __u64 rsvd2;
>> +};
>> +
>> +struct drm_i915_gem_exec_object2 {
>> + /**
>> + * User's handle for a buffer to be bound into the GTT for this
>> + * operation.
>> + */
>> + __u32 handle;
>> +
>> + /** Number of relocations to be performed on this buffer */
>> + __u32 relocation_count;
>> + /**
>> + * Pointer to array of struct drm_i915_gem_relocation_entry containing
>> + * the relocations to be performed in this buffer.
>> + */
>> + __u64 relocs_ptr;
>> +
>> + /** Required alignment in graphics aperture */
>> + __u64 alignment;
>> +
>> + /**
>> + * When the EXEC_OBJECT_PINNED flag is specified this is populated by
>> + * the user with the GTT offset at which this object will be pinned.
>> + * When the I915_EXEC_NO_RELOC flag is specified this must contain the
>> + * presumed_offset of the object.
>> + * During execbuffer2 the kernel populates it with the value of the
>> + * current GTT offset of the object, for future presumed_offset writes.
>> + */
>> + __u64 offset;
>> +
>> +#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
>> +#define EXEC_OBJECT_NEEDS_GTT (1<<1)
>> +#define EXEC_OBJECT_WRITE (1<<2)
>> +#define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
>> +#define EXEC_OBJECT_PINNED (1<<4)
>> +#define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PINNED<<1)
>> + __u64 flags;
>> +
>> + __u64 rsvd1;
>> + __u64 rsvd2;
>> +};
>> +
>> +struct drm_i915_gem_relocation_entry {
>> + /**
>> + * Handle of the buffer being pointed to by this relocation entry.
>> + *
>> + * It's appealing to make this be an index into the mm_validate_entry
>> + * list to refer to the buffer, but this allows the driver to create
>> + * a relocation list for state buffers and not re-write it per
>> + * exec using the buffer.
>> + */
>> + __u32 target_handle;
>> +
>> + /**
>> + * Value to be added to the offset of the target buffer to make up
>> + * the relocation entry.
>> + */
>> + __u32 delta;
>> +
>> + /** Offset in the buffer the relocation entry will be written into */
>> + __u64 offset;
>> +
>> + /**
>> + * Offset value of the target buffer that the relocation entry was last
>> + * written as.
>> + *
>> + * If the buffer has the same offset as last time, we can skip syncing
>> + * and writing the relocation. This value is written back out by
>> + * the execbuffer ioctl when the relocation is written.
>> + */
>> + __u64 presumed_offset;
>> +
>> + /**
>> + * Target memory domains read by this operation.
>> + */
>> + __u32 read_domains;
>> +
>> + /**
>> + * Target memory domains written by this operation.
>> + *
>> + * Note that only one domain may be written by the whole
>> + * execbuffer operation, so that where there are conflicts,
>> + * the application will get -EINVAL back.
>> + */
>> + __u32 write_domain;
>> +};
>> +
>> +struct drm_i915_gem_get_tiling {
>> + /** Handle of the buffer to get tiling state for. */
>> + __u32 handle;
>> +
>> + /**
>> + * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
>> + * I915_TILING_Y).
>> + */
>> + __u32 tiling_mode;
>> +
>> + /**
>> + * Returned address bit 6 swizzling required for CPU access through
>> + * mmap mapping.
>> + */
>> + __u32 swizzle_mode;
>> +
>> + /**
>> + * Returned address bit 6 swizzling required for CPU access through
>> + * mmap mapping whilst bound.
>> + */
>> + __u32 phys_swizzle_mode;
>> +};
>> +
>> +struct drm_i915_gem_set_tiling {
>> + /** Handle of the buffer to have its tiling state updated */
>> + __u32 handle;
>> +
>> + /**
>> + * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
>> + * I915_TILING_Y).
>> + *
>> + * This value is to be set on request, and will be updated by the
>> + * kernel on successful return with the actual chosen tiling layout.
>> + *
>> + * The tiling mode may be demoted to I915_TILING_NONE when the system
>> + * has bit 6 swizzling that can't be managed correctly by GEM.
>> + *
>> + * Buffer contents become undefined when changing tiling_mode.
>> + */
>> + __u32 tiling_mode;
>> +
>> + /**
>> + * Stride in bytes for the object when in I915_TILING_X or
>> + * I915_TILING_Y.
>> + */
>> + __u32 stride;
>> +
>> + /**
>> + * Returned address bit 6 swizzling required for CPU access through
>> + * mmap mapping.
>> + */
>> + __u32 swizzle_mode;
>> +};
>> +
>> +struct drm_i915_gem_pwrite {
>> + /** Handle for the object being written to. */
>> + __u32 handle;
>> + __u32 pad;
>> + /** Offset into the object to write to */
>> + __u64 offset;
>> + /** Length of data to write */
>> + __u64 size;
>> + /**
>> + * Pointer to read the data from.
>> + *
>> + * This is a fixed-size type for 32/64 compatibility.
>> + */
>> + __u64 data_ptr;
>> +};
>> +
>> +struct drm_i915_gem_pread {
>> + /** Handle for the object being read. */
>> + __u32 handle;
>> + __u32 pad;
>> + /** Offset into the object to read from */
>> + __u64 offset;
>> + /** Length of data to read */
>> + __u64 size;
>> + /**
>> + * Pointer to write the data into.
>> + *
>> + * This is a fixed-size type for 32/64 compatibility.
>> + */
>> + __u64 data_ptr;
>> +};
>> +
>> +struct drm_i915_gem_set_domain {
>> + /** Handle for the object */
>> + __u32 handle;
>> +
>> + /** New read domains */
>> + __u32 read_domains;
>> +
>> + /** New write domain */
>> + __u32 write_domain;
>> +};
>> +
>> +struct drm_i915_gem_wait {
>> + /** Handle of BO we shall wait on */
>> + __u32 bo_handle;
>> + __u32 flags;
>> + /** Number of nanoseconds to wait, Returns time remaining. */
>> + __s64 timeout_ns;
>> +};
>> +
>> +struct drm_i915_gem_busy {
>> + /** Handle of the buffer to check for busy */
>> + __u32 handle;
>> +
>> + /** Return busy status (1 if busy, 0 if idle).
>> + * The high word is used to indicate on which rings the object
>> + * currently resides:
>> + * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
>> + */
>> + __u32 busy;
>> +};
>> +
>> +struct drm_i915_gem_get_aperture {
>> + /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
>> + __u64 aper_size;
>> +
>> + /**
>> + * Available space in the aperture used by i915_gem_execbuffer, in
>> + * bytes
>> + */
>> + __u64 aper_available_size;
>> +};
>> +
>> +struct drm_i915_gem_create {
>> + /**
>> + * Requested size for the object.
>> + *
>> + * The (page-aligned) allocated size for the object will be returned.
>> + */
>> + __u64 size;
>> + /**
>> + * Returned handle for the object.
>> + *
>> + * Object handles are nonzero.
>> + */
>> + __u32 handle;
>> + __u32 pad;
>> +};
>> +
>> +struct drm_i915_gem_mmap_gtt {
>> + /** Handle for the object being mapped. */
>> + __u32 handle;
>> + __u32 pad;
>> + /**
>> + * Fake offset to use for subsequent mmap call
>> + *
>> + * This is a fixed-size type for 32/64 compatibility.
>> + */
>> + __u64 offset;
>> +};
>> +
>> +struct drm_i915_gem_sw_finish {
>> + /** Handle for the object */
>> + __u32 handle;
>> +};
>> +
>> +struct drm_i915_gem_mmap {
>> + /** Handle for the object being mapped. */
>> + __u32 handle;
>> + __u32 pad;
>> + /** Offset in the object to map. */
>> + __u64 offset;
>> + /**
>> + * Length of data to map.
>> + *
>> + * The value will be page-aligned.
>> + */
>> + __u64 size;
>> + /**
>> + * Returned pointer the data was mapped at.
>> + *
>> + * This is a fixed-size type for 32/64 compatibility.
>> + */
>> + __u64 addr_ptr;
>> +
>> + /**
>> + * Flags for extended behaviour.
>> + *
>> + * Added in version 2.
>> + */
>> + __u64 flags;
>> +#define I915_MMAP_WC 0x1
>> +};
>> +
>> +struct drm_i915_gem_madvise {
>> + /** Handle of the buffer to change the backing store advice */
>> + __u32 handle;
>> +
>> + /* Advice: either the buffer will be needed again in the near future,
>> + * or wont be and could be discarded under memory pressure.
>> + */
>> + __u32 madv;
>> +
>> + /** Whether the backing store still exists. */
>> + __u32 retained;
>> +};
>> +
>> +struct drm_i915_gem_context_create {
>> + /* output: id of new context*/
>> + __u32 ctx_id;
>> + __u32 pad;
>> +};
>> +
>> +struct drm_i915_gem_context_destroy {
>> + __u32 ctx_id;
>> + __u32 pad;
>> +};
>> +
>> +typedef struct _drm_intel_aub_annotation {
>> + uint32_t type;
>> + uint32_t subtype;
>> + uint32_t ending_offset;
>> +} drm_intel_aub_annotation;
>> +
>> +struct drm_i915_gem_pin {
>> + /** Handle of the buffer to be pinned. */
>> + __u32 handle;
>> + __u32 pad;
>> +
>> + /** alignment required within the aperture */
>> + __u64 alignment;
>> +
>> + /** Returned GTT offset of the buffer. */
>> + __u64 offset;
>> +};
>> +
>> +#define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
>> +#define I915_SET_COLORKEY_DESTINATION (1<<1)
>> +#define I915_SET_COLORKEY_SOURCE (1<<2)
>> +struct drm_intel_sprite_colorkey {
>> + __u32 plane_id;
>> + __u32 min_value;
>> + __u32 channel_mask;
>> + __u32 max_value;
>> + __u32 flags;
>> +};
>> +
>> +struct drm_i915_reg_read {
>> + /*
>> + * Register offset.
>> + * For 64bit wide registers where the upper 32bits don't immediately
>> + * follow the lower 32bits, the offset of the lower 32bits must
>> + * be specified
>> + */
>> + __u64 offset;
>> + __u64 val; /* Return value */
>> +};
>> +
>> +drm_intel_bufmgr *drm_intel_bufmgr_gem_init(int fd, int batch_size);
>> +void drm_intel_bo_unreference(drm_intel_bo *bo);
>> +drm_intel_bo *drm_intel_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
>> + unsigned long size, unsigned int alignment);
>> +int drm_intel_bo_subdata(drm_intel_bo *bo, unsigned long offset,
>> + unsigned long size, const void *data);
>> +int drm_intel_gem_bo_context_exec(drm_intel_bo *bo, drm_intel_context *ctx,
>> + int used, unsigned int flags);
>> +int drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
>> + drm_intel_bo *target_bo, uint32_t target_offset,
>> + uint32_t read_domains, uint32_t write_domain);
>> +int drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset,
>> + drm_intel_bo *target_bo,
>> + uint32_t target_offset,
>> + uint32_t read_domains, uint32_t write_domain);
>> +int drm_intel_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
>> + uint32_t * swizzle_mode);
>> +int drm_intel_bo_mrb_exec(drm_intel_bo *bo, int used,
>> + struct drm_clip_rect *cliprects, int num_cliprects, int DR4,
>> + unsigned int flags);
>> +void drm_intel_bufmgr_gem_set_aub_annotations(drm_intel_bo *bo,
>> + drm_intel_aub_annotation *annotations,
>> + unsigned count);
>> +void drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr);
>> +int drm_intel_bo_exec(drm_intel_bo *bo, int used,
>> + struct drm_clip_rect *cliprects, int num_cliprects, int DR4);
>> +void drm_intel_bufmgr_destroy(drm_intel_bufmgr *bufmgr);
>> +void drm_intel_bo_wait_rendering(drm_intel_bo *bo);
>> +int drm_intel_bo_get_subdata(drm_intel_bo *bo, unsigned long offset,
>> + unsigned long size, void *data);
>> +int drm_intel_bo_map(drm_intel_bo *bo, int write_enable);
>> +int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo);
>> +void drm_intel_bufmgr_gem_enable_fenced_relocs(drm_intel_bufmgr *bufmgr);
>> +int drm_intel_bo_unmap(drm_intel_bo *bo);
>> +int drm_intel_bo_flink(drm_intel_bo *bo, uint32_t * name);
>> +drm_intel_bo *drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr,
>> + const char *name,
>> + unsigned int handle);
>> +int drm_intel_bo_gem_export_to_prime(drm_intel_bo *bo, int *prime_fd);
>> +drm_intel_bo *drm_intel_bo_gem_create_from_prime(drm_intel_bufmgr *bufmgr,
>> + int prime_fd, int size);
>> +void drm_intel_bufmgr_gem_set_vma_cache_size(drm_intel_bufmgr *bufmgr,
>> + int limit);
>> +int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo);
>> +drm_intel_context *drm_intel_gem_context_create(drm_intel_bufmgr *bufmgr);
>> +void drm_intel_gem_context_destroy(drm_intel_context *ctx);
>> +drm_intel_bo *drm_intel_bo_alloc_tiled(drm_intel_bufmgr *bufmgr,
>> + const char *name,
>> + int x, int y, int cpp,
>> + uint32_t *tiling_mode,
>> + unsigned long *pitch,
>> + unsigned long flags);
>> +void drm_intel_bufmgr_gem_set_aub_filename(drm_intel_bufmgr *bufmgr,
>> + const char *filename);
>> +void drm_intel_bufmgr_gem_set_aub_dump(drm_intel_bufmgr *bufmgr, int enable);
>> +void drm_intel_gem_bo_aub_dump_bmp(drm_intel_bo *bo,
>> + int x1, int y1, int width, int height,
>> + enum aub_dump_bmp_format format,
>> + int pitch, int offset);
>> +void drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable);
>> +int drm_intel_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode,
>> + uint32_t stride);
>> +int drm_intel_bo_disable_reuse(drm_intel_bo *bo);
>> +void drm_intel_bo_reference(drm_intel_bo *bo);
>> +int drm_intel_bufmgr_gem_get_devid(drm_intel_bufmgr *bufmgr);
>> +drm_intel_bo *drm_intel_bo_alloc_for_render(drm_intel_bufmgr *bufmgr,
>> + const char *name,
>> + unsigned long size,
>> + unsigned int alignment);
>> +int drm_intel_bo_references(drm_intel_bo *bo, drm_intel_bo *target_bo);
>> +int drm_intel_gem_bo_wait(drm_intel_bo *bo, int64_t timeout_ns);
>> +
>> +#endif
>> +
>> +#endif//INTEL_DRM_STUBS_H
>> --
>> 2.7.4
>>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [RFC i-g-t 8/9] lib: Replace intel specific header includes with intel_drm_stubs.h.
2016-05-24 8:07 ` Daniel Vetter
@ 2016-05-25 18:00 ` Robert Foss
0 siblings, 0 replies; 29+ messages in thread
From: Robert Foss @ 2016-05-25 18:00 UTC (permalink / raw)
To: Daniel Vetter
Cc: daniel.stone, tomeu.vizoso, daniel.vetter, intel-gfx, emil.velikov
On 2016-05-24 04:07 AM, Daniel Vetter wrote:
> On Fri, May 20, 2016 at 06:59:32PM -0400, robert.foss@collabora.com wrote:
>> From: Robert Foss <robert.foss@collabora.com>
>>
>> Replace intel specific header includes with intel_drm_stubs.h.
>>
>> The stubbed functions will all call igt_require(false) and cause a skip.
>>
>> Signed-off-by: Robert Foss <robert.foss@collabora.com>
>
> Do we need this sed job really? I kinda hoped we could have a dummy header
> somewhere, like lib/stubs/drm/i915_drm.h and similar (instead of your
> intel_drm_stubs.h), and then add lib/stubs/ to the include path when
> !HAVE_LIBDRM_INTEL? That way 0 changes to tests/lib itself should be
> needed.
> -Daniel
This is a much cleaner solution, I've added it to v2. I'm somewhat
worried about not having grokked the automake syntax for including the
correct header files depending in HAVE_LIBDRM_INTEL though.
Rob.
>
>> ---
>> lib/drmtest.c | 2 +-
>> lib/gpgpu_fill.c | 7 +++----
>> lib/igt_aux.c | 2 +-
>> lib/igt_aux.h | 3 ++-
>> lib/igt_debugfs.c | 4 ++--
>> lib/igt_draw.h | 3 +--
>> lib/igt_fb.h | 3 ++-
>> lib/igt_kms.c | 3 +--
>> lib/intel_batchbuffer.c | 4 ----
>> lib/intel_batchbuffer.h | 3 +--
>> lib/intel_chipset.c | 2 +-
>> lib/ioctl_wrappers.c | 1 -
>> lib/ioctl_wrappers.h | 4 ++--
>> lib/media_fill_gen7.c | 3 +--
>> lib/media_fill_gen8.c | 4 +---
>> lib/media_fill_gen8lp.c | 6 ++----
>> lib/media_fill_gen9.c | 4 +---
>> lib/media_spin.c | 2 --
>> lib/rendercopy_gen6.c | 5 ++---
>> lib/rendercopy_gen7.c | 4 +---
>> lib/rendercopy_gen8.c | 4 +---
>> lib/rendercopy_gen9.c | 5 +----
>> lib/rendercopy_i830.c | 5 +----
>> lib/rendercopy_i915.c | 9 +++------
>> 24 files changed, 31 insertions(+), 61 deletions(-)
>>
>> diff --git a/lib/drmtest.c b/lib/drmtest.c
>> index 7d6b74a..f043607 100644
>> --- a/lib/drmtest.c
>> +++ b/lib/drmtest.c
>> @@ -48,13 +48,13 @@
>> #include <termios.h>
>>
>> #include "drmtest.h"
>> -#include "i915_drm.h"
>> #include "intel_chipset.h"
>> #include "intel_io.h"
>> #include "igt_gt.h"
>> #include "igt_debugfs.h"
>> #include "version.h"
>> #include "config.h"
>> +#include "intel_drm_stubs.h"
>> #include "intel_reg.h"
>> #include "ioctl_wrappers.h"
>>
>> diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
>> index 4d98643..62b1161 100644
>> --- a/lib/gpgpu_fill.c
>> +++ b/lib/gpgpu_fill.c
>> @@ -25,15 +25,14 @@
>> * Dominik Zeromski <dominik.zeromski@intel.com>
>> */
>>
>> -#include <intel_bufmgr.h>
>> -#include <i915_drm.h>
>>
>> -#include "intel_reg.h"
>> #include "drmtest.h"
>> -#include "intel_batchbuffer.h"
>> #include "gen7_media.h"
>> #include "gen8_media.h"
>> #include "gpgpu_fill.h"
>> +#include "intel_batchbuffer.h"
>> +#include "intel_drm_stubs.h"
>> +#include "intel_reg.h"
>>
>> /* shaders/gpgpu/gpgpu_fill.gxa */
>> static const uint32_t gen7_gpgpu_kernel[][4] = {
>> diff --git a/lib/igt_aux.c b/lib/igt_aux.c
>> index fe18365..772c902 100644
>> --- a/lib/igt_aux.c
>> +++ b/lib/igt_aux.c
>> @@ -52,12 +52,12 @@
>> #include <assert.h>
>>
>> #include "drmtest.h"
>> -#include "i915_drm.h"
>> #include "intel_chipset.h"
>> #include "igt_aux.h"
>> #include "igt_debugfs.h"
>> #include "igt_gt.h"
>> #include "config.h"
>> +#include "intel_drm_stubs.h"
>> #include "intel_reg.h"
>> #include "ioctl_wrappers.h"
>> #include "igt_kms.h"
>> diff --git a/lib/igt_aux.h b/lib/igt_aux.h
>> index f66de72..c66121b 100644
>> --- a/lib/igt_aux.h
>> +++ b/lib/igt_aux.h
>> @@ -28,10 +28,11 @@
>> #ifndef IGT_AUX_H
>> #define IGT_AUX_H
>>
>> -#include <intel_bufmgr.h>
>> #include <stdbool.h>
>> #include <sys/time.h>
>>
>> +#include "intel_drm_stubs.h"
>> +
>> extern drm_intel_bo **trash_bos;
>> extern int num_trash_bos;
>>
>> diff --git a/lib/igt_debugfs.c b/lib/igt_debugfs.c
>> index a32ed78..d9f371f 100644
>> --- a/lib/igt_debugfs.c
>> +++ b/lib/igt_debugfs.c
>> @@ -32,12 +32,12 @@
>> #include <string.h>
>> #include <fcntl.h>
>> #include <unistd.h>
>> -#include <i915_drm.h>
>>
>> #include "drmtest.h"
>> +#include "intel_drm_stubs.h"
>> #include "igt_aux.h"
>> -#include "igt_kms.h"
>> #include "igt_debugfs.h"
>> +#include "igt_kms.h"
>>
>> /**
>> * SECTION:igt_debugfs
>> diff --git a/lib/igt_draw.h b/lib/igt_draw.h
>> index b030131..c0e95ca 100644
>> --- a/lib/igt_draw.h
>> +++ b/lib/igt_draw.h
>> @@ -25,9 +25,8 @@
>> #ifndef __IGT_DRAW_H__
>> #define __IGT_DRAW_H__
>>
>> -#include <intel_bufmgr.h>
>> #include "igt_fb.h"
>> -
>> +#include "intel_drm_stubs.h"
>> /**
>> * igt_draw_method:
>> * @IGT_DRAW_MMAP_CPU: draw using a CPU mmap.
>> diff --git a/lib/igt_fb.h b/lib/igt_fb.h
>> index ce2cc0f..82dbacb 100644
>> --- a/lib/igt_fb.h
>> +++ b/lib/igt_fb.h
>> @@ -38,10 +38,11 @@ typedef struct _cairo cairo_t;
>>
>> #include <stddef.h>
>> #include <stdbool.h>
>> +#include <stdint.h>
>> #include <drm_fourcc.h>
>> #include <xf86drmMode.h>
>>
>> -#include <i915_drm.h>
>> +#include "intel_drm_stubs.h"
>>
>> /* helpers to create nice-looking framebuffers */
>> struct igt_fb {
>> diff --git a/lib/igt_kms.c b/lib/igt_kms.c
>> index f85be1e..7afee53 100644
>> --- a/lib/igt_kms.c
>> +++ b/lib/igt_kms.c
>> @@ -41,12 +41,11 @@
>> #include <errno.h>
>> #include <time.h>
>>
>> -#include <i915_drm.h>
>> -
>> #include "drmtest.h"
>> #include "igt_kms.h"
>> #include "igt_aux.h"
>> #include "intel_chipset.h"
>> +#include "intel_drm_stubs.h"
>> #include "igt_debugfs.h"
>>
>> /* list of connectors that need resetting on exit */
>> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
>> index 692521f..a28eb33 100644
>> --- a/lib/intel_batchbuffer.c
>> +++ b/lib/intel_batchbuffer.c
>> @@ -31,10 +31,8 @@
>> #include <string.h>
>> #include <assert.h>
>>
>> -#include "drm.h"
>> #include "drmtest.h"
>> #include "intel_batchbuffer.h"
>> -#include "intel_bufmgr.h"
>> #include "intel_chipset.h"
>> #include "intel_reg.h"
>> #include "rendercopy.h"
>> @@ -43,8 +41,6 @@
>> #include "media_spin.h"
>> #include "gpgpu_fill.h"
>>
>> -#include <i915_drm.h>
>> -
>> /**
>> * SECTION:intel_batchbuffer
>> * @short_description: Batchbuffer and blitter support
>> diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
>> index 869747d..bd365db 100644
>> --- a/lib/intel_batchbuffer.h
>> +++ b/lib/intel_batchbuffer.h
>> @@ -2,10 +2,9 @@
>> #define INTEL_BATCHBUFFER_H
>>
>> #include <stdint.h>
>> -#include <intel_bufmgr.h>
>> -#include <i915_drm.h>
>>
>> #include "igt_core.h"
>> +#include "intel_drm_stubs.h"
>> #include "intel_reg.h"
>>
>> #define BATCH_SZ 4096
>> diff --git a/lib/intel_chipset.c b/lib/intel_chipset.c
>> index 56746b0..6ac74e9 100644
>> --- a/lib/intel_chipset.c
>> +++ b/lib/intel_chipset.c
>> @@ -36,9 +36,9 @@
>> #include <fcntl.h>
>> #include <sys/stat.h>
>> #include <sys/mman.h>
>> -#include "i915_drm.h"
>>
>> #include "drmtest.h"
>> +#include "intel_drm_stubs.h"
>> #include "intel_chipset.h"
>> #include "igt_core.h"
>>
>> diff --git a/lib/ioctl_wrappers.c b/lib/ioctl_wrappers.c
>> index f224091..e46811a 100644
>> --- a/lib/ioctl_wrappers.c
>> +++ b/lib/ioctl_wrappers.c
>> @@ -50,7 +50,6 @@
>> #include <errno.h>
>>
>> #include "drmtest.h"
>> -#include "i915_drm.h"
>> #include "intel_chipset.h"
>> #include "intel_io.h"
>> #include "igt_debugfs.h"
>> diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
>> index 8fe35b0..aa8c60f 100644
>> --- a/lib/ioctl_wrappers.h
>> +++ b/lib/ioctl_wrappers.h
>> @@ -32,8 +32,8 @@
>>
>> #include <stdint.h>
>> #include <stdbool.h>
>> -#include <intel_bufmgr.h>
>> -#include <i915_drm.h>
>> +
>> +#include "intel_drm_stubs.h"
>>
>> extern int (*igt_ioctl)(int fd, unsigned long request, void *arg);
>>
>> diff --git a/lib/media_fill_gen7.c b/lib/media_fill_gen7.c
>> index 6fb4479..5ec8502 100644
>> --- a/lib/media_fill_gen7.c
>> +++ b/lib/media_fill_gen7.c
>> @@ -1,9 +1,8 @@
>> -#include <intel_bufmgr.h>
>> -#include <i915_drm.h>
>>
>> #include "media_fill.h"
>> #include "gen7_media.h"
>> #include "intel_reg.h"
>> +#include "intel_drm_stubs.h"
>> #include "drmtest.h"
>>
>> #include <assert.h>
>> diff --git a/lib/media_fill_gen8.c b/lib/media_fill_gen8.c
>> index 4a8fe5a..a1e1fe4 100644
>> --- a/lib/media_fill_gen8.c
>> +++ b/lib/media_fill_gen8.c
>> @@ -1,8 +1,6 @@
>> -#include <intel_bufmgr.h>
>> -#include <i915_drm.h>
>> -
>> #include "media_fill.h"
>> #include "gen8_media.h"
>> +#include "intel_drm_stubs.h"
>> #include "intel_reg.h"
>> #include "drmtest.h"
>>
>> diff --git a/lib/media_fill_gen8lp.c b/lib/media_fill_gen8lp.c
>> index 1f8a4ad..eed26ee 100644
>> --- a/lib/media_fill_gen8lp.c
>> +++ b/lib/media_fill_gen8lp.c
>> @@ -1,13 +1,11 @@
>> -#include <intel_bufmgr.h>
>> -#include <i915_drm.h>
>> +#include <assert.h>
>>
>> #include "media_fill.h"
>> #include "gen8_media.h"
>> +#include "intel_drm_stubs.h"
>> #include "intel_reg.h"
>> #include "drmtest.h"
>>
>> -#include <assert.h>
>> -
>>
>> static const uint32_t media_kernel[][4] = {
>> { 0x00400001, 0x20202288, 0x00000020, 0x00000000 },
>> diff --git a/lib/media_fill_gen9.c b/lib/media_fill_gen9.c
>> index 3fd2181..902b28b 100644
>> --- a/lib/media_fill_gen9.c
>> +++ b/lib/media_fill_gen9.c
>> @@ -1,8 +1,6 @@
>> -#include <intel_bufmgr.h>
>> -#include <i915_drm.h>
>> -
>> #include "media_fill.h"
>> #include "gen8_media.h"
>> +#include "intel_drm_stubs.h"
>> #include "intel_reg.h"
>>
>> #include <assert.h>
>> diff --git a/lib/media_spin.c b/lib/media_spin.c
>> index 580c109..f4a432a 100644
>> --- a/lib/media_spin.c
>> +++ b/lib/media_spin.c
>> @@ -24,8 +24,6 @@
>> * Jeff McGee <jeff.mcgee@intel.com>
>> */
>>
>> -#include <intel_bufmgr.h>
>> -#include <i915_drm.h>
>> #include "intel_reg.h"
>> #include "drmtest.h"
>> #include "intel_batchbuffer.h"
>> diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c
>> index 8c24cf8..d5207d5 100644
>> --- a/lib/rendercopy_gen6.c
>> +++ b/lib/rendercopy_gen6.c
>> @@ -9,11 +9,10 @@
>> #include <errno.h>
>> #include <sys/stat.h>
>> #include <sys/time.h>
>> -#include "drm.h"
>> -#include "i915_drm.h"
>> +
>> #include "drmtest.h"
>> -#include "intel_bufmgr.h"
>> #include "intel_batchbuffer.h"
>> +#include "intel_drm_stubs.h"
>> #include "intel_io.h"
>> #include "rendercopy.h"
>> #include "gen6_render.h"
>> diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c
>> index 3b92406..dc48a99 100644
>> --- a/lib/rendercopy_gen7.c
>> +++ b/lib/rendercopy_gen7.c
>> @@ -9,10 +9,8 @@
>> #include <errno.h>
>> #include <sys/stat.h>
>> #include <sys/time.h>
>> -#include "drm.h"
>> -#include "i915_drm.h"
>> +
>> #include "drmtest.h"
>> -#include "intel_bufmgr.h"
>> #include "intel_batchbuffer.h"
>> #include "intel_io.h"
>> #include "intel_chipset.h"
>> diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c
>> index a7fc2c4..6fbb680 100644
>> --- a/lib/rendercopy_gen8.c
>> +++ b/lib/rendercopy_gen8.c
>> @@ -10,12 +10,10 @@
>> #include <sys/stat.h>
>> #include <sys/time.h>
>>
>> -#include <drm.h>
>> -#include <i915_drm.h>
>>
>> #include "drmtest.h"
>> -#include "intel_bufmgr.h"
>> #include "intel_batchbuffer.h"
>> +#include "intel_drm_stubs.h"
>> #include "intel_io.h"
>> #include "rendercopy.h"
>> #include "gen8_render.h"
>> diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
>> index 9537480..d575ddf 100644
>> --- a/lib/rendercopy_gen9.c
>> +++ b/lib/rendercopy_gen9.c
>> @@ -11,12 +11,9 @@
>> #include <sys/time.h>
>> #include <getopt.h>
>>
>> -#include <drm.h>
>> -#include <i915_drm.h>
>> -
>> #include "drmtest.h"
>> -#include "intel_bufmgr.h"
>> #include "intel_batchbuffer.h"
>> +#include "intel_drm_stubs.h"
>> #include "intel_io.h"
>> #include "rendercopy.h"
>> #include "gen9_render.h"
>> diff --git a/lib/rendercopy_i830.c b/lib/rendercopy_i830.c
>> index 04215b1..738d4d2 100644
>> --- a/lib/rendercopy_i830.c
>> +++ b/lib/rendercopy_i830.c
>> @@ -8,13 +8,10 @@
>> #include <errno.h>
>> #include <sys/stat.h>
>> #include <sys/time.h>
>> -#include "drm.h"
>> -#include "i915_drm.h"
>> +
>> #include "drmtest.h"
>> -#include "intel_bufmgr.h"
>> #include "intel_batchbuffer.h"
>> #include "intel_io.h"
>> -
>> #include "i830_reg.h"
>> #include "rendercopy.h"
>>
>> diff --git a/lib/rendercopy_i915.c b/lib/rendercopy_i915.c
>> index fc9583c..8846fdc 100644
>> --- a/lib/rendercopy_i915.c
>> +++ b/lib/rendercopy_i915.c
>> @@ -8,15 +8,12 @@
>> #include <errno.h>
>> #include <sys/stat.h>
>> #include <sys/time.h>
>> -#include "drm.h"
>> -#include "i915_drm.h"
>> -#include "drmtest.h"
>> -#include "intel_bufmgr.h"
>> -#include "intel_batchbuffer.h"
>> -#include "intel_io.h"
>>
>> +#include "drmtest.h"
>> #include "i915_reg.h"
>> #include "i915_3d.h"
>> +#include "intel_batchbuffer.h"
>> +#include "intel_io.h"
>> #include "rendercopy.h"
>>
>> void gen3_render_copyfunc(struct intel_batchbuffer *batch,
>> --
>> 2.7.4
>>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2016-05-25 18:00 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-05-20 22:59 [RFC i-g-t 0/9] Remove compile time depencencies on libdrm_intel robert.foss
2016-05-20 22:59 ` [RFC i-g-t 1/9] configure.ac: Test for libdrm_intel and build for it if present robert.foss
2016-05-21 7:55 ` Chris Wilson
2016-05-21 13:15 ` Robert Foss
2016-05-23 15:03 ` ?==?utf-8?q? ?==?utf-8?q? [RFC i-g-t 1/9]?==?utf-8?q? " Emil Velikov
2016-05-24 14:58 ` [RFC i-g-t 1/9] " Robert Foss
2016-05-20 22:59 ` [RFC i-g-t 2/9] benchmarks/Makefile: Don't build benchmarks that depend on libdrm_intel robert.foss
2016-05-23 14:04 ` ?==?utf-8?q? " Emil Velikov
2016-05-24 8:01 ` Daniel Vetter
2016-05-25 17:47 ` Robert Foss
2016-05-20 22:59 ` [RFC i-g-t 3/9] tools/Makefile: Don't build tools " robert.foss
2016-05-23 14:09 ` ?==?utf-8?q? " Emil Velikov
2016-05-20 22:59 ` [RFC i-g-t 4/9] demos/Makefile: " robert.foss
2016-05-20 22:59 ` [RFC i-g-t 5/9] tests/gem_ppgtt: Switched to new aliases of intel specific functions robert.foss
2016-05-23 14:14 ` ?==?utf-8?q? " Emil Velikov
2016-05-23 14:15 ` Emil Velikov
2016-05-24 8:03 ` Daniel Vetter
2016-05-20 22:59 ` [RFC i-g-t 6/9] tests/gem_render_tiled_blits: " robert.foss
2016-05-23 14:39 ` ?==?utf-8?q? " Emil Velikov
2016-05-24 8:04 ` Daniel Vetter
2016-05-20 22:59 ` [RFC i-g-t 7/9] lib/intel_drm_stubs: Add stubs for functionality from libdrm_intel robert.foss
2016-05-23 14:53 ` ?==?utf-8?q? " Emil Velikov
2016-05-24 8:05 ` Daniel Vetter
2016-05-25 17:48 ` Robert Foss
2016-05-20 22:59 ` [RFC i-g-t 8/9] lib: Replace intel specific header includes with intel_drm_stubs.h robert.foss
2016-05-23 14:57 ` ?==?utf-8?q? " Emil Velikov
2016-05-24 8:07 ` Daniel Vetter
2016-05-25 18:00 ` Robert Foss
2016-05-20 22:59 ` [RFC i-g-t 9/9] tests: " robert.foss
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.