* [PATCH RESEND v2 1/3] dt: bindings: add bindings for Allwinner A64 usb phy
@ 2016-08-12 3:06 ` Icenowy Zheng
0 siblings, 0 replies; 18+ messages in thread
From: Icenowy Zheng @ 2016-08-12 3:06 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Alan Stern, Hans de Goede
Cc: Mark Rutland, devicetree, linux-usb, Greg Kroah-Hartman,
Reinder de Haan, linux-kernel, Kishon Vijay Abraham I,
Tony Prisk, Icenowy Zheng, linux-arm-kernel
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 95736d7..287150d 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -10,6 +10,7 @@ Required properties:
* allwinner,sun8i-a23-usb-phy
* allwinner,sun8i-a33-usb-phy
* allwinner,sun8i-h3-usb-phy
+ * allwinner,sun50i-a64-usb-phy
- reg : a list of offset + length pairs
- reg-names :
* "phy_ctrl"
--
2.9.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH RESEND v2 1/3] dt: bindings: add bindings for Allwinner A64 usb phy
@ 2016-08-12 3:06 ` Icenowy Zheng
0 siblings, 0 replies; 18+ messages in thread
From: Icenowy Zheng @ 2016-08-12 3:06 UTC (permalink / raw)
To: linux-arm-kernel
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index 95736d7..287150d 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -10,6 +10,7 @@ Required properties:
* allwinner,sun8i-a23-usb-phy
* allwinner,sun8i-a33-usb-phy
* allwinner,sun8i-h3-usb-phy
+ * allwinner,sun50i-a64-usb-phy
- reg : a list of offset + length pairs
- reg-names :
* "phy_ctrl"
--
2.9.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH RESEND v2 2/3] phy: sun4i: add support for A64 usb phy
2016-08-12 3:06 ` Icenowy Zheng
@ 2016-08-12 3:06 ` Icenowy Zheng
-1 siblings, 0 replies; 18+ messages in thread
From: Icenowy Zheng @ 2016-08-12 3:06 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Alan Stern, Hans de Goede
Cc: Mark Rutland, devicetree, linux-usb, Greg Kroah-Hartman,
Reinder de Haan, linux-kernel, Kishon Vijay Abraham I,
Tony Prisk, Icenowy Zheng, linux-arm-kernel
There's something unknown in the pmu part that shared with H3.
It's renamed as PMU_UNK1 from PMU_UNK_H3.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
drivers/phy/phy-sun4i-usb.c | 34 ++++++++++++++++++++++++++++------
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index 0a45bc6..a4db658 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -49,7 +49,7 @@
#define REG_PHYCTL_A33 0x10
#define REG_PHY_UNK_H3 0x20
-#define REG_PMU_UNK_H3 0x10
+#define REG_PMU_UNK1 0x10
#define PHYCTL_DATA BIT(7)
@@ -97,6 +97,7 @@ enum sun4i_usb_phy_type {
sun6i_a31_phy,
sun8i_a33_phy,
sun8i_h3_phy,
+ sun50i_a64_phy,
};
struct sun4i_usb_phy_cfg {
@@ -105,6 +106,7 @@ struct sun4i_usb_phy_cfg {
u32 disc_thresh;
u8 phyctl_offset;
bool dedicated_clocks;
+ bool enable_pmu_unk1;
};
struct sun4i_usb_phy_data {
@@ -180,8 +182,9 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
mutex_lock(&phy_data->mutex);
- if (phy_data->cfg->type == sun8i_a33_phy) {
- /* A33 needs us to set phyctl to 0 explicitly */
+ if (phy_data->cfg->type == sun8i_a33_phy ||
+ phy_data->cfg->type == sun50i_a64_phy) {
+ /* A33 or A64 needs us to set phyctl to 0 explicitly */
writel(0, phyctl);
}
@@ -255,14 +258,16 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
+ if (data->cfg->enable_pmu_unk1) {
+ val = readl(phy->pmu + REG_PMU_UNK1);
+ writel(val & ~2, phy->pmu + REG_PMU_UNK1);
+ }
+
if (data->cfg->type == sun8i_h3_phy) {
if (phy->index == 0) {
val = readl(data->base + REG_PHY_UNK_H3);
writel(val & ~1, data->base + REG_PHY_UNK_H3);
}
-
- val = readl(phy->pmu + REG_PMU_UNK_H3);
- writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
} else {
/* Enable USB 45 Ohm resistor calibration */
if (phy->index == 0)
@@ -713,6 +718,7 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
+ .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
@@ -721,6 +727,7 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
+ .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
@@ -729,6 +736,7 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
+ .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
@@ -737,6 +745,7 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
+ .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
@@ -745,6 +754,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
+ .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
@@ -753,6 +763,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
+ .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
@@ -760,6 +771,16 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
.type = sun8i_h3_phy,
.disc_thresh = 3,
.dedicated_clocks = true,
+ .enable_pmu_unk1 = true,
+};
+
+static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
+ .num_phys = 2,
+ .type = sun50i_a64_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .enable_pmu_unk1 = true,
};
static const struct of_device_id sun4i_usb_phy_of_match[] = {
@@ -770,6 +791,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
+ { .compatible = "allwinner,sun50i-a64-usb-phy", .data = &sun50i_a64_cfg},
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.9.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH RESEND v2 2/3] phy: sun4i: add support for A64 usb phy
@ 2016-08-12 3:06 ` Icenowy Zheng
0 siblings, 0 replies; 18+ messages in thread
From: Icenowy Zheng @ 2016-08-12 3:06 UTC (permalink / raw)
To: linux-arm-kernel
There's something unknown in the pmu part that shared with H3.
It's renamed as PMU_UNK1 from PMU_UNK_H3.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
drivers/phy/phy-sun4i-usb.c | 34 ++++++++++++++++++++++++++++------
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
index 0a45bc6..a4db658 100644
--- a/drivers/phy/phy-sun4i-usb.c
+++ b/drivers/phy/phy-sun4i-usb.c
@@ -49,7 +49,7 @@
#define REG_PHYCTL_A33 0x10
#define REG_PHY_UNK_H3 0x20
-#define REG_PMU_UNK_H3 0x10
+#define REG_PMU_UNK1 0x10
#define PHYCTL_DATA BIT(7)
@@ -97,6 +97,7 @@ enum sun4i_usb_phy_type {
sun6i_a31_phy,
sun8i_a33_phy,
sun8i_h3_phy,
+ sun50i_a64_phy,
};
struct sun4i_usb_phy_cfg {
@@ -105,6 +106,7 @@ struct sun4i_usb_phy_cfg {
u32 disc_thresh;
u8 phyctl_offset;
bool dedicated_clocks;
+ bool enable_pmu_unk1;
};
struct sun4i_usb_phy_data {
@@ -180,8 +182,9 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
mutex_lock(&phy_data->mutex);
- if (phy_data->cfg->type == sun8i_a33_phy) {
- /* A33 needs us to set phyctl to 0 explicitly */
+ if (phy_data->cfg->type == sun8i_a33_phy ||
+ phy_data->cfg->type == sun50i_a64_phy) {
+ /* A33 or A64 needs us to set phyctl to 0 explicitly */
writel(0, phyctl);
}
@@ -255,14 +258,16 @@ static int sun4i_usb_phy_init(struct phy *_phy)
return ret;
}
+ if (data->cfg->enable_pmu_unk1) {
+ val = readl(phy->pmu + REG_PMU_UNK1);
+ writel(val & ~2, phy->pmu + REG_PMU_UNK1);
+ }
+
if (data->cfg->type == sun8i_h3_phy) {
if (phy->index == 0) {
val = readl(data->base + REG_PHY_UNK_H3);
writel(val & ~1, data->base + REG_PHY_UNK_H3);
}
-
- val = readl(phy->pmu + REG_PMU_UNK_H3);
- writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
} else {
/* Enable USB 45 Ohm resistor calibration */
if (phy->index == 0)
@@ -713,6 +718,7 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
+ .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
@@ -721,6 +727,7 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
+ .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
@@ -729,6 +736,7 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
+ .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
@@ -737,6 +745,7 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
.disc_thresh = 2,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = false,
+ .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
@@ -745,6 +754,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A10,
.dedicated_clocks = true,
+ .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
@@ -753,6 +763,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
.disc_thresh = 3,
.phyctl_offset = REG_PHYCTL_A33,
.dedicated_clocks = true,
+ .enable_pmu_unk1 = false,
};
static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
@@ -760,6 +771,16 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
.type = sun8i_h3_phy,
.disc_thresh = 3,
.dedicated_clocks = true,
+ .enable_pmu_unk1 = true,
+};
+
+static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
+ .num_phys = 2,
+ .type = sun50i_a64_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A33,
+ .dedicated_clocks = true,
+ .enable_pmu_unk1 = true,
};
static const struct of_device_id sun4i_usb_phy_of_match[] = {
@@ -770,6 +791,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
{ .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
{ .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
+ { .compatible = "allwinner,sun50i-a64-usb-phy", .data = &sun50i_a64_cfg},
{ },
};
MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
--
2.9.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH RESEND v2 3/3] ehci-platform: add the max clock number to 4
2016-08-12 3:06 ` Icenowy Zheng
@ 2016-08-12 3:06 ` Icenowy Zheng
-1 siblings, 0 replies; 18+ messages in thread
From: Icenowy Zheng @ 2016-08-12 3:06 UTC (permalink / raw)
To: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Alan Stern, Hans de Goede
Cc: Mark Rutland, devicetree, linux-usb, Greg Kroah-Hartman,
Reinder de Haan, linux-kernel, Kishon Vijay Abraham I,
Tony Prisk, Icenowy Zheng, linux-arm-kernel
Allwinner A64 EHCI requires 4 clocks to be enabled.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
drivers/usb/host/ehci-platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
index 6816b8c..876dca4 100644
--- a/drivers/usb/host/ehci-platform.c
+++ b/drivers/usb/host/ehci-platform.c
@@ -38,7 +38,7 @@
#include "ehci.h"
#define DRIVER_DESC "EHCI generic platform driver"
-#define EHCI_MAX_CLKS 3
+#define EHCI_MAX_CLKS 4
#define EHCI_MAX_RSTS 3
#define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv)
--
2.9.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH RESEND v2 3/3] ehci-platform: add the max clock number to 4
@ 2016-08-12 3:06 ` Icenowy Zheng
0 siblings, 0 replies; 18+ messages in thread
From: Icenowy Zheng @ 2016-08-12 3:06 UTC (permalink / raw)
To: linux-arm-kernel
Allwinner A64 EHCI requires 4 clocks to be enabled.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
drivers/usb/host/ehci-platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
index 6816b8c..876dca4 100644
--- a/drivers/usb/host/ehci-platform.c
+++ b/drivers/usb/host/ehci-platform.c
@@ -38,7 +38,7 @@
#include "ehci.h"
#define DRIVER_DESC "EHCI generic platform driver"
-#define EHCI_MAX_CLKS 3
+#define EHCI_MAX_CLKS 4
#define EHCI_MAX_RSTS 3
#define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv)
--
2.9.2
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH RESEND v2 1/3] dt: bindings: add bindings for Allwinner A64 usb phy
2016-08-12 3:06 ` Icenowy Zheng
(?)
@ 2016-08-12 8:15 ` Hans de Goede
-1 siblings, 0 replies; 18+ messages in thread
From: Hans de Goede @ 2016-08-12 8:15 UTC (permalink / raw)
To: Icenowy Zheng, Rob Herring, Maxime Ripard, Chen-Yu Tsai, Alan Stern
Cc: Mark Rutland, Kishon Vijay Abraham I, Tony Prisk,
Greg Kroah-Hartman, Reinder de Haan, devicetree,
linux-arm-kernel, linux-kernel, linux-usb
Hi,
On 12-08-16 05:06, Icenowy Zheng wrote:
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Series is still:
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Regards,
Hans
> ---
> Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> index 95736d7..287150d 100644
> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> @@ -10,6 +10,7 @@ Required properties:
> * allwinner,sun8i-a23-usb-phy
> * allwinner,sun8i-a33-usb-phy
> * allwinner,sun8i-h3-usb-phy
> + * allwinner,sun50i-a64-usb-phy
> - reg : a list of offset + length pairs
> - reg-names :
> * "phy_ctrl"
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RESEND v2 1/3] dt: bindings: add bindings for Allwinner A64 usb phy
@ 2016-08-12 8:15 ` Hans de Goede
0 siblings, 0 replies; 18+ messages in thread
From: Hans de Goede @ 2016-08-12 8:15 UTC (permalink / raw)
To: Icenowy Zheng, Rob Herring, Maxime Ripard, Chen-Yu Tsai, Alan Stern
Cc: Mark Rutland, devicetree, linux-usb, Greg Kroah-Hartman,
Reinder de Haan, linux-kernel, Kishon Vijay Abraham I,
Tony Prisk, linux-arm-kernel
Hi,
On 12-08-16 05:06, Icenowy Zheng wrote:
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Series is still:
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Regards,
Hans
> ---
> Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> index 95736d7..287150d 100644
> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> @@ -10,6 +10,7 @@ Required properties:
> * allwinner,sun8i-a23-usb-phy
> * allwinner,sun8i-a33-usb-phy
> * allwinner,sun8i-h3-usb-phy
> + * allwinner,sun50i-a64-usb-phy
> - reg : a list of offset + length pairs
> - reg-names :
> * "phy_ctrl"
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RESEND v2 1/3] dt: bindings: add bindings for Allwinner A64 usb phy
@ 2016-08-12 8:15 ` Hans de Goede
0 siblings, 0 replies; 18+ messages in thread
From: Hans de Goede @ 2016-08-12 8:15 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
On 12-08-16 05:06, Icenowy Zheng wrote:
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Series is still:
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Regards,
Hans
> ---
> Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> index 95736d7..287150d 100644
> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> @@ -10,6 +10,7 @@ Required properties:
> * allwinner,sun8i-a23-usb-phy
> * allwinner,sun8i-a33-usb-phy
> * allwinner,sun8i-h3-usb-phy
> + * allwinner,sun50i-a64-usb-phy
> - reg : a list of offset + length pairs
> - reg-names :
> * "phy_ctrl"
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RESEND v2 1/3] dt: bindings: add bindings for Allwinner A64 usb phy
2016-08-12 3:06 ` Icenowy Zheng
(?)
@ 2016-08-12 9:39 ` Kishon Vijay Abraham I
-1 siblings, 0 replies; 18+ messages in thread
From: Kishon Vijay Abraham I @ 2016-08-12 9:39 UTC (permalink / raw)
To: Icenowy Zheng, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Alan Stern, Hans de Goede
Cc: Mark Rutland, Tony Prisk, Greg Kroah-Hartman, Reinder de Haan,
devicetree, linux-arm-kernel, linux-kernel, linux-usb
On Friday 12 August 2016 08:36 AM, Icenowy Zheng wrote:
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Added "Update sun4i usb phy dt binding documentation to include support for
Allwinner A64 usb phy." and then merged this.
Thanks
Kishon
> ---
> Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> index 95736d7..287150d 100644
> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> @@ -10,6 +10,7 @@ Required properties:
> * allwinner,sun8i-a23-usb-phy
> * allwinner,sun8i-a33-usb-phy
> * allwinner,sun8i-h3-usb-phy
> + * allwinner,sun50i-a64-usb-phy
> - reg : a list of offset + length pairs
> - reg-names :
> * "phy_ctrl"
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RESEND v2 1/3] dt: bindings: add bindings for Allwinner A64 usb phy
@ 2016-08-12 9:39 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 18+ messages in thread
From: Kishon Vijay Abraham I @ 2016-08-12 9:39 UTC (permalink / raw)
To: Icenowy Zheng, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Alan Stern, Hans de Goede
Cc: Mark Rutland, devicetree, linux-usb, Greg Kroah-Hartman,
Reinder de Haan, linux-kernel, Tony Prisk, linux-arm-kernel
On Friday 12 August 2016 08:36 AM, Icenowy Zheng wrote:
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Added "Update sun4i usb phy dt binding documentation to include support for
Allwinner A64 usb phy." and then merged this.
Thanks
Kishon
> ---
> Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> index 95736d7..287150d 100644
> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> @@ -10,6 +10,7 @@ Required properties:
> * allwinner,sun8i-a23-usb-phy
> * allwinner,sun8i-a33-usb-phy
> * allwinner,sun8i-h3-usb-phy
> + * allwinner,sun50i-a64-usb-phy
> - reg : a list of offset + length pairs
> - reg-names :
> * "phy_ctrl"
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RESEND v2 1/3] dt: bindings: add bindings for Allwinner A64 usb phy
@ 2016-08-12 9:39 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 18+ messages in thread
From: Kishon Vijay Abraham I @ 2016-08-12 9:39 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 12 August 2016 08:36 AM, Icenowy Zheng wrote:
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Added "Update sun4i usb phy dt binding documentation to include support for
Allwinner A64 usb phy." and then merged this.
Thanks
Kishon
> ---
> Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> index 95736d7..287150d 100644
> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> @@ -10,6 +10,7 @@ Required properties:
> * allwinner,sun8i-a23-usb-phy
> * allwinner,sun8i-a33-usb-phy
> * allwinner,sun8i-h3-usb-phy
> + * allwinner,sun50i-a64-usb-phy
> - reg : a list of offset + length pairs
> - reg-names :
> * "phy_ctrl"
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RESEND v2 2/3] phy: sun4i: add support for A64 usb phy
2016-08-12 3:06 ` Icenowy Zheng
(?)
@ 2016-08-12 9:40 ` Kishon Vijay Abraham I
-1 siblings, 0 replies; 18+ messages in thread
From: Kishon Vijay Abraham I @ 2016-08-12 9:40 UTC (permalink / raw)
To: Icenowy Zheng, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Alan Stern, Hans de Goede
Cc: Mark Rutland, Tony Prisk, Greg Kroah-Hartman, Reinder de Haan,
devicetree, linux-arm-kernel, linux-kernel, linux-usb
On Friday 12 August 2016 08:36 AM, Icenowy Zheng wrote:
> There's something unknown in the pmu part that shared with H3.
> It's renamed as PMU_UNK1 from PMU_UNK_H3.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Fixed the following checkpatch warning and merged this to linux-phy tree.
WARNING: line over 80 characters
#311: FILE: drivers/phy/phy-sun4i-usb.c:794:
+ { .compatible = "allwinner,sun50i-a64-usb-phy", .data = &sun50i_a64_cfg},
Thanks
Kishon
> ---
> drivers/phy/phy-sun4i-usb.c | 34 ++++++++++++++++++++++++++++------
> 1 file changed, 28 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> index 0a45bc6..a4db658 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -49,7 +49,7 @@
> #define REG_PHYCTL_A33 0x10
> #define REG_PHY_UNK_H3 0x20
>
> -#define REG_PMU_UNK_H3 0x10
> +#define REG_PMU_UNK1 0x10
>
> #define PHYCTL_DATA BIT(7)
>
> @@ -97,6 +97,7 @@ enum sun4i_usb_phy_type {
> sun6i_a31_phy,
> sun8i_a33_phy,
> sun8i_h3_phy,
> + sun50i_a64_phy,
> };
>
> struct sun4i_usb_phy_cfg {
> @@ -105,6 +106,7 @@ struct sun4i_usb_phy_cfg {
> u32 disc_thresh;
> u8 phyctl_offset;
> bool dedicated_clocks;
> + bool enable_pmu_unk1;
> };
>
> struct sun4i_usb_phy_data {
> @@ -180,8 +182,9 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
>
> mutex_lock(&phy_data->mutex);
>
> - if (phy_data->cfg->type == sun8i_a33_phy) {
> - /* A33 needs us to set phyctl to 0 explicitly */
> + if (phy_data->cfg->type == sun8i_a33_phy ||
> + phy_data->cfg->type == sun50i_a64_phy) {
> + /* A33 or A64 needs us to set phyctl to 0 explicitly */
> writel(0, phyctl);
> }
>
> @@ -255,14 +258,16 @@ static int sun4i_usb_phy_init(struct phy *_phy)
> return ret;
> }
>
> + if (data->cfg->enable_pmu_unk1) {
> + val = readl(phy->pmu + REG_PMU_UNK1);
> + writel(val & ~2, phy->pmu + REG_PMU_UNK1);
> + }
> +
> if (data->cfg->type == sun8i_h3_phy) {
> if (phy->index == 0) {
> val = readl(data->base + REG_PHY_UNK_H3);
> writel(val & ~1, data->base + REG_PHY_UNK_H3);
> }
> -
> - val = readl(phy->pmu + REG_PMU_UNK_H3);
> - writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
> } else {
> /* Enable USB 45 Ohm resistor calibration */
> if (phy->index == 0)
> @@ -713,6 +718,7 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
> .disc_thresh = 3,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = false,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
> @@ -721,6 +727,7 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
> .disc_thresh = 2,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = false,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
> @@ -729,6 +736,7 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
> .disc_thresh = 3,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = true,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
> @@ -737,6 +745,7 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
> .disc_thresh = 2,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = false,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
> @@ -745,6 +754,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
> .disc_thresh = 3,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = true,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
> @@ -753,6 +763,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
> .disc_thresh = 3,
> .phyctl_offset = REG_PHYCTL_A33,
> .dedicated_clocks = true,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
> @@ -760,6 +771,16 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
> .type = sun8i_h3_phy,
> .disc_thresh = 3,
> .dedicated_clocks = true,
> + .enable_pmu_unk1 = true,
> +};
> +
> +static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
> + .num_phys = 2,
> + .type = sun50i_a64_phy,
> + .disc_thresh = 3,
> + .phyctl_offset = REG_PHYCTL_A33,
> + .dedicated_clocks = true,
> + .enable_pmu_unk1 = true,
> };
>
> static const struct of_device_id sun4i_usb_phy_of_match[] = {
> @@ -770,6 +791,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
> { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
> { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
> { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
> + { .compatible = "allwinner,sun50i-a64-usb-phy", .data = &sun50i_a64_cfg},
> { },
> };
> MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RESEND v2 2/3] phy: sun4i: add support for A64 usb phy
@ 2016-08-12 9:40 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 18+ messages in thread
From: Kishon Vijay Abraham I @ 2016-08-12 9:40 UTC (permalink / raw)
To: Icenowy Zheng, Rob Herring, Maxime Ripard, Chen-Yu Tsai,
Alan Stern, Hans de Goede
Cc: Mark Rutland, devicetree, linux-usb, Greg Kroah-Hartman,
Reinder de Haan, linux-kernel, Tony Prisk, linux-arm-kernel
On Friday 12 August 2016 08:36 AM, Icenowy Zheng wrote:
> There's something unknown in the pmu part that shared with H3.
> It's renamed as PMU_UNK1 from PMU_UNK_H3.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Fixed the following checkpatch warning and merged this to linux-phy tree.
WARNING: line over 80 characters
#311: FILE: drivers/phy/phy-sun4i-usb.c:794:
+ { .compatible = "allwinner,sun50i-a64-usb-phy", .data = &sun50i_a64_cfg},
Thanks
Kishon
> ---
> drivers/phy/phy-sun4i-usb.c | 34 ++++++++++++++++++++++++++++------
> 1 file changed, 28 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> index 0a45bc6..a4db658 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -49,7 +49,7 @@
> #define REG_PHYCTL_A33 0x10
> #define REG_PHY_UNK_H3 0x20
>
> -#define REG_PMU_UNK_H3 0x10
> +#define REG_PMU_UNK1 0x10
>
> #define PHYCTL_DATA BIT(7)
>
> @@ -97,6 +97,7 @@ enum sun4i_usb_phy_type {
> sun6i_a31_phy,
> sun8i_a33_phy,
> sun8i_h3_phy,
> + sun50i_a64_phy,
> };
>
> struct sun4i_usb_phy_cfg {
> @@ -105,6 +106,7 @@ struct sun4i_usb_phy_cfg {
> u32 disc_thresh;
> u8 phyctl_offset;
> bool dedicated_clocks;
> + bool enable_pmu_unk1;
> };
>
> struct sun4i_usb_phy_data {
> @@ -180,8 +182,9 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
>
> mutex_lock(&phy_data->mutex);
>
> - if (phy_data->cfg->type == sun8i_a33_phy) {
> - /* A33 needs us to set phyctl to 0 explicitly */
> + if (phy_data->cfg->type == sun8i_a33_phy ||
> + phy_data->cfg->type == sun50i_a64_phy) {
> + /* A33 or A64 needs us to set phyctl to 0 explicitly */
> writel(0, phyctl);
> }
>
> @@ -255,14 +258,16 @@ static int sun4i_usb_phy_init(struct phy *_phy)
> return ret;
> }
>
> + if (data->cfg->enable_pmu_unk1) {
> + val = readl(phy->pmu + REG_PMU_UNK1);
> + writel(val & ~2, phy->pmu + REG_PMU_UNK1);
> + }
> +
> if (data->cfg->type == sun8i_h3_phy) {
> if (phy->index == 0) {
> val = readl(data->base + REG_PHY_UNK_H3);
> writel(val & ~1, data->base + REG_PHY_UNK_H3);
> }
> -
> - val = readl(phy->pmu + REG_PMU_UNK_H3);
> - writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
> } else {
> /* Enable USB 45 Ohm resistor calibration */
> if (phy->index == 0)
> @@ -713,6 +718,7 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
> .disc_thresh = 3,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = false,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
> @@ -721,6 +727,7 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
> .disc_thresh = 2,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = false,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
> @@ -729,6 +736,7 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
> .disc_thresh = 3,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = true,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
> @@ -737,6 +745,7 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
> .disc_thresh = 2,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = false,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
> @@ -745,6 +754,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
> .disc_thresh = 3,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = true,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
> @@ -753,6 +763,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
> .disc_thresh = 3,
> .phyctl_offset = REG_PHYCTL_A33,
> .dedicated_clocks = true,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
> @@ -760,6 +771,16 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
> .type = sun8i_h3_phy,
> .disc_thresh = 3,
> .dedicated_clocks = true,
> + .enable_pmu_unk1 = true,
> +};
> +
> +static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
> + .num_phys = 2,
> + .type = sun50i_a64_phy,
> + .disc_thresh = 3,
> + .phyctl_offset = REG_PHYCTL_A33,
> + .dedicated_clocks = true,
> + .enable_pmu_unk1 = true,
> };
>
> static const struct of_device_id sun4i_usb_phy_of_match[] = {
> @@ -770,6 +791,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
> { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
> { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
> { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
> + { .compatible = "allwinner,sun50i-a64-usb-phy", .data = &sun50i_a64_cfg},
> { },
> };
> MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RESEND v2 2/3] phy: sun4i: add support for A64 usb phy
@ 2016-08-12 9:40 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 18+ messages in thread
From: Kishon Vijay Abraham I @ 2016-08-12 9:40 UTC (permalink / raw)
To: linux-arm-kernel
On Friday 12 August 2016 08:36 AM, Icenowy Zheng wrote:
> There's something unknown in the pmu part that shared with H3.
> It's renamed as PMU_UNK1 from PMU_UNK_H3.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Fixed the following checkpatch warning and merged this to linux-phy tree.
WARNING: line over 80 characters
#311: FILE: drivers/phy/phy-sun4i-usb.c:794:
+ { .compatible = "allwinner,sun50i-a64-usb-phy", .data = &sun50i_a64_cfg},
Thanks
Kishon
> ---
> drivers/phy/phy-sun4i-usb.c | 34 ++++++++++++++++++++++++++++------
> 1 file changed, 28 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/phy/phy-sun4i-usb.c b/drivers/phy/phy-sun4i-usb.c
> index 0a45bc6..a4db658 100644
> --- a/drivers/phy/phy-sun4i-usb.c
> +++ b/drivers/phy/phy-sun4i-usb.c
> @@ -49,7 +49,7 @@
> #define REG_PHYCTL_A33 0x10
> #define REG_PHY_UNK_H3 0x20
>
> -#define REG_PMU_UNK_H3 0x10
> +#define REG_PMU_UNK1 0x10
>
> #define PHYCTL_DATA BIT(7)
>
> @@ -97,6 +97,7 @@ enum sun4i_usb_phy_type {
> sun6i_a31_phy,
> sun8i_a33_phy,
> sun8i_h3_phy,
> + sun50i_a64_phy,
> };
>
> struct sun4i_usb_phy_cfg {
> @@ -105,6 +106,7 @@ struct sun4i_usb_phy_cfg {
> u32 disc_thresh;
> u8 phyctl_offset;
> bool dedicated_clocks;
> + bool enable_pmu_unk1;
> };
>
> struct sun4i_usb_phy_data {
> @@ -180,8 +182,9 @@ static void sun4i_usb_phy_write(struct sun4i_usb_phy *phy, u32 addr, u32 data,
>
> mutex_lock(&phy_data->mutex);
>
> - if (phy_data->cfg->type == sun8i_a33_phy) {
> - /* A33 needs us to set phyctl to 0 explicitly */
> + if (phy_data->cfg->type == sun8i_a33_phy ||
> + phy_data->cfg->type == sun50i_a64_phy) {
> + /* A33 or A64 needs us to set phyctl to 0 explicitly */
> writel(0, phyctl);
> }
>
> @@ -255,14 +258,16 @@ static int sun4i_usb_phy_init(struct phy *_phy)
> return ret;
> }
>
> + if (data->cfg->enable_pmu_unk1) {
> + val = readl(phy->pmu + REG_PMU_UNK1);
> + writel(val & ~2, phy->pmu + REG_PMU_UNK1);
> + }
> +
> if (data->cfg->type == sun8i_h3_phy) {
> if (phy->index == 0) {
> val = readl(data->base + REG_PHY_UNK_H3);
> writel(val & ~1, data->base + REG_PHY_UNK_H3);
> }
> -
> - val = readl(phy->pmu + REG_PMU_UNK_H3);
> - writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
> } else {
> /* Enable USB 45 Ohm resistor calibration */
> if (phy->index == 0)
> @@ -713,6 +718,7 @@ static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
> .disc_thresh = 3,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = false,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
> @@ -721,6 +727,7 @@ static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
> .disc_thresh = 2,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = false,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
> @@ -729,6 +736,7 @@ static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
> .disc_thresh = 3,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = true,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
> @@ -737,6 +745,7 @@ static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
> .disc_thresh = 2,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = false,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
> @@ -745,6 +754,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
> .disc_thresh = 3,
> .phyctl_offset = REG_PHYCTL_A10,
> .dedicated_clocks = true,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
> @@ -753,6 +763,7 @@ static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
> .disc_thresh = 3,
> .phyctl_offset = REG_PHYCTL_A33,
> .dedicated_clocks = true,
> + .enable_pmu_unk1 = false,
> };
>
> static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
> @@ -760,6 +771,16 @@ static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
> .type = sun8i_h3_phy,
> .disc_thresh = 3,
> .dedicated_clocks = true,
> + .enable_pmu_unk1 = true,
> +};
> +
> +static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
> + .num_phys = 2,
> + .type = sun50i_a64_phy,
> + .disc_thresh = 3,
> + .phyctl_offset = REG_PHYCTL_A33,
> + .dedicated_clocks = true,
> + .enable_pmu_unk1 = true,
> };
>
> static const struct of_device_id sun4i_usb_phy_of_match[] = {
> @@ -770,6 +791,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
> { .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
> { .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
> { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
> + { .compatible = "allwinner,sun50i-a64-usb-phy", .data = &sun50i_a64_cfg},
> { },
> };
> MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RESEND v2 3/3] ehci-platform: add the max clock number to 4
2016-08-12 3:06 ` Icenowy Zheng
(?)
@ 2016-08-12 15:28 ` Alan Stern
-1 siblings, 0 replies; 18+ messages in thread
From: Alan Stern @ 2016-08-12 15:28 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Hans de Goede,
Mark Rutland, Kishon Vijay Abraham I, Tony Prisk,
Greg Kroah-Hartman, Reinder de Haan, devicetree,
linux-arm-kernel, linux-kernel, linux-usb
On Fri, 12 Aug 2016, Icenowy Zheng wrote:
> Allwinner A64 EHCI requires 4 clocks to be enabled.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> drivers/usb/host/ehci-platform.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
> index 6816b8c..876dca4 100644
> --- a/drivers/usb/host/ehci-platform.c
> +++ b/drivers/usb/host/ehci-platform.c
> @@ -38,7 +38,7 @@
> #include "ehci.h"
>
> #define DRIVER_DESC "EHCI generic platform driver"
> -#define EHCI_MAX_CLKS 3
> +#define EHCI_MAX_CLKS 4
> #define EHCI_MAX_RSTS 3
> #define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv)
Acked-by: Alan Stern <stern@rowland.harvard.edu>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH RESEND v2 3/3] ehci-platform: add the max clock number to 4
@ 2016-08-12 15:28 ` Alan Stern
0 siblings, 0 replies; 18+ messages in thread
From: Alan Stern @ 2016-08-12 15:28 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Rob Herring, Maxime Ripard, Chen-Yu Tsai, Hans de Goede,
Mark Rutland, Kishon Vijay Abraham I, Tony Prisk,
Greg Kroah-Hartman, Reinder de Haan, devicetree,
linux-arm-kernel, linux-kernel, linux-usb
On Fri, 12 Aug 2016, Icenowy Zheng wrote:
> Allwinner A64 EHCI requires 4 clocks to be enabled.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> drivers/usb/host/ehci-platform.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
> index 6816b8c..876dca4 100644
> --- a/drivers/usb/host/ehci-platform.c
> +++ b/drivers/usb/host/ehci-platform.c
> @@ -38,7 +38,7 @@
> #include "ehci.h"
>
> #define DRIVER_DESC "EHCI generic platform driver"
> -#define EHCI_MAX_CLKS 3
> +#define EHCI_MAX_CLKS 4
> #define EHCI_MAX_RSTS 3
> #define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv)
Acked-by: Alan Stern <stern@rowland.harvard.edu>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH RESEND v2 3/3] ehci-platform: add the max clock number to 4
@ 2016-08-12 15:28 ` Alan Stern
0 siblings, 0 replies; 18+ messages in thread
From: Alan Stern @ 2016-08-12 15:28 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, 12 Aug 2016, Icenowy Zheng wrote:
> Allwinner A64 EHCI requires 4 clocks to be enabled.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> drivers/usb/host/ehci-platform.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
> index 6816b8c..876dca4 100644
> --- a/drivers/usb/host/ehci-platform.c
> +++ b/drivers/usb/host/ehci-platform.c
> @@ -38,7 +38,7 @@
> #include "ehci.h"
>
> #define DRIVER_DESC "EHCI generic platform driver"
> -#define EHCI_MAX_CLKS 3
> +#define EHCI_MAX_CLKS 4
> #define EHCI_MAX_RSTS 3
> #define hcd_to_ehci_priv(h) ((struct ehci_platform_priv *)hcd_to_ehci(h)->priv)
Acked-by: Alan Stern <stern@rowland.harvard.edu>
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2016-08-12 15:29 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2016-08-12 3:06 [PATCH RESEND v2 1/3] dt: bindings: add bindings for Allwinner A64 usb phy Icenowy Zheng
2016-08-12 3:06 ` Icenowy Zheng
2016-08-12 3:06 ` [PATCH RESEND v2 2/3] phy: sun4i: add support for " Icenowy Zheng
2016-08-12 3:06 ` Icenowy Zheng
2016-08-12 9:40 ` Kishon Vijay Abraham I
2016-08-12 9:40 ` Kishon Vijay Abraham I
2016-08-12 9:40 ` Kishon Vijay Abraham I
2016-08-12 3:06 ` [PATCH RESEND v2 3/3] ehci-platform: add the max clock number to 4 Icenowy Zheng
2016-08-12 3:06 ` Icenowy Zheng
2016-08-12 15:28 ` Alan Stern
2016-08-12 15:28 ` Alan Stern
2016-08-12 15:28 ` Alan Stern
2016-08-12 8:15 ` [PATCH RESEND v2 1/3] dt: bindings: add bindings for Allwinner A64 usb phy Hans de Goede
2016-08-12 8:15 ` Hans de Goede
2016-08-12 8:15 ` Hans de Goede
2016-08-12 9:39 ` Kishon Vijay Abraham I
2016-08-12 9:39 ` Kishon Vijay Abraham I
2016-08-12 9:39 ` Kishon Vijay Abraham I
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