[PATCH 1/2] arm: rmobile: Add RZ/G2M SoC

* [PATCH 1/2] arm: rmobile: Add RZ/G2M SoC
@ 2020-09-18 16:03 Biju Das
  2020-09-18 16:03 ` [PATCH 2/2] arm: rmobile: Add HopeRun HiHope RZ/G2M board support Biju Das
  2020-09-19  2:47 ` [PATCH 1/2] arm: rmobile: Add RZ/G2M SoC Marek Vasut
  0 siblings, 2 replies; 18+ messages in thread
From: Biju Das @ 2020-09-18 16:03 UTC (permalink / raw)
  To: u-boot

Add CPU and PRR IDs for R8A774A1(a.k.a RZ/G2M) SoC.

RZ/Gx SoC's are identical to R-Car SoC's apart from some automotive
peripherals and they also share the same PRR CPU ID's.

For example the RZ/G2M SoC has the same PRR ID 0x52 as R-Car M3W SoC.

To differentiate RZ/G SoC's from R-Car SoC's add a member family_type
in struct rmobile_cpuinfo and compare the compatible string from
device tree for SoC identification of RZ/G SoC.

Also sorted the header alphabetically.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
V1-->V2
   Add comments in the code for SoC identification logic for RZ/G SoC's
---
 arch/arm/mach-rmobile/cpu_info.c             | 83 +++++++++++++++-----
 arch/arm/mach-rmobile/include/mach/rmobile.h |  1 +
 2 files changed, 65 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c
index fdbbd72e28..d45a474ba9 100644
--- a/arch/arm/mach-rmobile/cpu_info.c
+++ b/arch/arm/mach-rmobile/cpu_info.c
@@ -3,13 +3,23 @@
  * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  * (C) Copyright 2012 Renesas Solutions Corp.
  */
-#include <common.h>
-#include <cpu_func.h>
 #include <asm/cache.h>
-#include <init.h>
 #include <asm/io.h>
+#include <common.h>
+#include <cpu_func.h>
+#include <dm/device.h>
 #include <env.h>
+#include <init.h>
 #include <linux/ctype.h>
+#include <linux/libfdt.h>
+
+enum soc_family_type {
+	SOC_SHMOBILE = 0,
+	SOC_RMOBILE,
+	SOC_RZG2,
+	SOC_RCAR_GEN2,
+	SOC_RCAR_GEN3,
+};
 
 #ifdef CONFIG_ARCH_CPU_INIT
 int arch_cpu_init(void)
@@ -31,6 +41,7 @@ void enable_caches(void)
 
 #ifdef CONFIG_DISPLAY_CPUINFO
 #ifndef CONFIG_RZA1
+DECLARE_GLOBAL_DATA_PTR;
 static u32 __rmobile_get_cpu_type(void)
 {
 	return 0x0;
@@ -52,36 +63,70 @@ static u32 __rmobile_get_cpu_rev_fraction(void)
 u32 rmobile_get_cpu_rev_fraction(void)
 		__attribute__((weak, alias("__rmobile_get_cpu_rev_fraction")));
 
+static const struct udevice_id soc_ids[] = {
+	{ .compatible = "renesas,r8a774a1", .data = SOC_RZG2 },
+	{ },
+};
+
 /* CPU infomation table */
 static const struct {
 	u16 cpu_type;
 	u8 cpu_name[10];
+	enum soc_family_type family_type;
 } rmobile_cpuinfo[] = {
-	{ RMOBILE_CPU_TYPE_SH73A0, "SH73A0" },
-	{ RMOBILE_CPU_TYPE_R8A7740, "R8A7740" },
-	{ RMOBILE_CPU_TYPE_R8A7790, "R8A7790" },
-	{ RMOBILE_CPU_TYPE_R8A7791, "R8A7791" },
-	{ RMOBILE_CPU_TYPE_R8A7792, "R8A7792" },
-	{ RMOBILE_CPU_TYPE_R8A7793, "R8A7793" },
-	{ RMOBILE_CPU_TYPE_R8A7794, "R8A7794" },
-	{ RMOBILE_CPU_TYPE_R8A7795, "R8A7795" },
-	{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796" },
-	{ RMOBILE_CPU_TYPE_R8A77965, "R8A77965" },
-	{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970" },
-	{ RMOBILE_CPU_TYPE_R8A77980, "R8A77980" },
-	{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990" },
-	{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995" },
+	{ RMOBILE_CPU_TYPE_SH73A0, "SH73A0", SOC_SHMOBILE },
+	{ RMOBILE_CPU_TYPE_R8A7740, "R8A7740", SOC_RMOBILE },
+	{ RMOBILE_CPU_TYPE_R8A774A1, "R8A774A1", SOC_RZG2 },
+	{ RMOBILE_CPU_TYPE_R8A7790, "R8A7790", SOC_RCAR_GEN2 },
+	{ RMOBILE_CPU_TYPE_R8A7791, "R8A7791", SOC_RCAR_GEN2 },
+	{ RMOBILE_CPU_TYPE_R8A7792, "R8A7792", SOC_RCAR_GEN2 },
+	{ RMOBILE_CPU_TYPE_R8A7793, "R8A7793", SOC_RCAR_GEN2 },
+	{ RMOBILE_CPU_TYPE_R8A7794, "R8A7794", SOC_RCAR_GEN2 },
+	{ RMOBILE_CPU_TYPE_R8A7795, "R8A7795", SOC_RCAR_GEN3 },
+	{ RMOBILE_CPU_TYPE_R8A7796, "R8A7796", SOC_RCAR_GEN3 },
+	{ RMOBILE_CPU_TYPE_R8A77965, "R8A77965", SOC_RCAR_GEN3 },
+	{ RMOBILE_CPU_TYPE_R8A77970, "R8A77970", SOC_RCAR_GEN3 },
+	{ RMOBILE_CPU_TYPE_R8A77980, "R8A77980", SOC_RCAR_GEN3 },
+	{ RMOBILE_CPU_TYPE_R8A77990, "R8A77990", SOC_RCAR_GEN3 },
+	{ RMOBILE_CPU_TYPE_R8A77995, "R8A77995", SOC_RCAR_GEN3 },
 	{ 0x0, "CPU" },
 };
 
+static const struct udevice_id *of_soc_match_compatible(void)
+{
+	const struct udevice_id *of_match = soc_ids;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(soc_ids); i++) {
+		if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+					       of_match->compatible))
+			return of_match;
+		of_match++;
+	}
+
+	return NULL;
+}
+
 static int rmobile_cpuinfo_idx(void)
 {
 	int i = 0;
 	u32 cpu_type = rmobile_get_cpu_type();
+	const struct udevice_id *match = of_soc_match_compatible();
 
+	/*
+	 * This loop identifies CPU based on PRR register, it differentiates
+	 * RZ/G SoC's from R-Car SoC's by matching RZ/G SoC compatible string
+	 * from DT against the family_type.
+	 */
 	for (; i < ARRAY_SIZE(rmobile_cpuinfo); i++)
-		if (rmobile_cpuinfo[i].cpu_type == cpu_type)
-			break;
+		if (rmobile_cpuinfo[i].cpu_type == cpu_type) {
+			if (match &&
+			    rmobile_cpuinfo[i].family_type == match->data)
+				break;
+			else if (!match &&
+				 rmobile_cpuinfo[i].family_type != SOC_RZG2)
+				break;
+		}
 
 	return i;
 }
diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h
index a50249dc96..8bb64f59dd 100644
--- a/arch/arm/mach-rmobile/include/mach/rmobile.h
+++ b/arch/arm/mach-rmobile/include/mach/rmobile.h
@@ -27,6 +27,7 @@
 /* PRR CPU IDs */
 #define RMOBILE_CPU_TYPE_SH73A0		0x37
 #define RMOBILE_CPU_TYPE_R8A7740	0x40
+#define RMOBILE_CPU_TYPE_R8A774A1	0x52
 #define RMOBILE_CPU_TYPE_R8A7790	0x45
 #define RMOBILE_CPU_TYPE_R8A7791	0x47
 #define RMOBILE_CPU_TYPE_R8A7792	0x4A
-- 
2.17.1

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