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From: David Howells <dhowells@redhat.com>
To: Linus Torvalds <torvalds@linux-foundation.org>
Cc: dhowells@redhat.com, Peter Zijlstra <peterz@infradead.org>,
	kernel test robot <lkp@intel.com>, LKP <lkp@01.org>,
	Linux List Kernel Mailing <linux-kernel@vger.kernel.org>,
	Linux-MM <linux-mm@kvack.org>,
	linux-arch <linux-arch@vger.kernel.org>,
	Ingo Molnar <mingo@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Will Deacon <will.deacon@arm.com>,
	Andy Lutomirski <luto@kernel.org>, Nadav Amit <namit@vmware.com>
Subject: Re: 1808d65b55 ("asm-generic/tlb: Remove arch_tlb*_mmu()"): BUG: KASAN: stack-out-of-bounds in __change_page_attr_set_clr
Date: Fri, 12 Apr 2019 17:50:30 +0100	[thread overview]
Message-ID: <5890.1555087830@warthog.procyon.org.uk> (raw)
In-Reply-To: <CAHk-=wieBr3G=_ZGoCndi8XnuG1wtkedaGqkWB+=AVq65=_8sQ@mail.gmail.com>

Linus Torvalds <torvalds@linux-foundation.org> wrote:

> We should never have stack alignment bigger than 16 bytes.  And
> preferably not even that.

At least one arch I know of (FRV) had instructions that could atomically
load/store register pairs or register quads, but they had to be pair- or
quad-aligned (ie. 8- or 16-byte), which made for more efficient code if you
could use them.

I don't know whether any arch we currently support has features like this (I
know some have multi-reg load/stores, but they seem to require only
word-alignment).

David

WARNING: multiple messages have this Message-ID (diff)
From: David Howells <dhowells@redhat.com>
To: lkp@lists.01.org
Subject: Re: 1808d65b55 ("asm-generic/tlb: Remove arch_tlb*_mmu()"): BUG: KASAN: stack-out-of-bounds in __change_page_attr_set_clr
Date: Fri, 12 Apr 2019 17:50:30 +0100	[thread overview]
Message-ID: <5890.1555087830@warthog.procyon.org.uk> (raw)
In-Reply-To: <CAHk-=wieBr3G=_ZGoCndi8XnuG1wtkedaGqkWB+=AVq65=_8sQ@mail.gmail.com>

[-- Attachment #1: Type: text/plain, Size: 573 bytes --]

Linus Torvalds <torvalds@linux-foundation.org> wrote:

> We should never have stack alignment bigger than 16 bytes.  And
> preferably not even that.

At least one arch I know of (FRV) had instructions that could atomically
load/store register pairs or register quads, but they had to be pair- or
quad-aligned (ie. 8- or 16-byte), which made for more efficient code if you
could use them.

I don't know whether any arch we currently support has features like this (I
know some have multi-reg load/stores, but they seem to require only
word-alignment).

David

  parent reply	other threads:[~2019-04-12 16:50 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-04-10 14:55 1808d65b55 ("asm-generic/tlb: Remove arch_tlb*_mmu()"): BUG: KASAN: stack-out-of-bounds in __change_page_attr_set_clr kernel test robot
2019-04-10 14:55 ` kernel test robot
2019-04-11 19:39 ` Peter Zijlstra
2019-04-11 19:39   ` Peter Zijlstra
2019-04-11 19:54   ` Peter Zijlstra
2019-04-11 19:54     ` Peter Zijlstra
2019-04-11 21:13     ` Peter Zijlstra
2019-04-11 21:13       ` Peter Zijlstra
2019-04-12 10:56       ` Peter Zijlstra
2019-04-12 10:56         ` Peter Zijlstra
2019-04-12 11:17         ` Peter Zijlstra
2019-04-12 11:17           ` Peter Zijlstra
2019-04-12 15:11           ` Nadav Amit
2019-04-12 15:11             ` Nadav Amit
2019-04-12 15:18             ` Nadav Amit
2019-04-12 15:18               ` Nadav Amit
2019-04-12 17:05             ` Nadav Amit
2019-04-12 17:05               ` Nadav Amit
2019-04-12 17:14               ` Andy Lutomirski
2019-04-12 17:14                 ` Andy Lutomirski
2019-04-12 17:49                 ` Nadav Amit
2019-04-12 17:49                   ` Nadav Amit
2019-04-12 18:13               ` Peter Zijlstra
2019-04-12 18:13                 ` Peter Zijlstra
2019-04-12 18:19             ` Peter Zijlstra
2019-04-12 18:19               ` Peter Zijlstra
2019-04-12 19:42               ` Nadav Amit
2019-04-12 19:42                 ` Nadav Amit
2019-04-12 15:32         ` Linus Torvalds
2019-04-12 15:32           ` Linus Torvalds
2019-04-12 15:32           ` Linus Torvalds
2019-04-12 16:50         ` David Howells [this message]
2019-04-12 16:50           ` David Howells
2019-04-12 18:15           ` Peter Zijlstra
2019-04-12 18:15             ` Peter Zijlstra

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