All of lore.kernel.org
 help / color / mirror / Atom feed
From: James Morse <james.morse@arm.com>
To: Xie XiuQi <xiexiuqi@huawei.com>
Cc: christoffer.dall@linaro.org, marc.zyngier@arm.com,
	catalin.marinas@arm.com, will.deacon@arm.com, fu.wei@linaro.org,
	rostedt@goodmis.org, hanjun.guo@linaro.org,
	shiju.jose@huawei.com, linux-arm-kernel@lists.infradead.org,
	kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org,
	gengdongjiu@huawei.com, zhengqiang10@huawei.com,
	wuquanming@huawei.com, wangxiongfeng2@huawei.com
Subject: Re: [PATCH v3 4/8] APEI: GHES: reserve a virtual page for SEI context
Date: Fri, 31 Mar 2017 17:22:42 +0100	[thread overview]
Message-ID: <58DE8252.7070709@arm.com> (raw)
In-Reply-To: <1490869877-118713-5-git-send-email-xiexiuqi@huawei.com>

Hi Xie XiuQi,

On 30/03/17 11:31, Xie XiuQi wrote:
> On arm64 platform, SEI may interrupt code which had interrupts masked.
> But SEI could be masked, so it's not treated as NMI, however SEA is
> treated as NMI.
> 
> So, the  memory area used to transfer hardware error information from
> BIOS to Linux can be determined only in NMI, SEI(arm64), IRQ or timer
> handler.
> 
> In this patch, we add a virtual page for SEI context.

I don't think this is the best way of solving the interaction problem. If we
ever need to add another notification method this gets even more complicated,
and the ioremap code has to know how these methods can interact.


> diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
> index 045d101..b1f9b1f 100644
> --- a/drivers/acpi/apei/ghes.c
> +++ b/drivers/acpi/apei/ghes.c
> @@ -155,54 +162,55 @@ static void ghes_ioremap_exit(void)

> -static void __iomem *ghes_ioremap_pfn_irq(u64 pfn)
> -{
> -	unsigned long vaddr, paddr;
> -	pgprot_t prot;
> -
> -	vaddr = (unsigned long)GHES_IOREMAP_IRQ_PAGE(ghes_ioremap_area->addr);
> +	if (in_nmi()) {
> +		raw_spin_lock(&ghes_ioremap_lock_nmi);
> +		vaddr = (unsigned long)GHES_IOREMAP_NMI_PAGE(ghes_ioremap_area->addr);
> +	} else if (this_cpu_read(sei_in_process)) {

> +		spin_lock_irqsave(&ghes_ioremap_lock_sei, flags);

I think this one should be a raw_spin_lock. I'm pretty sure this is for RT-linux
where spin_lock() on a contented lock will call schedule() in the same way
mutex_lock() does. If interrupts were masked by arch code then you need to use
raw_spin_lock.
So now we need to know how we got in here, we interrupted the SError handler so
this should only be Synchronous External Abort. Having to know how we got here
is another problem with this approach.


As suggested earlier[0], I think the best way is to allocate one page of virtual
address space per struct ghes, and move the locks out to the notify calls, which
can know how they are called.

I've pushed a branch to:
http://www.linux-arm.org/git?p=linux-jm.git;a=commit;h=refs/heads/apei_ioremap_rework/v1

I intend to post those patches as an RFC series later in the cycle, I've only
build tested it so far.


Thanks,

James

> +		vaddr = (unsigned long)GHES_IOREMAP_SEI_PAGE(ghes_ioremap_area->addr);
> +	} else {
> +		spin_lock_irqsave(&ghes_ioremap_lock_irq, flags);
> +		vaddr = (unsigned long)GHES_IOREMAP_IRQ_PAGE(ghes_ioremap_area->addr);
> +	}


[0] https://lkml.org/lkml/2017/3/20/434


WARNING: multiple messages have this Message-ID (diff)
From: james.morse@arm.com (James Morse)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v3 4/8] APEI: GHES: reserve a virtual page for SEI context
Date: Fri, 31 Mar 2017 17:22:42 +0100	[thread overview]
Message-ID: <58DE8252.7070709@arm.com> (raw)
In-Reply-To: <1490869877-118713-5-git-send-email-xiexiuqi@huawei.com>

Hi Xie XiuQi,

On 30/03/17 11:31, Xie XiuQi wrote:
> On arm64 platform, SEI may interrupt code which had interrupts masked.
> But SEI could be masked, so it's not treated as NMI, however SEA is
> treated as NMI.
> 
> So, the  memory area used to transfer hardware error information from
> BIOS to Linux can be determined only in NMI, SEI(arm64), IRQ or timer
> handler.
> 
> In this patch, we add a virtual page for SEI context.

I don't think this is the best way of solving the interaction problem. If we
ever need to add another notification method this gets even more complicated,
and the ioremap code has to know how these methods can interact.


> diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
> index 045d101..b1f9b1f 100644
> --- a/drivers/acpi/apei/ghes.c
> +++ b/drivers/acpi/apei/ghes.c
> @@ -155,54 +162,55 @@ static void ghes_ioremap_exit(void)

> -static void __iomem *ghes_ioremap_pfn_irq(u64 pfn)
> -{
> -	unsigned long vaddr, paddr;
> -	pgprot_t prot;
> -
> -	vaddr = (unsigned long)GHES_IOREMAP_IRQ_PAGE(ghes_ioremap_area->addr);
> +	if (in_nmi()) {
> +		raw_spin_lock(&ghes_ioremap_lock_nmi);
> +		vaddr = (unsigned long)GHES_IOREMAP_NMI_PAGE(ghes_ioremap_area->addr);
> +	} else if (this_cpu_read(sei_in_process)) {

> +		spin_lock_irqsave(&ghes_ioremap_lock_sei, flags);

I think this one should be a raw_spin_lock. I'm pretty sure this is for RT-linux
where spin_lock() on a contented lock will call schedule() in the same way
mutex_lock() does. If interrupts were masked by arch code then you need to use
raw_spin_lock.
So now we need to know how we got in here, we interrupted the SError handler so
this should only be Synchronous External Abort. Having to know how we got here
is another problem with this approach.


As suggested earlier[0], I think the best way is to allocate one page of virtual
address space per struct ghes, and move the locks out to the notify calls, which
can know how they are called.

I've pushed a branch to:
http://www.linux-arm.org/git?p=linux-jm.git;a=commit;h=refs/heads/apei_ioremap_rework/v1

I intend to post those patches as an RFC series later in the cycle, I've only
build tested it so far.


Thanks,

James

> +		vaddr = (unsigned long)GHES_IOREMAP_SEI_PAGE(ghes_ioremap_area->addr);
> +	} else {
> +		spin_lock_irqsave(&ghes_ioremap_lock_irq, flags);
> +		vaddr = (unsigned long)GHES_IOREMAP_IRQ_PAGE(ghes_ioremap_area->addr);
> +	}


[0] https://lkml.org/lkml/2017/3/20/434

  reply	other threads:[~2017-03-31 16:23 UTC|newest]

Thread overview: 139+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-30 10:31 [PATCH v3 0/8] arm64: acpi: apei: handle SEI notification type for ARMv8 Xie XiuQi
2017-03-30 10:31 ` Xie XiuQi
2017-03-30 10:31 ` Xie XiuQi
2017-03-30 10:31 ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 1/8] trace: ras: add ARM processor error information trace event Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 16:02   ` Steven Rostedt
2017-03-30 16:02     ` Steven Rostedt
2017-03-30 16:02     ` Steven Rostedt
2017-04-06  9:03     ` Xie XiuQi
2017-04-06  9:03       ` Xie XiuQi
2017-04-06  9:03       ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 2/8] acpi: apei: handle SEI notification type for ARMv8 Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-31 16:20   ` James Morse
2017-03-31 16:20     ` James Morse
2017-04-06  9:11     ` Xie XiuQi
2017-04-06  9:11       ` Xie XiuQi
2017-04-06  9:11       ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 3/8] arm64: apei: add a per-cpu variable to indecate sei is processing Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 4/8] APEI: GHES: reserve a virtual page for SEI context Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-31 16:22   ` James Morse [this message]
2017-03-31 16:22     ` James Morse
2017-04-06  9:25     ` Xie XiuQi
2017-04-06  9:25       ` Xie XiuQi
2017-04-06  9:25       ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 5/8] arm64: KVM: add guest SEI support Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 6/8] arm64: RAS: add ras extension runtime detection Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 7/8] arm64: exception: handle asynchronous SError interrupt Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-04-13  8:44   ` Xiongfeng Wang
2017-04-13  8:44     ` Xiongfeng Wang
2017-04-13  8:44     ` Xiongfeng Wang
2017-04-13 10:51   ` Mark Rutland
2017-04-13 10:51     ` Mark Rutland
2017-04-13 10:51     ` Mark Rutland
2017-04-14  7:03     ` Xie XiuQi
2017-04-14  7:03       ` Xie XiuQi
2017-04-14  7:03       ` Xie XiuQi
2017-04-18  1:09     ` Xiongfeng Wang
2017-04-18  1:09       ` Xiongfeng Wang
2017-04-18  1:09       ` Xiongfeng Wang
2017-04-18 10:51       ` James Morse
2017-04-18 10:51         ` James Morse
2017-04-18 10:51         ` James Morse
2017-04-19  2:37         ` Xiongfeng Wang
2017-04-19  2:37           ` Xiongfeng Wang
2017-04-19  2:37           ` Xiongfeng Wang
2017-04-20  8:52           ` James Morse
2017-04-20  8:52             ` James Morse
2017-04-20  8:52             ` James Morse
2017-04-21 11:33             ` Xiongfeng Wang
2017-04-21 11:33               ` Xiongfeng Wang
2017-04-21 11:33               ` Xiongfeng Wang
2017-04-24 17:14               ` James Morse
2017-04-24 17:14                 ` James Morse
2017-04-24 17:14                 ` James Morse
2017-04-28  2:55                 ` Xiongfeng Wang
2017-04-28  2:55                   ` Xiongfeng Wang
2017-04-28  2:55                   ` Xiongfeng Wang
2017-05-08 17:27                   ` James Morse
2017-05-08 17:27                     ` James Morse
2017-05-09  2:16                     ` Xiongfeng Wang
2017-05-09  2:16                       ` Xiongfeng Wang
2017-05-09  2:16                       ` Xiongfeng Wang
2017-04-21 10:46   ` Xiongfeng Wang
2017-04-21 10:46     ` Xiongfeng Wang
2017-04-21 10:46     ` Xiongfeng Wang
2017-03-30 10:31 ` [PATCH v3 8/8] arm64: exception: check shared writable page in SEI handler Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-04-07 15:56   ` James Morse
2017-04-07 15:56     ` James Morse
2017-04-07 15:56     ` James Morse
2017-04-12  8:35     ` Xiongfeng Wang
2017-04-12  8:35       ` Xiongfeng Wang
2017-04-12  8:35       ` Xiongfeng Wang
2017-03-30 10:31 ` [PATCH v3 0/8] arm64: acpi: apei: handle SEI notification type for ARMv8 Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 1/8] trace: ras: add ARM processor error information trace event Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-04-14 20:36   ` Baicar, Tyler
2017-04-14 20:36     ` Baicar, Tyler
2017-04-17  3:08     ` Xie XiuQi
2017-04-17  3:08       ` Xie XiuQi
2017-04-17  3:08       ` Xie XiuQi
2017-04-17  3:16       ` Xie XiuQi
2017-04-17  3:16         ` Xie XiuQi
2017-04-17  3:16         ` Xie XiuQi
2017-04-17 17:18         ` Baicar, Tyler
2017-04-17 17:18           ` Baicar, Tyler
2017-04-18  2:22           ` Xie XiuQi
2017-04-18  2:22             ` Xie XiuQi
2017-04-18  2:22             ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 2/8] acpi: apei: handle SEI notification type for ARMv8 Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 3/8] arm64: apei: add a per-cpu variable to indecate sei is processing Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 4/8] APEI: GHES: reserve a virtual page for SEI context Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 5/8] arm64: KVM: add guest SEI support Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 6/8] arm64: RAS: add ras extension runtime detection Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 7/8] arm64: exception: handle asynchronous SError interrupt Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31 ` [PATCH v3 8/8] arm64: exception: check shared writable page in SEI handler Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi
2017-03-30 10:31   ` Xie XiuQi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=58DE8252.7070709@arm.com \
    --to=james.morse@arm.com \
    --cc=catalin.marinas@arm.com \
    --cc=christoffer.dall@linaro.org \
    --cc=fu.wei@linaro.org \
    --cc=gengdongjiu@huawei.com \
    --cc=hanjun.guo@linaro.org \
    --cc=kvm@vger.kernel.org \
    --cc=kvmarm@lists.cs.columbia.edu \
    --cc=linux-acpi@vger.kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=marc.zyngier@arm.com \
    --cc=rostedt@goodmis.org \
    --cc=shiju.jose@huawei.com \
    --cc=wangxiongfeng2@huawei.com \
    --cc=will.deacon@arm.com \
    --cc=wuquanming@huawei.com \
    --cc=xiexiuqi@huawei.com \
    --cc=zhengqiang10@huawei.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.