* [PATCH v2] drm/amdgpu: PRT support for gfx9 (v2)
@ 2017-04-19 1:53 Junwei Zhang
[not found] ` <1492566809-7312-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 5+ messages in thread
From: Junwei Zhang @ 2017-04-19 1:53 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, nicolai.haehnle-5C7GfCeVMHo
Cc: Junwei Zhang, david1.zhou-5C7GfCeVMHo
v2: unify PRT bit for all ASICs
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Acked-by: David Zhou <david1.zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index f804d38..f4087c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -1473,6 +1473,11 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
spin_unlock(&vm->status_lock);
list_for_each_entry(mapping, &bo_va->invalids, list) {
+ if (mapping->flags & AMDGPU_PTE_PRT) {
+ flags |= AMDGPU_PTE_PRT;
+ flags &= ~AMDGPU_PTE_VALID;
+ }
+
r = amdgpu_vm_bo_split_mapping(adev, exclusive,
gtt_flags, pages_addr, vm,
mapping, flags, mem,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 0f547c6..8eba2d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -65,7 +65,8 @@
#define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
-#define AMDGPU_PTE_PRT (1ULL << 63)
+/* TILED for VEGA10, reserved for older ASICs */
+#define AMDGPU_PTE_PRT (1ULL << 51)
/* VEGA10 only */
#define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
--
1.9.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/amdgpu: PRT support for gfx9 (v2)
[not found] ` <1492566809-7312-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
@ 2017-04-19 7:28 ` Christian König
[not found] ` <b655c990-648a-1e0a-c22f-6cbd32010c71-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
0 siblings, 1 reply; 5+ messages in thread
From: Christian König @ 2017-04-19 7:28 UTC (permalink / raw)
To: Junwei Zhang, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
nicolai.haehnle-5C7GfCeVMHo
Cc: david1.zhou-5C7GfCeVMHo
Am 19.04.2017 um 03:53 schrieb Junwei Zhang:
> v2: unify PRT bit for all ASICs
>
> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
> Acked-by: David Zhou <david1.zhou@amd.com>
>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index f804d38..f4087c4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -1473,6 +1473,11 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
> spin_unlock(&vm->status_lock);
>
> list_for_each_entry(mapping, &bo_va->invalids, list) {
> + if (mapping->flags & AMDGPU_PTE_PRT) {
> + flags |= AMDGPU_PTE_PRT;
> + flags &= ~AMDGPU_PTE_VALID;
> + }
Please move that into amdgpu_vm_bo_split_mapping() where we apply the
other flags as well.
Additional to that we need a check like "&& adev->asic_type >=
CHIP_VEGA10" here.
Not nice to have that ASIC specifc code here, but we can clean that up
later on.
Regards,
Christian.
> +
> r = amdgpu_vm_bo_split_mapping(adev, exclusive,
> gtt_flags, pages_addr, vm,
> mapping, flags, mem,
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 0f547c6..8eba2d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -65,7 +65,8 @@
>
> #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
>
> -#define AMDGPU_PTE_PRT (1ULL << 63)
> +/* TILED for VEGA10, reserved for older ASICs */
> +#define AMDGPU_PTE_PRT (1ULL << 51)
>
> /* VEGA10 only */
> #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/amdgpu: PRT support for gfx9 (v2)
[not found] ` <b655c990-648a-1e0a-c22f-6cbd32010c71-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
@ 2017-04-19 8:10 ` Zhang, Jerry (Junwei)
[not found] ` <58F71B88.8040006-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 5+ messages in thread
From: Zhang, Jerry (Junwei) @ 2017-04-19 8:10 UTC (permalink / raw)
To: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
nicolai.haehnle-5C7GfCeVMHo
Cc: david1.zhou-5C7GfCeVMHo
On 04/19/2017 03:28 PM, Christian König wrote:
> Am 19.04.2017 um 03:53 schrieb Junwei Zhang:
>> v2: unify PRT bit for all ASICs
>>
>> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
>> Acked-by: David Zhou <david1.zhou@amd.com>
>>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++-
>> 2 files changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index f804d38..f4087c4 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -1473,6 +1473,11 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
>> spin_unlock(&vm->status_lock);
>> list_for_each_entry(mapping, &bo_va->invalids, list) {
>> + if (mapping->flags & AMDGPU_PTE_PRT) {
>> + flags |= AMDGPU_PTE_PRT;
>> + flags &= ~AMDGPU_PTE_VALID;
>> + }
>
> Please move that into amdgpu_vm_bo_split_mapping() where we apply the other
> flags as well.
Actually I tried this way at first.
But it invalidates the CLEAR op and any calling amdgpu_vm_clear_freed(), as the
input flags 0 cannot clear the PTE TILED bit.
>
> Additional to that we need a check like "&& adev->asic_type >= CHIP_VEGA10" here.
>
> Not nice to have that ASIC specifc code here, but we can clean that up later on.
although that's reserved bit for older ASIC, it sounds reasonable.
Jerry
>
> Regards,
> Christian.
>
>> +
>> r = amdgpu_vm_bo_split_mapping(adev, exclusive,
>> gtt_flags, pages_addr, vm,
>> mapping, flags, mem,
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> index 0f547c6..8eba2d3 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> @@ -65,7 +65,8 @@
>> #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
>> -#define AMDGPU_PTE_PRT (1ULL << 63)
>> +/* TILED for VEGA10, reserved for older ASICs */
>> +#define AMDGPU_PTE_PRT (1ULL << 51)
>> /* VEGA10 only */
>> #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
>
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/amdgpu: PRT support for gfx9 (v2)
[not found] ` <58F71B88.8040006-5C7GfCeVMHo@public.gmane.org>
@ 2017-04-19 11:40 ` Christian König
[not found] ` <3f5eac3c-c7da-58e4-819e-a640785dbfdc-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
0 siblings, 1 reply; 5+ messages in thread
From: Christian König @ 2017-04-19 11:40 UTC (permalink / raw)
To: Zhang, Jerry (Junwei),
amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
nicolai.haehnle-5C7GfCeVMHo
Cc: david1.zhou-5C7GfCeVMHo
Am 19.04.2017 um 10:10 schrieb Zhang, Jerry (Junwei):
> On 04/19/2017 03:28 PM, Christian König wrote:
>> Am 19.04.2017 um 03:53 schrieb Junwei Zhang:
>>> v2: unify PRT bit for all ASICs
>>>
>>> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
>>> Acked-by: David Zhou <david1.zhou@amd.com>
>>>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++-
>>> 2 files changed, 7 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>> index f804d38..f4087c4 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>> @@ -1473,6 +1473,11 @@ int amdgpu_vm_bo_update(struct amdgpu_device
>>> *adev,
>>> spin_unlock(&vm->status_lock);
>>> list_for_each_entry(mapping, &bo_va->invalids, list) {
>>> + if (mapping->flags & AMDGPU_PTE_PRT) {
>>> + flags |= AMDGPU_PTE_PRT;
>>> + flags &= ~AMDGPU_PTE_VALID;
>>> + }
>>
>> Please move that into amdgpu_vm_bo_split_mapping() where we apply the
>> other
>> flags as well.
>
> Actually I tried this way at first.
> But it invalidates the CLEAR op and any calling
> amdgpu_vm_clear_freed(), as the input flags 0 cannot clear the PTE
> TILED bit.
Good point, but calling amdgpu_vm_bo_split_mapping() from
amdgpu_vm_clear_freed() is nonsense in the first place.
We can clear a whole PT with just a single command, no need for
splitting it into smaller operations.
I'm going to send a patch to fix this in a minute.
Christian.
>
>>
>> Additional to that we need a check like "&& adev->asic_type >=
>> CHIP_VEGA10" here.
>>
>> Not nice to have that ASIC specifc code here, but we can clean that
>> up later on.
>
> although that's reserved bit for older ASIC, it sounds reasonable.
>
> Jerry
>
>>
>> Regards,
>> Christian.
>>
>>> +
>>> r = amdgpu_vm_bo_split_mapping(adev, exclusive,
>>> gtt_flags, pages_addr, vm,
>>> mapping, flags, mem,
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>> index 0f547c6..8eba2d3 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>> @@ -65,7 +65,8 @@
>>> #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
>>> -#define AMDGPU_PTE_PRT (1ULL << 63)
>>> +/* TILED for VEGA10, reserved for older ASICs */
>>> +#define AMDGPU_PTE_PRT (1ULL << 51)
>>> /* VEGA10 only */
>>> #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
>>
>>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v2] drm/amdgpu: PRT support for gfx9 (v2)
[not found] ` <3f5eac3c-c7da-58e4-819e-a640785dbfdc-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
@ 2017-04-20 6:56 ` Zhang, Jerry (Junwei)
0 siblings, 0 replies; 5+ messages in thread
From: Zhang, Jerry (Junwei) @ 2017-04-20 6:56 UTC (permalink / raw)
To: Christian König, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
nicolai.haehnle-5C7GfCeVMHo
Cc: david1.zhou-5C7GfCeVMHo
On 04/19/2017 07:40 PM, Christian König wrote:
> Am 19.04.2017 um 10:10 schrieb Zhang, Jerry (Junwei):
>> On 04/19/2017 03:28 PM, Christian König wrote:
>>> Am 19.04.2017 um 03:53 schrieb Junwei Zhang:
>>>> v2: unify PRT bit for all ASICs
>>>>
>>>> Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
>>>> Acked-by: David Zhou <david1.zhou@amd.com>
>>>>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ++-
>>>> 2 files changed, 7 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>>> index f804d38..f4087c4 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>>> @@ -1473,6 +1473,11 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
>>>> spin_unlock(&vm->status_lock);
>>>> list_for_each_entry(mapping, &bo_va->invalids, list) {
>>>> + if (mapping->flags & AMDGPU_PTE_PRT) {
>>>> + flags |= AMDGPU_PTE_PRT;
>>>> + flags &= ~AMDGPU_PTE_VALID;
>>>> + }
>>>
>>> Please move that into amdgpu_vm_bo_split_mapping() where we apply the other
>>> flags as well.
>>
>> Actually I tried this way at first.
>> But it invalidates the CLEAR op and any calling amdgpu_vm_clear_freed(), as
>> the input flags 0 cannot clear the PTE TILED bit.
>
> Good point, but calling amdgpu_vm_bo_split_mapping() from
> amdgpu_vm_clear_freed() is nonsense in the first place.
>
> We can clear a whole PT with just a single command, no need for splitting it
> into smaller operations.
>
> I'm going to send a patch to fix this in a minute.
Thanks for your patch.
Based on that, I prepare the patch v3, it works on my side.
Please help to check it.
Jerry
>
> Christian.
>
>>
>>>
>>> Additional to that we need a check like "&& adev->asic_type >= CHIP_VEGA10"
>>> here.
>>>
>>> Not nice to have that ASIC specifc code here, but we can clean that up later
>>> on.
>>
>> although that's reserved bit for older ASIC, it sounds reasonable.
>>
>> Jerry
>>
>>>
>>> Regards,
>>> Christian.
>>>
>>>> +
>>>> r = amdgpu_vm_bo_split_mapping(adev, exclusive,
>>>> gtt_flags, pages_addr, vm,
>>>> mapping, flags, mem,
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>>> index 0f547c6..8eba2d3 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>>>> @@ -65,7 +65,8 @@
>>>> #define AMDGPU_PTE_FRAG(x) ((x & 0x1fULL) << 7)
>>>> -#define AMDGPU_PTE_PRT (1ULL << 63)
>>>> +/* TILED for VEGA10, reserved for older ASICs */
>>>> +#define AMDGPU_PTE_PRT (1ULL << 51)
>>>> /* VEGA10 only */
>>>> #define AMDGPU_PTE_MTYPE(a) ((uint64_t)a << 57)
>>>
>>>
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-04-20 6:56 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-04-19 1:53 [PATCH v2] drm/amdgpu: PRT support for gfx9 (v2) Junwei Zhang
[not found] ` <1492566809-7312-1-git-send-email-Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
2017-04-19 7:28 ` Christian König
[not found] ` <b655c990-648a-1e0a-c22f-6cbd32010c71-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-19 8:10 ` Zhang, Jerry (Junwei)
[not found] ` <58F71B88.8040006-5C7GfCeVMHo@public.gmane.org>
2017-04-19 11:40 ` Christian König
[not found] ` <3f5eac3c-c7da-58e4-819e-a640785dbfdc-ANTagKRnAhcb1SvskN2V4Q@public.gmane.org>
2017-04-20 6:56 ` Zhang, Jerry (Junwei)
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