* [PATCH v2] MIPS: io: add a barrier after register read in readX()
@ 2018-04-02 18:13 ` Sinan Kaya
0 siblings, 0 replies; 6+ messages in thread
From: Sinan Kaya @ 2018-04-02 18:13 UTC (permalink / raw)
To: linux-mips, timur, sulrich
Cc: arnd, linux-arm-msm, linux-arm-kernel, Sinan Kaya, Ralf Baechle,
James Hogan, Paul Burton, linux-kernel
While a barrier is present in writeX() function before the register write,
a similar barrier is missing in the readX() function after the register
read. This could allow memory accesses following readX() to observe
stale data.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Reported-by: Arnd Bergmann <arnd@arndb.de>
---
arch/mips/include/asm/io.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 0cbf3af..7f9068d 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -377,6 +377,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
BUG(); \
} \
\
+ war_io_reorder_wmb(); \
return pfx##ioswab##bwlq(__mem, __val); \
}
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2] MIPS: io: add a barrier after register read in readX()
@ 2018-04-02 18:13 ` Sinan Kaya
0 siblings, 0 replies; 6+ messages in thread
From: Sinan Kaya @ 2018-04-02 18:13 UTC (permalink / raw)
To: linux-arm-kernel
While a barrier is present in writeX() function before the register write,
a similar barrier is missing in the readX() function after the register
read. This could allow memory accesses following readX() to observe
stale data.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
Reported-by: Arnd Bergmann <arnd@arndb.de>
---
arch/mips/include/asm/io.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 0cbf3af..7f9068d 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -377,6 +377,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
BUG(); \
} \
\
+ war_io_reorder_wmb(); \
return pfx##ioswab##bwlq(__mem, __val); \
}
--
2.7.4
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2] MIPS: io: add a barrier after register read in readX()
2018-04-02 18:13 ` Sinan Kaya
@ 2018-04-03 7:21 ` Arnd Bergmann
-1 siblings, 0 replies; 6+ messages in thread
From: Arnd Bergmann @ 2018-04-03 7:21 UTC (permalink / raw)
To: Sinan Kaya
Cc: open list:RALINK MIPS ARCHITECTURE, Timur Tabi, sulrich,
linux-arm-msm, Linux ARM, Ralf Baechle, James Hogan, Paul Burton,
Linux Kernel Mailing List
On Mon, Apr 2, 2018 at 8:13 PM, Sinan Kaya <okaya@codeaurora.org> wrote:
> While a barrier is present in writeX() function before the register write,
> a similar barrier is missing in the readX() function after the register
> read. This could allow memory accesses following readX() to observe
> stale data.
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
> Reported-by: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/mips/include/asm/io.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> index 0cbf3af..7f9068d 100644
> --- a/arch/mips/include/asm/io.h
> +++ b/arch/mips/include/asm/io.h
> @@ -377,6 +377,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
> BUG(); \
> } \
> \
> + war_io_reorder_wmb(); \
> return pfx##ioswab##bwlq(__mem, __val); \
> }
I'm not sure if this is the right barrier: what we want here is a read
barrier to
prevent any following memory access from being prefetched ahead of the readl(),
so I would have expected a kind of rmb() rather than wmb().
The barrier you used here is defined as
#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
#define war_io_reorder_wmb() wmb()
#else
#define war_io_reorder_wmb() do { } while (0)
#endif
which appears to list the particular CPUs that have a reordering
write buffer. That may not be the same set of CPUs that have the
capability to do out-of-order loads.
Arnd
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2] MIPS: io: add a barrier after register read in readX()
@ 2018-04-03 7:21 ` Arnd Bergmann
0 siblings, 0 replies; 6+ messages in thread
From: Arnd Bergmann @ 2018-04-03 7:21 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Apr 2, 2018 at 8:13 PM, Sinan Kaya <okaya@codeaurora.org> wrote:
> While a barrier is present in writeX() function before the register write,
> a similar barrier is missing in the readX() function after the register
> read. This could allow memory accesses following readX() to observe
> stale data.
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
> Reported-by: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/mips/include/asm/io.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> index 0cbf3af..7f9068d 100644
> --- a/arch/mips/include/asm/io.h
> +++ b/arch/mips/include/asm/io.h
> @@ -377,6 +377,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
> BUG(); \
> } \
> \
> + war_io_reorder_wmb(); \
> return pfx##ioswab##bwlq(__mem, __val); \
> }
I'm not sure if this is the right barrier: what we want here is a read
barrier to
prevent any following memory access from being prefetched ahead of the readl(),
so I would have expected a kind of rmb() rather than wmb().
The barrier you used here is defined as
#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
#define war_io_reorder_wmb() wmb()
#else
#define war_io_reorder_wmb() do { } while (0)
#endif
which appears to list the particular CPUs that have a reordering
write buffer. That may not be the same set of CPUs that have the
capability to do out-of-order loads.
Arnd
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2] MIPS: io: add a barrier after register read in readX()
2018-04-03 7:21 ` Arnd Bergmann
@ 2018-04-03 12:38 ` Sinan Kaya
-1 siblings, 0 replies; 6+ messages in thread
From: Sinan Kaya @ 2018-04-03 12:38 UTC (permalink / raw)
To: Arnd Bergmann
Cc: open list:RALINK MIPS ARCHITECTURE, Timur Tabi, sulrich,
linux-arm-msm, Linux ARM, Ralf Baechle, James Hogan, Paul Burton,
Linux Kernel Mailing List
On 4/3/2018 3:21 AM, Arnd Bergmann wrote:
> On Mon, Apr 2, 2018 at 8:13 PM, Sinan Kaya <okaya@codeaurora.org> wrote:
>> While a barrier is present in writeX() function before the register write,
>> a similar barrier is missing in the readX() function after the register
>> read. This could allow memory accesses following readX() to observe
>> stale data.
>>
>> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
>> Reported-by: Arnd Bergmann <arnd@arndb.de>
>> ---
>> arch/mips/include/asm/io.h | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
>> index 0cbf3af..7f9068d 100644
>> --- a/arch/mips/include/asm/io.h
>> +++ b/arch/mips/include/asm/io.h
>> @@ -377,6 +377,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
>> BUG(); \
>> } \
>> \
>> + war_io_reorder_wmb(); \
>> return pfx##ioswab##bwlq(__mem, __val); \
>> }
>
> I'm not sure if this is the right barrier: what we want here is a read
> barrier to
> prevent any following memory access from being prefetched ahead of the readl(),
> so I would have expected a kind of rmb() rather than wmb().
>
That's true. There was too much macro-ism in the code. I was thinking war_io_reorder_wmb()
to be a mb() under the hood. I'll fix and post an update.
> The barrier you used here is defined as
>
> #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
> #define war_io_reorder_wmb() wmb()
> #else
> #define war_io_reorder_wmb() do { } while (0)
> #endif
>
> which appears to list the particular CPUs that have a reordering
> write buffer. That may not be the same set of CPUs that have the
> capability to do out-of-order loads.
>
> Arnd
>
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2] MIPS: io: add a barrier after register read in readX()
@ 2018-04-03 12:38 ` Sinan Kaya
0 siblings, 0 replies; 6+ messages in thread
From: Sinan Kaya @ 2018-04-03 12:38 UTC (permalink / raw)
To: linux-arm-kernel
On 4/3/2018 3:21 AM, Arnd Bergmann wrote:
> On Mon, Apr 2, 2018 at 8:13 PM, Sinan Kaya <okaya@codeaurora.org> wrote:
>> While a barrier is present in writeX() function before the register write,
>> a similar barrier is missing in the readX() function after the register
>> read. This could allow memory accesses following readX() to observe
>> stale data.
>>
>> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
>> Reported-by: Arnd Bergmann <arnd@arndb.de>
>> ---
>> arch/mips/include/asm/io.h | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
>> index 0cbf3af..7f9068d 100644
>> --- a/arch/mips/include/asm/io.h
>> +++ b/arch/mips/include/asm/io.h
>> @@ -377,6 +377,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
>> BUG(); \
>> } \
>> \
>> + war_io_reorder_wmb(); \
>> return pfx##ioswab##bwlq(__mem, __val); \
>> }
>
> I'm not sure if this is the right barrier: what we want here is a read
> barrier to
> prevent any following memory access from being prefetched ahead of the readl(),
> so I would have expected a kind of rmb() rather than wmb().
>
That's true. There was too much macro-ism in the code. I was thinking war_io_reorder_wmb()
to be a mb() under the hood. I'll fix and post an update.
> The barrier you used here is defined as
>
> #if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT)
> #define war_io_reorder_wmb() wmb()
> #else
> #define war_io_reorder_wmb() do { } while (0)
> #endif
>
> which appears to list the particular CPUs that have a reordering
> write buffer. That may not be the same set of CPUs that have the
> capability to do out-of-order loads.
>
> Arnd
>
--
Sinan Kaya
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-04-03 12:38 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2018-04-02 18:13 [PATCH v2] MIPS: io: add a barrier after register read in readX() Sinan Kaya
2018-04-02 18:13 ` Sinan Kaya
2018-04-03 7:21 ` Arnd Bergmann
2018-04-03 7:21 ` Arnd Bergmann
2018-04-03 12:38 ` Sinan Kaya
2018-04-03 12:38 ` Sinan Kaya
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