* [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
@ 2017-05-02 14:05 ` Laxman Dewangan
0 siblings, 0 replies; 11+ messages in thread
From: Laxman Dewangan @ 2017-05-02 14:05 UTC (permalink / raw)
To: thierry.reding-Re5JQEeQqe8AvxtiuMwx3w, jonathanh-DDmLM1+adcrQT0dZR+AlfA
Cc: linux-pwm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Laxman Dewangan
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
From HW team:
Before Tegra186, it is 38.4MHz.
In Tegra186, it is 102MHz.
Add support to limit the clock source frequency to the maximum IP
supported frequency. Provide these values via SoC chipdata.
Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
---
Changes from V1:
- Set the 48MHz maximum frequency for Tegra210 and earlier.
- Set the maximum frequency unconditionally as per V1 review comment.
---
drivers/pwm/pwm-tegra.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 8c6ed55..e9b33f0 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -41,6 +41,9 @@
struct tegra_pwm_soc {
unsigned int num_channels;
+
+ /* Maximum IP frequency for given SoCs */
+ unsigned long max_frequency;
};
struct tegra_pwm_chip {
@@ -201,7 +204,18 @@ static int tegra_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->clk))
return PTR_ERR(pwm->clk);
- /* Read PWM clock rate from source */
+ /* Set maximum frequency of the IP */
+ ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * The requested and configured frequency may differ due to
+ * clock register resolutions. Get the configured frequency
+ * so that PWM period can be calculated more accurately.
+ */
pwm->clk_rate = clk_get_rate(pwm->clk);
pwm->rst = devm_reset_control_get(&pdev->dev, "pwm");
@@ -273,10 +287,12 @@ static int tegra_pwm_resume(struct device *dev)
static const struct tegra_pwm_soc tegra20_pwm_soc = {
.num_channels = 4,
+ .max_frequency = 48000000UL,
};
static const struct tegra_pwm_soc tegra186_pwm_soc = {
.num_channels = 1,
+ .max_frequency = 102000000UL,
};
static const struct of_device_id tegra_pwm_of_match[] = {
--
2.1.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
@ 2017-05-02 14:05 ` Laxman Dewangan
0 siblings, 0 replies; 11+ messages in thread
From: Laxman Dewangan @ 2017-05-02 14:05 UTC (permalink / raw)
To: thierry.reding, jonathanh
Cc: linux-pwm, linux-tegra, linux-kernel, Laxman Dewangan
The PWM hardware IP is taped-out with different maximum frequency
on different SoCs.
>From HW team:
Before Tegra186, it is 38.4MHz.
In Tegra186, it is 102MHz.
Add support to limit the clock source frequency to the maximum IP
supported frequency. Provide these values via SoC chipdata.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
---
Changes from V1:
- Set the 48MHz maximum frequency for Tegra210 and earlier.
- Set the maximum frequency unconditionally as per V1 review comment.
---
drivers/pwm/pwm-tegra.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c
index 8c6ed55..e9b33f0 100644
--- a/drivers/pwm/pwm-tegra.c
+++ b/drivers/pwm/pwm-tegra.c
@@ -41,6 +41,9 @@
struct tegra_pwm_soc {
unsigned int num_channels;
+
+ /* Maximum IP frequency for given SoCs */
+ unsigned long max_frequency;
};
struct tegra_pwm_chip {
@@ -201,7 +204,18 @@ static int tegra_pwm_probe(struct platform_device *pdev)
if (IS_ERR(pwm->clk))
return PTR_ERR(pwm->clk);
- /* Read PWM clock rate from source */
+ /* Set maximum frequency of the IP */
+ ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * The requested and configured frequency may differ due to
+ * clock register resolutions. Get the configured frequency
+ * so that PWM period can be calculated more accurately.
+ */
pwm->clk_rate = clk_get_rate(pwm->clk);
pwm->rst = devm_reset_control_get(&pdev->dev, "pwm");
@@ -273,10 +287,12 @@ static int tegra_pwm_resume(struct device *dev)
static const struct tegra_pwm_soc tegra20_pwm_soc = {
.num_channels = 4,
+ .max_frequency = 48000000UL,
};
static const struct tegra_pwm_soc tegra186_pwm_soc = {
.num_channels = 1,
+ .max_frequency = 102000000UL,
};
static const struct of_device_id tegra_pwm_of_match[] = {
--
2.1.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
[parent not found: <1493733937-15822-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
2017-05-02 14:05 ` Laxman Dewangan
@ 2017-05-02 15:23 ` Jon Hunter
-1 siblings, 0 replies; 11+ messages in thread
From: Jon Hunter @ 2017-05-02 15:23 UTC (permalink / raw)
To: Laxman Dewangan, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w
Cc: linux-pwm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 02/05/17 15:05, Laxman Dewangan wrote:
> The PWM hardware IP is taped-out with different maximum frequency
> on different SoCs.
>
> From HW team:
> Before Tegra186, it is 38.4MHz.
> In Tegra186, it is 102MHz.
>
> Add support to limit the clock source frequency to the maximum IP
> supported frequency. Provide these values via SoC chipdata.
>
> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>
> ---
> Changes from V1:
> - Set the 48MHz maximum frequency for Tegra210 and earlier.
I think that your changelog needs to be updated, because it still says
38.4MHz and not 48MHz.
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
@ 2017-05-02 15:23 ` Jon Hunter
0 siblings, 0 replies; 11+ messages in thread
From: Jon Hunter @ 2017-05-02 15:23 UTC (permalink / raw)
To: Laxman Dewangan, thierry.reding; +Cc: linux-pwm, linux-tegra, linux-kernel
On 02/05/17 15:05, Laxman Dewangan wrote:
> The PWM hardware IP is taped-out with different maximum frequency
> on different SoCs.
>
> From HW team:
> Before Tegra186, it is 38.4MHz.
> In Tegra186, it is 102MHz.
>
> Add support to limit the clock source frequency to the maximum IP
> supported frequency. Provide these values via SoC chipdata.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>
> ---
> Changes from V1:
> - Set the 48MHz maximum frequency for Tegra210 and earlier.
I think that your changelog needs to be updated, because it still says
38.4MHz and not 48MHz.
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 11+ messages in thread
[parent not found: <908ed0dc-2a75-4348-357c-191fa7348974-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
2017-05-02 15:23 ` Jon Hunter
@ 2017-05-02 17:43 ` Laxman Dewangan
-1 siblings, 0 replies; 11+ messages in thread
From: Laxman Dewangan @ 2017-05-02 17:43 UTC (permalink / raw)
To: Jon Hunter, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w
Cc: linux-pwm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
> On 02/05/17 15:05, Laxman Dewangan wrote:
>> The PWM hardware IP is taped-out with different maximum frequency
>> on different SoCs.
>>
>> From HW team:
>> Before Tegra186, it is 38.4MHz.
>> In Tegra186, it is 102MHz.
>>
>> Add support to limit the clock source frequency to the maximum IP
>> supported frequency. Provide these values via SoC chipdata.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> ---
>> Changes from V1:
>> - Set the 48MHz maximum frequency for Tegra210 and earlier.
> I think that your changelog needs to be updated, because it still says
> 38.4MHz and not 48MHz.
>
Oops, thanks for pointing.
Thierry,
Do I need to recycle the patch or can be corrected when applying?
If there is any further review comment in code then I will recycle and
correct it.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
@ 2017-05-02 17:43 ` Laxman Dewangan
0 siblings, 0 replies; 11+ messages in thread
From: Laxman Dewangan @ 2017-05-02 17:43 UTC (permalink / raw)
To: Jon Hunter, thierry.reding; +Cc: linux-pwm, linux-tegra, linux-kernel
On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
> On 02/05/17 15:05, Laxman Dewangan wrote:
>> The PWM hardware IP is taped-out with different maximum frequency
>> on different SoCs.
>>
>> From HW team:
>> Before Tegra186, it is 38.4MHz.
>> In Tegra186, it is 102MHz.
>>
>> Add support to limit the clock source frequency to the maximum IP
>> supported frequency. Provide these values via SoC chipdata.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>>
>> ---
>> Changes from V1:
>> - Set the 48MHz maximum frequency for Tegra210 and earlier.
> I think that your changelog needs to be updated, because it still says
> 38.4MHz and not 48MHz.
>
Oops, thanks for pointing.
Thierry,
Do I need to recycle the patch or can be corrected when applying?
If there is any further review comment in code then I will recycle and
correct it.
^ permalink raw reply [flat|nested] 11+ messages in thread
[parent not found: <5908C555.7090204-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
2017-05-02 17:43 ` Laxman Dewangan
@ 2017-05-02 20:10 ` Jon Hunter
-1 siblings, 0 replies; 11+ messages in thread
From: Jon Hunter @ 2017-05-02 20:10 UTC (permalink / raw)
To: Laxman Dewangan, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w
Cc: linux-pwm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On 02/05/17 18:43, Laxman Dewangan wrote:
>
> On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
>> On 02/05/17 15:05, Laxman Dewangan wrote:
>>> The PWM hardware IP is taped-out with different maximum frequency
>>> on different SoCs.
>>>
>>> From HW team:
>>> Before Tegra186, it is 38.4MHz.
>>> In Tegra186, it is 102MHz.
>>>
>>> Add support to limit the clock source frequency to the maximum IP
>>> supported frequency. Provide these values via SoC chipdata.
>>>
>>> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>>
>>> ---
>>> Changes from V1:
>>> - Set the 48MHz maximum frequency for Tegra210 and earlier.
>> I think that your changelog needs to be updated, because it still says
>> 38.4MHz and not 48MHz.
>>
>
> Oops, thanks for pointing.
>
> Thierry,
> Do I need to recycle the patch or can be corrected when applying?
> If there is any further review comment in code then I will recycle and
> correct it.
Feel free to add my ...
Acked-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
@ 2017-05-02 20:10 ` Jon Hunter
0 siblings, 0 replies; 11+ messages in thread
From: Jon Hunter @ 2017-05-02 20:10 UTC (permalink / raw)
To: Laxman Dewangan, thierry.reding; +Cc: linux-pwm, linux-tegra, linux-kernel
On 02/05/17 18:43, Laxman Dewangan wrote:
>
> On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
>> On 02/05/17 15:05, Laxman Dewangan wrote:
>>> The PWM hardware IP is taped-out with different maximum frequency
>>> on different SoCs.
>>>
>>> From HW team:
>>> Before Tegra186, it is 38.4MHz.
>>> In Tegra186, it is 102MHz.
>>>
>>> Add support to limit the clock source frequency to the maximum IP
>>> supported frequency. Provide these values via SoC chipdata.
>>>
>>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>>>
>>> ---
>>> Changes from V1:
>>> - Set the 48MHz maximum frequency for Tegra210 and earlier.
>> I think that your changelog needs to be updated, because it still says
>> 38.4MHz and not 48MHz.
>>
>
> Oops, thanks for pointing.
>
> Thierry,
> Do I need to recycle the patch or can be corrected when applying?
> If there is any further review comment in code then I will recycle and
> correct it.
Feel free to add my ...
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
2017-05-02 17:43 ` Laxman Dewangan
@ 2017-05-15 15:17 ` Laxman Dewangan
-1 siblings, 0 replies; 11+ messages in thread
From: Laxman Dewangan @ 2017-05-15 15:17 UTC (permalink / raw)
To: Jon Hunter, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w
Cc: linux-pwm-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
On Tuesday 02 May 2017 11:13 PM, Laxman Dewangan wrote:
>
> On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
>> On 02/05/17 15:05, Laxman Dewangan wrote:
>>> The PWM hardware IP is taped-out with different maximum frequency
>>> on different SoCs.
>>>
>>> From HW team:
>>> Before Tegra186, it is 38.4MHz.
>>> In Tegra186, it is 102MHz.
>>>
>>> Add support to limit the clock source frequency to the maximum IP
>>> supported frequency. Provide these values via SoC chipdata.
>>>
>>> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>>
>>> ---
>>> Changes from V1:
>>> - Set the 48MHz maximum frequency for Tegra210 and earlier.
>> I think that your changelog needs to be updated, because it still says
>> 38.4MHz and not 48MHz.
>>
>
> Oops, thanks for pointing.
>
> Thierry,
> Do I need to recycle the patch or can be corrected when applying?
> If there is any further review comment in code then I will recycle and
> correct it.
Thierry,
Can you please review?
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
@ 2017-05-15 15:17 ` Laxman Dewangan
0 siblings, 0 replies; 11+ messages in thread
From: Laxman Dewangan @ 2017-05-15 15:17 UTC (permalink / raw)
To: Jon Hunter, thierry.reding; +Cc: linux-pwm, linux-tegra, linux-kernel
On Tuesday 02 May 2017 11:13 PM, Laxman Dewangan wrote:
>
> On Tuesday 02 May 2017 08:53 PM, Jon Hunter wrote:
>> On 02/05/17 15:05, Laxman Dewangan wrote:
>>> The PWM hardware IP is taped-out with different maximum frequency
>>> on different SoCs.
>>>
>>> From HW team:
>>> Before Tegra186, it is 38.4MHz.
>>> In Tegra186, it is 102MHz.
>>>
>>> Add support to limit the clock source frequency to the maximum IP
>>> supported frequency. Provide these values via SoC chipdata.
>>>
>>> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>>>
>>> ---
>>> Changes from V1:
>>> - Set the 48MHz maximum frequency for Tegra210 and earlier.
>> I think that your changelog needs to be updated, because it still says
>> 38.4MHz and not 48MHz.
>>
>
> Oops, thanks for pointing.
>
> Thierry,
> Do I need to recycle the patch or can be corrected when applying?
> If there is any further review comment in code then I will recycle and
> correct it.
Thierry,
Can you please review?
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout
2017-05-02 14:05 ` Laxman Dewangan
(?)
(?)
@ 2017-06-13 12:32 ` Thierry Reding
-1 siblings, 0 replies; 11+ messages in thread
From: Thierry Reding @ 2017-06-13 12:32 UTC (permalink / raw)
To: Laxman Dewangan; +Cc: jonathanh, linux-pwm, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 802 bytes --]
On Tue, May 02, 2017 at 07:35:37PM +0530, Laxman Dewangan wrote:
> The PWM hardware IP is taped-out with different maximum frequency
> on different SoCs.
>
> From HW team:
> Before Tegra186, it is 38.4MHz.
> In Tegra186, it is 102MHz.
>
> Add support to limit the clock source frequency to the maximum IP
> supported frequency. Provide these values via SoC chipdata.
>
> Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
>
> ---
> Changes from V1:
> - Set the 48MHz maximum frequency for Tegra210 and earlier.
> - Set the maximum frequency unconditionally as per V1 review comment.
> ---
> drivers/pwm/pwm-tegra.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
Applied with a fixed up commit message and Jon's Acked-by.
Thanks,
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2017-06-13 12:32 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-05-02 14:05 [PATCH V2] pwm: tegra: Set maximum pwm clock source per SoC tapeout Laxman Dewangan
2017-05-02 14:05 ` Laxman Dewangan
[not found] ` <1493733937-15822-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-05-02 15:23 ` Jon Hunter
2017-05-02 15:23 ` Jon Hunter
[not found] ` <908ed0dc-2a75-4348-357c-191fa7348974-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-05-02 17:43 ` Laxman Dewangan
2017-05-02 17:43 ` Laxman Dewangan
[not found] ` <5908C555.7090204-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-05-02 20:10 ` Jon Hunter
2017-05-02 20:10 ` Jon Hunter
2017-05-15 15:17 ` Laxman Dewangan
2017-05-15 15:17 ` Laxman Dewangan
2017-06-13 12:32 ` Thierry Reding
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